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24#ifndef PP_ATOMFWCTRL_H
25#define PP_ATOMFWCTRL_H
26
27#include "hwmgr.h"
28
29typedef enum atom_smu9_syspll0_clock_id BIOS_CLKID;
30
31#define GetIndexIntoMasterCmdTable(FieldName) \
32 (((char*)(&((struct atom_master_list_of_command_functions_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
33#define GetIndexIntoMasterDataTable(FieldName) \
34 (((char*)(&((struct atom_master_list_of_data_tables_v2_1*)0)->FieldName)-(char*)0)/sizeof(uint16_t))
35
36#define PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES 32
37
38struct pp_atomfwctrl_voltage_table_entry {
39 uint16_t value;
40 uint32_t smio_low;
41};
42
43struct pp_atomfwctrl_voltage_table {
44 uint32_t count;
45 uint32_t mask_low;
46 uint32_t phase_delay;
47 uint8_t psi0_enable;
48 uint8_t psi1_enable;
49 uint8_t max_vid_step;
50 uint8_t telemetry_offset;
51 uint8_t telemetry_slope;
52 struct pp_atomfwctrl_voltage_table_entry entries[PP_ATOMFWCTRL_MAX_VOLTAGE_ENTRIES];
53};
54
55struct pp_atomfwctrl_gpio_pin_assignment {
56 uint16_t us_gpio_pin_aindex;
57 uint8_t uc_gpio_pin_bit_shift;
58};
59
60struct pp_atomfwctrl_clock_dividers_soc15 {
61 uint32_t ulClock;
62 uint32_t ulDid;
63 uint32_t ulPll_fb_mult;
64 uint32_t ulPll_ss_fbsmult;
65 uint16_t usPll_ss_slew_frac;
66 uint8_t ucPll_ss_enable;
67 uint8_t ucReserve;
68 uint32_t ulReserve[2];
69};
70
71struct pp_atomfwctrl_avfs_parameters {
72 uint32_t ulMaxVddc;
73 uint32_t ulMinVddc;
74
75 uint32_t ulMeanNsigmaAcontant0;
76 uint32_t ulMeanNsigmaAcontant1;
77 uint32_t ulMeanNsigmaAcontant2;
78 uint16_t usMeanNsigmaDcTolSigma;
79 uint16_t usMeanNsigmaPlatformMean;
80 uint16_t usMeanNsigmaPlatformSigma;
81 uint32_t ulGbVdroopTableCksoffA0;
82 uint32_t ulGbVdroopTableCksoffA1;
83 uint32_t ulGbVdroopTableCksoffA2;
84 uint32_t ulGbVdroopTableCksonA0;
85 uint32_t ulGbVdroopTableCksonA1;
86 uint32_t ulGbVdroopTableCksonA2;
87
88 uint32_t ulGbFuseTableCksoffM1;
89 uint32_t ulGbFuseTableCksoffM2;
90 uint32_t ulGbFuseTableCksoffB;
91
92 uint32_t ulGbFuseTableCksonM1;
93 uint32_t ulGbFuseTableCksonM2;
94 uint32_t ulGbFuseTableCksonB;
95
96 uint8_t ucEnableGbVdroopTableCkson;
97 uint8_t ucEnableGbFuseTableCkson;
98 uint16_t usPsmAgeComfactor;
99
100 uint32_t ulDispclk2GfxclkM1;
101 uint32_t ulDispclk2GfxclkM2;
102 uint32_t ulDispclk2GfxclkB;
103 uint32_t ulDcefclk2GfxclkM1;
104 uint32_t ulDcefclk2GfxclkM2;
105 uint32_t ulDcefclk2GfxclkB;
106 uint32_t ulPixelclk2GfxclkM1;
107 uint32_t ulPixelclk2GfxclkM2;
108 uint32_t ulPixelclk2GfxclkB;
109 uint32_t ulPhyclk2GfxclkM1;
110 uint32_t ulPhyclk2GfxclkM2;
111 uint32_t ulPhyclk2GfxclkB;
112 uint32_t ulAcgGbVdroopTableA0;
113 uint32_t ulAcgGbVdroopTableA1;
114 uint32_t ulAcgGbVdroopTableA2;
115 uint32_t ulAcgGbFuseTableM1;
116 uint32_t ulAcgGbFuseTableM2;
117 uint32_t ulAcgGbFuseTableB;
118 uint32_t ucAcgEnableGbVdroopTable;
119 uint32_t ucAcgEnableGbFuseTable;
120};
121
122struct pp_atomfwctrl_gpio_parameters {
123 uint8_t ucAcDcGpio;
124 uint8_t ucAcDcPolarity;
125 uint8_t ucVR0HotGpio;
126 uint8_t ucVR0HotPolarity;
127 uint8_t ucVR1HotGpio;
128 uint8_t ucVR1HotPolarity;
129 uint8_t ucFwCtfGpio;
130 uint8_t ucFwCtfPolarity;
131};
132
133struct pp_atomfwctrl_bios_boot_up_values {
134 uint32_t ulRevision;
135 uint32_t ulGfxClk;
136 uint32_t ulUClk;
137 uint32_t ulSocClk;
138 uint32_t ulDCEFClk;
139 uint16_t usVddc;
140 uint16_t usVddci;
141 uint16_t usMvddc;
142 uint16_t usVddGfx;
143 uint8_t ucCoolingID;
144};
145
146struct pp_atomfwctrl_smc_dpm_parameters
147{
148 uint8_t liquid1_i2c_address;
149 uint8_t liquid2_i2c_address;
150 uint8_t vr_i2c_address;
151 uint8_t plx_i2c_address;
152 uint8_t liquid_i2c_linescl;
153 uint8_t liquid_i2c_linesda;
154 uint8_t vr_i2c_linescl;
155 uint8_t vr_i2c_linesda;
156 uint8_t plx_i2c_linescl;
157 uint8_t plx_i2c_linesda;
158 uint8_t vrsensorpresent;
159 uint8_t liquidsensorpresent;
160 uint16_t maxvoltagestepgfx;
161 uint16_t maxvoltagestepsoc;
162 uint8_t vddgfxvrmapping;
163 uint8_t vddsocvrmapping;
164 uint8_t vddmem0vrmapping;
165 uint8_t vddmem1vrmapping;
166 uint8_t gfxulvphasesheddingmask;
167 uint8_t soculvphasesheddingmask;
168
169 uint16_t gfxmaxcurrent;
170 uint8_t gfxoffset;
171 uint8_t padding_telemetrygfx;
172 uint16_t socmaxcurrent;
173 uint8_t socoffset;
174 uint8_t padding_telemetrysoc;
175 uint16_t mem0maxcurrent;
176 uint8_t mem0offset;
177 uint8_t padding_telemetrymem0;
178 uint16_t mem1maxcurrent;
179 uint8_t mem1offset;
180 uint8_t padding_telemetrymem1;
181
182 uint8_t acdcgpio;
183 uint8_t acdcpolarity;
184 uint8_t vr0hotgpio;
185 uint8_t vr0hotpolarity;
186 uint8_t vr1hotgpio;
187 uint8_t vr1hotpolarity;
188 uint8_t padding1;
189 uint8_t padding2;
190
191 uint8_t ledpin0;
192 uint8_t ledpin1;
193 uint8_t ledpin2;
194
195 uint8_t pllgfxclkspreadenabled;
196 uint8_t pllgfxclkspreadpercent;
197 uint16_t pllgfxclkspreadfreq;
198
199 uint8_t uclkspreadenabled;
200 uint8_t uclkspreadpercent;
201 uint16_t uclkspreadfreq;
202
203 uint8_t socclkspreadenabled;
204 uint8_t socclkspreadpercent;
205 uint16_t socclkspreadfreq;
206
207 uint8_t acggfxclkspreadenabled;
208 uint8_t acggfxclkspreadpercent;
209 uint16_t acggfxclkspreadfreq;
210};
211
212int pp_atomfwctrl_get_gpu_pll_dividers_vega10(struct pp_hwmgr *hwmgr,
213 uint32_t clock_type, uint32_t clock_value,
214 struct pp_atomfwctrl_clock_dividers_soc15 *dividers);
215int pp_atomfwctrl_enter_self_refresh(struct pp_hwmgr *hwmgr);
216bool pp_atomfwctrl_get_pp_assign_pin(struct pp_hwmgr *hwmgr, const uint32_t pin_id,
217 struct pp_atomfwctrl_gpio_pin_assignment *gpio_pin_assignment);
218
219int pp_atomfwctrl_get_voltage_table_v4(struct pp_hwmgr *hwmgr, uint8_t voltage_type,
220 uint8_t voltage_mode, struct pp_atomfwctrl_voltage_table *voltage_table);
221bool pp_atomfwctrl_is_voltage_controlled_by_gpio_v4(struct pp_hwmgr *hwmgr,
222 uint8_t voltage_type, uint8_t voltage_mode);
223
224int pp_atomfwctrl_get_avfs_information(struct pp_hwmgr *hwmgr,
225 struct pp_atomfwctrl_avfs_parameters *param);
226int pp_atomfwctrl_get_gpio_information(struct pp_hwmgr *hwmgr,
227 struct pp_atomfwctrl_gpio_parameters *param);
228
229int pp_atomfwctrl_get_vbios_bootup_values(struct pp_hwmgr *hwmgr,
230 struct pp_atomfwctrl_bios_boot_up_values *boot_values);
231int pp_atomfwctrl_get_smc_dpm_information(struct pp_hwmgr *hwmgr,
232 struct pp_atomfwctrl_smc_dpm_parameters *param);
233
234#endif
235
236