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23#include "pp_debug.h"
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/slab.h>
27#include "atom-types.h"
28#include "atombios.h"
29#include "processpptables.h"
30#include "cgs_common.h"
31#include "smumgr.h"
32#include "hwmgr.h"
33#include "hardwaremanager.h"
34#include "rv_ppsmc.h"
35#include "smu10_hwmgr.h"
36#include "power_state.h"
37#include "pp_soc15.h"
38
39#define SMU10_MAX_DEEPSLEEP_DIVIDER_ID 5
40#define SMU10_MINIMUM_ENGINE_CLOCK 800
41#define SCLK_MIN_DIV_INTV_SHIFT 12
42#define SMU10_DISPCLK_BYPASS_THRESHOLD 10000
43#define SMC_RAM_END 0x40000
44
45static const unsigned long SMU10_Magic = (unsigned long) PHM_Rv_Magic;
46
47
48static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
49 struct pp_display_clock_request *clock_req);
50
51
52static struct smu10_power_state *cast_smu10_ps(struct pp_hw_power_state *hw_ps)
53{
54 if (SMU10_Magic != hw_ps->magic)
55 return NULL;
56
57 return (struct smu10_power_state *)hw_ps;
58}
59
60static const struct smu10_power_state *cast_const_smu10_ps(
61 const struct pp_hw_power_state *hw_ps)
62{
63 if (SMU10_Magic != hw_ps->magic)
64 return NULL;
65
66 return (struct smu10_power_state *)hw_ps;
67}
68
69static int smu10_initialize_dpm_defaults(struct pp_hwmgr *hwmgr)
70{
71 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
72
73 smu10_data->dce_slow_sclk_threshold = 30000;
74 smu10_data->thermal_auto_throttling_treshold = 0;
75 smu10_data->is_nb_dpm_enabled = 1;
76 smu10_data->dpm_flags = 1;
77 smu10_data->gfx_off_controled_by_driver = false;
78 smu10_data->need_min_deep_sleep_dcefclk = true;
79 smu10_data->num_active_display = 0;
80 smu10_data->deep_sleep_dcefclk = 0;
81
82 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
83 PHM_PlatformCaps_SclkDeepSleep);
84
85 phm_cap_unset(hwmgr->platform_descriptor.platformCaps,
86 PHM_PlatformCaps_SclkThrottleLowNotification);
87
88 phm_cap_set(hwmgr->platform_descriptor.platformCaps,
89 PHM_PlatformCaps_PowerPlaySupport);
90 return 0;
91}
92
93static int smu10_construct_max_power_limits_table(struct pp_hwmgr *hwmgr,
94 struct phm_clock_and_voltage_limits *table)
95{
96 return 0;
97}
98
99static int smu10_init_dynamic_state_adjustment_rule_settings(
100 struct pp_hwmgr *hwmgr)
101{
102 uint32_t table_size =
103 sizeof(struct phm_clock_voltage_dependency_table) +
104 (7 * sizeof(struct phm_clock_voltage_dependency_record));
105
106 struct phm_clock_voltage_dependency_table *table_clk_vlt =
107 kzalloc(table_size, GFP_KERNEL);
108
109 if (NULL == table_clk_vlt) {
110 pr_err("Can not allocate memory!\n");
111 return -ENOMEM;
112 }
113
114 table_clk_vlt->count = 8;
115 table_clk_vlt->entries[0].clk = PP_DAL_POWERLEVEL_0;
116 table_clk_vlt->entries[0].v = 0;
117 table_clk_vlt->entries[1].clk = PP_DAL_POWERLEVEL_1;
118 table_clk_vlt->entries[1].v = 1;
119 table_clk_vlt->entries[2].clk = PP_DAL_POWERLEVEL_2;
120 table_clk_vlt->entries[2].v = 2;
121 table_clk_vlt->entries[3].clk = PP_DAL_POWERLEVEL_3;
122 table_clk_vlt->entries[3].v = 3;
123 table_clk_vlt->entries[4].clk = PP_DAL_POWERLEVEL_4;
124 table_clk_vlt->entries[4].v = 4;
125 table_clk_vlt->entries[5].clk = PP_DAL_POWERLEVEL_5;
126 table_clk_vlt->entries[5].v = 5;
127 table_clk_vlt->entries[6].clk = PP_DAL_POWERLEVEL_6;
128 table_clk_vlt->entries[6].v = 6;
129 table_clk_vlt->entries[7].clk = PP_DAL_POWERLEVEL_7;
130 table_clk_vlt->entries[7].v = 7;
131 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = table_clk_vlt;
132
133 return 0;
134}
135
136static int smu10_get_system_info_data(struct pp_hwmgr *hwmgr)
137{
138 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)hwmgr->backend;
139
140 smu10_data->sys_info.htc_hyst_lmt = 5;
141 smu10_data->sys_info.htc_tmp_lmt = 203;
142
143 if (smu10_data->thermal_auto_throttling_treshold == 0)
144 smu10_data->thermal_auto_throttling_treshold = 203;
145
146 smu10_construct_max_power_limits_table (hwmgr,
147 &hwmgr->dyn_state.max_clock_voltage_on_ac);
148
149 smu10_init_dynamic_state_adjustment_rule_settings(hwmgr);
150
151 return 0;
152}
153
154static int smu10_construct_boot_state(struct pp_hwmgr *hwmgr)
155{
156 return 0;
157}
158
159static int smu10_set_clock_limit(struct pp_hwmgr *hwmgr, const void *input)
160{
161 struct PP_Clocks clocks = {0};
162 struct pp_display_clock_request clock_req;
163
164 clocks.dcefClock = hwmgr->display_config.min_dcef_set_clk;
165 clock_req.clock_type = amd_pp_dcf_clock;
166 clock_req.clock_freq_in_khz = clocks.dcefClock * 10;
167
168 PP_ASSERT_WITH_CODE(!smu10_display_clock_voltage_request(hwmgr, &clock_req),
169 "Attempt to set DCF Clock Failed!", return -EINVAL);
170
171 return 0;
172}
173
174static int smu10_set_deep_sleep_dcefclk(struct pp_hwmgr *hwmgr, uint32_t clock)
175{
176 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
177
178 if (smu10_data->need_min_deep_sleep_dcefclk && smu10_data->deep_sleep_dcefclk != clock/100) {
179 smu10_data->deep_sleep_dcefclk = clock/100;
180 smum_send_msg_to_smc_with_parameter(hwmgr,
181 PPSMC_MSG_SetMinDeepSleepDcefclk,
182 smu10_data->deep_sleep_dcefclk);
183 }
184 return 0;
185}
186
187static int smu10_set_active_display_count(struct pp_hwmgr *hwmgr, uint32_t count)
188{
189 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
190
191 if (smu10_data->num_active_display != count) {
192 smu10_data->num_active_display = count;
193 smum_send_msg_to_smc_with_parameter(hwmgr,
194 PPSMC_MSG_SetDisplayCount,
195 smu10_data->num_active_display);
196 }
197
198 return 0;
199}
200
201static int smu10_set_power_state_tasks(struct pp_hwmgr *hwmgr, const void *input)
202{
203 return smu10_set_clock_limit(hwmgr, input);
204}
205
206static int smu10_init_power_gate_state(struct pp_hwmgr *hwmgr)
207{
208 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
209
210 smu10_data->vcn_power_gated = true;
211 smu10_data->isp_tileA_power_gated = true;
212 smu10_data->isp_tileB_power_gated = true;
213
214 return 0;
215}
216
217
218static int smu10_setup_asic_task(struct pp_hwmgr *hwmgr)
219{
220 return smu10_init_power_gate_state(hwmgr);
221}
222
223static int smu10_reset_cc6_data(struct pp_hwmgr *hwmgr)
224{
225 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
226
227 smu10_data->separation_time = 0;
228 smu10_data->cc6_disable = false;
229 smu10_data->pstate_disable = false;
230 smu10_data->cc6_setting_changed = false;
231
232 return 0;
233}
234
235static int smu10_power_off_asic(struct pp_hwmgr *hwmgr)
236{
237 return smu10_reset_cc6_data(hwmgr);
238}
239
240static int smu10_disable_gfx_off(struct pp_hwmgr *hwmgr)
241{
242 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
243
244 if (smu10_data->gfx_off_controled_by_driver)
245 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_DisableGfxOff);
246
247 return 0;
248}
249
250static int smu10_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
251{
252 return smu10_disable_gfx_off(hwmgr);
253}
254
255static int smu10_enable_gfx_off(struct pp_hwmgr *hwmgr)
256{
257 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
258
259 if (smu10_data->gfx_off_controled_by_driver)
260 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_EnableGfxOff);
261
262 return 0;
263}
264
265static int smu10_enable_dpm_tasks(struct pp_hwmgr *hwmgr)
266{
267 return smu10_enable_gfx_off(hwmgr);
268}
269
270static int smu10_apply_state_adjust_rules(struct pp_hwmgr *hwmgr,
271 struct pp_power_state *prequest_ps,
272 const struct pp_power_state *pcurrent_ps)
273{
274 return 0;
275}
276
277
278static const DpmClock_t VddDcfClk[]= {
279 { 300, 2600},
280 { 600, 3200},
281 { 600, 3600},
282};
283
284static const DpmClock_t VddSocClk[]= {
285 { 478, 2600},
286 { 722, 3200},
287 { 722, 3600},
288};
289
290static const DpmClock_t VddFClk[]= {
291 { 400, 2600},
292 {1200, 3200},
293 {1200, 3600},
294};
295
296static const DpmClock_t VddDispClk[]= {
297 { 435, 2600},
298 { 661, 3200},
299 {1086, 3600},
300};
301
302static const DpmClock_t VddDppClk[]= {
303 { 435, 2600},
304 { 661, 3200},
305 { 661, 3600},
306};
307
308static const DpmClock_t VddPhyClk[]= {
309 { 540, 2600},
310 { 810, 3200},
311 { 810, 3600},
312};
313
314static int smu10_get_clock_voltage_dependency_table(struct pp_hwmgr *hwmgr,
315 struct smu10_voltage_dependency_table **pptable,
316 uint32_t num_entry, const DpmClock_t *pclk_dependency_table)
317{
318 uint32_t table_size, i;
319 struct smu10_voltage_dependency_table *ptable;
320
321 table_size = sizeof(uint32_t) + sizeof(struct smu10_voltage_dependency_table) * num_entry;
322 ptable = kzalloc(table_size, GFP_KERNEL);
323
324 if (NULL == ptable)
325 return -ENOMEM;
326
327 ptable->count = num_entry;
328
329 for (i = 0; i < ptable->count; i++) {
330 ptable->entries[i].clk = pclk_dependency_table->Freq * 100;
331 ptable->entries[i].vol = pclk_dependency_table->Vol;
332 pclk_dependency_table++;
333 }
334
335 *pptable = ptable;
336
337 return 0;
338}
339
340
341static int smu10_populate_clock_table(struct pp_hwmgr *hwmgr)
342{
343 int result;
344
345 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
346 DpmClocks_t *table = &(smu10_data->clock_table);
347 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
348
349 result = smum_smc_table_manager(hwmgr, (uint8_t *)table, SMU10_CLOCKTABLE, true);
350
351 PP_ASSERT_WITH_CODE((0 == result),
352 "Attempt to copy clock table from smc failed",
353 return result);
354
355 if (0 == result && table->DcefClocks[0].Freq != 0) {
356 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
357 NUM_DCEFCLK_DPM_LEVELS,
358 &smu10_data->clock_table.DcefClocks[0]);
359 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
360 NUM_SOCCLK_DPM_LEVELS,
361 &smu10_data->clock_table.SocClocks[0]);
362 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
363 NUM_FCLK_DPM_LEVELS,
364 &smu10_data->clock_table.FClocks[0]);
365 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_mclk,
366 NUM_MEMCLK_DPM_LEVELS,
367 &smu10_data->clock_table.MemClocks[0]);
368 } else {
369 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dcefclk,
370 ARRAY_SIZE(VddDcfClk),
371 &VddDcfClk[0]);
372 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_socclk,
373 ARRAY_SIZE(VddSocClk),
374 &VddSocClk[0]);
375 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_fclk,
376 ARRAY_SIZE(VddFClk),
377 &VddFClk[0]);
378 }
379 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dispclk,
380 ARRAY_SIZE(VddDispClk),
381 &VddDispClk[0]);
382 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_dppclk,
383 ARRAY_SIZE(VddDppClk), &VddDppClk[0]);
384 smu10_get_clock_voltage_dependency_table(hwmgr, &pinfo->vdd_dep_on_phyclk,
385 ARRAY_SIZE(VddPhyClk), &VddPhyClk[0]);
386
387 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMinGfxclkFrequency);
388 result = smum_get_argument(hwmgr);
389 smu10_data->gfx_min_freq_limit = result * 100;
390
391 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetMaxGfxclkFrequency);
392 result = smum_get_argument(hwmgr);
393 smu10_data->gfx_max_freq_limit = result * 100;
394
395 return 0;
396}
397
398static int smu10_hwmgr_backend_init(struct pp_hwmgr *hwmgr)
399{
400 int result = 0;
401 struct smu10_hwmgr *data;
402
403 data = kzalloc(sizeof(struct smu10_hwmgr), GFP_KERNEL);
404 if (data == NULL)
405 return -ENOMEM;
406
407 hwmgr->backend = data;
408
409 result = smu10_initialize_dpm_defaults(hwmgr);
410 if (result != 0) {
411 pr_err("smu10_initialize_dpm_defaults failed\n");
412 return result;
413 }
414
415 smu10_populate_clock_table(hwmgr);
416
417 result = smu10_get_system_info_data(hwmgr);
418 if (result != 0) {
419 pr_err("smu10_get_system_info_data failed\n");
420 return result;
421 }
422
423 smu10_construct_boot_state(hwmgr);
424
425 hwmgr->platform_descriptor.hardwareActivityPerformanceLevels =
426 SMU10_MAX_HARDWARE_POWERLEVELS;
427
428 hwmgr->platform_descriptor.hardwarePerformanceLevels =
429 SMU10_MAX_HARDWARE_POWERLEVELS;
430
431 hwmgr->platform_descriptor.vbiosInterruptId = 0;
432
433 hwmgr->platform_descriptor.clockStep.engineClock = 500;
434
435 hwmgr->platform_descriptor.clockStep.memoryClock = 500;
436
437 hwmgr->platform_descriptor.minimumClocksReductionPercentage = 50;
438
439 hwmgr->pstate_sclk = SMU10_UMD_PSTATE_GFXCLK;
440 hwmgr->pstate_mclk = SMU10_UMD_PSTATE_FCLK;
441
442 return result;
443}
444
445static int smu10_hwmgr_backend_fini(struct pp_hwmgr *hwmgr)
446{
447 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
448 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
449
450 kfree(pinfo->vdd_dep_on_dcefclk);
451 pinfo->vdd_dep_on_dcefclk = NULL;
452 kfree(pinfo->vdd_dep_on_socclk);
453 pinfo->vdd_dep_on_socclk = NULL;
454 kfree(pinfo->vdd_dep_on_fclk);
455 pinfo->vdd_dep_on_fclk = NULL;
456 kfree(pinfo->vdd_dep_on_dispclk);
457 pinfo->vdd_dep_on_dispclk = NULL;
458 kfree(pinfo->vdd_dep_on_dppclk);
459 pinfo->vdd_dep_on_dppclk = NULL;
460 kfree(pinfo->vdd_dep_on_phyclk);
461 pinfo->vdd_dep_on_phyclk = NULL;
462
463 kfree(hwmgr->dyn_state.vddc_dep_on_dal_pwrl);
464 hwmgr->dyn_state.vddc_dep_on_dal_pwrl = NULL;
465
466 kfree(hwmgr->backend);
467 hwmgr->backend = NULL;
468
469 return 0;
470}
471
472static int smu10_dpm_force_dpm_level(struct pp_hwmgr *hwmgr,
473 enum amd_dpm_forced_level level)
474{
475 if (hwmgr->smu_version < 0x1E3700) {
476 pr_info("smu firmware version too old, can not set dpm level\n");
477 return 0;
478 }
479
480 switch (level) {
481 case AMD_DPM_FORCED_LEVEL_HIGH:
482 case AMD_DPM_FORCED_LEVEL_PROFILE_PEAK:
483 smum_send_msg_to_smc_with_parameter(hwmgr,
484 PPSMC_MSG_SetHardMinGfxClk,
485 SMU10_UMD_PSTATE_PEAK_GFXCLK);
486 smum_send_msg_to_smc_with_parameter(hwmgr,
487 PPSMC_MSG_SetHardMinFclkByFreq,
488 SMU10_UMD_PSTATE_PEAK_FCLK);
489 smum_send_msg_to_smc_with_parameter(hwmgr,
490 PPSMC_MSG_SetHardMinSocclkByFreq,
491 SMU10_UMD_PSTATE_PEAK_SOCCLK);
492 smum_send_msg_to_smc_with_parameter(hwmgr,
493 PPSMC_MSG_SetHardMinVcn,
494 SMU10_UMD_PSTATE_VCE);
495
496 smum_send_msg_to_smc_with_parameter(hwmgr,
497 PPSMC_MSG_SetSoftMaxGfxClk,
498 SMU10_UMD_PSTATE_PEAK_GFXCLK);
499 smum_send_msg_to_smc_with_parameter(hwmgr,
500 PPSMC_MSG_SetSoftMaxFclkByFreq,
501 SMU10_UMD_PSTATE_PEAK_FCLK);
502 smum_send_msg_to_smc_with_parameter(hwmgr,
503 PPSMC_MSG_SetSoftMaxSocclkByFreq,
504 SMU10_UMD_PSTATE_PEAK_SOCCLK);
505 smum_send_msg_to_smc_with_parameter(hwmgr,
506 PPSMC_MSG_SetSoftMaxVcn,
507 SMU10_UMD_PSTATE_VCE);
508 break;
509 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_SCLK:
510 smum_send_msg_to_smc_with_parameter(hwmgr,
511 PPSMC_MSG_SetHardMinGfxClk,
512 SMU10_UMD_PSTATE_MIN_GFXCLK);
513 smum_send_msg_to_smc_with_parameter(hwmgr,
514 PPSMC_MSG_SetSoftMaxGfxClk,
515 SMU10_UMD_PSTATE_MIN_GFXCLK);
516 break;
517 case AMD_DPM_FORCED_LEVEL_PROFILE_MIN_MCLK:
518 smum_send_msg_to_smc_with_parameter(hwmgr,
519 PPSMC_MSG_SetHardMinFclkByFreq,
520 SMU10_UMD_PSTATE_MIN_FCLK);
521 smum_send_msg_to_smc_with_parameter(hwmgr,
522 PPSMC_MSG_SetSoftMaxFclkByFreq,
523 SMU10_UMD_PSTATE_MIN_FCLK);
524 break;
525 case AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD:
526 smum_send_msg_to_smc_with_parameter(hwmgr,
527 PPSMC_MSG_SetHardMinGfxClk,
528 SMU10_UMD_PSTATE_GFXCLK);
529 smum_send_msg_to_smc_with_parameter(hwmgr,
530 PPSMC_MSG_SetHardMinFclkByFreq,
531 SMU10_UMD_PSTATE_FCLK);
532 smum_send_msg_to_smc_with_parameter(hwmgr,
533 PPSMC_MSG_SetHardMinSocclkByFreq,
534 SMU10_UMD_PSTATE_SOCCLK);
535 smum_send_msg_to_smc_with_parameter(hwmgr,
536 PPSMC_MSG_SetHardMinVcn,
537 SMU10_UMD_PSTATE_VCE);
538
539 smum_send_msg_to_smc_with_parameter(hwmgr,
540 PPSMC_MSG_SetSoftMaxGfxClk,
541 SMU10_UMD_PSTATE_GFXCLK);
542 smum_send_msg_to_smc_with_parameter(hwmgr,
543 PPSMC_MSG_SetSoftMaxFclkByFreq,
544 SMU10_UMD_PSTATE_FCLK);
545 smum_send_msg_to_smc_with_parameter(hwmgr,
546 PPSMC_MSG_SetSoftMaxSocclkByFreq,
547 SMU10_UMD_PSTATE_SOCCLK);
548 smum_send_msg_to_smc_with_parameter(hwmgr,
549 PPSMC_MSG_SetSoftMaxVcn,
550 SMU10_UMD_PSTATE_VCE);
551 break;
552 case AMD_DPM_FORCED_LEVEL_AUTO:
553 smum_send_msg_to_smc_with_parameter(hwmgr,
554 PPSMC_MSG_SetHardMinGfxClk,
555 SMU10_UMD_PSTATE_MIN_GFXCLK);
556 smum_send_msg_to_smc_with_parameter(hwmgr,
557 PPSMC_MSG_SetHardMinFclkByFreq,
558 SMU10_UMD_PSTATE_MIN_FCLK);
559 smum_send_msg_to_smc_with_parameter(hwmgr,
560 PPSMC_MSG_SetHardMinSocclkByFreq,
561 SMU10_UMD_PSTATE_MIN_SOCCLK);
562 smum_send_msg_to_smc_with_parameter(hwmgr,
563 PPSMC_MSG_SetHardMinVcn,
564 SMU10_UMD_PSTATE_MIN_VCE);
565
566 smum_send_msg_to_smc_with_parameter(hwmgr,
567 PPSMC_MSG_SetSoftMaxGfxClk,
568 SMU10_UMD_PSTATE_PEAK_GFXCLK);
569 smum_send_msg_to_smc_with_parameter(hwmgr,
570 PPSMC_MSG_SetSoftMaxFclkByFreq,
571 SMU10_UMD_PSTATE_PEAK_FCLK);
572 smum_send_msg_to_smc_with_parameter(hwmgr,
573 PPSMC_MSG_SetSoftMaxSocclkByFreq,
574 SMU10_UMD_PSTATE_PEAK_SOCCLK);
575 smum_send_msg_to_smc_with_parameter(hwmgr,
576 PPSMC_MSG_SetSoftMaxVcn,
577 SMU10_UMD_PSTATE_VCE);
578 break;
579 case AMD_DPM_FORCED_LEVEL_LOW:
580 smum_send_msg_to_smc_with_parameter(hwmgr,
581 PPSMC_MSG_SetHardMinGfxClk,
582 SMU10_UMD_PSTATE_MIN_GFXCLK);
583 smum_send_msg_to_smc_with_parameter(hwmgr,
584 PPSMC_MSG_SetSoftMaxGfxClk,
585 SMU10_UMD_PSTATE_MIN_GFXCLK);
586 smum_send_msg_to_smc_with_parameter(hwmgr,
587 PPSMC_MSG_SetHardMinFclkByFreq,
588 SMU10_UMD_PSTATE_MIN_FCLK);
589 smum_send_msg_to_smc_with_parameter(hwmgr,
590 PPSMC_MSG_SetSoftMaxFclkByFreq,
591 SMU10_UMD_PSTATE_MIN_FCLK);
592 break;
593 case AMD_DPM_FORCED_LEVEL_MANUAL:
594 case AMD_DPM_FORCED_LEVEL_PROFILE_EXIT:
595 default:
596 break;
597 }
598 return 0;
599}
600
601static uint32_t smu10_dpm_get_mclk(struct pp_hwmgr *hwmgr, bool low)
602{
603 struct smu10_hwmgr *data;
604
605 if (hwmgr == NULL)
606 return -EINVAL;
607
608 data = (struct smu10_hwmgr *)(hwmgr->backend);
609
610 if (low)
611 return data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
612 else
613 return data->clock_vol_info.vdd_dep_on_fclk->entries[
614 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
615}
616
617static uint32_t smu10_dpm_get_sclk(struct pp_hwmgr *hwmgr, bool low)
618{
619 struct smu10_hwmgr *data;
620
621 if (hwmgr == NULL)
622 return -EINVAL;
623
624 data = (struct smu10_hwmgr *)(hwmgr->backend);
625
626 if (low)
627 return data->gfx_min_freq_limit;
628 else
629 return data->gfx_max_freq_limit;
630}
631
632static int smu10_dpm_patch_boot_state(struct pp_hwmgr *hwmgr,
633 struct pp_hw_power_state *hw_ps)
634{
635 return 0;
636}
637
638static int smu10_dpm_get_pp_table_entry_callback(
639 struct pp_hwmgr *hwmgr,
640 struct pp_hw_power_state *hw_ps,
641 unsigned int index,
642 const void *clock_info)
643{
644 struct smu10_power_state *smu10_ps = cast_smu10_ps(hw_ps);
645
646 smu10_ps->levels[index].engine_clock = 0;
647
648 smu10_ps->levels[index].vddc_index = 0;
649 smu10_ps->level = index + 1;
650
651 if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
652 smu10_ps->levels[index].ds_divider_index = 5;
653 smu10_ps->levels[index].ss_divider_index = 5;
654 }
655
656 return 0;
657}
658
659static int smu10_dpm_get_num_of_pp_table_entries(struct pp_hwmgr *hwmgr)
660{
661 int result;
662 unsigned long ret = 0;
663
664 result = pp_tables_get_num_of_entries(hwmgr, &ret);
665
666 return result ? 0 : ret;
667}
668
669static int smu10_dpm_get_pp_table_entry(struct pp_hwmgr *hwmgr,
670 unsigned long entry, struct pp_power_state *ps)
671{
672 int result;
673 struct smu10_power_state *smu10_ps;
674
675 ps->hardware.magic = SMU10_Magic;
676
677 smu10_ps = cast_smu10_ps(&(ps->hardware));
678
679 result = pp_tables_get_entry(hwmgr, entry, ps,
680 smu10_dpm_get_pp_table_entry_callback);
681
682 smu10_ps->uvd_clocks.vclk = ps->uvd_clocks.VCLK;
683 smu10_ps->uvd_clocks.dclk = ps->uvd_clocks.DCLK;
684
685 return result;
686}
687
688static int smu10_get_power_state_size(struct pp_hwmgr *hwmgr)
689{
690 return sizeof(struct smu10_power_state);
691}
692
693static int smu10_set_cpu_power_state(struct pp_hwmgr *hwmgr)
694{
695 return 0;
696}
697
698
699static int smu10_store_cc6_data(struct pp_hwmgr *hwmgr, uint32_t separation_time,
700 bool cc6_disable, bool pstate_disable, bool pstate_switch_disable)
701{
702 return 0;
703}
704
705static int smu10_get_dal_power_level(struct pp_hwmgr *hwmgr,
706 struct amd_pp_simple_clock_info *info)
707{
708 return -EINVAL;
709}
710
711static int smu10_force_clock_level(struct pp_hwmgr *hwmgr,
712 enum pp_clock_type type, uint32_t mask)
713{
714 return 0;
715}
716
717static int smu10_print_clock_levels(struct pp_hwmgr *hwmgr,
718 enum pp_clock_type type, char *buf)
719{
720 struct smu10_hwmgr *data = (struct smu10_hwmgr *)(hwmgr->backend);
721 struct smu10_voltage_dependency_table *mclk_table =
722 data->clock_vol_info.vdd_dep_on_fclk;
723 int i, now, size = 0;
724
725 switch (type) {
726 case PP_SCLK:
727 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
728 now = smum_get_argument(hwmgr);
729
730 size += sprintf(buf + size, "0: %uMhz %s\n",
731 data->gfx_min_freq_limit / 100,
732 ((data->gfx_min_freq_limit / 100)
733 == now) ? "*" : "");
734 size += sprintf(buf + size, "1: %uMhz %s\n",
735 data->gfx_max_freq_limit / 100,
736 ((data->gfx_max_freq_limit / 100)
737 == now) ? "*" : "");
738 break;
739 case PP_MCLK:
740 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
741 now = smum_get_argument(hwmgr);
742
743 for (i = 0; i < mclk_table->count; i++)
744 size += sprintf(buf + size, "%d: %uMhz %s\n",
745 i,
746 mclk_table->entries[i].clk / 100,
747 ((mclk_table->entries[i].clk / 100)
748 == now) ? "*" : "");
749 break;
750 default:
751 break;
752 }
753
754 return size;
755}
756
757static int smu10_get_performance_level(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *state,
758 PHM_PerformanceLevelDesignation designation, uint32_t index,
759 PHM_PerformanceLevel *level)
760{
761 struct smu10_hwmgr *data;
762
763 if (level == NULL || hwmgr == NULL || state == NULL)
764 return -EINVAL;
765
766 data = (struct smu10_hwmgr *)(hwmgr->backend);
767
768 if (index == 0) {
769 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[0].clk;
770 level->coreClock = data->gfx_min_freq_limit;
771 } else {
772 level->memory_clock = data->clock_vol_info.vdd_dep_on_fclk->entries[
773 data->clock_vol_info.vdd_dep_on_fclk->count - 1].clk;
774 level->coreClock = data->gfx_max_freq_limit;
775 }
776
777 level->nonLocalMemoryFreq = 0;
778 level->nonLocalMemoryWidth = 0;
779
780 return 0;
781}
782
783static int smu10_get_current_shallow_sleep_clocks(struct pp_hwmgr *hwmgr,
784 const struct pp_hw_power_state *state, struct pp_clock_info *clock_info)
785{
786 const struct smu10_power_state *ps = cast_const_smu10_ps(state);
787
788 clock_info->min_eng_clk = ps->levels[0].engine_clock / (1 << (ps->levels[0].ss_divider_index));
789 clock_info->max_eng_clk = ps->levels[ps->level - 1].engine_clock / (1 << (ps->levels[ps->level - 1].ss_divider_index));
790
791 return 0;
792}
793
794#define MEM_FREQ_LOW_LATENCY 25000
795#define MEM_FREQ_HIGH_LATENCY 80000
796#define MEM_LATENCY_HIGH 245
797#define MEM_LATENCY_LOW 35
798#define MEM_LATENCY_ERR 0xFFFF
799
800
801static uint32_t smu10_get_mem_latency(struct pp_hwmgr *hwmgr,
802 uint32_t clock)
803{
804 if (clock >= MEM_FREQ_LOW_LATENCY &&
805 clock < MEM_FREQ_HIGH_LATENCY)
806 return MEM_LATENCY_HIGH;
807 else if (clock >= MEM_FREQ_HIGH_LATENCY)
808 return MEM_LATENCY_LOW;
809 else
810 return MEM_LATENCY_ERR;
811}
812
813static int smu10_get_clock_by_type_with_latency(struct pp_hwmgr *hwmgr,
814 enum amd_pp_clock_type type,
815 struct pp_clock_levels_with_latency *clocks)
816{
817 uint32_t i;
818 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
819 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
820 struct smu10_voltage_dependency_table *pclk_vol_table;
821 bool latency_required = false;
822
823 if (pinfo == NULL)
824 return -EINVAL;
825
826 switch (type) {
827 case amd_pp_mem_clock:
828 pclk_vol_table = pinfo->vdd_dep_on_mclk;
829 latency_required = true;
830 break;
831 case amd_pp_f_clock:
832 pclk_vol_table = pinfo->vdd_dep_on_fclk;
833 latency_required = true;
834 break;
835 case amd_pp_dcf_clock:
836 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
837 break;
838 case amd_pp_disp_clock:
839 pclk_vol_table = pinfo->vdd_dep_on_dispclk;
840 break;
841 case amd_pp_phy_clock:
842 pclk_vol_table = pinfo->vdd_dep_on_phyclk;
843 break;
844 case amd_pp_dpp_clock:
845 pclk_vol_table = pinfo->vdd_dep_on_dppclk;
846 default:
847 return -EINVAL;
848 }
849
850 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
851 return -EINVAL;
852
853 clocks->num_levels = 0;
854 for (i = 0; i < pclk_vol_table->count; i++) {
855 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
856 clocks->data[i].latency_in_us = latency_required ?
857 smu10_get_mem_latency(hwmgr,
858 pclk_vol_table->entries[i].clk) :
859 0;
860 clocks->num_levels++;
861 }
862
863 return 0;
864}
865
866static int smu10_get_clock_by_type_with_voltage(struct pp_hwmgr *hwmgr,
867 enum amd_pp_clock_type type,
868 struct pp_clock_levels_with_voltage *clocks)
869{
870 uint32_t i;
871 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
872 struct smu10_clock_voltage_information *pinfo = &(smu10_data->clock_vol_info);
873 struct smu10_voltage_dependency_table *pclk_vol_table = NULL;
874
875 if (pinfo == NULL)
876 return -EINVAL;
877
878 switch (type) {
879 case amd_pp_mem_clock:
880 pclk_vol_table = pinfo->vdd_dep_on_mclk;
881 break;
882 case amd_pp_f_clock:
883 pclk_vol_table = pinfo->vdd_dep_on_fclk;
884 break;
885 case amd_pp_dcf_clock:
886 pclk_vol_table = pinfo->vdd_dep_on_dcefclk;
887 break;
888 case amd_pp_soc_clock:
889 pclk_vol_table = pinfo->vdd_dep_on_socclk;
890 break;
891 default:
892 return -EINVAL;
893 }
894
895 if (pclk_vol_table == NULL || pclk_vol_table->count == 0)
896 return -EINVAL;
897
898 clocks->num_levels = 0;
899 for (i = 0; i < pclk_vol_table->count; i++) {
900 clocks->data[i].clocks_in_khz = pclk_vol_table->entries[i].clk;
901 clocks->data[i].voltage_in_mv = pclk_vol_table->entries[i].vol;
902 clocks->num_levels++;
903 }
904
905 return 0;
906}
907
908static int smu10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
909 struct pp_display_clock_request *clock_req)
910{
911 struct smu10_hwmgr *smu10_data = (struct smu10_hwmgr *)(hwmgr->backend);
912 enum amd_pp_clock_type clk_type = clock_req->clock_type;
913 uint32_t clk_freq = clock_req->clock_freq_in_khz / 1000;
914 PPSMC_Msg msg;
915
916 switch (clk_type) {
917 case amd_pp_dcf_clock:
918 if (clk_freq == smu10_data->dcf_actual_hard_min_freq)
919 return 0;
920 msg = PPSMC_MSG_SetHardMinDcefclkByFreq;
921 smu10_data->dcf_actual_hard_min_freq = clk_freq;
922 break;
923 case amd_pp_soc_clock:
924 msg = PPSMC_MSG_SetHardMinSocclkByFreq;
925 break;
926 case amd_pp_f_clock:
927 if (clk_freq == smu10_data->f_actual_hard_min_freq)
928 return 0;
929 smu10_data->f_actual_hard_min_freq = clk_freq;
930 msg = PPSMC_MSG_SetHardMinFclkByFreq;
931 break;
932 default:
933 pr_info("[DisplayClockVoltageRequest]Invalid Clock Type!");
934 return -EINVAL;
935 }
936
937 smum_send_msg_to_smc_with_parameter(hwmgr, msg, clk_freq);
938
939 return 0;
940}
941
942static int smu10_get_max_high_clocks(struct pp_hwmgr *hwmgr, struct amd_pp_simple_clock_info *clocks)
943{
944 clocks->engine_max_clock = 80000;
945 return 0;
946}
947
948static int smu10_thermal_get_temperature(struct pp_hwmgr *hwmgr)
949{
950 uint32_t reg_offset = soc15_get_register_offset(THM_HWID, 0,
951 mmTHM_TCON_CUR_TMP_BASE_IDX, mmTHM_TCON_CUR_TMP);
952 uint32_t reg_value = cgs_read_register(hwmgr->device, reg_offset);
953 int cur_temp =
954 (reg_value & THM_TCON_CUR_TMP__CUR_TEMP_MASK) >> THM_TCON_CUR_TMP__CUR_TEMP__SHIFT;
955
956 if (cur_temp & THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK)
957 cur_temp = ((cur_temp / 8) - 49) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
958 else
959 cur_temp = (cur_temp / 8) * PP_TEMPERATURE_UNITS_PER_CENTIGRADES;
960
961 return cur_temp;
962}
963
964static int smu10_read_sensor(struct pp_hwmgr *hwmgr, int idx,
965 void *value, int *size)
966{
967 uint32_t sclk, mclk;
968 int ret = 0;
969
970 switch (idx) {
971 case AMDGPU_PP_SENSOR_GFX_SCLK:
972 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetGfxclkFrequency);
973 sclk = smum_get_argument(hwmgr);
974
975 *((uint32_t *)value) = sclk * 100;
976 *size = 4;
977 break;
978 case AMDGPU_PP_SENSOR_GFX_MCLK:
979 smum_send_msg_to_smc(hwmgr, PPSMC_MSG_GetFclkFrequency);
980 mclk = smum_get_argument(hwmgr);
981
982 *((uint32_t *)value) = mclk * 100;
983 *size = 4;
984 break;
985 case AMDGPU_PP_SENSOR_GPU_TEMP:
986 *((uint32_t *)value) = smu10_thermal_get_temperature(hwmgr);
987 break;
988 default:
989 ret = -EINVAL;
990 break;
991 }
992
993 return ret;
994}
995
996static int smu10_set_mmhub_powergating_by_smu(struct pp_hwmgr *hwmgr)
997{
998 return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_PowerGateMmHub);
999}
1000
1001static const struct pp_hwmgr_func smu10_hwmgr_funcs = {
1002 .backend_init = smu10_hwmgr_backend_init,
1003 .backend_fini = smu10_hwmgr_backend_fini,
1004 .asic_setup = NULL,
1005 .apply_state_adjust_rules = smu10_apply_state_adjust_rules,
1006 .force_dpm_level = smu10_dpm_force_dpm_level,
1007 .get_power_state_size = smu10_get_power_state_size,
1008 .powerdown_uvd = NULL,
1009 .powergate_uvd = NULL,
1010 .powergate_vce = NULL,
1011 .get_mclk = smu10_dpm_get_mclk,
1012 .get_sclk = smu10_dpm_get_sclk,
1013 .patch_boot_state = smu10_dpm_patch_boot_state,
1014 .get_pp_table_entry = smu10_dpm_get_pp_table_entry,
1015 .get_num_of_pp_table_entries = smu10_dpm_get_num_of_pp_table_entries,
1016 .set_cpu_power_state = smu10_set_cpu_power_state,
1017 .store_cc6_data = smu10_store_cc6_data,
1018 .force_clock_level = smu10_force_clock_level,
1019 .print_clock_levels = smu10_print_clock_levels,
1020 .get_dal_power_level = smu10_get_dal_power_level,
1021 .get_performance_level = smu10_get_performance_level,
1022 .get_current_shallow_sleep_clocks = smu10_get_current_shallow_sleep_clocks,
1023 .get_clock_by_type_with_latency = smu10_get_clock_by_type_with_latency,
1024 .get_clock_by_type_with_voltage = smu10_get_clock_by_type_with_voltage,
1025 .get_max_high_clocks = smu10_get_max_high_clocks,
1026 .read_sensor = smu10_read_sensor,
1027 .set_active_display_count = smu10_set_active_display_count,
1028 .set_deep_sleep_dcefclk = smu10_set_deep_sleep_dcefclk,
1029 .dynamic_state_management_enable = smu10_enable_dpm_tasks,
1030 .power_off_asic = smu10_power_off_asic,
1031 .asic_setup = smu10_setup_asic_task,
1032 .power_state_set = smu10_set_power_state_tasks,
1033 .dynamic_state_management_disable = smu10_disable_dpm_tasks,
1034 .set_mmhub_powergating_by_smu = smu10_set_mmhub_powergating_by_smu,
1035};
1036
1037int smu10_init_function_pointers(struct pp_hwmgr *hwmgr)
1038{
1039 hwmgr->hwmgr_func = &smu10_hwmgr_funcs;
1040 hwmgr->pptable_func = &pptable_funcs;
1041 return 0;
1042}
1043
