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20#ifndef _PSB_DRV_H_
21#define _PSB_DRV_H_
22
23#include <linux/kref.h>
24
25#include <drm/drmP.h>
26#include <drm/drm_global.h>
27#include <drm/gma_drm.h>
28#include "psb_reg.h"
29#include "psb_intel_drv.h"
30#include "gma_display.h"
31#include "intel_bios.h"
32#include "gtt.h"
33#include "power.h"
34#include "opregion.h"
35#include "oaktrail.h"
36#include "mmu.h"
37
38#define DRIVER_AUTHOR "Alan Cox <alan@linux.intel.com> and others"
39
40#define DRIVER_NAME "gma500"
41#define DRIVER_DESC "DRM driver for the Intel GMA500, GMA600, GMA3600, GMA3650"
42#define DRIVER_DATE "20140314"
43
44#define DRIVER_MAJOR 1
45#define DRIVER_MINOR 0
46#define DRIVER_PATCHLEVEL 0
47
48
49#define DRM_MODE_SCALE_NO_SCALE 2
50
51enum {
52 CHIP_PSB_8108 = 0,
53 CHIP_PSB_8109 = 1,
54 CHIP_MRST_4100 = 2,
55 CHIP_MFLD_0130 = 3,
56};
57
58#define IS_PSB(dev) (((dev)->pdev->device & 0xfffe) == 0x8108)
59#define IS_MRST(dev) (((dev)->pdev->device & 0xfff0) == 0x4100)
60#define IS_MFLD(dev) (((dev)->pdev->device & 0xfff8) == 0x0130)
61#define IS_CDV(dev) (((dev)->pdev->device & 0xfff0) == 0x0be0)
62
63
64#define PSB_VDC_OFFSET 0x00000000
65#define PSB_VDC_SIZE 0x000080000
66#define MRST_MMIO_SIZE 0x0000C0000
67#define MDFLD_MMIO_SIZE 0x000100000
68#define PSB_SGX_SIZE 0x8000
69#define PSB_SGX_OFFSET 0x00040000
70#define MRST_SGX_OFFSET 0x00080000
71
72
73#define PSB_MMIO_RESOURCE 0
74#define PSB_AUX_RESOURCE 0
75#define PSB_GATT_RESOURCE 2
76#define PSB_GTT_RESOURCE 3
77
78
79#define PSB_GMCH_CTRL 0x52
80#define PSB_BSM 0x5C
81#define _PSB_GMCH_ENABLED 0x4
82#define PSB_PGETBL_CTL 0x2020
83#define _PSB_PGETBL_ENABLED 0x00000001
84#define PSB_SGX_2D_SLAVE_PORT 0x4000
85#define PSB_LPC_GBA 0x44
86
87
88#define PSB_TT_PRIV0_LIMIT (256*1024*1024)
89#define PSB_TT_PRIV0_PLIMIT (PSB_TT_PRIV0_LIMIT >> PAGE_SHIFT)
90
91
92
93
94#define PSB_MMU_CACHED_MEMORY 0x0001
95#define PSB_MMU_RO_MEMORY 0x0002
96#define PSB_MMU_WO_MEMORY 0x0004
97
98
99#define PSB_PDE_MASK 0x003FFFFF
100#define PSB_PDE_SHIFT 22
101#define PSB_PTE_SHIFT 12
102
103
104#define PSB_PTE_VALID 0x0001
105#define PSB_PTE_WO 0x0002
106#define PSB_PTE_RO 0x0004
107#define PSB_PTE_CACHED 0x0008
108
109
110#define PSB_MSVDX_CLOCKGATING 0x2064
111#define PSB_TOPAZ_CLOCKGATING 0x2068
112#define PSB_HWSTAM 0x2098
113#define PSB_INSTPM 0x20C0
114#define PSB_INT_IDENTITY_R 0x20A4
115#define _PSB_IRQ_ASLE (1<<0)
116#define _MDFLD_PIPEC_EVENT_FLAG (1<<2)
117#define _MDFLD_PIPEC_VBLANK_FLAG (1<<3)
118#define _PSB_DPST_PIPEB_FLAG (1<<4)
119#define _MDFLD_PIPEB_EVENT_FLAG (1<<4)
120#define _PSB_VSYNC_PIPEB_FLAG (1<<5)
121#define _PSB_DPST_PIPEA_FLAG (1<<6)
122#define _PSB_PIPEA_EVENT_FLAG (1<<6)
123#define _PSB_VSYNC_PIPEA_FLAG (1<<7)
124#define _MDFLD_MIPIA_FLAG (1<<16)
125#define _MDFLD_MIPIC_FLAG (1<<17)
126#define _PSB_IRQ_DISP_HOTSYNC (1<<17)
127#define _PSB_IRQ_SGX_FLAG (1<<18)
128#define _PSB_IRQ_MSVDX_FLAG (1<<19)
129#define _LNC_IRQ_TOPAZ_FLAG (1<<20)
130
131#define _PSB_PIPE_EVENT_FLAG (_PSB_VSYNC_PIPEA_FLAG | \
132 _PSB_VSYNC_PIPEB_FLAG)
133
134
135#define _MDFLD_DISP_ALL_IRQ_FLAG (_MDFLD_PIPEC_EVENT_FLAG | \
136 _MDFLD_PIPEB_EVENT_FLAG | \
137 _PSB_PIPEA_EVENT_FLAG | \
138 _PSB_VSYNC_PIPEA_FLAG | \
139 _MDFLD_MIPIA_FLAG | \
140 _MDFLD_MIPIC_FLAG)
141#define PSB_INT_IDENTITY_R 0x20A4
142#define PSB_INT_MASK_R 0x20A8
143#define PSB_INT_ENABLE_R 0x20A0
144
145#define _PSB_MMU_ER_MASK 0x0001FF00
146#define _PSB_MMU_ER_HOST (1 << 16)
147#define GPIOA 0x5010
148#define GPIOB 0x5014
149#define GPIOC 0x5018
150#define GPIOD 0x501c
151#define GPIOE 0x5020
152#define GPIOF 0x5024
153#define GPIOG 0x5028
154#define GPIOH 0x502c
155#define GPIO_CLOCK_DIR_MASK (1 << 0)
156#define GPIO_CLOCK_DIR_IN (0 << 1)
157#define GPIO_CLOCK_DIR_OUT (1 << 1)
158#define GPIO_CLOCK_VAL_MASK (1 << 2)
159#define GPIO_CLOCK_VAL_OUT (1 << 3)
160#define GPIO_CLOCK_VAL_IN (1 << 4)
161#define GPIO_CLOCK_PULLUP_DISABLE (1 << 5)
162#define GPIO_DATA_DIR_MASK (1 << 8)
163#define GPIO_DATA_DIR_IN (0 << 9)
164#define GPIO_DATA_DIR_OUT (1 << 9)
165#define GPIO_DATA_VAL_MASK (1 << 10)
166#define GPIO_DATA_VAL_OUT (1 << 11)
167#define GPIO_DATA_VAL_IN (1 << 12)
168#define GPIO_DATA_PULLUP_DISABLE (1 << 13)
169
170#define VCLK_DIVISOR_VGA0 0x6000
171#define VCLK_DIVISOR_VGA1 0x6004
172#define VCLK_POST_DIV 0x6010
173
174#define PSB_COMM_2D (PSB_ENGINE_2D << 4)
175#define PSB_COMM_3D (PSB_ENGINE_3D << 4)
176#define PSB_COMM_TA (PSB_ENGINE_TA << 4)
177#define PSB_COMM_HP (PSB_ENGINE_HP << 4)
178#define PSB_COMM_USER_IRQ (1024 >> 2)
179#define PSB_COMM_USER_IRQ_LOST (PSB_COMM_USER_IRQ + 1)
180#define PSB_COMM_FW (2048 >> 2)
181
182#define PSB_UIRQ_VISTEST 1
183#define PSB_UIRQ_OOM_REPLY 2
184#define PSB_UIRQ_FIRE_TA_REPLY 3
185#define PSB_UIRQ_FIRE_RASTER_REPLY 4
186
187#define PSB_2D_SIZE (256*1024*1024)
188#define PSB_MAX_RELOC_PAGES 1024
189
190#define PSB_LOW_REG_OFFS 0x0204
191#define PSB_HIGH_REG_OFFS 0x0600
192
193#define PSB_NUM_VBLANKS 2
194
195
196#define PSB_2D_SIZE (256*1024*1024)
197#define PSB_MAX_RELOC_PAGES 1024
198
199#define PSB_LOW_REG_OFFS 0x0204
200#define PSB_HIGH_REG_OFFS 0x0600
201
202#define PSB_NUM_VBLANKS 2
203#define PSB_WATCHDOG_DELAY (HZ * 2)
204#define PSB_LID_DELAY (HZ / 10)
205
206#define MDFLD_PNW_B0 0x04
207#define MDFLD_PNW_C0 0x08
208
209#define MDFLD_DSR_2D_3D_0 (1 << 0)
210#define MDFLD_DSR_2D_3D_2 (1 << 1)
211#define MDFLD_DSR_CURSOR_0 (1 << 2)
212#define MDFLD_DSR_CURSOR_2 (1 << 3)
213#define MDFLD_DSR_OVERLAY_0 (1 << 4)
214#define MDFLD_DSR_OVERLAY_2 (1 << 5)
215#define MDFLD_DSR_MIPI_CONTROL (1 << 6)
216#define MDFLD_DSR_DAMAGE_MASK_0 ((1 << 0) | (1 << 2) | (1 << 4))
217#define MDFLD_DSR_DAMAGE_MASK_2 ((1 << 1) | (1 << 3) | (1 << 5))
218#define MDFLD_DSR_2D_3D (MDFLD_DSR_2D_3D_0 | MDFLD_DSR_2D_3D_2)
219
220#define MDFLD_DSR_RR 45
221#define MDFLD_DPU_ENABLE (1 << 31)
222#define MDFLD_DSR_FULLSCREEN (1 << 30)
223#define MDFLD_DSR_DELAY (HZ / MDFLD_DSR_RR)
224
225#define PSB_PWR_STATE_ON 1
226#define PSB_PWR_STATE_OFF 2
227
228#define PSB_PMPOLICY_NOPM 0
229#define PSB_PMPOLICY_CLOCKGATING 1
230#define PSB_PMPOLICY_POWERDOWN 2
231
232#define PSB_PMSTATE_POWERUP 0
233#define PSB_PMSTATE_CLOCKGATED 1
234#define PSB_PMSTATE_POWERDOWN 2
235#define PSB_PCIx_MSI_ADDR_LOC 0x94
236#define PSB_PCIx_MSI_DATA_LOC 0x98
237
238
239#define KSEL_CRYSTAL_19 1
240#define KSEL_BYPASS_19 5
241#define KSEL_BYPASS_25 6
242#define KSEL_BYPASS_83_100 7
243
244struct opregion_header;
245struct opregion_acpi;
246struct opregion_swsci;
247struct opregion_asle;
248
249struct psb_intel_opregion {
250 struct opregion_header *header;
251 struct opregion_acpi *acpi;
252 struct opregion_swsci *swsci;
253 struct opregion_asle *asle;
254 void *vbt;
255 u32 __iomem *lid_state;
256 struct work_struct asle_work;
257};
258
259struct sdvo_device_mapping {
260 u8 initialized;
261 u8 dvo_port;
262 u8 slave_addr;
263 u8 dvo_wiring;
264 u8 i2c_pin;
265 u8 i2c_speed;
266 u8 ddc_pin;
267};
268
269struct intel_gmbus {
270 struct i2c_adapter adapter;
271 struct i2c_adapter *force_bit;
272 u32 reg0;
273};
274
275
276struct psb_offset {
277 u32 fp0;
278 u32 fp1;
279 u32 cntr;
280 u32 conf;
281 u32 src;
282 u32 dpll;
283 u32 dpll_md;
284 u32 htotal;
285 u32 hblank;
286 u32 hsync;
287 u32 vtotal;
288 u32 vblank;
289 u32 vsync;
290 u32 stride;
291 u32 size;
292 u32 pos;
293 u32 surf;
294 u32 addr;
295 u32 base;
296 u32 status;
297 u32 linoff;
298 u32 tileoff;
299 u32 palette;
300};
301
302
303
304
305
306
307
308
309
310struct psb_pipe {
311 u32 fp0;
312 u32 fp1;
313 u32 cntr;
314 u32 conf;
315 u32 src;
316 u32 dpll;
317 u32 dpll_md;
318 u32 htotal;
319 u32 hblank;
320 u32 hsync;
321 u32 vtotal;
322 u32 vblank;
323 u32 vsync;
324 u32 stride;
325 u32 size;
326 u32 pos;
327 u32 base;
328 u32 surf;
329 u32 addr;
330 u32 status;
331 u32 linoff;
332 u32 tileoff;
333 u32 palette[256];
334};
335
336struct psb_state {
337 uint32_t saveVCLK_DIVISOR_VGA0;
338 uint32_t saveVCLK_DIVISOR_VGA1;
339 uint32_t saveVCLK_POST_DIV;
340 uint32_t saveVGACNTRL;
341 uint32_t saveADPA;
342 uint32_t saveLVDS;
343 uint32_t saveDVOA;
344 uint32_t saveDVOB;
345 uint32_t saveDVOC;
346 uint32_t savePP_ON;
347 uint32_t savePP_OFF;
348 uint32_t savePP_CONTROL;
349 uint32_t savePP_CYCLE;
350 uint32_t savePFIT_CONTROL;
351 uint32_t saveCLOCKGATING;
352 uint32_t saveDSPARB;
353 uint32_t savePFIT_AUTO_RATIOS;
354 uint32_t savePFIT_PGM_RATIOS;
355 uint32_t savePP_ON_DELAYS;
356 uint32_t savePP_OFF_DELAYS;
357 uint32_t savePP_DIVISOR;
358 uint32_t saveBCLRPAT_A;
359 uint32_t saveBCLRPAT_B;
360 uint32_t savePERF_MODE;
361 uint32_t saveDSPFW1;
362 uint32_t saveDSPFW2;
363 uint32_t saveDSPFW3;
364 uint32_t saveDSPFW4;
365 uint32_t saveDSPFW5;
366 uint32_t saveDSPFW6;
367 uint32_t saveCHICKENBIT;
368 uint32_t saveDSPACURSOR_CTRL;
369 uint32_t saveDSPBCURSOR_CTRL;
370 uint32_t saveDSPACURSOR_BASE;
371 uint32_t saveDSPBCURSOR_BASE;
372 uint32_t saveDSPACURSOR_POS;
373 uint32_t saveDSPBCURSOR_POS;
374 uint32_t saveOV_OVADD;
375 uint32_t saveOV_OGAMC0;
376 uint32_t saveOV_OGAMC1;
377 uint32_t saveOV_OGAMC2;
378 uint32_t saveOV_OGAMC3;
379 uint32_t saveOV_OGAMC4;
380 uint32_t saveOV_OGAMC5;
381 uint32_t saveOVC_OVADD;
382 uint32_t saveOVC_OGAMC0;
383 uint32_t saveOVC_OGAMC1;
384 uint32_t saveOVC_OGAMC2;
385 uint32_t saveOVC_OGAMC3;
386 uint32_t saveOVC_OGAMC4;
387 uint32_t saveOVC_OGAMC5;
388
389
390 uint32_t saveHISTOGRAM_INT_CONTROL_REG;
391 uint32_t saveHISTOGRAM_LOGIC_CONTROL_REG;
392 uint32_t savePWM_CONTROL_LOGIC;
393};
394
395struct medfield_state {
396 uint32_t saveMIPI;
397 uint32_t saveMIPI_C;
398
399 uint32_t savePFIT_CONTROL;
400 uint32_t savePFIT_PGM_RATIOS;
401 uint32_t saveHDMIPHYMISCCTL;
402 uint32_t saveHDMIB_CONTROL;
403};
404
405struct cdv_state {
406 uint32_t saveDSPCLK_GATE_D;
407 uint32_t saveRAMCLK_GATE_D;
408 uint32_t saveDSPARB;
409 uint32_t saveDSPFW[6];
410 uint32_t saveADPA;
411 uint32_t savePP_CONTROL;
412 uint32_t savePFIT_PGM_RATIOS;
413 uint32_t saveLVDS;
414 uint32_t savePFIT_CONTROL;
415 uint32_t savePP_ON_DELAYS;
416 uint32_t savePP_OFF_DELAYS;
417 uint32_t savePP_CYCLE;
418 uint32_t saveVGACNTRL;
419 uint32_t saveIER;
420 uint32_t saveIMR;
421 u8 saveLBB;
422};
423
424struct psb_save_area {
425 struct psb_pipe pipe[3];
426 uint32_t saveBSM;
427 uint32_t saveVBT;
428 union {
429 struct psb_state psb;
430 struct medfield_state mdfld;
431 struct cdv_state cdv;
432 };
433 uint32_t saveBLC_PWM_CTL2;
434 uint32_t saveBLC_PWM_CTL;
435};
436
437struct psb_ops;
438
439#define PSB_NUM_PIPE 3
440
441struct drm_psb_private {
442 struct drm_device *dev;
443 struct pci_dev *aux_pdev;
444 struct pci_dev *lpc_pdev;
445 const struct psb_ops *ops;
446 const struct psb_offset *regmap;
447
448 struct child_device_config *child_dev;
449 int child_dev_num;
450
451 struct psb_gtt gtt;
452
453
454 struct psb_gtt_mm *gtt_mm;
455 struct page *scratch_page;
456 u32 __iomem *gtt_map;
457 uint32_t stolen_base;
458 u8 __iomem *vram_addr;
459 unsigned long vram_stolen_size;
460 int gtt_initialized;
461 u16 gmch_ctrl;
462 u32 pge_ctl;
463
464 struct mutex gtt_mutex;
465 struct resource *gtt_mem;
466
467 struct mutex mmap_mutex;
468
469 struct psb_mmu_driver *mmu;
470 struct psb_mmu_pd *pf_pd;
471
472
473 uint8_t __iomem *sgx_reg;
474 uint8_t __iomem *vdc_reg;
475 uint8_t __iomem *aux_reg;
476 uint16_t lpc_gpio_base;
477 uint32_t gatt_free_offset;
478
479
480 uint32_t vdc_irq_mask;
481 uint32_t pipestat[PSB_NUM_PIPE];
482
483 spinlock_t irqmask_lock;
484
485
486 bool suspended;
487 bool display_power;
488 int display_count;
489
490
491 struct psb_intel_mode_device mode_dev;
492 bool modeset;
493
494 struct drm_crtc *plane_to_crtc_mapping[PSB_NUM_PIPE];
495 struct drm_crtc *pipe_to_crtc_mapping[PSB_NUM_PIPE];
496 uint32_t num_pipe;
497
498
499 uint32_t ospm_base;
500
501
502 u32 fuse_reg_value;
503 u32 video_device_fuse;
504
505
506 uint8_t platform_rev_id;
507
508
509 struct intel_gmbus *gmbus;
510 uint8_t __iomem *gmbus_reg;
511
512
513 int crt_ddc_pin;
514
515
516 struct sdvo_device_mapping sdvo_mappings[2];
517 u32 hotplug_supported_mask;
518 struct drm_property *broadcast_rgb_property;
519 struct drm_property *force_audio_property;
520
521
522 int backlight_duty_cycle;
523 bool panel_wants_dither;
524 struct drm_display_mode *panel_fixed_mode;
525 struct drm_display_mode *lfp_lvds_vbt_mode;
526 struct drm_display_mode *sdvo_lvds_vbt_mode;
527
528 struct bdb_lvds_backlight *lvds_bl;
529 struct psb_intel_i2c_chan *lvds_i2c_bus;
530
531
532 unsigned int int_tv_support:1;
533 unsigned int lvds_dither:1;
534 unsigned int lvds_vbt:1;
535 unsigned int int_crt_support:1;
536 unsigned int lvds_use_ssc:1;
537 int lvds_ssc_freq;
538 bool is_lvds_on;
539 bool is_mipi_on;
540 u32 mipi_ctrl_display;
541
542 unsigned int core_freq;
543 uint32_t iLVDS_enable;
544
545
546 int rpm_enabled;
547
548
549 bool has_gct;
550 struct oaktrail_gct_data gct_data;
551
552
553 struct oaktrail_hdmi_dev *hdmi_priv;
554
555
556 struct psb_save_area regs;
557
558
559 uint32_t msi_addr;
560 uint32_t msi_data;
561
562
563 struct work_struct hotplug_work;
564
565
566 spinlock_t lid_lock;
567 struct timer_list lid_timer;
568 struct psb_intel_opregion opregion;
569 u32 lid_last_state;
570
571
572 uint32_t apm_reg;
573 uint16_t apm_base;
574
575
576
577
578
579 struct backlight_device *backlight_device;
580 struct drm_property *backlight_property;
581 bool backlight_enabled;
582 int backlight_level;
583 uint32_t blc_adj1;
584 uint32_t blc_adj2;
585
586 void *fbdev;
587
588
589 spinlock_t lock_2d;
590
591
592 int brightness;
593 int brightness_adjusted;
594
595 bool dsr_enable;
596 u32 dsr_fb_update;
597 bool dpi_panel_on[3];
598 void *dsi_configs[2];
599 u32 bpp;
600 u32 bpp2;
601
602 u32 pipeconf[3];
603 u32 dspcntr[3];
604
605 int mdfld_panel_id;
606
607 bool dplla_96mhz;
608
609 struct {
610 int rate;
611 int lanes;
612 int preemphasis;
613 int vswing;
614
615 bool initialized;
616 bool support;
617 int bpp;
618 struct edp_power_seq pps;
619 } edp;
620 uint8_t panel_type;
621};
622
623
624
625struct psb_ops {
626 const char *name;
627 unsigned int accel_2d:1;
628 int pipes;
629 int crtcs;
630 int sgx_offset;
631 int hdmi_mask;
632 int lvds_mask;
633 int sdvo_mask;
634 int cursor_needs_phys;
635
636
637 struct drm_crtc_helper_funcs const *crtc_helper;
638 struct drm_crtc_funcs const *crtc_funcs;
639 const struct gma_clock_funcs *clock_funcs;
640
641
642 int (*chip_setup)(struct drm_device *dev);
643 void (*chip_teardown)(struct drm_device *dev);
644
645 void (*errata)(struct drm_device *dev);
646
647
648 int (*output_init)(struct drm_device *dev);
649 int (*hotplug)(struct drm_device *dev);
650 void (*hotplug_enable)(struct drm_device *dev, bool on);
651
652 void (*init_pm)(struct drm_device *dev);
653 int (*save_regs)(struct drm_device *dev);
654 int (*restore_regs)(struct drm_device *dev);
655 void (*save_crtc)(struct drm_crtc *crtc);
656 void (*restore_crtc)(struct drm_crtc *crtc);
657 int (*power_up)(struct drm_device *dev);
658 int (*power_down)(struct drm_device *dev);
659 void (*update_wm)(struct drm_device *dev, struct drm_crtc *crtc);
660 void (*disable_sr)(struct drm_device *dev);
661
662 void (*lvds_bl_power)(struct drm_device *dev, bool on);
663#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
664
665 int (*backlight_init)(struct drm_device *dev);
666#endif
667 int i2c_bus;
668};
669
670
671
672extern int drm_crtc_probe_output_modes(struct drm_device *dev, int, int);
673extern int drm_pick_crtcs(struct drm_device *dev);
674
675static inline struct drm_psb_private *psb_priv(struct drm_device *dev)
676{
677 return (struct drm_psb_private *) dev->dev_private;
678}
679
680
681extern irqreturn_t psb_irq_handler(int irq, void *arg);
682extern int psb_irq_enable_dpst(struct drm_device *dev);
683extern int psb_irq_disable_dpst(struct drm_device *dev);
684extern void psb_irq_preinstall(struct drm_device *dev);
685extern int psb_irq_postinstall(struct drm_device *dev);
686extern void psb_irq_uninstall(struct drm_device *dev);
687extern void psb_irq_turn_on_dpst(struct drm_device *dev);
688extern void psb_irq_turn_off_dpst(struct drm_device *dev);
689
690extern void psb_irq_uninstall_islands(struct drm_device *dev, int hw_islands);
691extern int psb_vblank_wait2(struct drm_device *dev, unsigned int *sequence);
692extern int psb_vblank_wait(struct drm_device *dev, unsigned int *sequence);
693extern int psb_enable_vblank(struct drm_device *dev, unsigned int pipe);
694extern void psb_disable_vblank(struct drm_device *dev, unsigned int pipe);
695void
696psb_enable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
697
698void
699psb_disable_pipestat(struct drm_psb_private *dev_priv, int pipe, u32 mask);
700
701extern u32 psb_get_vblank_counter(struct drm_device *dev, unsigned int pipe);
702
703
704extern int psbfb_probed(struct drm_device *dev);
705extern int psbfb_remove(struct drm_device *dev,
706 struct drm_framebuffer *fb);
707
708extern void psbfb_copyarea(struct fb_info *info,
709 const struct fb_copyarea *region);
710extern int psbfb_sync(struct fb_info *info);
711extern void psb_spank(struct drm_psb_private *dev_priv);
712
713
714extern void psb_lid_timer_init(struct drm_psb_private *dev_priv);
715extern void psb_lid_timer_takedown(struct drm_psb_private *dev_priv);
716extern void psb_print_pagefault(struct drm_psb_private *dev_priv);
717
718
719extern void psb_modeset_init(struct drm_device *dev);
720extern void psb_modeset_cleanup(struct drm_device *dev);
721extern int psb_fbdev_init(struct drm_device *dev);
722
723
724int gma_backlight_init(struct drm_device *dev);
725void gma_backlight_exit(struct drm_device *dev);
726void gma_backlight_disable(struct drm_device *dev);
727void gma_backlight_enable(struct drm_device *dev);
728void gma_backlight_set(struct drm_device *dev, int v);
729
730
731extern const struct drm_crtc_helper_funcs oaktrail_helper_funcs;
732
733
734extern void oaktrail_lvds_init(struct drm_device *dev,
735 struct psb_intel_mode_device *mode_dev);
736
737
738extern const struct drm_crtc_helper_funcs psb_intel_helper_funcs;
739extern const struct drm_crtc_funcs psb_intel_crtc_funcs;
740
741
742extern const struct drm_connector_helper_funcs
743 psb_intel_lvds_connector_helper_funcs;
744extern const struct drm_connector_funcs psb_intel_lvds_connector_funcs;
745
746
747extern void psb_gem_free_object(struct drm_gem_object *obj);
748extern int psb_gem_get_aperture(struct drm_device *dev, void *data,
749 struct drm_file *file);
750extern int psb_gem_dumb_create(struct drm_file *file, struct drm_device *dev,
751 struct drm_mode_create_dumb *args);
752extern int psb_gem_fault(struct vm_fault *vmf);
753
754
755extern const struct psb_ops psb_chip_ops;
756
757
758extern const struct psb_ops oaktrail_chip_ops;
759
760
761extern const struct psb_ops mdfld_chip_ops;
762
763
764extern const struct psb_ops cdv_chip_ops;
765
766
767#define PSB_D_GENERAL (1 << 0)
768#define PSB_D_INIT (1 << 1)
769#define PSB_D_IRQ (1 << 2)
770#define PSB_D_ENTRY (1 << 3)
771
772#define PSB_D_HV (1 << 4)
773#define PSB_D_DBI_BF (1 << 5)
774#define PSB_D_PM (1 << 6)
775#define PSB_D_RENDER (1 << 7)
776#define PSB_D_REG (1 << 8)
777#define PSB_D_MSVDX (1 << 9)
778#define PSB_D_TOPAZ (1 << 10)
779
780extern int drm_idle_check_interval;
781
782
783static inline u32 MRST_MSG_READ32(int domain, uint port, uint offset)
784{
785 int mcr = (0xD0<<24) | (port << 16) | (offset << 8);
786 uint32_t ret_val = 0;
787 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
788 pci_write_config_dword(pci_root, 0xD0, mcr);
789 pci_read_config_dword(pci_root, 0xD4, &ret_val);
790 pci_dev_put(pci_root);
791 return ret_val;
792}
793static inline void MRST_MSG_WRITE32(int domain, uint port, uint offset,
794 u32 value)
795{
796 int mcr = (0xE0<<24) | (port << 16) | (offset << 8) | 0xF0;
797 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
798 pci_write_config_dword(pci_root, 0xD4, value);
799 pci_write_config_dword(pci_root, 0xD0, mcr);
800 pci_dev_put(pci_root);
801}
802static inline u32 MDFLD_MSG_READ32(int domain, uint port, uint offset)
803{
804 int mcr = (0x10<<24) | (port << 16) | (offset << 8);
805 uint32_t ret_val = 0;
806 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
807 pci_write_config_dword(pci_root, 0xD0, mcr);
808 pci_read_config_dword(pci_root, 0xD4, &ret_val);
809 pci_dev_put(pci_root);
810 return ret_val;
811}
812static inline void MDFLD_MSG_WRITE32(int domain, uint port, uint offset,
813 u32 value)
814{
815 int mcr = (0x11<<24) | (port << 16) | (offset << 8) | 0xF0;
816 struct pci_dev *pci_root = pci_get_domain_bus_and_slot(domain, 0, 0);
817 pci_write_config_dword(pci_root, 0xD4, value);
818 pci_write_config_dword(pci_root, 0xD0, mcr);
819 pci_dev_put(pci_root);
820}
821
822static inline uint32_t REGISTER_READ(struct drm_device *dev, uint32_t reg)
823{
824 struct drm_psb_private *dev_priv = dev->dev_private;
825 return ioread32(dev_priv->vdc_reg + reg);
826}
827
828static inline uint32_t REGISTER_READ_AUX(struct drm_device *dev, uint32_t reg)
829{
830 struct drm_psb_private *dev_priv = dev->dev_private;
831 return ioread32(dev_priv->aux_reg + reg);
832}
833
834#define REG_READ(reg) REGISTER_READ(dev, (reg))
835#define REG_READ_AUX(reg) REGISTER_READ_AUX(dev, (reg))
836
837
838static inline uint32_t REGISTER_READ_WITH_AUX(struct drm_device *dev,
839 uint32_t reg, int aux)
840{
841 uint32_t val;
842
843 if (aux)
844 val = REG_READ_AUX(reg);
845 else
846 val = REG_READ(reg);
847
848 return val;
849}
850
851#define REG_READ_WITH_AUX(reg, aux) REGISTER_READ_WITH_AUX(dev, (reg), (aux))
852
853static inline void REGISTER_WRITE(struct drm_device *dev, uint32_t reg,
854 uint32_t val)
855{
856 struct drm_psb_private *dev_priv = dev->dev_private;
857 iowrite32((val), dev_priv->vdc_reg + (reg));
858}
859
860static inline void REGISTER_WRITE_AUX(struct drm_device *dev, uint32_t reg,
861 uint32_t val)
862{
863 struct drm_psb_private *dev_priv = dev->dev_private;
864 iowrite32((val), dev_priv->aux_reg + (reg));
865}
866
867#define REG_WRITE(reg, val) REGISTER_WRITE(dev, (reg), (val))
868#define REG_WRITE_AUX(reg, val) REGISTER_WRITE_AUX(dev, (reg), (val))
869
870static inline void REGISTER_WRITE_WITH_AUX(struct drm_device *dev, uint32_t reg,
871 uint32_t val, int aux)
872{
873 if (aux)
874 REG_WRITE_AUX(reg, val);
875 else
876 REG_WRITE(reg, val);
877}
878
879#define REG_WRITE_WITH_AUX(reg, val, aux) REGISTER_WRITE_WITH_AUX(dev, (reg), (val), (aux))
880
881static inline void REGISTER_WRITE16(struct drm_device *dev,
882 uint32_t reg, uint32_t val)
883{
884 struct drm_psb_private *dev_priv = dev->dev_private;
885 iowrite16((val), dev_priv->vdc_reg + (reg));
886}
887
888#define REG_WRITE16(reg, val) REGISTER_WRITE16(dev, (reg), (val))
889
890static inline void REGISTER_WRITE8(struct drm_device *dev,
891 uint32_t reg, uint32_t val)
892{
893 struct drm_psb_private *dev_priv = dev->dev_private;
894 iowrite8((val), dev_priv->vdc_reg + (reg));
895}
896
897#define REG_WRITE8(reg, val) REGISTER_WRITE8(dev, (reg), (val))
898
899#define PSB_WVDC32(_val, _offs) iowrite32(_val, dev_priv->vdc_reg + (_offs))
900#define PSB_RVDC32(_offs) ioread32(dev_priv->vdc_reg + (_offs))
901
902
903#ifdef TRAP_SGX_PM_FAULT
904#define PSB_RSGX32(_offs) \
905({ \
906 if (inl(dev_priv->apm_base + PSB_APM_STS) & 0x3) { \
907 pr_err("access sgx when it's off!! (READ) %s, %d\n", \
908 __FILE__, __LINE__); \
909 melay(1000); \
910 } \
911 ioread32(dev_priv->sgx_reg + (_offs)); \
912})
913#else
914#define PSB_RSGX32(_offs) ioread32(dev_priv->sgx_reg + (_offs))
915#endif
916#define PSB_WSGX32(_val, _offs) iowrite32(_val, dev_priv->sgx_reg + (_offs))
917
918#define MSVDX_REG_DUMP 0
919
920#define PSB_WMSVDX32(_val, _offs) iowrite32(_val, dev_priv->msvdx_reg + (_offs))
921#define PSB_RMSVDX32(_offs) ioread32(dev_priv->msvdx_reg + (_offs))
922
923#endif
924
