1
2#ifndef __NVIF_CLASS_H__
3#define __NVIF_CLASS_H__
4
5
6#define NVIF_CLASS_CLIENT -0x00000000
7
8#define NVIF_CLASS_CONTROL -0x00000001
9
10#define NVIF_CLASS_PERFMON -0x00000002
11#define NVIF_CLASS_PERFDOM -0x00000003
12
13#define NVIF_CLASS_SW_NV04 -0x00000004
14#define NVIF_CLASS_SW_NV10 -0x00000005
15#define NVIF_CLASS_SW_NV50 -0x00000006
16#define NVIF_CLASS_SW_GF100 -0x00000007
17
18#define NVIF_CLASS_MMU 0x80000008
19#define NVIF_CLASS_MMU_NV04 0x80000009
20#define NVIF_CLASS_MMU_NV50 0x80005009
21#define NVIF_CLASS_MMU_GF100 0x80009009
22
23#define NVIF_CLASS_MEM 0x8000000a
24#define NVIF_CLASS_MEM_NV04 0x8000000b
25#define NVIF_CLASS_MEM_NV50 0x8000500b
26#define NVIF_CLASS_MEM_GF100 0x8000900b
27
28#define NVIF_CLASS_VMM 0x8000000c
29#define NVIF_CLASS_VMM_NV04 0x8000000d
30#define NVIF_CLASS_VMM_NV50 0x8000500d
31#define NVIF_CLASS_VMM_GF100 0x8000900d
32#define NVIF_CLASS_VMM_GM200 0x8000b00d
33#define NVIF_CLASS_VMM_GP100 0x8000c00d
34
35
36#define NV_NULL_CLASS 0x00000030
37
38#define NV_DEVICE 0x00000080
39
40#define NV_DMA_FROM_MEMORY 0x00000002
41#define NV_DMA_TO_MEMORY 0x00000003
42#define NV_DMA_IN_MEMORY 0x0000003d
43
44#define NV50_TWOD 0x0000502d
45#define FERMI_TWOD_A 0x0000902d
46
47#define NV50_MEMORY_TO_MEMORY_FORMAT 0x00005039
48#define FERMI_MEMORY_TO_MEMORY_FORMAT_A 0x00009039
49
50#define KEPLER_INLINE_TO_MEMORY_A 0x0000a040
51#define KEPLER_INLINE_TO_MEMORY_B 0x0000a140
52
53#define NV04_DISP 0x00000046
54
55#define NV03_CHANNEL_DMA 0x0000006b
56#define NV10_CHANNEL_DMA 0x0000006e
57#define NV17_CHANNEL_DMA 0x0000176e
58#define NV40_CHANNEL_DMA 0x0000406e
59#define NV50_CHANNEL_DMA 0x0000506e
60#define G82_CHANNEL_DMA 0x0000826e
61
62#define NV50_CHANNEL_GPFIFO 0x0000506f
63#define G82_CHANNEL_GPFIFO 0x0000826f
64#define FERMI_CHANNEL_GPFIFO 0x0000906f
65#define KEPLER_CHANNEL_GPFIFO_A 0x0000a06f
66#define KEPLER_CHANNEL_GPFIFO_B 0x0000a16f
67#define MAXWELL_CHANNEL_GPFIFO_A 0x0000b06f
68#define PASCAL_CHANNEL_GPFIFO_A 0x0000c06f
69
70#define NV50_DISP 0x00005070
71#define G82_DISP 0x00008270
72#define GT200_DISP 0x00008370
73#define GT214_DISP 0x00008570
74#define GT206_DISP 0x00008870
75#define GF110_DISP 0x00009070
76#define GK104_DISP 0x00009170
77#define GK110_DISP 0x00009270
78#define GM107_DISP 0x00009470
79#define GM200_DISP 0x00009570
80#define GP100_DISP 0x00009770
81#define GP102_DISP 0x00009870
82
83#define NV31_MPEG 0x00003174
84#define G82_MPEG 0x00008274
85
86#define NV74_VP2 0x00007476
87
88#define NV50_DISP_CURSOR 0x0000507a
89#define G82_DISP_CURSOR 0x0000827a
90#define GT214_DISP_CURSOR 0x0000857a
91#define GF110_DISP_CURSOR 0x0000907a
92#define GK104_DISP_CURSOR 0x0000917a
93
94#define NV50_DISP_OVERLAY 0x0000507b
95#define G82_DISP_OVERLAY 0x0000827b
96#define GT214_DISP_OVERLAY 0x0000857b
97#define GF110_DISP_OVERLAY 0x0000907b
98#define GK104_DISP_OVERLAY 0x0000917b
99
100#define NV50_DISP_BASE_CHANNEL_DMA 0x0000507c
101#define G82_DISP_BASE_CHANNEL_DMA 0x0000827c
102#define GT200_DISP_BASE_CHANNEL_DMA 0x0000837c
103#define GT214_DISP_BASE_CHANNEL_DMA 0x0000857c
104#define GF110_DISP_BASE_CHANNEL_DMA 0x0000907c
105#define GK104_DISP_BASE_CHANNEL_DMA 0x0000917c
106#define GK110_DISP_BASE_CHANNEL_DMA 0x0000927c
107
108#define NV50_DISP_CORE_CHANNEL_DMA 0x0000507d
109#define G82_DISP_CORE_CHANNEL_DMA 0x0000827d
110#define GT200_DISP_CORE_CHANNEL_DMA 0x0000837d
111#define GT214_DISP_CORE_CHANNEL_DMA 0x0000857d
112#define GT206_DISP_CORE_CHANNEL_DMA 0x0000887d
113#define GF110_DISP_CORE_CHANNEL_DMA 0x0000907d
114#define GK104_DISP_CORE_CHANNEL_DMA 0x0000917d
115#define GK110_DISP_CORE_CHANNEL_DMA 0x0000927d
116#define GM107_DISP_CORE_CHANNEL_DMA 0x0000947d
117#define GM200_DISP_CORE_CHANNEL_DMA 0x0000957d
118#define GP100_DISP_CORE_CHANNEL_DMA 0x0000977d
119#define GP102_DISP_CORE_CHANNEL_DMA 0x0000987d
120
121#define NV50_DISP_OVERLAY_CHANNEL_DMA 0x0000507e
122#define G82_DISP_OVERLAY_CHANNEL_DMA 0x0000827e
123#define GT200_DISP_OVERLAY_CHANNEL_DMA 0x0000837e
124#define GT214_DISP_OVERLAY_CHANNEL_DMA 0x0000857e
125#define GF110_DISP_OVERLAY_CONTROL_DMA 0x0000907e
126#define GK104_DISP_OVERLAY_CONTROL_DMA 0x0000917e
127
128#define NV50_TESLA 0x00005097
129#define G82_TESLA 0x00008297
130#define GT200_TESLA 0x00008397
131#define GT214_TESLA 0x00008597
132#define GT21A_TESLA 0x00008697
133
134#define FERMI_A 0x00009097
135#define FERMI_B 0x00009197
136#define FERMI_C 0x00009297
137
138#define KEPLER_A 0x0000a097
139#define KEPLER_B 0x0000a197
140#define KEPLER_C 0x0000a297
141
142#define MAXWELL_A 0x0000b097
143#define MAXWELL_B 0x0000b197
144
145#define PASCAL_A 0x0000c097
146#define PASCAL_B 0x0000c197
147
148#define NV74_BSP 0x000074b0
149
150#define GT212_MSVLD 0x000085b1
151#define IGT21A_MSVLD 0x000086b1
152#define G98_MSVLD 0x000088b1
153#define GF100_MSVLD 0x000090b1
154#define GK104_MSVLD 0x000095b1
155
156#define GT212_MSPDEC 0x000085b2
157#define G98_MSPDEC 0x000088b2
158#define GF100_MSPDEC 0x000090b2
159#define GK104_MSPDEC 0x000095b2
160
161#define GT212_MSPPP 0x000085b3
162#define G98_MSPPP 0x000088b3
163#define GF100_MSPPP 0x000090b3
164
165#define G98_SEC 0x000088b4
166
167#define GT212_DMA 0x000085b5
168#define FERMI_DMA 0x000090b5
169#define KEPLER_DMA_COPY_A 0x0000a0b5
170#define MAXWELL_DMA_COPY_A 0x0000b0b5
171#define PASCAL_DMA_COPY_A 0x0000c0b5
172#define PASCAL_DMA_COPY_B 0x0000c1b5
173
174#define FERMI_DECOMPRESS 0x000090b8
175
176#define NV50_COMPUTE 0x000050c0
177#define GT214_COMPUTE 0x000085c0
178#define FERMI_COMPUTE_A 0x000090c0
179#define FERMI_COMPUTE_B 0x000091c0
180#define KEPLER_COMPUTE_A 0x0000a0c0
181#define KEPLER_COMPUTE_B 0x0000a1c0
182#define MAXWELL_COMPUTE_A 0x0000b0c0
183#define MAXWELL_COMPUTE_B 0x0000b1c0
184#define PASCAL_COMPUTE_A 0x0000c0c0
185#define PASCAL_COMPUTE_B 0x0000c1c0
186
187#define NV74_CIPHER 0x000074c1
188#endif
189
