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28#include <linux/console.h>
29#include <linux/slab.h>
30#include <drm/drmP.h>
31#include <drm/drm_crtc_helper.h>
32#include <drm/drm_cache.h>
33#include <drm/radeon_drm.h>
34#include <linux/pm_runtime.h>
35#include <linux/vgaarb.h>
36#include <linux/vga_switcheroo.h>
37#include <linux/efi.h>
38#include "radeon_reg.h"
39#include "radeon.h"
40#include "atom.h"
41
42static const char radeon_family_name[][16] = {
43 "R100",
44 "RV100",
45 "RS100",
46 "RV200",
47 "RS200",
48 "R200",
49 "RV250",
50 "RS300",
51 "RV280",
52 "R300",
53 "R350",
54 "RV350",
55 "RV380",
56 "R420",
57 "R423",
58 "RV410",
59 "RS400",
60 "RS480",
61 "RS600",
62 "RS690",
63 "RS740",
64 "RV515",
65 "R520",
66 "RV530",
67 "RV560",
68 "RV570",
69 "R580",
70 "R600",
71 "RV610",
72 "RV630",
73 "RV670",
74 "RV620",
75 "RV635",
76 "RS780",
77 "RS880",
78 "RV770",
79 "RV730",
80 "RV710",
81 "RV740",
82 "CEDAR",
83 "REDWOOD",
84 "JUNIPER",
85 "CYPRESS",
86 "HEMLOCK",
87 "PALM",
88 "SUMO",
89 "SUMO2",
90 "BARTS",
91 "TURKS",
92 "CAICOS",
93 "CAYMAN",
94 "ARUBA",
95 "TAHITI",
96 "PITCAIRN",
97 "VERDE",
98 "OLAND",
99 "HAINAN",
100 "BONAIRE",
101 "KAVERI",
102 "KABINI",
103 "HAWAII",
104 "MULLINS",
105 "LAST",
106};
107
108#if defined(CONFIG_VGA_SWITCHEROO)
109bool radeon_has_atpx_dgpu_power_cntl(void);
110bool radeon_is_atpx_hybrid(void);
111#else
112static inline bool radeon_has_atpx_dgpu_power_cntl(void) { return false; }
113static inline bool radeon_is_atpx_hybrid(void) { return false; }
114#endif
115
116#define RADEON_PX_QUIRK_DISABLE_PX (1 << 0)
117
118struct radeon_px_quirk {
119 u32 chip_vendor;
120 u32 chip_device;
121 u32 subsys_vendor;
122 u32 subsys_device;
123 u32 px_quirk_flags;
124};
125
126static struct radeon_px_quirk radeon_px_quirk_list[] = {
127
128
129
130 { PCI_VENDOR_ID_ATI, 0x6760, 0x1025, 0x0672, RADEON_PX_QUIRK_DISABLE_PX },
131
132
133
134 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x108c, RADEON_PX_QUIRK_DISABLE_PX },
135
136
137
138 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
139
140
141
142 { PCI_VENDOR_ID_ATI, 0x6741, 0x1043, 0x2122, RADEON_PX_QUIRK_DISABLE_PX },
143
144
145
146 { PCI_VENDOR_ID_ATI, 0x6840, 0x1043, 0x2123, RADEON_PX_QUIRK_DISABLE_PX },
147 { 0, 0, 0, 0, 0 },
148};
149
150bool radeon_is_px(struct drm_device *dev)
151{
152 struct radeon_device *rdev = dev->dev_private;
153
154 if (rdev->flags & RADEON_IS_PX)
155 return true;
156 return false;
157}
158
159static void radeon_device_handle_px_quirks(struct radeon_device *rdev)
160{
161 struct radeon_px_quirk *p = radeon_px_quirk_list;
162
163
164 while (p && p->chip_device != 0) {
165 if (rdev->pdev->vendor == p->chip_vendor &&
166 rdev->pdev->device == p->chip_device &&
167 rdev->pdev->subsystem_vendor == p->subsys_vendor &&
168 rdev->pdev->subsystem_device == p->subsys_device) {
169 rdev->px_quirk_flags = p->px_quirk_flags;
170 break;
171 }
172 ++p;
173 }
174
175 if (rdev->px_quirk_flags & RADEON_PX_QUIRK_DISABLE_PX)
176 rdev->flags &= ~RADEON_IS_PX;
177
178
179 if (!radeon_is_atpx_hybrid() &&
180 !radeon_has_atpx_dgpu_power_cntl())
181 rdev->flags &= ~RADEON_IS_PX;
182}
183
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188
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191
192
193
194void radeon_program_register_sequence(struct radeon_device *rdev,
195 const u32 *registers,
196 const u32 array_size)
197{
198 u32 tmp, reg, and_mask, or_mask;
199 int i;
200
201 if (array_size % 3)
202 return;
203
204 for (i = 0; i < array_size; i +=3) {
205 reg = registers[i + 0];
206 and_mask = registers[i + 1];
207 or_mask = registers[i + 2];
208
209 if (and_mask == 0xffffffff) {
210 tmp = or_mask;
211 } else {
212 tmp = RREG32(reg);
213 tmp &= ~and_mask;
214 tmp |= or_mask;
215 }
216 WREG32(reg, tmp);
217 }
218}
219
220void radeon_pci_config_reset(struct radeon_device *rdev)
221{
222 pci_write_config_dword(rdev->pdev, 0x7c, RADEON_ASIC_RESET_DATA);
223}
224
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228
229
230
231
232void radeon_surface_init(struct radeon_device *rdev)
233{
234
235 if (rdev->family < CHIP_R600) {
236 int i;
237
238 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
239 if (rdev->surface_regs[i].bo)
240 radeon_bo_get_surface_reg(rdev->surface_regs[i].bo);
241 else
242 radeon_clear_surface_reg(rdev, i);
243 }
244
245 WREG32(RADEON_SURFACE_CNTL, 0);
246 }
247}
248
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256
257
258
259void radeon_scratch_init(struct radeon_device *rdev)
260{
261 int i;
262
263
264 if (rdev->family < CHIP_R300) {
265 rdev->scratch.num_reg = 5;
266 } else {
267 rdev->scratch.num_reg = 7;
268 }
269 rdev->scratch.reg_base = RADEON_SCRATCH_REG0;
270 for (i = 0; i < rdev->scratch.num_reg; i++) {
271 rdev->scratch.free[i] = true;
272 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4);
273 }
274}
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284
285int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg)
286{
287 int i;
288
289 for (i = 0; i < rdev->scratch.num_reg; i++) {
290 if (rdev->scratch.free[i]) {
291 rdev->scratch.free[i] = false;
292 *reg = rdev->scratch.reg[i];
293 return 0;
294 }
295 }
296 return -EINVAL;
297}
298
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305
306
307void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg)
308{
309 int i;
310
311 for (i = 0; i < rdev->scratch.num_reg; i++) {
312 if (rdev->scratch.reg[i] == reg) {
313 rdev->scratch.free[i] = true;
314 return;
315 }
316 }
317}
318
319
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327
328
329
330static int radeon_doorbell_init(struct radeon_device *rdev)
331{
332
333 rdev->doorbell.base = pci_resource_start(rdev->pdev, 2);
334 rdev->doorbell.size = pci_resource_len(rdev->pdev, 2);
335
336 rdev->doorbell.num_doorbells = min_t(u32, rdev->doorbell.size / sizeof(u32), RADEON_MAX_DOORBELLS);
337 if (rdev->doorbell.num_doorbells == 0)
338 return -EINVAL;
339
340 rdev->doorbell.ptr = ioremap(rdev->doorbell.base, rdev->doorbell.num_doorbells * sizeof(u32));
341 if (rdev->doorbell.ptr == NULL) {
342 return -ENOMEM;
343 }
344 DRM_INFO("doorbell mmio base: 0x%08X\n", (uint32_t)rdev->doorbell.base);
345 DRM_INFO("doorbell mmio size: %u\n", (unsigned)rdev->doorbell.size);
346
347 memset(&rdev->doorbell.used, 0, sizeof(rdev->doorbell.used));
348
349 return 0;
350}
351
352
353
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357
358
359static void radeon_doorbell_fini(struct radeon_device *rdev)
360{
361 iounmap(rdev->doorbell.ptr);
362 rdev->doorbell.ptr = NULL;
363}
364
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373
374int radeon_doorbell_get(struct radeon_device *rdev, u32 *doorbell)
375{
376 unsigned long offset = find_first_zero_bit(rdev->doorbell.used, rdev->doorbell.num_doorbells);
377 if (offset < rdev->doorbell.num_doorbells) {
378 __set_bit(offset, rdev->doorbell.used);
379 *doorbell = offset;
380 return 0;
381 } else {
382 return -EINVAL;
383 }
384}
385
386
387
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389
390
391
392
393
394void radeon_doorbell_free(struct radeon_device *rdev, u32 doorbell)
395{
396 if (doorbell < rdev->doorbell.num_doorbells)
397 __clear_bit(doorbell, rdev->doorbell.used);
398}
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413
414void radeon_wb_disable(struct radeon_device *rdev)
415{
416 rdev->wb.enabled = false;
417}
418
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422
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424
425
426
427void radeon_wb_fini(struct radeon_device *rdev)
428{
429 radeon_wb_disable(rdev);
430 if (rdev->wb.wb_obj) {
431 if (!radeon_bo_reserve(rdev->wb.wb_obj, false)) {
432 radeon_bo_kunmap(rdev->wb.wb_obj);
433 radeon_bo_unpin(rdev->wb.wb_obj);
434 radeon_bo_unreserve(rdev->wb.wb_obj);
435 }
436 radeon_bo_unref(&rdev->wb.wb_obj);
437 rdev->wb.wb = NULL;
438 rdev->wb.wb_obj = NULL;
439 }
440}
441
442
443
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446
447
448
449
450
451int radeon_wb_init(struct radeon_device *rdev)
452{
453 int r;
454
455 if (rdev->wb.wb_obj == NULL) {
456 r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true,
457 RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
458 &rdev->wb.wb_obj);
459 if (r) {
460 dev_warn(rdev->dev, "(%d) create WB bo failed\n", r);
461 return r;
462 }
463 r = radeon_bo_reserve(rdev->wb.wb_obj, false);
464 if (unlikely(r != 0)) {
465 radeon_wb_fini(rdev);
466 return r;
467 }
468 r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT,
469 &rdev->wb.gpu_addr);
470 if (r) {
471 radeon_bo_unreserve(rdev->wb.wb_obj);
472 dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r);
473 radeon_wb_fini(rdev);
474 return r;
475 }
476 r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb);
477 radeon_bo_unreserve(rdev->wb.wb_obj);
478 if (r) {
479 dev_warn(rdev->dev, "(%d) map WB bo failed\n", r);
480 radeon_wb_fini(rdev);
481 return r;
482 }
483 }
484
485
486 memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE);
487
488 rdev->wb.use_event = false;
489
490 if (radeon_no_wb == 1) {
491 rdev->wb.enabled = false;
492 } else {
493 if (rdev->flags & RADEON_IS_AGP) {
494
495 rdev->wb.enabled = false;
496 } else if (rdev->family < CHIP_R300) {
497
498 rdev->wb.enabled = false;
499 } else {
500 rdev->wb.enabled = true;
501
502 if (rdev->family >= CHIP_R600) {
503 rdev->wb.use_event = true;
504 }
505 }
506 }
507
508 if (rdev->family >= CHIP_PALM) {
509 rdev->wb.enabled = true;
510 rdev->wb.use_event = true;
511 }
512
513 dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis");
514
515 return 0;
516}
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559void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base)
560{
561 uint64_t limit = (uint64_t)radeon_vram_limit << 20;
562
563 mc->vram_start = base;
564 if (mc->mc_vram_size > (rdev->mc.mc_mask - base + 1)) {
565 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
566 mc->real_vram_size = mc->aper_size;
567 mc->mc_vram_size = mc->aper_size;
568 }
569 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
570 if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) {
571 dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n");
572 mc->real_vram_size = mc->aper_size;
573 mc->mc_vram_size = mc->aper_size;
574 }
575 mc->vram_end = mc->vram_start + mc->mc_vram_size - 1;
576 if (limit && limit < mc->real_vram_size)
577 mc->real_vram_size = limit;
578 dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n",
579 mc->mc_vram_size >> 20, mc->vram_start,
580 mc->vram_end, mc->real_vram_size >> 20);
581}
582
583
584
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592
593
594
595void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc)
596{
597 u64 size_af, size_bf;
598
599 size_af = ((rdev->mc.mc_mask - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align;
600 size_bf = mc->vram_start & ~mc->gtt_base_align;
601 if (size_bf > size_af) {
602 if (mc->gtt_size > size_bf) {
603 dev_warn(rdev->dev, "limiting GTT\n");
604 mc->gtt_size = size_bf;
605 }
606 mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size;
607 } else {
608 if (mc->gtt_size > size_af) {
609 dev_warn(rdev->dev, "limiting GTT\n");
610 mc->gtt_size = size_af;
611 }
612 mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align;
613 }
614 mc->gtt_end = mc->gtt_start + mc->gtt_size - 1;
615 dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n",
616 mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end);
617}
618
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628
629
630bool radeon_device_is_virtual(void)
631{
632#ifdef CONFIG_X86
633 return boot_cpu_has(X86_FEATURE_HYPERVISOR);
634#else
635 return false;
636#endif
637}
638
639
640
641
642
643
644
645
646
647
648bool radeon_card_posted(struct radeon_device *rdev)
649{
650 uint32_t reg;
651
652
653 if (rdev->family >= CHIP_BONAIRE &&
654 radeon_device_is_virtual())
655 return false;
656
657
658 if (efi_enabled(EFI_BOOT) &&
659 (rdev->pdev->subsystem_vendor == PCI_VENDOR_ID_APPLE) &&
660 (rdev->family < CHIP_R600))
661 return false;
662
663 if (ASIC_IS_NODCE(rdev))
664 goto check_memsize;
665
666
667 if (ASIC_IS_DCE4(rdev)) {
668 reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) |
669 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET);
670 if (rdev->num_crtc >= 4) {
671 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) |
672 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET);
673 }
674 if (rdev->num_crtc >= 6) {
675 reg |= RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) |
676 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET);
677 }
678 if (reg & EVERGREEN_CRTC_MASTER_EN)
679 return true;
680 } else if (ASIC_IS_AVIVO(rdev)) {
681 reg = RREG32(AVIVO_D1CRTC_CONTROL) |
682 RREG32(AVIVO_D2CRTC_CONTROL);
683 if (reg & AVIVO_CRTC_EN) {
684 return true;
685 }
686 } else {
687 reg = RREG32(RADEON_CRTC_GEN_CNTL) |
688 RREG32(RADEON_CRTC2_GEN_CNTL);
689 if (reg & RADEON_CRTC_EN) {
690 return true;
691 }
692 }
693
694check_memsize:
695
696 if (rdev->family >= CHIP_R600)
697 reg = RREG32(R600_CONFIG_MEMSIZE);
698 else
699 reg = RREG32(RADEON_CONFIG_MEMSIZE);
700
701 if (reg)
702 return true;
703
704 return false;
705
706}
707
708
709
710
711
712
713
714
715
716void radeon_update_bandwidth_info(struct radeon_device *rdev)
717{
718 fixed20_12 a;
719 u32 sclk = rdev->pm.current_sclk;
720 u32 mclk = rdev->pm.current_mclk;
721
722
723 a.full = dfixed_const(100);
724 rdev->pm.sclk.full = dfixed_const(sclk);
725 rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a);
726 rdev->pm.mclk.full = dfixed_const(mclk);
727 rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a);
728
729 if (rdev->flags & RADEON_IS_IGP) {
730 a.full = dfixed_const(16);
731
732 rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a);
733 }
734}
735
736
737
738
739
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741
742
743
744
745bool radeon_boot_test_post_card(struct radeon_device *rdev)
746{
747 if (radeon_card_posted(rdev))
748 return true;
749
750 if (rdev->bios) {
751 DRM_INFO("GPU not posted. posting now...\n");
752 if (rdev->is_atom_bios)
753 atom_asic_init(rdev->mode_info.atom_context);
754 else
755 radeon_combios_asic_init(rdev->ddev);
756 return true;
757 } else {
758 dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n");
759 return false;
760 }
761}
762
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766
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768
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770
771
772
773int radeon_dummy_page_init(struct radeon_device *rdev)
774{
775 if (rdev->dummy_page.page)
776 return 0;
777 rdev->dummy_page.page = alloc_page(GFP_DMA32 | GFP_KERNEL | __GFP_ZERO);
778 if (rdev->dummy_page.page == NULL)
779 return -ENOMEM;
780 rdev->dummy_page.addr = pci_map_page(rdev->pdev, rdev->dummy_page.page,
781 0, PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
782 if (pci_dma_mapping_error(rdev->pdev, rdev->dummy_page.addr)) {
783 dev_err(&rdev->pdev->dev, "Failed to DMA MAP the dummy page\n");
784 __free_page(rdev->dummy_page.page);
785 rdev->dummy_page.page = NULL;
786 return -ENOMEM;
787 }
788 rdev->dummy_page.entry = radeon_gart_get_page_entry(rdev->dummy_page.addr,
789 RADEON_GART_PAGE_DUMMY);
790 return 0;
791}
792
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795
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798
799
800void radeon_dummy_page_fini(struct radeon_device *rdev)
801{
802 if (rdev->dummy_page.page == NULL)
803 return;
804 pci_unmap_page(rdev->pdev, rdev->dummy_page.addr,
805 PAGE_SIZE, PCI_DMA_BIDIRECTIONAL);
806 __free_page(rdev->dummy_page.page);
807 rdev->dummy_page.page = NULL;
808}
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829static uint32_t cail_pll_read(struct card_info *info, uint32_t reg)
830{
831 struct radeon_device *rdev = info->dev->dev_private;
832 uint32_t r;
833
834 r = rdev->pll_rreg(rdev, reg);
835 return r;
836}
837
838
839
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844
845
846
847static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val)
848{
849 struct radeon_device *rdev = info->dev->dev_private;
850
851 rdev->pll_wreg(rdev, reg, val);
852}
853
854
855
856
857
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859
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861
862
863static uint32_t cail_mc_read(struct card_info *info, uint32_t reg)
864{
865 struct radeon_device *rdev = info->dev->dev_private;
866 uint32_t r;
867
868 r = rdev->mc_rreg(rdev, reg);
869 return r;
870}
871
872
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879
880
881static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val)
882{
883 struct radeon_device *rdev = info->dev->dev_private;
884
885 rdev->mc_wreg(rdev, reg, val);
886}
887
888
889
890
891
892
893
894
895
896
897static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val)
898{
899 struct radeon_device *rdev = info->dev->dev_private;
900
901 WREG32(reg*4, val);
902}
903
904
905
906
907
908
909
910
911
912
913static uint32_t cail_reg_read(struct card_info *info, uint32_t reg)
914{
915 struct radeon_device *rdev = info->dev->dev_private;
916 uint32_t r;
917
918 r = RREG32(reg*4);
919 return r;
920}
921
922
923
924
925
926
927
928
929
930
931static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val)
932{
933 struct radeon_device *rdev = info->dev->dev_private;
934
935 WREG32_IO(reg*4, val);
936}
937
938
939
940
941
942
943
944
945
946
947static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg)
948{
949 struct radeon_device *rdev = info->dev->dev_private;
950 uint32_t r;
951
952 r = RREG32_IO(reg*4);
953 return r;
954}
955
956
957
958
959
960
961
962
963
964
965
966int radeon_atombios_init(struct radeon_device *rdev)
967{
968 struct card_info *atom_card_info =
969 kzalloc(sizeof(struct card_info), GFP_KERNEL);
970
971 if (!atom_card_info)
972 return -ENOMEM;
973
974 rdev->mode_info.atom_card_info = atom_card_info;
975 atom_card_info->dev = rdev->ddev;
976 atom_card_info->reg_read = cail_reg_read;
977 atom_card_info->reg_write = cail_reg_write;
978
979 if (rdev->rio_mem) {
980 atom_card_info->ioreg_read = cail_ioreg_read;
981 atom_card_info->ioreg_write = cail_ioreg_write;
982 } else {
983 DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n");
984 atom_card_info->ioreg_read = cail_reg_read;
985 atom_card_info->ioreg_write = cail_reg_write;
986 }
987 atom_card_info->mc_read = cail_mc_read;
988 atom_card_info->mc_write = cail_mc_write;
989 atom_card_info->pll_read = cail_pll_read;
990 atom_card_info->pll_write = cail_pll_write;
991
992 rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios);
993 if (!rdev->mode_info.atom_context) {
994 radeon_atombios_fini(rdev);
995 return -ENOMEM;
996 }
997
998 mutex_init(&rdev->mode_info.atom_context->mutex);
999 mutex_init(&rdev->mode_info.atom_context->scratch_mutex);
1000 radeon_atom_initialize_bios_scratch_regs(rdev->ddev);
1001 atom_allocate_fb_scratch(rdev->mode_info.atom_context);
1002 return 0;
1003}
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014void radeon_atombios_fini(struct radeon_device *rdev)
1015{
1016 if (rdev->mode_info.atom_context) {
1017 kfree(rdev->mode_info.atom_context->scratch);
1018 }
1019 kfree(rdev->mode_info.atom_context);
1020 rdev->mode_info.atom_context = NULL;
1021 kfree(rdev->mode_info.atom_card_info);
1022 rdev->mode_info.atom_card_info = NULL;
1023}
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041int radeon_combios_init(struct radeon_device *rdev)
1042{
1043 radeon_combios_initialize_bios_scratch_regs(rdev->ddev);
1044 return 0;
1045}
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055void radeon_combios_fini(struct radeon_device *rdev)
1056{
1057}
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069static unsigned int radeon_vga_set_decode(void *cookie, bool state)
1070{
1071 struct radeon_device *rdev = cookie;
1072 radeon_vga_set_state(rdev, state);
1073 if (state)
1074 return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM |
1075 VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1076 else
1077 return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM;
1078}
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088static bool radeon_check_pot_argument(int arg)
1089{
1090 return (arg & (arg - 1)) == 0;
1091}
1092
1093
1094
1095
1096
1097
1098static int radeon_gart_size_auto(enum radeon_family family)
1099{
1100
1101 if (family >= CHIP_TAHITI)
1102 return 2048;
1103 else if (family >= CHIP_RV770)
1104 return 1024;
1105 else
1106 return 512;
1107}
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117static void radeon_check_arguments(struct radeon_device *rdev)
1118{
1119
1120 if (!radeon_check_pot_argument(radeon_vram_limit)) {
1121 dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n",
1122 radeon_vram_limit);
1123 radeon_vram_limit = 0;
1124 }
1125
1126 if (radeon_gart_size == -1) {
1127 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1128 }
1129
1130 if (radeon_gart_size < 32) {
1131 dev_warn(rdev->dev, "gart size (%d) too small\n",
1132 radeon_gart_size);
1133 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1134 } else if (!radeon_check_pot_argument(radeon_gart_size)) {
1135 dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n",
1136 radeon_gart_size);
1137 radeon_gart_size = radeon_gart_size_auto(rdev->family);
1138 }
1139 rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20;
1140
1141
1142 switch (radeon_agpmode) {
1143 case -1:
1144 case 0:
1145 case 1:
1146 case 2:
1147 case 4:
1148 case 8:
1149 break;
1150 default:
1151 dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: "
1152 "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode);
1153 radeon_agpmode = 0;
1154 break;
1155 }
1156
1157 if (!radeon_check_pot_argument(radeon_vm_size)) {
1158 dev_warn(rdev->dev, "VM size (%d) must be a power of 2\n",
1159 radeon_vm_size);
1160 radeon_vm_size = 4;
1161 }
1162
1163 if (radeon_vm_size < 1) {
1164 dev_warn(rdev->dev, "VM size (%d) too small, min is 1GB\n",
1165 radeon_vm_size);
1166 radeon_vm_size = 4;
1167 }
1168
1169
1170
1171
1172 if (radeon_vm_size > 1024) {
1173 dev_warn(rdev->dev, "VM size (%d) too large, max is 1TB\n",
1174 radeon_vm_size);
1175 radeon_vm_size = 4;
1176 }
1177
1178
1179
1180
1181 if (radeon_vm_block_size == -1) {
1182
1183
1184 unsigned bits = ilog2(radeon_vm_size) + 18;
1185
1186
1187
1188 if (radeon_vm_size <= 8)
1189 radeon_vm_block_size = bits - 9;
1190 else
1191 radeon_vm_block_size = (bits + 3) / 2;
1192
1193 } else if (radeon_vm_block_size < 9) {
1194 dev_warn(rdev->dev, "VM page table size (%d) too small\n",
1195 radeon_vm_block_size);
1196 radeon_vm_block_size = 9;
1197 }
1198
1199 if (radeon_vm_block_size > 24 ||
1200 (radeon_vm_size * 1024) < (1ull << radeon_vm_block_size)) {
1201 dev_warn(rdev->dev, "VM page table size (%d) too large\n",
1202 radeon_vm_block_size);
1203 radeon_vm_block_size = 9;
1204 }
1205}
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216static void radeon_switcheroo_set_state(struct pci_dev *pdev, enum vga_switcheroo_state state)
1217{
1218 struct drm_device *dev = pci_get_drvdata(pdev);
1219
1220 if (radeon_is_px(dev) && state == VGA_SWITCHEROO_OFF)
1221 return;
1222
1223 if (state == VGA_SWITCHEROO_ON) {
1224 pr_info("radeon: switched on\n");
1225
1226 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1227
1228 radeon_resume_kms(dev, true, true);
1229
1230 dev->switch_power_state = DRM_SWITCH_POWER_ON;
1231 drm_kms_helper_poll_enable(dev);
1232 } else {
1233 pr_info("radeon: switched off\n");
1234 drm_kms_helper_poll_disable(dev);
1235 dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
1236 radeon_suspend_kms(dev, true, true, false);
1237 dev->switch_power_state = DRM_SWITCH_POWER_OFF;
1238 }
1239}
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250static bool radeon_switcheroo_can_switch(struct pci_dev *pdev)
1251{
1252 struct drm_device *dev = pci_get_drvdata(pdev);
1253
1254
1255
1256
1257
1258
1259 return dev->open_count == 0;
1260}
1261
1262static const struct vga_switcheroo_client_ops radeon_switcheroo_ops = {
1263 .set_gpu_state = radeon_switcheroo_set_state,
1264 .reprobe = NULL,
1265 .can_switch = radeon_switcheroo_can_switch,
1266};
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280int radeon_device_init(struct radeon_device *rdev,
1281 struct drm_device *ddev,
1282 struct pci_dev *pdev,
1283 uint32_t flags)
1284{
1285 int r, i;
1286 int dma_bits;
1287 bool runtime = false;
1288
1289 rdev->shutdown = false;
1290 rdev->dev = &pdev->dev;
1291 rdev->ddev = ddev;
1292 rdev->pdev = pdev;
1293 rdev->flags = flags;
1294 rdev->family = flags & RADEON_FAMILY_MASK;
1295 rdev->is_atom_bios = false;
1296 rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT;
1297 rdev->mc.gtt_size = 512 * 1024 * 1024;
1298 rdev->accel_working = false;
1299
1300 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1301 rdev->ring[i].idx = i;
1302 }
1303 rdev->fence_context = dma_fence_context_alloc(RADEON_NUM_RINGS);
1304
1305 DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X 0x%02X).\n",
1306 radeon_family_name[rdev->family], pdev->vendor, pdev->device,
1307 pdev->subsystem_vendor, pdev->subsystem_device, pdev->revision);
1308
1309
1310
1311 mutex_init(&rdev->ring_lock);
1312 mutex_init(&rdev->dc_hw_i2c_mutex);
1313 atomic_set(&rdev->ih.lock, 0);
1314 mutex_init(&rdev->gem.mutex);
1315 mutex_init(&rdev->pm.mutex);
1316 mutex_init(&rdev->gpu_clock_mutex);
1317 mutex_init(&rdev->srbm_mutex);
1318 init_rwsem(&rdev->pm.mclk_lock);
1319 init_rwsem(&rdev->exclusive_lock);
1320 init_waitqueue_head(&rdev->irq.vblank_queue);
1321 mutex_init(&rdev->mn_lock);
1322 hash_init(rdev->mn_hash);
1323 r = radeon_gem_init(rdev);
1324 if (r)
1325 return r;
1326
1327 radeon_check_arguments(rdev);
1328
1329
1330
1331 rdev->vm_manager.max_pfn = radeon_vm_size << 18;
1332
1333
1334 r = radeon_asic_init(rdev);
1335 if (r)
1336 return r;
1337
1338
1339
1340
1341 if ((rdev->family >= CHIP_RS400) &&
1342 (rdev->flags & RADEON_IS_IGP)) {
1343 rdev->flags &= ~RADEON_IS_AGP;
1344 }
1345
1346 if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) {
1347 radeon_agp_disable(rdev);
1348 }
1349
1350
1351
1352
1353
1354 if (rdev->family >= CHIP_CAYMAN)
1355 rdev->mc.mc_mask = 0xffffffffffULL;
1356 else if (rdev->family >= CHIP_CEDAR)
1357 rdev->mc.mc_mask = 0xfffffffffULL;
1358 else
1359 rdev->mc.mc_mask = 0xffffffffULL;
1360
1361
1362
1363
1364
1365
1366
1367 rdev->need_dma32 = false;
1368 if (rdev->flags & RADEON_IS_AGP)
1369 rdev->need_dma32 = true;
1370 if ((rdev->flags & RADEON_IS_PCI) &&
1371 (rdev->family <= CHIP_RS740))
1372 rdev->need_dma32 = true;
1373#ifdef CONFIG_PPC64
1374 if (rdev->family == CHIP_CEDAR)
1375 rdev->need_dma32 = true;
1376#endif
1377
1378 dma_bits = rdev->need_dma32 ? 32 : 40;
1379 r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1380 if (r) {
1381 rdev->need_dma32 = true;
1382 dma_bits = 32;
1383 pr_warn("radeon: No suitable DMA available\n");
1384 }
1385 r = pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits));
1386 if (r) {
1387 pci_set_consistent_dma_mask(rdev->pdev, DMA_BIT_MASK(32));
1388 pr_warn("radeon: No coherent DMA available\n");
1389 }
1390 rdev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
1391
1392
1393
1394 spin_lock_init(&rdev->mmio_idx_lock);
1395 spin_lock_init(&rdev->smc_idx_lock);
1396 spin_lock_init(&rdev->pll_idx_lock);
1397 spin_lock_init(&rdev->mc_idx_lock);
1398 spin_lock_init(&rdev->pcie_idx_lock);
1399 spin_lock_init(&rdev->pciep_idx_lock);
1400 spin_lock_init(&rdev->pif_idx_lock);
1401 spin_lock_init(&rdev->cg_idx_lock);
1402 spin_lock_init(&rdev->uvd_idx_lock);
1403 spin_lock_init(&rdev->rcu_idx_lock);
1404 spin_lock_init(&rdev->didt_idx_lock);
1405 spin_lock_init(&rdev->end_idx_lock);
1406 if (rdev->family >= CHIP_BONAIRE) {
1407 rdev->rmmio_base = pci_resource_start(rdev->pdev, 5);
1408 rdev->rmmio_size = pci_resource_len(rdev->pdev, 5);
1409 } else {
1410 rdev->rmmio_base = pci_resource_start(rdev->pdev, 2);
1411 rdev->rmmio_size = pci_resource_len(rdev->pdev, 2);
1412 }
1413 rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size);
1414 if (rdev->rmmio == NULL)
1415 return -ENOMEM;
1416
1417
1418 if (rdev->family >= CHIP_BONAIRE)
1419 radeon_doorbell_init(rdev);
1420
1421
1422 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
1423 if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) {
1424 rdev->rio_mem_size = pci_resource_len(rdev->pdev, i);
1425 rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size);
1426 break;
1427 }
1428 }
1429 if (rdev->rio_mem == NULL)
1430 DRM_ERROR("Unable to find PCI I/O BAR\n");
1431
1432 if (rdev->flags & RADEON_IS_PX)
1433 radeon_device_handle_px_quirks(rdev);
1434
1435
1436
1437
1438 vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode);
1439
1440 if (rdev->flags & RADEON_IS_PX)
1441 runtime = true;
1442 if (!pci_is_thunderbolt_attached(rdev->pdev))
1443 vga_switcheroo_register_client(rdev->pdev,
1444 &radeon_switcheroo_ops, runtime);
1445 if (runtime)
1446 vga_switcheroo_init_domain_pm_ops(rdev->dev, &rdev->vga_pm_domain);
1447
1448 r = radeon_init(rdev);
1449 if (r)
1450 goto failed;
1451
1452 r = radeon_gem_debugfs_init(rdev);
1453 if (r) {
1454 DRM_ERROR("registering gem debugfs failed (%d).\n", r);
1455 }
1456
1457 r = radeon_mst_debugfs_init(rdev);
1458 if (r) {
1459 DRM_ERROR("registering mst debugfs failed (%d).\n", r);
1460 }
1461
1462 if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) {
1463
1464
1465
1466 radeon_asic_reset(rdev);
1467 radeon_fini(rdev);
1468 radeon_agp_disable(rdev);
1469 r = radeon_init(rdev);
1470 if (r)
1471 goto failed;
1472 }
1473
1474 r = radeon_ib_ring_tests(rdev);
1475 if (r)
1476 DRM_ERROR("ib ring test failed (%d).\n", r);
1477
1478
1479
1480
1481
1482
1483 if (rdev->pm.dpm_enabled &&
1484 (rdev->pm.pm_method == PM_METHOD_DPM) &&
1485 (rdev->family == CHIP_TURKS) &&
1486 (rdev->flags & RADEON_IS_MOBILITY)) {
1487 mutex_lock(&rdev->pm.mutex);
1488 radeon_dpm_disable(rdev);
1489 radeon_dpm_enable(rdev);
1490 mutex_unlock(&rdev->pm.mutex);
1491 }
1492
1493 if ((radeon_testing & 1)) {
1494 if (rdev->accel_working)
1495 radeon_test_moves(rdev);
1496 else
1497 DRM_INFO("radeon: acceleration disabled, skipping move tests\n");
1498 }
1499 if ((radeon_testing & 2)) {
1500 if (rdev->accel_working)
1501 radeon_test_syncing(rdev);
1502 else
1503 DRM_INFO("radeon: acceleration disabled, skipping sync tests\n");
1504 }
1505 if (radeon_benchmarking) {
1506 if (rdev->accel_working)
1507 radeon_benchmark(rdev, radeon_benchmarking);
1508 else
1509 DRM_INFO("radeon: acceleration disabled, skipping benchmarks\n");
1510 }
1511 return 0;
1512
1513failed:
1514
1515 if (radeon_is_px(ddev))
1516 pm_runtime_put_noidle(ddev->dev);
1517 if (runtime)
1518 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1519 return r;
1520}
1521
1522
1523
1524
1525
1526
1527
1528
1529
1530void radeon_device_fini(struct radeon_device *rdev)
1531{
1532 DRM_INFO("radeon: finishing device.\n");
1533 rdev->shutdown = true;
1534
1535 radeon_bo_evict_vram(rdev);
1536 radeon_fini(rdev);
1537 if (!pci_is_thunderbolt_attached(rdev->pdev))
1538 vga_switcheroo_unregister_client(rdev->pdev);
1539 if (rdev->flags & RADEON_IS_PX)
1540 vga_switcheroo_fini_domain_pm_ops(rdev->dev);
1541 vga_client_register(rdev->pdev, NULL, NULL, NULL);
1542 if (rdev->rio_mem)
1543 pci_iounmap(rdev->pdev, rdev->rio_mem);
1544 rdev->rio_mem = NULL;
1545 iounmap(rdev->rmmio);
1546 rdev->rmmio = NULL;
1547 if (rdev->family >= CHIP_BONAIRE)
1548 radeon_doorbell_fini(rdev);
1549}
1550
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565int radeon_suspend_kms(struct drm_device *dev, bool suspend,
1566 bool fbcon, bool freeze)
1567{
1568 struct radeon_device *rdev;
1569 struct drm_crtc *crtc;
1570 struct drm_connector *connector;
1571 int i, r;
1572
1573 if (dev == NULL || dev->dev_private == NULL) {
1574 return -ENODEV;
1575 }
1576
1577 rdev = dev->dev_private;
1578
1579 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1580 return 0;
1581
1582 drm_kms_helper_poll_disable(dev);
1583
1584 drm_modeset_lock_all(dev);
1585
1586 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1587 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_OFF);
1588 }
1589 drm_modeset_unlock_all(dev);
1590
1591
1592 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1593 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1594 struct radeon_framebuffer *rfb = to_radeon_framebuffer(crtc->primary->fb);
1595 struct radeon_bo *robj;
1596
1597 if (radeon_crtc->cursor_bo) {
1598 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1599 r = radeon_bo_reserve(robj, false);
1600 if (r == 0) {
1601 radeon_bo_unpin(robj);
1602 radeon_bo_unreserve(robj);
1603 }
1604 }
1605
1606 if (rfb == NULL || rfb->obj == NULL) {
1607 continue;
1608 }
1609 robj = gem_to_radeon_bo(rfb->obj);
1610
1611 if (!radeon_fbdev_robj_is_fb(rdev, robj)) {
1612 r = radeon_bo_reserve(robj, false);
1613 if (r == 0) {
1614 radeon_bo_unpin(robj);
1615 radeon_bo_unreserve(robj);
1616 }
1617 }
1618 }
1619
1620 radeon_bo_evict_vram(rdev);
1621
1622
1623 for (i = 0; i < RADEON_NUM_RINGS; i++) {
1624 r = radeon_fence_wait_empty(rdev, i);
1625 if (r) {
1626
1627 radeon_fence_driver_force_completion(rdev, i);
1628 }
1629 }
1630
1631 radeon_save_bios_scratch_regs(rdev);
1632
1633 radeon_suspend(rdev);
1634 radeon_hpd_fini(rdev);
1635
1636
1637
1638
1639 radeon_bo_evict_vram(rdev);
1640
1641 radeon_agp_suspend(rdev);
1642
1643 pci_save_state(dev->pdev);
1644 if (freeze && rdev->family >= CHIP_CEDAR && !(rdev->flags & RADEON_IS_IGP)) {
1645 rdev->asic->asic_reset(rdev, true);
1646 pci_restore_state(dev->pdev);
1647 } else if (suspend) {
1648
1649 pci_disable_device(dev->pdev);
1650 pci_set_power_state(dev->pdev, PCI_D3hot);
1651 }
1652
1653 if (fbcon) {
1654 console_lock();
1655 radeon_fbdev_set_suspend(rdev, 1);
1656 console_unlock();
1657 }
1658 return 0;
1659}
1660
1661
1662
1663
1664
1665
1666
1667
1668
1669
1670int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon)
1671{
1672 struct drm_connector *connector;
1673 struct radeon_device *rdev = dev->dev_private;
1674 struct drm_crtc *crtc;
1675 int r;
1676
1677 if (dev->switch_power_state == DRM_SWITCH_POWER_OFF)
1678 return 0;
1679
1680 if (fbcon) {
1681 console_lock();
1682 }
1683 if (resume) {
1684 pci_set_power_state(dev->pdev, PCI_D0);
1685 pci_restore_state(dev->pdev);
1686 if (pci_enable_device(dev->pdev)) {
1687 if (fbcon)
1688 console_unlock();
1689 return -1;
1690 }
1691 }
1692
1693 radeon_agp_resume(rdev);
1694 radeon_resume(rdev);
1695
1696 r = radeon_ib_ring_tests(rdev);
1697 if (r)
1698 DRM_ERROR("ib ring test failed (%d).\n", r);
1699
1700 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1701
1702 r = radeon_pm_late_init(rdev);
1703 if (r) {
1704 rdev->pm.dpm_enabled = false;
1705 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1706 }
1707 } else {
1708
1709 radeon_pm_resume(rdev);
1710 }
1711
1712 radeon_restore_bios_scratch_regs(rdev);
1713
1714
1715 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
1716 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
1717
1718 if (radeon_crtc->cursor_bo) {
1719 struct radeon_bo *robj = gem_to_radeon_bo(radeon_crtc->cursor_bo);
1720 r = radeon_bo_reserve(robj, false);
1721 if (r == 0) {
1722
1723 r = radeon_bo_pin_restricted(robj,
1724 RADEON_GEM_DOMAIN_VRAM,
1725 ASIC_IS_AVIVO(rdev) ?
1726 0 : 1 << 27,
1727 &radeon_crtc->cursor_addr);
1728 if (r != 0)
1729 DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
1730 radeon_bo_unreserve(robj);
1731 }
1732 }
1733 }
1734
1735
1736 if (rdev->is_atom_bios) {
1737 radeon_atom_encoder_init(rdev);
1738 radeon_atom_disp_eng_pll_init(rdev);
1739
1740 if (rdev->mode_info.bl_encoder) {
1741 u8 bl_level = radeon_get_backlight_level(rdev,
1742 rdev->mode_info.bl_encoder);
1743 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1744 bl_level);
1745 }
1746 }
1747
1748 radeon_hpd_init(rdev);
1749
1750 if (fbcon) {
1751 drm_helper_resume_force_mode(dev);
1752
1753 drm_modeset_lock_all(dev);
1754 list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
1755 drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON);
1756 }
1757 drm_modeset_unlock_all(dev);
1758 }
1759
1760 drm_kms_helper_poll_enable(dev);
1761
1762
1763 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1764 radeon_pm_compute_clocks(rdev);
1765
1766 if (fbcon) {
1767 radeon_fbdev_set_suspend(rdev, 0);
1768 console_unlock();
1769 }
1770
1771 return 0;
1772}
1773
1774
1775
1776
1777
1778
1779
1780
1781
1782int radeon_gpu_reset(struct radeon_device *rdev)
1783{
1784 unsigned ring_sizes[RADEON_NUM_RINGS];
1785 uint32_t *ring_data[RADEON_NUM_RINGS];
1786
1787 bool saved = false;
1788
1789 int i, r;
1790 int resched;
1791
1792 down_write(&rdev->exclusive_lock);
1793
1794 if (!rdev->needs_reset) {
1795 up_write(&rdev->exclusive_lock);
1796 return 0;
1797 }
1798
1799 atomic_inc(&rdev->gpu_reset_counter);
1800
1801 radeon_save_bios_scratch_regs(rdev);
1802
1803 resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1804 radeon_suspend(rdev);
1805 radeon_hpd_fini(rdev);
1806
1807 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1808 ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i],
1809 &ring_data[i]);
1810 if (ring_sizes[i]) {
1811 saved = true;
1812 dev_info(rdev->dev, "Saved %d dwords of commands "
1813 "on ring %d.\n", ring_sizes[i], i);
1814 }
1815 }
1816
1817 r = radeon_asic_reset(rdev);
1818 if (!r) {
1819 dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n");
1820 radeon_resume(rdev);
1821 }
1822
1823 radeon_restore_bios_scratch_regs(rdev);
1824
1825 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1826 if (!r && ring_data[i]) {
1827 radeon_ring_restore(rdev, &rdev->ring[i],
1828 ring_sizes[i], ring_data[i]);
1829 } else {
1830 radeon_fence_driver_force_completion(rdev, i);
1831 kfree(ring_data[i]);
1832 }
1833 }
1834
1835 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) {
1836
1837 r = radeon_pm_late_init(rdev);
1838 if (r) {
1839 rdev->pm.dpm_enabled = false;
1840 DRM_ERROR("radeon_pm_late_init failed, disabling dpm\n");
1841 }
1842 } else {
1843
1844 radeon_pm_resume(rdev);
1845 }
1846
1847
1848 if (rdev->is_atom_bios) {
1849 radeon_atom_encoder_init(rdev);
1850 radeon_atom_disp_eng_pll_init(rdev);
1851
1852 if (rdev->mode_info.bl_encoder) {
1853 u8 bl_level = radeon_get_backlight_level(rdev,
1854 rdev->mode_info.bl_encoder);
1855 radeon_set_backlight_level(rdev, rdev->mode_info.bl_encoder,
1856 bl_level);
1857 }
1858 }
1859
1860 radeon_hpd_init(rdev);
1861
1862 ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1863
1864 rdev->in_reset = true;
1865 rdev->needs_reset = false;
1866
1867 downgrade_write(&rdev->exclusive_lock);
1868
1869 drm_helper_resume_force_mode(rdev->ddev);
1870
1871
1872 if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled)
1873 radeon_pm_compute_clocks(rdev);
1874
1875 if (!r) {
1876 r = radeon_ib_ring_tests(rdev);
1877 if (r && saved)
1878 r = -EAGAIN;
1879 } else {
1880
1881 dev_info(rdev->dev, "GPU reset failed\n");
1882 }
1883
1884 rdev->needs_reset = r == -EAGAIN;
1885 rdev->in_reset = false;
1886
1887 up_read(&rdev->exclusive_lock);
1888 return r;
1889}
1890
1891
1892
1893
1894
1895int radeon_debugfs_add_files(struct radeon_device *rdev,
1896 struct drm_info_list *files,
1897 unsigned nfiles)
1898{
1899 unsigned i;
1900
1901 for (i = 0; i < rdev->debugfs_count; i++) {
1902 if (rdev->debugfs[i].files == files) {
1903
1904 return 0;
1905 }
1906 }
1907
1908 i = rdev->debugfs_count + 1;
1909 if (i > RADEON_DEBUGFS_MAX_COMPONENTS) {
1910 DRM_ERROR("Reached maximum number of debugfs components.\n");
1911 DRM_ERROR("Report so we increase "
1912 "RADEON_DEBUGFS_MAX_COMPONENTS.\n");
1913 return -EINVAL;
1914 }
1915 rdev->debugfs[rdev->debugfs_count].files = files;
1916 rdev->debugfs[rdev->debugfs_count].num_files = nfiles;
1917 rdev->debugfs_count = i;
1918#if defined(CONFIG_DEBUG_FS)
1919 drm_debugfs_create_files(files, nfiles,
1920 rdev->ddev->primary->debugfs_root,
1921 rdev->ddev->primary);
1922#endif
1923 return 0;
1924}
1925