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28#include "vmwgfx_kms.h"
29#include "device_include/svga3d_surfacedefs.h"
30#include <drm/drm_plane_helper.h>
31#include <drm/drm_atomic.h>
32#include <drm/drm_atomic_helper.h>
33
34
35#define vmw_crtc_to_stdu(x) \
36 container_of(x, struct vmw_screen_target_display_unit, base.crtc)
37#define vmw_encoder_to_stdu(x) \
38 container_of(x, struct vmw_screen_target_display_unit, base.encoder)
39#define vmw_connector_to_stdu(x) \
40 container_of(x, struct vmw_screen_target_display_unit, base.connector)
41
42
43
44enum stdu_content_type {
45 SAME_AS_DISPLAY = 0,
46 SEPARATE_SURFACE,
47 SEPARATE_DMA
48};
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64struct vmw_stdu_dirty {
65 struct vmw_kms_dirty base;
66 SVGA3dTransferType transfer;
67 s32 left, right, top, bottom;
68 s32 fb_left, fb_top;
69 u32 pitch;
70 union {
71 struct vmw_dma_buffer *buf;
72 u32 sid;
73 };
74};
75
76
77
78
79
80struct vmw_stdu_update {
81 SVGA3dCmdHeader header;
82 SVGA3dCmdUpdateGBScreenTarget body;
83};
84
85struct vmw_stdu_dma {
86 SVGA3dCmdHeader header;
87 SVGA3dCmdSurfaceDMA body;
88};
89
90struct vmw_stdu_surface_copy {
91 SVGA3dCmdHeader header;
92 SVGA3dCmdSurfaceCopy body;
93};
94
95
96
97
98
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102
103
104
105
106
107
108struct vmw_screen_target_display_unit {
109 struct vmw_display_unit base;
110 const struct vmw_surface *display_srf;
111 enum stdu_content_type content_fb_type;
112 s32 display_width, display_height;
113
114 bool defined;
115
116
117 unsigned int cpp;
118};
119
120
121
122static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu);
123
124
125
126
127
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130
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132
133
134
135
136static void vmw_stdu_crtc_destroy(struct drm_crtc *crtc)
137{
138 vmw_stdu_destroy(vmw_crtc_to_stdu(crtc));
139}
140
141
142
143
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153
154
155
156static int vmw_stdu_define_st(struct vmw_private *dev_priv,
157 struct vmw_screen_target_display_unit *stdu,
158 struct drm_display_mode *mode,
159 int crtc_x, int crtc_y)
160{
161 struct {
162 SVGA3dCmdHeader header;
163 SVGA3dCmdDefineGBScreenTarget body;
164 } *cmd;
165
166 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
167
168 if (unlikely(cmd == NULL)) {
169 DRM_ERROR("Out of FIFO space defining Screen Target\n");
170 return -ENOMEM;
171 }
172
173 cmd->header.id = SVGA_3D_CMD_DEFINE_GB_SCREENTARGET;
174 cmd->header.size = sizeof(cmd->body);
175
176 cmd->body.stid = stdu->base.unit;
177 cmd->body.width = mode->hdisplay;
178 cmd->body.height = mode->vdisplay;
179 cmd->body.flags = (0 == cmd->body.stid) ? SVGA_STFLAG_PRIMARY : 0;
180 cmd->body.dpi = 0;
181 if (stdu->base.is_implicit) {
182 cmd->body.xRoot = crtc_x;
183 cmd->body.yRoot = crtc_y;
184 } else {
185 cmd->body.xRoot = stdu->base.gui_x;
186 cmd->body.yRoot = stdu->base.gui_y;
187 }
188 stdu->base.set_gui_x = cmd->body.xRoot;
189 stdu->base.set_gui_y = cmd->body.yRoot;
190
191 vmw_fifo_commit(dev_priv, sizeof(*cmd));
192
193 stdu->defined = true;
194 stdu->display_width = mode->hdisplay;
195 stdu->display_height = mode->vdisplay;
196
197 return 0;
198}
199
200
201
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209
210
211static int vmw_stdu_bind_st(struct vmw_private *dev_priv,
212 struct vmw_screen_target_display_unit *stdu,
213 const struct vmw_resource *res)
214{
215 SVGA3dSurfaceImageId image;
216
217 struct {
218 SVGA3dCmdHeader header;
219 SVGA3dCmdBindGBScreenTarget body;
220 } *cmd;
221
222
223 if (!stdu->defined) {
224 DRM_ERROR("No screen target defined\n");
225 return -EINVAL;
226 }
227
228
229 memset(&image, 0, sizeof(image));
230 image.sid = res ? res->id : SVGA3D_INVALID_ID;
231
232 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
233
234 if (unlikely(cmd == NULL)) {
235 DRM_ERROR("Out of FIFO space binding a screen target\n");
236 return -ENOMEM;
237 }
238
239 cmd->header.id = SVGA_3D_CMD_BIND_GB_SCREENTARGET;
240 cmd->header.size = sizeof(cmd->body);
241
242 cmd->body.stid = stdu->base.unit;
243 cmd->body.image = image;
244
245 vmw_fifo_commit(dev_priv, sizeof(*cmd));
246
247 return 0;
248}
249
250
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253
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259
260
261static void vmw_stdu_populate_update(void *cmd, int unit,
262 s32 left, s32 right, s32 top, s32 bottom)
263{
264 struct vmw_stdu_update *update = cmd;
265
266 update->header.id = SVGA_3D_CMD_UPDATE_GB_SCREENTARGET;
267 update->header.size = sizeof(update->body);
268
269 update->body.stid = unit;
270 update->body.rect.x = left;
271 update->body.rect.y = top;
272 update->body.rect.w = right - left;
273 update->body.rect.h = bottom - top;
274}
275
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287
288
289static int vmw_stdu_update_st(struct vmw_private *dev_priv,
290 struct vmw_screen_target_display_unit *stdu)
291{
292 struct vmw_stdu_update *cmd;
293
294 if (!stdu->defined) {
295 DRM_ERROR("No screen target defined");
296 return -EINVAL;
297 }
298
299 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
300
301 if (unlikely(cmd == NULL)) {
302 DRM_ERROR("Out of FIFO space updating a Screen Target\n");
303 return -ENOMEM;
304 }
305
306 vmw_stdu_populate_update(cmd, stdu->base.unit,
307 0, stdu->display_width,
308 0, stdu->display_height);
309
310 vmw_fifo_commit(dev_priv, sizeof(*cmd));
311
312 return 0;
313}
314
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319
320
321
322
323static int vmw_stdu_destroy_st(struct vmw_private *dev_priv,
324 struct vmw_screen_target_display_unit *stdu)
325{
326 int ret;
327
328 struct {
329 SVGA3dCmdHeader header;
330 SVGA3dCmdDestroyGBScreenTarget body;
331 } *cmd;
332
333
334
335 if (unlikely(!stdu->defined))
336 return 0;
337
338 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
339
340 if (unlikely(cmd == NULL)) {
341 DRM_ERROR("Out of FIFO space, screen target not destroyed\n");
342 return -ENOMEM;
343 }
344
345 cmd->header.id = SVGA_3D_CMD_DESTROY_GB_SCREENTARGET;
346 cmd->header.size = sizeof(cmd->body);
347
348 cmd->body.stid = stdu->base.unit;
349
350 vmw_fifo_commit(dev_priv, sizeof(*cmd));
351
352
353 ret = vmw_fallback_wait(dev_priv, false, true, 0, false, 3*HZ);
354 if (unlikely(ret != 0))
355 DRM_ERROR("Failed to sync with HW");
356
357 stdu->defined = false;
358 stdu->display_width = 0;
359 stdu->display_height = 0;
360
361 return ret;
362}
363
364
365
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367
368
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370
371
372
373static void vmw_stdu_crtc_mode_set_nofb(struct drm_crtc *crtc)
374{
375 struct vmw_private *dev_priv;
376 struct vmw_screen_target_display_unit *stdu;
377 int ret;
378
379
380 stdu = vmw_crtc_to_stdu(crtc);
381 dev_priv = vmw_priv(crtc->dev);
382
383 if (stdu->defined) {
384 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
385 if (ret)
386 DRM_ERROR("Failed to blank CRTC\n");
387
388 (void) vmw_stdu_update_st(dev_priv, stdu);
389
390 ret = vmw_stdu_destroy_st(dev_priv, stdu);
391 if (ret)
392 DRM_ERROR("Failed to destroy Screen Target\n");
393
394 stdu->content_fb_type = SAME_AS_DISPLAY;
395 }
396
397 if (!crtc->state->enable)
398 return;
399
400 vmw_svga_enable(dev_priv);
401 ret = vmw_stdu_define_st(dev_priv, stdu, &crtc->mode, crtc->x, crtc->y);
402
403 if (ret)
404 DRM_ERROR("Failed to define Screen Target of size %dx%d\n",
405 crtc->x, crtc->y);
406}
407
408
409static void vmw_stdu_crtc_helper_prepare(struct drm_crtc *crtc)
410{
411}
412
413
414static void vmw_stdu_crtc_atomic_enable(struct drm_crtc *crtc,
415 struct drm_crtc_state *old_state)
416{
417 struct vmw_private *dev_priv;
418 struct vmw_screen_target_display_unit *stdu;
419 struct vmw_framebuffer *vfb;
420 struct drm_framebuffer *fb;
421
422
423 stdu = vmw_crtc_to_stdu(crtc);
424 dev_priv = vmw_priv(crtc->dev);
425 fb = crtc->primary->fb;
426
427 vfb = (fb) ? vmw_framebuffer_to_vfb(fb) : NULL;
428
429 if (vfb)
430 vmw_kms_add_active(dev_priv, &stdu->base, vfb);
431 else
432 vmw_kms_del_active(dev_priv, &stdu->base);
433}
434
435static void vmw_stdu_crtc_atomic_disable(struct drm_crtc *crtc,
436 struct drm_crtc_state *old_state)
437{
438 struct vmw_private *dev_priv;
439 struct vmw_screen_target_display_unit *stdu;
440 int ret;
441
442
443 if (!crtc) {
444 DRM_ERROR("CRTC is NULL\n");
445 return;
446 }
447
448 stdu = vmw_crtc_to_stdu(crtc);
449 dev_priv = vmw_priv(crtc->dev);
450
451 if (stdu->defined) {
452 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
453 if (ret)
454 DRM_ERROR("Failed to blank CRTC\n");
455
456 (void) vmw_stdu_update_st(dev_priv, stdu);
457
458 ret = vmw_stdu_destroy_st(dev_priv, stdu);
459 if (ret)
460 DRM_ERROR("Failed to destroy Screen Target\n");
461
462 stdu->content_fb_type = SAME_AS_DISPLAY;
463 }
464}
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484
485static int vmw_stdu_crtc_page_flip(struct drm_crtc *crtc,
486 struct drm_framebuffer *new_fb,
487 struct drm_pending_vblank_event *event,
488 uint32_t flags,
489 struct drm_modeset_acquire_ctx *ctx)
490
491{
492 struct vmw_private *dev_priv = vmw_priv(crtc->dev);
493 struct vmw_screen_target_display_unit *stdu = vmw_crtc_to_stdu(crtc);
494 int ret;
495
496 if (!stdu->defined || !vmw_kms_crtc_flippable(dev_priv, crtc))
497 return -EINVAL;
498
499 ret = drm_atomic_helper_page_flip(crtc, new_fb, event, flags, ctx);
500 if (ret) {
501 DRM_ERROR("Page flip error %d.\n", ret);
502 return ret;
503 }
504
505 return 0;
506}
507
508
509
510
511
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514
515
516
517static void vmw_stdu_dmabuf_clip(struct vmw_kms_dirty *dirty)
518{
519 struct vmw_stdu_dirty *ddirty =
520 container_of(dirty, struct vmw_stdu_dirty, base);
521 struct vmw_stdu_dma *cmd = dirty->cmd;
522 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
523
524 blit += dirty->num_hits;
525 blit->srcx = dirty->fb_x;
526 blit->srcy = dirty->fb_y;
527 blit->x = dirty->unit_x1;
528 blit->y = dirty->unit_y1;
529 blit->d = 1;
530 blit->w = dirty->unit_x2 - dirty->unit_x1;
531 blit->h = dirty->unit_y2 - dirty->unit_y1;
532 dirty->num_hits++;
533
534 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM)
535 return;
536
537
538 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
539 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
540 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
541 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
542}
543
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549
550
551
552static void vmw_stdu_dmabuf_fifo_commit(struct vmw_kms_dirty *dirty)
553{
554 struct vmw_stdu_dirty *ddirty =
555 container_of(dirty, struct vmw_stdu_dirty, base);
556 struct vmw_screen_target_display_unit *stdu =
557 container_of(dirty->unit, typeof(*stdu), base);
558 struct vmw_stdu_dma *cmd = dirty->cmd;
559 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
560 SVGA3dCmdSurfaceDMASuffix *suffix =
561 (SVGA3dCmdSurfaceDMASuffix *) &blit[dirty->num_hits];
562 size_t blit_size = sizeof(*blit) * dirty->num_hits + sizeof(*suffix);
563
564 if (!dirty->num_hits) {
565 vmw_fifo_commit(dirty->dev_priv, 0);
566 return;
567 }
568
569 cmd->header.id = SVGA_3D_CMD_SURFACE_DMA;
570 cmd->header.size = sizeof(cmd->body) + blit_size;
571 vmw_bo_get_guest_ptr(&ddirty->buf->base, &cmd->body.guest.ptr);
572 cmd->body.guest.pitch = ddirty->pitch;
573 cmd->body.host.sid = stdu->display_srf->res.id;
574 cmd->body.host.face = 0;
575 cmd->body.host.mipmap = 0;
576 cmd->body.transfer = ddirty->transfer;
577 suffix->suffixSize = sizeof(*suffix);
578 suffix->maximumOffset = ddirty->buf->base.num_pages * PAGE_SIZE;
579
580 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM) {
581 blit_size += sizeof(struct vmw_stdu_update);
582
583 vmw_stdu_populate_update(&suffix[1], stdu->base.unit,
584 ddirty->left, ddirty->right,
585 ddirty->top, ddirty->bottom);
586 }
587
588 vmw_fifo_commit(dirty->dev_priv, sizeof(*cmd) + blit_size);
589
590 ddirty->left = ddirty->top = S32_MAX;
591 ddirty->right = ddirty->bottom = S32_MIN;
592}
593
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597
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599
600
601
602static void vmw_stdu_dmabuf_cpu_clip(struct vmw_kms_dirty *dirty)
603{
604 struct vmw_stdu_dirty *ddirty =
605 container_of(dirty, struct vmw_stdu_dirty, base);
606
607 dirty->num_hits = 1;
608
609
610 ddirty->left = min_t(s32, ddirty->left, dirty->unit_x1);
611 ddirty->top = min_t(s32, ddirty->top, dirty->unit_y1);
612 ddirty->right = max_t(s32, ddirty->right, dirty->unit_x2);
613 ddirty->bottom = max_t(s32, ddirty->bottom, dirty->unit_y2);
614
615
616
617
618
619
620 ddirty->fb_left = min_t(s32, ddirty->fb_left, dirty->fb_x);
621 ddirty->fb_top = min_t(s32, ddirty->fb_top, dirty->fb_y);
622}
623
624
625
626
627
628
629
630
631
632
633static void vmw_stdu_dmabuf_cpu_commit(struct vmw_kms_dirty *dirty)
634{
635 struct vmw_stdu_dirty *ddirty =
636 container_of(dirty, struct vmw_stdu_dirty, base);
637 struct vmw_screen_target_display_unit *stdu =
638 container_of(dirty->unit, typeof(*stdu), base);
639 s32 width, height;
640 s32 src_pitch, dst_pitch;
641 struct ttm_buffer_object *src_bo, *dst_bo;
642 u32 src_offset, dst_offset;
643 struct vmw_diff_cpy diff = VMW_CPU_BLIT_DIFF_INITIALIZER(stdu->cpp);
644
645 if (!dirty->num_hits)
646 return;
647
648 width = ddirty->right - ddirty->left;
649 height = ddirty->bottom - ddirty->top;
650
651 if (width == 0 || height == 0)
652 return;
653
654
655 dst_pitch = stdu->display_srf->base_size.width * stdu->cpp;
656 dst_bo = &stdu->display_srf->res.backup->base;
657 dst_offset = ddirty->top * dst_pitch + ddirty->left * stdu->cpp;
658
659 src_pitch = ddirty->pitch;
660 src_bo = &ddirty->buf->base;
661 src_offset = ddirty->fb_top * src_pitch + ddirty->fb_left * stdu->cpp;
662
663
664 if (ddirty->transfer != SVGA3D_WRITE_HOST_VRAM) {
665 swap(dst_pitch, src_pitch);
666 swap(dst_bo, src_bo);
667 swap(src_offset, dst_offset);
668 }
669
670 (void) vmw_bo_cpu_blit(dst_bo, dst_offset, dst_pitch,
671 src_bo, src_offset, src_pitch,
672 width * stdu->cpp, height, &diff);
673
674 if (ddirty->transfer == SVGA3D_WRITE_HOST_VRAM &&
675 drm_rect_visible(&diff.rect)) {
676 struct vmw_private *dev_priv;
677 struct vmw_stdu_update *cmd;
678 struct drm_clip_rect region;
679 int ret;
680
681
682 region.x1 = diff.rect.x1;
683 region.x2 = diff.rect.x2;
684 region.y1 = diff.rect.y1;
685 region.y2 = diff.rect.y2;
686 ret = vmw_kms_update_proxy(
687 (struct vmw_resource *) &stdu->display_srf->res,
688 (const struct drm_clip_rect *) ®ion, 1, 1);
689 if (ret)
690 goto out_cleanup;
691
692
693 dev_priv = vmw_priv(stdu->base.crtc.dev);
694 cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
695
696 if (!cmd) {
697 DRM_ERROR("Cannot reserve FIFO space to update STDU");
698 goto out_cleanup;
699 }
700
701 vmw_stdu_populate_update(cmd, stdu->base.unit,
702 region.x1, region.x2,
703 region.y1, region.y2);
704
705 vmw_fifo_commit(dev_priv, sizeof(*cmd));
706 }
707
708out_cleanup:
709 ddirty->left = ddirty->top = ddirty->fb_left = ddirty->fb_top = S32_MAX;
710 ddirty->right = ddirty->bottom = S32_MIN;
711}
712
713
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736
737int vmw_kms_stdu_dma(struct vmw_private *dev_priv,
738 struct drm_file *file_priv,
739 struct vmw_framebuffer *vfb,
740 struct drm_vmw_fence_rep __user *user_fence_rep,
741 struct drm_clip_rect *clips,
742 struct drm_vmw_rect *vclips,
743 uint32_t num_clips,
744 int increment,
745 bool to_surface,
746 bool interruptible,
747 struct drm_crtc *crtc)
748{
749 struct vmw_dma_buffer *buf =
750 container_of(vfb, struct vmw_framebuffer_dmabuf, base)->buffer;
751 struct vmw_stdu_dirty ddirty;
752 int ret;
753 bool cpu_blit = !(dev_priv->capabilities & SVGA_CAP_3D);
754
755
756
757
758
759
760 ret = vmw_kms_helper_buffer_prepare(dev_priv, buf, interruptible,
761 false, cpu_blit);
762 if (ret)
763 return ret;
764
765 ddirty.transfer = (to_surface) ? SVGA3D_WRITE_HOST_VRAM :
766 SVGA3D_READ_HOST_VRAM;
767 ddirty.left = ddirty.top = S32_MAX;
768 ddirty.right = ddirty.bottom = S32_MIN;
769 ddirty.fb_left = ddirty.fb_top = S32_MAX;
770 ddirty.pitch = vfb->base.pitches[0];
771 ddirty.buf = buf;
772 ddirty.base.fifo_commit = vmw_stdu_dmabuf_fifo_commit;
773 ddirty.base.clip = vmw_stdu_dmabuf_clip;
774 ddirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_dma) +
775 num_clips * sizeof(SVGA3dCopyBox) +
776 sizeof(SVGA3dCmdSurfaceDMASuffix);
777 if (to_surface)
778 ddirty.base.fifo_reserve_size += sizeof(struct vmw_stdu_update);
779
780
781 if (cpu_blit) {
782 ddirty.base.fifo_commit = vmw_stdu_dmabuf_cpu_commit;
783 ddirty.base.clip = vmw_stdu_dmabuf_cpu_clip;
784 ddirty.base.fifo_reserve_size = 0;
785 }
786
787 ddirty.base.crtc = crtc;
788
789 ret = vmw_kms_helper_dirty(dev_priv, vfb, clips, vclips,
790 0, 0, num_clips, increment, &ddirty.base);
791 vmw_kms_helper_buffer_finish(dev_priv, file_priv, buf, NULL,
792 user_fence_rep);
793
794 return ret;
795}
796
797
798
799
800
801
802
803
804
805static void vmw_kms_stdu_surface_clip(struct vmw_kms_dirty *dirty)
806{
807 struct vmw_stdu_dirty *sdirty =
808 container_of(dirty, struct vmw_stdu_dirty, base);
809 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
810 struct vmw_screen_target_display_unit *stdu =
811 container_of(dirty->unit, typeof(*stdu), base);
812
813 if (sdirty->sid != stdu->display_srf->res.id) {
814 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
815
816 blit += dirty->num_hits;
817 blit->srcx = dirty->fb_x;
818 blit->srcy = dirty->fb_y;
819 blit->x = dirty->unit_x1;
820 blit->y = dirty->unit_y1;
821 blit->d = 1;
822 blit->w = dirty->unit_x2 - dirty->unit_x1;
823 blit->h = dirty->unit_y2 - dirty->unit_y1;
824 }
825
826 dirty->num_hits++;
827
828
829 sdirty->left = min_t(s32, sdirty->left, dirty->unit_x1);
830 sdirty->top = min_t(s32, sdirty->top, dirty->unit_y1);
831 sdirty->right = max_t(s32, sdirty->right, dirty->unit_x2);
832 sdirty->bottom = max_t(s32, sdirty->bottom, dirty->unit_y2);
833}
834
835
836
837
838
839
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841
842
843
844static void vmw_kms_stdu_surface_fifo_commit(struct vmw_kms_dirty *dirty)
845{
846 struct vmw_stdu_dirty *sdirty =
847 container_of(dirty, struct vmw_stdu_dirty, base);
848 struct vmw_screen_target_display_unit *stdu =
849 container_of(dirty->unit, typeof(*stdu), base);
850 struct vmw_stdu_surface_copy *cmd = dirty->cmd;
851 struct vmw_stdu_update *update;
852 size_t blit_size = sizeof(SVGA3dCopyBox) * dirty->num_hits;
853 size_t commit_size;
854
855 if (!dirty->num_hits) {
856 vmw_fifo_commit(dirty->dev_priv, 0);
857 return;
858 }
859
860 if (sdirty->sid != stdu->display_srf->res.id) {
861 struct SVGA3dCopyBox *blit = (struct SVGA3dCopyBox *) &cmd[1];
862
863 cmd->header.id = SVGA_3D_CMD_SURFACE_COPY;
864 cmd->header.size = sizeof(cmd->body) + blit_size;
865 cmd->body.src.sid = sdirty->sid;
866 cmd->body.dest.sid = stdu->display_srf->res.id;
867 update = (struct vmw_stdu_update *) &blit[dirty->num_hits];
868 commit_size = sizeof(*cmd) + blit_size + sizeof(*update);
869 } else {
870 update = dirty->cmd;
871 commit_size = sizeof(*update);
872 }
873
874 vmw_stdu_populate_update(update, stdu->base.unit, sdirty->left,
875 sdirty->right, sdirty->top, sdirty->bottom);
876
877 vmw_fifo_commit(dirty->dev_priv, commit_size);
878
879 sdirty->left = sdirty->top = S32_MAX;
880 sdirty->right = sdirty->bottom = S32_MIN;
881}
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905int vmw_kms_stdu_surface_dirty(struct vmw_private *dev_priv,
906 struct vmw_framebuffer *framebuffer,
907 struct drm_clip_rect *clips,
908 struct drm_vmw_rect *vclips,
909 struct vmw_resource *srf,
910 s32 dest_x,
911 s32 dest_y,
912 unsigned num_clips, int inc,
913 struct vmw_fence_obj **out_fence,
914 struct drm_crtc *crtc)
915{
916 struct vmw_framebuffer_surface *vfbs =
917 container_of(framebuffer, typeof(*vfbs), base);
918 struct vmw_stdu_dirty sdirty;
919 struct vmw_validation_ctx ctx;
920 int ret;
921
922 if (!srf)
923 srf = &vfbs->surface->res;
924
925 ret = vmw_kms_helper_resource_prepare(srf, true, &ctx);
926 if (ret)
927 return ret;
928
929 if (vfbs->is_dmabuf_proxy) {
930 ret = vmw_kms_update_proxy(srf, clips, num_clips, inc);
931 if (ret)
932 goto out_finish;
933 }
934
935 sdirty.base.fifo_commit = vmw_kms_stdu_surface_fifo_commit;
936 sdirty.base.clip = vmw_kms_stdu_surface_clip;
937 sdirty.base.fifo_reserve_size = sizeof(struct vmw_stdu_surface_copy) +
938 sizeof(SVGA3dCopyBox) * num_clips +
939 sizeof(struct vmw_stdu_update);
940 sdirty.base.crtc = crtc;
941 sdirty.sid = srf->id;
942 sdirty.left = sdirty.top = S32_MAX;
943 sdirty.right = sdirty.bottom = S32_MIN;
944
945 ret = vmw_kms_helper_dirty(dev_priv, framebuffer, clips, vclips,
946 dest_x, dest_y, num_clips, inc,
947 &sdirty.base);
948out_finish:
949 vmw_kms_helper_resource_finish(&ctx, out_fence);
950
951 return ret;
952}
953
954
955
956
957
958static const struct drm_crtc_funcs vmw_stdu_crtc_funcs = {
959 .gamma_set = vmw_du_crtc_gamma_set,
960 .destroy = vmw_stdu_crtc_destroy,
961 .reset = vmw_du_crtc_reset,
962 .atomic_duplicate_state = vmw_du_crtc_duplicate_state,
963 .atomic_destroy_state = vmw_du_crtc_destroy_state,
964 .set_config = vmw_kms_set_config,
965 .page_flip = vmw_stdu_crtc_page_flip,
966};
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984static void vmw_stdu_encoder_destroy(struct drm_encoder *encoder)
985{
986 vmw_stdu_destroy(vmw_encoder_to_stdu(encoder));
987}
988
989static const struct drm_encoder_funcs vmw_stdu_encoder_funcs = {
990 .destroy = vmw_stdu_encoder_destroy,
991};
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009static void vmw_stdu_connector_destroy(struct drm_connector *connector)
1010{
1011 vmw_stdu_destroy(vmw_connector_to_stdu(connector));
1012}
1013
1014
1015
1016static const struct drm_connector_funcs vmw_stdu_connector_funcs = {
1017 .dpms = vmw_du_connector_dpms,
1018 .detect = vmw_du_connector_detect,
1019 .fill_modes = vmw_du_connector_fill_modes,
1020 .set_property = vmw_du_connector_set_property,
1021 .destroy = vmw_stdu_connector_destroy,
1022 .reset = vmw_du_connector_reset,
1023 .atomic_duplicate_state = vmw_du_connector_duplicate_state,
1024 .atomic_destroy_state = vmw_du_connector_destroy_state,
1025 .atomic_set_property = vmw_du_connector_atomic_set_property,
1026 .atomic_get_property = vmw_du_connector_atomic_get_property,
1027};
1028
1029
1030static const struct
1031drm_connector_helper_funcs vmw_stdu_connector_helper_funcs = {
1032 .best_encoder = drm_atomic_helper_best_encoder,
1033};
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053static void
1054vmw_stdu_primary_plane_cleanup_fb(struct drm_plane *plane,
1055 struct drm_plane_state *old_state)
1056{
1057 struct vmw_plane_state *vps = vmw_plane_state_to_vps(old_state);
1058
1059 if (vps->surf)
1060 WARN_ON(!vps->pinned);
1061
1062 vmw_du_plane_cleanup_fb(plane, old_state);
1063
1064 vps->content_fb_type = SAME_AS_DISPLAY;
1065 vps->cpp = 0;
1066}
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082static int
1083vmw_stdu_primary_plane_prepare_fb(struct drm_plane *plane,
1084 struct drm_plane_state *new_state)
1085{
1086 struct vmw_private *dev_priv = vmw_priv(plane->dev);
1087 struct drm_framebuffer *new_fb = new_state->fb;
1088 struct vmw_framebuffer *vfb;
1089 struct vmw_plane_state *vps = vmw_plane_state_to_vps(new_state);
1090 enum stdu_content_type new_content_type;
1091 struct vmw_framebuffer_surface *new_vfbs;
1092 struct drm_crtc *crtc = new_state->crtc;
1093 uint32_t hdisplay = new_state->crtc_w, vdisplay = new_state->crtc_h;
1094 int ret;
1095
1096
1097 if (!new_fb) {
1098 if (vps->surf) {
1099 WARN_ON(vps->pinned != 0);
1100 vmw_surface_unreference(&vps->surf);
1101 }
1102
1103 return 0;
1104 }
1105
1106 vfb = vmw_framebuffer_to_vfb(new_fb);
1107 new_vfbs = (vfb->dmabuf) ? NULL : vmw_framebuffer_to_vfbs(new_fb);
1108
1109 if (new_vfbs && new_vfbs->surface->base_size.width == hdisplay &&
1110 new_vfbs->surface->base_size.height == vdisplay)
1111 new_content_type = SAME_AS_DISPLAY;
1112 else if (vfb->dmabuf)
1113 new_content_type = SEPARATE_DMA;
1114 else
1115 new_content_type = SEPARATE_SURFACE;
1116
1117 if (new_content_type != SAME_AS_DISPLAY) {
1118 struct vmw_surface content_srf;
1119 struct drm_vmw_size display_base_size = {0};
1120
1121 display_base_size.width = hdisplay;
1122 display_base_size.height = vdisplay;
1123 display_base_size.depth = 1;
1124
1125
1126
1127
1128
1129 if (new_content_type == SEPARATE_DMA) {
1130
1131 switch (new_fb->format->cpp[0]*8) {
1132 case 32:
1133 content_srf.format = SVGA3D_X8R8G8B8;
1134 break;
1135
1136 case 16:
1137 content_srf.format = SVGA3D_R5G6B5;
1138 break;
1139
1140 case 8:
1141 content_srf.format = SVGA3D_P8;
1142 break;
1143
1144 default:
1145 DRM_ERROR("Invalid format\n");
1146 return -EINVAL;
1147 }
1148
1149 content_srf.flags = 0;
1150 content_srf.mip_levels[0] = 1;
1151 content_srf.multisample_count = 0;
1152 } else {
1153 content_srf = *new_vfbs->surface;
1154 }
1155
1156 if (vps->surf) {
1157 struct drm_vmw_size cur_base_size = vps->surf->base_size;
1158
1159 if (cur_base_size.width != display_base_size.width ||
1160 cur_base_size.height != display_base_size.height ||
1161 vps->surf->format != content_srf.format) {
1162 WARN_ON(vps->pinned != 0);
1163 vmw_surface_unreference(&vps->surf);
1164 }
1165
1166 }
1167
1168 if (!vps->surf) {
1169 ret = vmw_surface_gb_priv_define
1170 (crtc->dev,
1171
1172 0,
1173 content_srf.flags,
1174 content_srf.format,
1175 true,
1176 content_srf.mip_levels[0],
1177 content_srf.multisample_count,
1178 0,
1179 display_base_size,
1180 &vps->surf);
1181 if (ret != 0) {
1182 DRM_ERROR("Couldn't allocate STDU surface.\n");
1183 return ret;
1184 }
1185 }
1186 } else {
1187
1188
1189
1190
1191
1192
1193 if (vps->surf) {
1194 WARN_ON(vps->pinned != 0);
1195 vmw_surface_unreference(&vps->surf);
1196 }
1197
1198 vps->surf = vmw_surface_reference(new_vfbs->surface);
1199 }
1200
1201 if (vps->surf) {
1202
1203
1204 ret = vmw_resource_pin(&vps->surf->res, false);
1205 if (ret)
1206 goto out_srf_unref;
1207
1208 vps->pinned++;
1209 }
1210
1211 vps->content_fb_type = new_content_type;
1212
1213
1214
1215
1216
1217
1218
1219 if (vps->content_fb_type == SEPARATE_DMA &&
1220 !(dev_priv->capabilities & SVGA_CAP_3D))
1221 vps->cpp = new_fb->pitches[0] / new_fb->width;
1222
1223 return 0;
1224
1225out_srf_unref:
1226 vmw_surface_unreference(&vps->surf);
1227 return ret;
1228}
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243static void
1244vmw_stdu_primary_plane_atomic_update(struct drm_plane *plane,
1245 struct drm_plane_state *old_state)
1246{
1247 struct vmw_plane_state *vps = vmw_plane_state_to_vps(plane->state);
1248 struct drm_crtc *crtc = plane->state->crtc;
1249 struct vmw_screen_target_display_unit *stdu;
1250 struct drm_pending_vblank_event *event;
1251 struct vmw_private *dev_priv;
1252 int ret;
1253
1254
1255
1256
1257
1258 if (crtc && plane->state->fb) {
1259 struct vmw_framebuffer *vfb =
1260 vmw_framebuffer_to_vfb(plane->state->fb);
1261 struct drm_vmw_rect vclips;
1262 stdu = vmw_crtc_to_stdu(crtc);
1263 dev_priv = vmw_priv(crtc->dev);
1264
1265 stdu->display_srf = vps->surf;
1266 stdu->content_fb_type = vps->content_fb_type;
1267 stdu->cpp = vps->cpp;
1268
1269 vclips.x = crtc->x;
1270 vclips.y = crtc->y;
1271 vclips.w = crtc->mode.hdisplay;
1272 vclips.h = crtc->mode.vdisplay;
1273
1274 ret = vmw_stdu_bind_st(dev_priv, stdu, &stdu->display_srf->res);
1275 if (ret)
1276 DRM_ERROR("Failed to bind surface to STDU.\n");
1277
1278 if (vfb->dmabuf)
1279 ret = vmw_kms_stdu_dma(dev_priv, NULL, vfb, NULL, NULL,
1280 &vclips, 1, 1, true, false,
1281 crtc);
1282 else
1283 ret = vmw_kms_stdu_surface_dirty(dev_priv, vfb, NULL,
1284 &vclips, NULL, 0, 0,
1285 1, 1, NULL, crtc);
1286 if (ret)
1287 DRM_ERROR("Failed to update STDU.\n");
1288
1289 crtc->primary->fb = plane->state->fb;
1290 } else {
1291 crtc = old_state->crtc;
1292 stdu = vmw_crtc_to_stdu(crtc);
1293 dev_priv = vmw_priv(crtc->dev);
1294
1295
1296
1297
1298
1299
1300
1301 if (!stdu->defined)
1302 return;
1303
1304 ret = vmw_stdu_bind_st(dev_priv, stdu, NULL);
1305 if (ret)
1306 DRM_ERROR("Failed to blank STDU\n");
1307
1308 ret = vmw_stdu_update_st(dev_priv, stdu);
1309 if (ret)
1310 DRM_ERROR("Failed to update STDU.\n");
1311
1312 return;
1313 }
1314
1315 event = crtc->state->event;
1316
1317
1318
1319
1320 if (event && (ret == 0)) {
1321 struct vmw_fence_obj *fence = NULL;
1322 struct drm_file *file_priv = event->base.file_priv;
1323
1324 vmw_execbuf_fence_commands(NULL, dev_priv, &fence, NULL);
1325
1326
1327
1328
1329 if (fence) {
1330 ret = vmw_event_fence_action_queue(
1331 file_priv, fence, &event->base,
1332 &event->event.vbl.tv_sec,
1333 &event->event.vbl.tv_usec,
1334 true);
1335 if (ret)
1336 DRM_ERROR("Failed to queue event on fence.\n");
1337 else
1338 crtc->state->event = NULL;
1339
1340 vmw_fence_obj_unreference(&fence);
1341 }
1342 } else {
1343 (void) vmw_fifo_flush(dev_priv, false);
1344 }
1345}
1346
1347
1348static const struct drm_plane_funcs vmw_stdu_plane_funcs = {
1349 .update_plane = drm_atomic_helper_update_plane,
1350 .disable_plane = drm_atomic_helper_disable_plane,
1351 .destroy = vmw_du_primary_plane_destroy,
1352 .reset = vmw_du_plane_reset,
1353 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
1354 .atomic_destroy_state = vmw_du_plane_destroy_state,
1355};
1356
1357static const struct drm_plane_funcs vmw_stdu_cursor_funcs = {
1358 .update_plane = drm_atomic_helper_update_plane,
1359 .disable_plane = drm_atomic_helper_disable_plane,
1360 .destroy = vmw_du_cursor_plane_destroy,
1361 .reset = vmw_du_plane_reset,
1362 .atomic_duplicate_state = vmw_du_plane_duplicate_state,
1363 .atomic_destroy_state = vmw_du_plane_destroy_state,
1364};
1365
1366
1367
1368
1369
1370static const struct
1371drm_plane_helper_funcs vmw_stdu_cursor_plane_helper_funcs = {
1372 .atomic_check = vmw_du_cursor_plane_atomic_check,
1373 .atomic_update = vmw_du_cursor_plane_atomic_update,
1374 .prepare_fb = vmw_du_cursor_plane_prepare_fb,
1375 .cleanup_fb = vmw_du_plane_cleanup_fb,
1376};
1377
1378static const struct
1379drm_plane_helper_funcs vmw_stdu_primary_plane_helper_funcs = {
1380 .atomic_check = vmw_du_primary_plane_atomic_check,
1381 .atomic_update = vmw_stdu_primary_plane_atomic_update,
1382 .prepare_fb = vmw_stdu_primary_plane_prepare_fb,
1383 .cleanup_fb = vmw_stdu_primary_plane_cleanup_fb,
1384};
1385
1386static const struct drm_crtc_helper_funcs vmw_stdu_crtc_helper_funcs = {
1387 .prepare = vmw_stdu_crtc_helper_prepare,
1388 .mode_set_nofb = vmw_stdu_crtc_mode_set_nofb,
1389 .atomic_check = vmw_du_crtc_atomic_check,
1390 .atomic_begin = vmw_du_crtc_atomic_begin,
1391 .atomic_flush = vmw_du_crtc_atomic_flush,
1392 .atomic_enable = vmw_stdu_crtc_atomic_enable,
1393 .atomic_disable = vmw_stdu_crtc_atomic_disable,
1394};
1395
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405
1406
1407static int vmw_stdu_init(struct vmw_private *dev_priv, unsigned unit)
1408{
1409 struct vmw_screen_target_display_unit *stdu;
1410 struct drm_device *dev = dev_priv->dev;
1411 struct drm_connector *connector;
1412 struct drm_encoder *encoder;
1413 struct drm_plane *primary, *cursor;
1414 struct drm_crtc *crtc;
1415 int ret;
1416
1417
1418 stdu = kzalloc(sizeof(*stdu), GFP_KERNEL);
1419 if (!stdu)
1420 return -ENOMEM;
1421
1422 stdu->base.unit = unit;
1423 crtc = &stdu->base.crtc;
1424 encoder = &stdu->base.encoder;
1425 connector = &stdu->base.connector;
1426 primary = &stdu->base.primary;
1427 cursor = &stdu->base.cursor;
1428
1429 stdu->base.pref_active = (unit == 0);
1430 stdu->base.pref_width = dev_priv->initial_width;
1431 stdu->base.pref_height = dev_priv->initial_height;
1432
1433
1434
1435
1436
1437 stdu->base.is_implicit = false;
1438
1439
1440 vmw_du_plane_reset(primary);
1441
1442 ret = drm_universal_plane_init(dev, primary,
1443 0, &vmw_stdu_plane_funcs,
1444 vmw_primary_plane_formats,
1445 ARRAY_SIZE(vmw_primary_plane_formats),
1446 NULL, DRM_PLANE_TYPE_PRIMARY, NULL);
1447 if (ret) {
1448 DRM_ERROR("Failed to initialize primary plane");
1449 goto err_free;
1450 }
1451
1452 drm_plane_helper_add(primary, &vmw_stdu_primary_plane_helper_funcs);
1453
1454
1455 vmw_du_plane_reset(cursor);
1456
1457 ret = drm_universal_plane_init(dev, cursor,
1458 0, &vmw_stdu_cursor_funcs,
1459 vmw_cursor_plane_formats,
1460 ARRAY_SIZE(vmw_cursor_plane_formats),
1461 NULL, DRM_PLANE_TYPE_CURSOR, NULL);
1462 if (ret) {
1463 DRM_ERROR("Failed to initialize cursor plane");
1464 drm_plane_cleanup(&stdu->base.primary);
1465 goto err_free;
1466 }
1467
1468 drm_plane_helper_add(cursor, &vmw_stdu_cursor_plane_helper_funcs);
1469
1470 vmw_du_connector_reset(connector);
1471
1472 ret = drm_connector_init(dev, connector, &vmw_stdu_connector_funcs,
1473 DRM_MODE_CONNECTOR_VIRTUAL);
1474 if (ret) {
1475 DRM_ERROR("Failed to initialize connector\n");
1476 goto err_free;
1477 }
1478
1479 drm_connector_helper_add(connector, &vmw_stdu_connector_helper_funcs);
1480 connector->status = vmw_du_connector_detect(connector, false);
1481 vmw_connector_state_to_vcs(connector->state)->is_implicit = false;
1482
1483 ret = drm_encoder_init(dev, encoder, &vmw_stdu_encoder_funcs,
1484 DRM_MODE_ENCODER_VIRTUAL, NULL);
1485 if (ret) {
1486 DRM_ERROR("Failed to initialize encoder\n");
1487 goto err_free_connector;
1488 }
1489
1490 (void) drm_mode_connector_attach_encoder(connector, encoder);
1491 encoder->possible_crtcs = (1 << unit);
1492 encoder->possible_clones = 0;
1493
1494 ret = drm_connector_register(connector);
1495 if (ret) {
1496 DRM_ERROR("Failed to register connector\n");
1497 goto err_free_encoder;
1498 }
1499
1500 vmw_du_crtc_reset(crtc);
1501 ret = drm_crtc_init_with_planes(dev, crtc, &stdu->base.primary,
1502 &stdu->base.cursor,
1503 &vmw_stdu_crtc_funcs, NULL);
1504 if (ret) {
1505 DRM_ERROR("Failed to initialize CRTC\n");
1506 goto err_free_unregister;
1507 }
1508
1509 drm_crtc_helper_add(crtc, &vmw_stdu_crtc_helper_funcs);
1510
1511 drm_mode_crtc_set_gamma_size(crtc, 256);
1512
1513 drm_object_attach_property(&connector->base,
1514 dev_priv->hotplug_mode_update_property, 1);
1515 drm_object_attach_property(&connector->base,
1516 dev->mode_config.suggested_x_property, 0);
1517 drm_object_attach_property(&connector->base,
1518 dev->mode_config.suggested_y_property, 0);
1519 if (dev_priv->implicit_placement_property)
1520 drm_object_attach_property
1521 (&connector->base,
1522 dev_priv->implicit_placement_property,
1523 stdu->base.is_implicit);
1524 return 0;
1525
1526err_free_unregister:
1527 drm_connector_unregister(connector);
1528err_free_encoder:
1529 drm_encoder_cleanup(encoder);
1530err_free_connector:
1531 drm_connector_cleanup(connector);
1532err_free:
1533 kfree(stdu);
1534 return ret;
1535}
1536
1537
1538
1539
1540
1541
1542
1543
1544
1545
1546static void vmw_stdu_destroy(struct vmw_screen_target_display_unit *stdu)
1547{
1548 vmw_du_cleanup(&stdu->base);
1549 kfree(stdu);
1550}
1551
1552
1553
1554
1555
1556
1557
1558
1559
1560
1561
1562
1563
1564
1565
1566
1567
1568
1569
1570
1571
1572
1573int vmw_kms_stdu_init_display(struct vmw_private *dev_priv)
1574{
1575 struct drm_device *dev = dev_priv->dev;
1576 int i, ret;
1577
1578
1579
1580 if (!VMWGFX_ENABLE_SCREEN_TARGET_OTABLE)
1581 return -ENOSYS;
1582
1583 if (!(dev_priv->capabilities & SVGA_CAP_GBOBJECTS))
1584 return -ENOSYS;
1585
1586 ret = drm_vblank_init(dev, VMWGFX_NUM_DISPLAY_UNITS);
1587 if (unlikely(ret != 0))
1588 return ret;
1589
1590 dev_priv->active_display_unit = vmw_du_screen_target;
1591
1592 if (dev_priv->capabilities & SVGA_CAP_3D) {
1593
1594
1595
1596
1597 uint32_t max_width, max_height;
1598
1599 max_width = min(dev_priv->texture_max_width,
1600 dev_priv->stdu_max_width);
1601 max_height = min(dev_priv->texture_max_height,
1602 dev_priv->stdu_max_height);
1603
1604 dev->mode_config.max_width = max_width;
1605 dev->mode_config.max_height = max_height;
1606 } else {
1607
1608
1609
1610
1611
1612
1613 dev->mode_config.max_width = 8192;
1614 dev->mode_config.max_height = 8192;
1615 }
1616
1617 vmw_kms_create_implicit_placement_property(dev_priv, false);
1618
1619 for (i = 0; i < VMWGFX_NUM_DISPLAY_UNITS; ++i) {
1620 ret = vmw_stdu_init(dev_priv, i);
1621
1622 if (unlikely(ret != 0)) {
1623 DRM_ERROR("Failed to initialize STDU %d", i);
1624 return ret;
1625 }
1626 }
1627
1628 DRM_INFO("Screen Target Display device initialized\n");
1629
1630 return 0;
1631}
1632