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15#include <linux/export.h>
16#include <linux/module.h>
17#include <linux/types.h>
18#include <linux/errno.h>
19#include <linux/delay.h>
20#include <linux/io.h>
21#include <linux/err.h>
22#include <linux/platform_device.h>
23#include <linux/videodev2.h>
24#include <uapi/linux/v4l2-mediabus.h>
25#include <linux/clk.h>
26#include <linux/clk-provider.h>
27#include <linux/clkdev.h>
28
29#include "ipu-prv.h"
30
31struct ipu_csi {
32 void __iomem *base;
33 int id;
34 u32 module;
35 struct clk *clk_ipu;
36 spinlock_t lock;
37 bool inuse;
38 struct ipu_soc *ipu;
39};
40
41
42#define CSI_SENS_CONF 0x0000
43#define CSI_SENS_FRM_SIZE 0x0004
44#define CSI_ACT_FRM_SIZE 0x0008
45#define CSI_OUT_FRM_CTRL 0x000c
46#define CSI_TST_CTRL 0x0010
47#define CSI_CCIR_CODE_1 0x0014
48#define CSI_CCIR_CODE_2 0x0018
49#define CSI_CCIR_CODE_3 0x001c
50#define CSI_MIPI_DI 0x0020
51#define CSI_SKIP 0x0024
52#define CSI_CPD_CTRL 0x0028
53#define CSI_CPD_RC(n) (0x002c + ((n)*4))
54#define CSI_CPD_RS(n) (0x004c + ((n)*4))
55#define CSI_CPD_GRC(n) (0x005c + ((n)*4))
56#define CSI_CPD_GRS(n) (0x007c + ((n)*4))
57#define CSI_CPD_GBC(n) (0x008c + ((n)*4))
58#define CSI_CPD_GBS(n) (0x00Ac + ((n)*4))
59#define CSI_CPD_BC(n) (0x00Bc + ((n)*4))
60#define CSI_CPD_BS(n) (0x00Dc + ((n)*4))
61#define CSI_CPD_OFFSET1 0x00ec
62#define CSI_CPD_OFFSET2 0x00f0
63
64
65#define CSI_SENS_CONF_DATA_FMT_SHIFT 8
66#define CSI_SENS_CONF_DATA_FMT_MASK 0x00000700
67#define CSI_SENS_CONF_DATA_FMT_RGB_YUV444 0L
68#define CSI_SENS_CONF_DATA_FMT_YUV422_YUYV 1L
69#define CSI_SENS_CONF_DATA_FMT_YUV422_UYVY 2L
70#define CSI_SENS_CONF_DATA_FMT_BAYER 3L
71#define CSI_SENS_CONF_DATA_FMT_RGB565 4L
72#define CSI_SENS_CONF_DATA_FMT_RGB555 5L
73#define CSI_SENS_CONF_DATA_FMT_RGB444 6L
74#define CSI_SENS_CONF_DATA_FMT_JPEG 7L
75
76#define CSI_SENS_CONF_VSYNC_POL_SHIFT 0
77#define CSI_SENS_CONF_HSYNC_POL_SHIFT 1
78#define CSI_SENS_CONF_DATA_POL_SHIFT 2
79#define CSI_SENS_CONF_PIX_CLK_POL_SHIFT 3
80#define CSI_SENS_CONF_SENS_PRTCL_MASK 0x00000070
81#define CSI_SENS_CONF_SENS_PRTCL_SHIFT 4
82#define CSI_SENS_CONF_PACK_TIGHT_SHIFT 7
83#define CSI_SENS_CONF_DATA_WIDTH_SHIFT 11
84#define CSI_SENS_CONF_EXT_VSYNC_SHIFT 15
85#define CSI_SENS_CONF_DIVRATIO_SHIFT 16
86
87#define CSI_SENS_CONF_DIVRATIO_MASK 0x00ff0000
88#define CSI_SENS_CONF_DATA_DEST_SHIFT 24
89#define CSI_SENS_CONF_DATA_DEST_MASK 0x07000000
90#define CSI_SENS_CONF_JPEG8_EN_SHIFT 27
91#define CSI_SENS_CONF_JPEG_EN_SHIFT 28
92#define CSI_SENS_CONF_FORCE_EOF_SHIFT 29
93#define CSI_SENS_CONF_DATA_EN_POL_SHIFT 31
94
95#define CSI_DATA_DEST_IC 2
96#define CSI_DATA_DEST_IDMAC 4
97
98#define CSI_CCIR_ERR_DET_EN 0x01000000
99#define CSI_HORI_DOWNSIZE_EN 0x80000000
100#define CSI_VERT_DOWNSIZE_EN 0x40000000
101#define CSI_TEST_GEN_MODE_EN 0x01000000
102
103#define CSI_HSC_MASK 0x1fff0000
104#define CSI_HSC_SHIFT 16
105#define CSI_VSC_MASK 0x00000fff
106#define CSI_VSC_SHIFT 0
107
108#define CSI_TEST_GEN_R_MASK 0x000000ff
109#define CSI_TEST_GEN_R_SHIFT 0
110#define CSI_TEST_GEN_G_MASK 0x0000ff00
111#define CSI_TEST_GEN_G_SHIFT 8
112#define CSI_TEST_GEN_B_MASK 0x00ff0000
113#define CSI_TEST_GEN_B_SHIFT 16
114
115#define CSI_MAX_RATIO_SKIP_SMFC_MASK 0x00000007
116#define CSI_MAX_RATIO_SKIP_SMFC_SHIFT 0
117#define CSI_SKIP_SMFC_MASK 0x000000f8
118#define CSI_SKIP_SMFC_SHIFT 3
119#define CSI_ID_2_SKIP_MASK 0x00000300
120#define CSI_ID_2_SKIP_SHIFT 8
121
122#define CSI_COLOR_FIRST_ROW_MASK 0x00000002
123#define CSI_COLOR_FIRST_COMP_MASK 0x00000001
124
125
126#define MIPI_DT_YUV420 0x18
127#define MIPI_DT_YUV420_LEGACY 0x1a
128#define MIPI_DT_YUV422 0x1e
129#define MIPI_DT_RGB444 0x20
130#define MIPI_DT_RGB555 0x21
131#define MIPI_DT_RGB565 0x22
132#define MIPI_DT_RGB666 0x23
133#define MIPI_DT_RGB888 0x24
134#define MIPI_DT_RAW6 0x28
135#define MIPI_DT_RAW7 0x29
136#define MIPI_DT_RAW8 0x2a
137#define MIPI_DT_RAW10 0x2b
138#define MIPI_DT_RAW12 0x2c
139#define MIPI_DT_RAW14 0x2d
140
141
142
143
144struct ipu_csi_bus_config {
145 unsigned data_width:4;
146 unsigned clk_mode:3;
147 unsigned ext_vsync:1;
148 unsigned vsync_pol:1;
149 unsigned hsync_pol:1;
150 unsigned pixclk_pol:1;
151 unsigned data_pol:1;
152 unsigned sens_clksrc:1;
153 unsigned pack_tight:1;
154 unsigned force_eof:1;
155 unsigned data_en_pol:1;
156
157 unsigned data_fmt;
158 unsigned mipi_dt;
159};
160
161
162
163
164enum ipu_csi_data_width {
165 IPU_CSI_DATA_WIDTH_4 = 0,
166 IPU_CSI_DATA_WIDTH_8 = 1,
167 IPU_CSI_DATA_WIDTH_10 = 3,
168 IPU_CSI_DATA_WIDTH_12 = 5,
169 IPU_CSI_DATA_WIDTH_16 = 9,
170};
171
172
173
174
175enum ipu_csi_clk_mode {
176 IPU_CSI_CLK_MODE_GATED_CLK,
177 IPU_CSI_CLK_MODE_NONGATED_CLK,
178 IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE,
179 IPU_CSI_CLK_MODE_CCIR656_INTERLACED,
180 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR,
181 IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR,
182 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR,
183 IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR,
184};
185
186static inline u32 ipu_csi_read(struct ipu_csi *csi, unsigned offset)
187{
188 return readl(csi->base + offset);
189}
190
191static inline void ipu_csi_write(struct ipu_csi *csi, u32 value,
192 unsigned offset)
193{
194 writel(value, csi->base + offset);
195}
196
197
198
199
200
201static int ipu_csi_set_testgen_mclk(struct ipu_csi *csi, u32 pixel_clk,
202 u32 ipu_clk)
203{
204 u32 temp;
205 int div_ratio;
206
207 div_ratio = (ipu_clk / pixel_clk) - 1;
208
209 if (div_ratio > 0xFF || div_ratio < 0) {
210 dev_err(csi->ipu->dev,
211 "value of pixel_clk extends normal range\n");
212 return -EINVAL;
213 }
214
215 temp = ipu_csi_read(csi, CSI_SENS_CONF);
216 temp &= ~CSI_SENS_CONF_DIVRATIO_MASK;
217 ipu_csi_write(csi, temp | (div_ratio << CSI_SENS_CONF_DIVRATIO_SHIFT),
218 CSI_SENS_CONF);
219
220 return 0;
221}
222
223
224
225
226
227static int mbus_code_to_bus_cfg(struct ipu_csi_bus_config *cfg, u32 mbus_code)
228{
229 switch (mbus_code) {
230 case MEDIA_BUS_FMT_BGR565_2X8_BE:
231 case MEDIA_BUS_FMT_BGR565_2X8_LE:
232 case MEDIA_BUS_FMT_RGB565_2X8_BE:
233 case MEDIA_BUS_FMT_RGB565_2X8_LE:
234 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB565;
235 cfg->mipi_dt = MIPI_DT_RGB565;
236 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
237 break;
238 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_BE:
239 case MEDIA_BUS_FMT_RGB444_2X8_PADHI_LE:
240 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB444;
241 cfg->mipi_dt = MIPI_DT_RGB444;
242 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
243 break;
244 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_BE:
245 case MEDIA_BUS_FMT_RGB555_2X8_PADHI_LE:
246 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_RGB555;
247 cfg->mipi_dt = MIPI_DT_RGB555;
248 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
249 break;
250 case MEDIA_BUS_FMT_UYVY8_2X8:
251 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_UYVY;
252 cfg->mipi_dt = MIPI_DT_YUV422;
253 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
254 break;
255 case MEDIA_BUS_FMT_YUYV8_2X8:
256 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_YUV422_YUYV;
257 cfg->mipi_dt = MIPI_DT_YUV422;
258 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
259 break;
260 case MEDIA_BUS_FMT_UYVY8_1X16:
261 case MEDIA_BUS_FMT_YUYV8_1X16:
262 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
263 cfg->mipi_dt = MIPI_DT_YUV422;
264 cfg->data_width = IPU_CSI_DATA_WIDTH_16;
265 break;
266 case MEDIA_BUS_FMT_SBGGR8_1X8:
267 case MEDIA_BUS_FMT_SGBRG8_1X8:
268 case MEDIA_BUS_FMT_SGRBG8_1X8:
269 case MEDIA_BUS_FMT_SRGGB8_1X8:
270 case MEDIA_BUS_FMT_Y8_1X8:
271 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
272 cfg->mipi_dt = MIPI_DT_RAW8;
273 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
274 break;
275 case MEDIA_BUS_FMT_SBGGR10_DPCM8_1X8:
276 case MEDIA_BUS_FMT_SGBRG10_DPCM8_1X8:
277 case MEDIA_BUS_FMT_SGRBG10_DPCM8_1X8:
278 case MEDIA_BUS_FMT_SRGGB10_DPCM8_1X8:
279 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_BE:
280 case MEDIA_BUS_FMT_SBGGR10_2X8_PADHI_LE:
281 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_BE:
282 case MEDIA_BUS_FMT_SBGGR10_2X8_PADLO_LE:
283 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
284 cfg->mipi_dt = MIPI_DT_RAW10;
285 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
286 break;
287 case MEDIA_BUS_FMT_SBGGR10_1X10:
288 case MEDIA_BUS_FMT_SGBRG10_1X10:
289 case MEDIA_BUS_FMT_SGRBG10_1X10:
290 case MEDIA_BUS_FMT_SRGGB10_1X10:
291 case MEDIA_BUS_FMT_Y10_1X10:
292 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
293 cfg->mipi_dt = MIPI_DT_RAW10;
294 cfg->data_width = IPU_CSI_DATA_WIDTH_10;
295 break;
296 case MEDIA_BUS_FMT_SBGGR12_1X12:
297 case MEDIA_BUS_FMT_SGBRG12_1X12:
298 case MEDIA_BUS_FMT_SGRBG12_1X12:
299 case MEDIA_BUS_FMT_SRGGB12_1X12:
300 case MEDIA_BUS_FMT_Y12_1X12:
301 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_BAYER;
302 cfg->mipi_dt = MIPI_DT_RAW12;
303 cfg->data_width = IPU_CSI_DATA_WIDTH_12;
304 break;
305 case MEDIA_BUS_FMT_JPEG_1X8:
306
307 cfg->data_fmt = CSI_SENS_CONF_DATA_FMT_JPEG;
308 cfg->mipi_dt = MIPI_DT_RAW8;
309 cfg->data_width = IPU_CSI_DATA_WIDTH_8;
310 break;
311 default:
312 return -EINVAL;
313 }
314
315 return 0;
316}
317
318
319
320
321static void fill_csi_bus_cfg(struct ipu_csi_bus_config *csicfg,
322 struct v4l2_mbus_config *mbus_cfg,
323 struct v4l2_mbus_framefmt *mbus_fmt)
324{
325 memset(csicfg, 0, sizeof(*csicfg));
326
327 mbus_code_to_bus_cfg(csicfg, mbus_fmt->code);
328
329 switch (mbus_cfg->type) {
330 case V4L2_MBUS_PARALLEL:
331 csicfg->ext_vsync = 1;
332 csicfg->vsync_pol = (mbus_cfg->flags &
333 V4L2_MBUS_VSYNC_ACTIVE_LOW) ? 1 : 0;
334 csicfg->hsync_pol = (mbus_cfg->flags &
335 V4L2_MBUS_HSYNC_ACTIVE_LOW) ? 1 : 0;
336 csicfg->pixclk_pol = (mbus_cfg->flags &
337 V4L2_MBUS_PCLK_SAMPLE_FALLING) ? 1 : 0;
338 csicfg->clk_mode = IPU_CSI_CLK_MODE_GATED_CLK;
339 break;
340 case V4L2_MBUS_BT656:
341 csicfg->ext_vsync = 0;
342 if (V4L2_FIELD_HAS_BOTH(mbus_fmt->field))
343 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_INTERLACED;
344 else
345 csicfg->clk_mode = IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE;
346 break;
347 case V4L2_MBUS_CSI2:
348
349
350
351
352 csicfg->clk_mode = IPU_CSI_CLK_MODE_NONGATED_CLK;
353 break;
354 default:
355
356 break;
357 }
358}
359
360int ipu_csi_init_interface(struct ipu_csi *csi,
361 struct v4l2_mbus_config *mbus_cfg,
362 struct v4l2_mbus_framefmt *mbus_fmt)
363{
364 struct ipu_csi_bus_config cfg;
365 unsigned long flags;
366 u32 width, height, data = 0;
367
368 fill_csi_bus_cfg(&cfg, mbus_cfg, mbus_fmt);
369
370
371 width = mbus_fmt->width;
372 height = mbus_fmt->height;
373
374
375 data |= cfg.data_width << CSI_SENS_CONF_DATA_WIDTH_SHIFT |
376 cfg.data_fmt << CSI_SENS_CONF_DATA_FMT_SHIFT |
377 cfg.data_pol << CSI_SENS_CONF_DATA_POL_SHIFT |
378 cfg.vsync_pol << CSI_SENS_CONF_VSYNC_POL_SHIFT |
379 cfg.hsync_pol << CSI_SENS_CONF_HSYNC_POL_SHIFT |
380 cfg.pixclk_pol << CSI_SENS_CONF_PIX_CLK_POL_SHIFT |
381 cfg.ext_vsync << CSI_SENS_CONF_EXT_VSYNC_SHIFT |
382 cfg.clk_mode << CSI_SENS_CONF_SENS_PRTCL_SHIFT |
383 cfg.pack_tight << CSI_SENS_CONF_PACK_TIGHT_SHIFT |
384 cfg.force_eof << CSI_SENS_CONF_FORCE_EOF_SHIFT |
385 cfg.data_en_pol << CSI_SENS_CONF_DATA_EN_POL_SHIFT;
386
387 spin_lock_irqsave(&csi->lock, flags);
388
389 ipu_csi_write(csi, data, CSI_SENS_CONF);
390
391
392
393 switch (cfg.clk_mode) {
394 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
395 ipu_csi_write(csi, 0x40030, CSI_CCIR_CODE_1);
396 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
397 break;
398 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
399 if (mbus_fmt->width == 720 && mbus_fmt->height == 576) {
400
401
402
403
404
405
406
407
408 height = 625;
409
410 ipu_csi_write(csi, 0x40596 | CSI_CCIR_ERR_DET_EN,
411 CSI_CCIR_CODE_1);
412 ipu_csi_write(csi, 0xD07DF, CSI_CCIR_CODE_2);
413 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
414 } else if (mbus_fmt->width == 720 && mbus_fmt->height == 480) {
415
416
417
418
419
420
421
422
423 height = 525;
424
425 ipu_csi_write(csi, 0xD07DF | CSI_CCIR_ERR_DET_EN,
426 CSI_CCIR_CODE_1);
427 ipu_csi_write(csi, 0x40596, CSI_CCIR_CODE_2);
428 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
429 } else {
430 dev_err(csi->ipu->dev,
431 "Unsupported CCIR656 interlaced video mode\n");
432 spin_unlock_irqrestore(&csi->lock, flags);
433 return -EINVAL;
434 }
435 break;
436 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
437 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
438 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
439 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
440 ipu_csi_write(csi, 0x40030 | CSI_CCIR_ERR_DET_EN,
441 CSI_CCIR_CODE_1);
442 ipu_csi_write(csi, 0xFF0000, CSI_CCIR_CODE_3);
443 break;
444 case IPU_CSI_CLK_MODE_GATED_CLK:
445 case IPU_CSI_CLK_MODE_NONGATED_CLK:
446 ipu_csi_write(csi, 0, CSI_CCIR_CODE_1);
447 break;
448 }
449
450
451 ipu_csi_write(csi, (width - 1) | ((height - 1) << 16),
452 CSI_SENS_FRM_SIZE);
453
454 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF = 0x%08X\n",
455 ipu_csi_read(csi, CSI_SENS_CONF));
456 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE = 0x%08X\n",
457 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
458
459 spin_unlock_irqrestore(&csi->lock, flags);
460
461 return 0;
462}
463EXPORT_SYMBOL_GPL(ipu_csi_init_interface);
464
465bool ipu_csi_is_interlaced(struct ipu_csi *csi)
466{
467 unsigned long flags;
468 u32 sensor_protocol;
469
470 spin_lock_irqsave(&csi->lock, flags);
471 sensor_protocol =
472 (ipu_csi_read(csi, CSI_SENS_CONF) &
473 CSI_SENS_CONF_SENS_PRTCL_MASK) >>
474 CSI_SENS_CONF_SENS_PRTCL_SHIFT;
475 spin_unlock_irqrestore(&csi->lock, flags);
476
477 switch (sensor_protocol) {
478 case IPU_CSI_CLK_MODE_GATED_CLK:
479 case IPU_CSI_CLK_MODE_NONGATED_CLK:
480 case IPU_CSI_CLK_MODE_CCIR656_PROGRESSIVE:
481 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_DDR:
482 case IPU_CSI_CLK_MODE_CCIR1120_PROGRESSIVE_SDR:
483 return false;
484 case IPU_CSI_CLK_MODE_CCIR656_INTERLACED:
485 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_DDR:
486 case IPU_CSI_CLK_MODE_CCIR1120_INTERLACED_SDR:
487 return true;
488 default:
489 dev_err(csi->ipu->dev,
490 "CSI %d sensor protocol unsupported\n", csi->id);
491 return false;
492 }
493}
494EXPORT_SYMBOL_GPL(ipu_csi_is_interlaced);
495
496void ipu_csi_get_window(struct ipu_csi *csi, struct v4l2_rect *w)
497{
498 unsigned long flags;
499 u32 reg;
500
501 spin_lock_irqsave(&csi->lock, flags);
502
503 reg = ipu_csi_read(csi, CSI_ACT_FRM_SIZE);
504 w->width = (reg & 0xFFFF) + 1;
505 w->height = (reg >> 16 & 0xFFFF) + 1;
506
507 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
508 w->left = (reg & CSI_HSC_MASK) >> CSI_HSC_SHIFT;
509 w->top = (reg & CSI_VSC_MASK) >> CSI_VSC_SHIFT;
510
511 spin_unlock_irqrestore(&csi->lock, flags);
512}
513EXPORT_SYMBOL_GPL(ipu_csi_get_window);
514
515void ipu_csi_set_window(struct ipu_csi *csi, struct v4l2_rect *w)
516{
517 unsigned long flags;
518 u32 reg;
519
520 spin_lock_irqsave(&csi->lock, flags);
521
522 ipu_csi_write(csi, (w->width - 1) | ((w->height - 1) << 16),
523 CSI_ACT_FRM_SIZE);
524
525 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
526 reg &= ~(CSI_HSC_MASK | CSI_VSC_MASK);
527 reg |= ((w->top << CSI_VSC_SHIFT) | (w->left << CSI_HSC_SHIFT));
528 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
529
530 spin_unlock_irqrestore(&csi->lock, flags);
531}
532EXPORT_SYMBOL_GPL(ipu_csi_set_window);
533
534void ipu_csi_set_downsize(struct ipu_csi *csi, bool horiz, bool vert)
535{
536 unsigned long flags;
537 u32 reg;
538
539 spin_lock_irqsave(&csi->lock, flags);
540
541 reg = ipu_csi_read(csi, CSI_OUT_FRM_CTRL);
542 reg &= ~(CSI_HORI_DOWNSIZE_EN | CSI_VERT_DOWNSIZE_EN);
543 reg |= (horiz ? CSI_HORI_DOWNSIZE_EN : 0) |
544 (vert ? CSI_VERT_DOWNSIZE_EN : 0);
545 ipu_csi_write(csi, reg, CSI_OUT_FRM_CTRL);
546
547 spin_unlock_irqrestore(&csi->lock, flags);
548}
549EXPORT_SYMBOL_GPL(ipu_csi_set_downsize);
550
551void ipu_csi_set_test_generator(struct ipu_csi *csi, bool active,
552 u32 r_value, u32 g_value, u32 b_value,
553 u32 pix_clk)
554{
555 unsigned long flags;
556 u32 ipu_clk = clk_get_rate(csi->clk_ipu);
557 u32 temp;
558
559 spin_lock_irqsave(&csi->lock, flags);
560
561 temp = ipu_csi_read(csi, CSI_TST_CTRL);
562
563 if (!active) {
564 temp &= ~CSI_TEST_GEN_MODE_EN;
565 ipu_csi_write(csi, temp, CSI_TST_CTRL);
566 } else {
567
568 ipu_csi_set_testgen_mclk(csi, pix_clk, ipu_clk);
569
570 temp &= ~(CSI_TEST_GEN_R_MASK | CSI_TEST_GEN_G_MASK |
571 CSI_TEST_GEN_B_MASK);
572 temp |= CSI_TEST_GEN_MODE_EN;
573 temp |= (r_value << CSI_TEST_GEN_R_SHIFT) |
574 (g_value << CSI_TEST_GEN_G_SHIFT) |
575 (b_value << CSI_TEST_GEN_B_SHIFT);
576 ipu_csi_write(csi, temp, CSI_TST_CTRL);
577 }
578
579 spin_unlock_irqrestore(&csi->lock, flags);
580}
581EXPORT_SYMBOL_GPL(ipu_csi_set_test_generator);
582
583int ipu_csi_set_mipi_datatype(struct ipu_csi *csi, u32 vc,
584 struct v4l2_mbus_framefmt *mbus_fmt)
585{
586 struct ipu_csi_bus_config cfg;
587 unsigned long flags;
588 u32 temp;
589
590 if (vc > 3)
591 return -EINVAL;
592
593 mbus_code_to_bus_cfg(&cfg, mbus_fmt->code);
594
595 spin_lock_irqsave(&csi->lock, flags);
596
597 temp = ipu_csi_read(csi, CSI_MIPI_DI);
598 temp &= ~(0xff << (vc * 8));
599 temp |= (cfg.mipi_dt << (vc * 8));
600 ipu_csi_write(csi, temp, CSI_MIPI_DI);
601
602 spin_unlock_irqrestore(&csi->lock, flags);
603
604 return 0;
605}
606EXPORT_SYMBOL_GPL(ipu_csi_set_mipi_datatype);
607
608int ipu_csi_set_skip_smfc(struct ipu_csi *csi, u32 skip,
609 u32 max_ratio, u32 id)
610{
611 unsigned long flags;
612 u32 temp;
613
614 if (max_ratio > 5 || id > 3)
615 return -EINVAL;
616
617 spin_lock_irqsave(&csi->lock, flags);
618
619 temp = ipu_csi_read(csi, CSI_SKIP);
620 temp &= ~(CSI_MAX_RATIO_SKIP_SMFC_MASK | CSI_ID_2_SKIP_MASK |
621 CSI_SKIP_SMFC_MASK);
622 temp |= (max_ratio << CSI_MAX_RATIO_SKIP_SMFC_SHIFT) |
623 (id << CSI_ID_2_SKIP_SHIFT) |
624 (skip << CSI_SKIP_SMFC_SHIFT);
625 ipu_csi_write(csi, temp, CSI_SKIP);
626
627 spin_unlock_irqrestore(&csi->lock, flags);
628
629 return 0;
630}
631EXPORT_SYMBOL_GPL(ipu_csi_set_skip_smfc);
632
633int ipu_csi_set_dest(struct ipu_csi *csi, enum ipu_csi_dest csi_dest)
634{
635 unsigned long flags;
636 u32 csi_sens_conf, dest;
637
638 if (csi_dest == IPU_CSI_DEST_IDMAC)
639 dest = CSI_DATA_DEST_IDMAC;
640 else
641 dest = CSI_DATA_DEST_IC;
642
643 spin_lock_irqsave(&csi->lock, flags);
644
645 csi_sens_conf = ipu_csi_read(csi, CSI_SENS_CONF);
646 csi_sens_conf &= ~CSI_SENS_CONF_DATA_DEST_MASK;
647 csi_sens_conf |= (dest << CSI_SENS_CONF_DATA_DEST_SHIFT);
648 ipu_csi_write(csi, csi_sens_conf, CSI_SENS_CONF);
649
650 spin_unlock_irqrestore(&csi->lock, flags);
651
652 return 0;
653}
654EXPORT_SYMBOL_GPL(ipu_csi_set_dest);
655
656int ipu_csi_enable(struct ipu_csi *csi)
657{
658 ipu_module_enable(csi->ipu, csi->module);
659
660 return 0;
661}
662EXPORT_SYMBOL_GPL(ipu_csi_enable);
663
664int ipu_csi_disable(struct ipu_csi *csi)
665{
666 ipu_module_disable(csi->ipu, csi->module);
667
668 return 0;
669}
670EXPORT_SYMBOL_GPL(ipu_csi_disable);
671
672struct ipu_csi *ipu_csi_get(struct ipu_soc *ipu, int id)
673{
674 unsigned long flags;
675 struct ipu_csi *csi, *ret;
676
677 if (id > 1)
678 return ERR_PTR(-EINVAL);
679
680 csi = ipu->csi_priv[id];
681 ret = csi;
682
683 spin_lock_irqsave(&csi->lock, flags);
684
685 if (csi->inuse) {
686 ret = ERR_PTR(-EBUSY);
687 goto unlock;
688 }
689
690 csi->inuse = true;
691unlock:
692 spin_unlock_irqrestore(&csi->lock, flags);
693 return ret;
694}
695EXPORT_SYMBOL_GPL(ipu_csi_get);
696
697void ipu_csi_put(struct ipu_csi *csi)
698{
699 unsigned long flags;
700
701 spin_lock_irqsave(&csi->lock, flags);
702 csi->inuse = false;
703 spin_unlock_irqrestore(&csi->lock, flags);
704}
705EXPORT_SYMBOL_GPL(ipu_csi_put);
706
707int ipu_csi_init(struct ipu_soc *ipu, struct device *dev, int id,
708 unsigned long base, u32 module, struct clk *clk_ipu)
709{
710 struct ipu_csi *csi;
711
712 if (id > 1)
713 return -ENODEV;
714
715 csi = devm_kzalloc(dev, sizeof(*csi), GFP_KERNEL);
716 if (!csi)
717 return -ENOMEM;
718
719 ipu->csi_priv[id] = csi;
720
721 spin_lock_init(&csi->lock);
722 csi->module = module;
723 csi->id = id;
724 csi->clk_ipu = clk_ipu;
725 csi->base = devm_ioremap(dev, base, PAGE_SIZE);
726 if (!csi->base)
727 return -ENOMEM;
728
729 dev_dbg(dev, "CSI%d base: 0x%08lx remapped to %p\n",
730 id, base, csi->base);
731 csi->ipu = ipu;
732
733 return 0;
734}
735
736void ipu_csi_exit(struct ipu_soc *ipu, int id)
737{
738}
739
740void ipu_csi_dump(struct ipu_csi *csi)
741{
742 dev_dbg(csi->ipu->dev, "CSI_SENS_CONF: %08x\n",
743 ipu_csi_read(csi, CSI_SENS_CONF));
744 dev_dbg(csi->ipu->dev, "CSI_SENS_FRM_SIZE: %08x\n",
745 ipu_csi_read(csi, CSI_SENS_FRM_SIZE));
746 dev_dbg(csi->ipu->dev, "CSI_ACT_FRM_SIZE: %08x\n",
747 ipu_csi_read(csi, CSI_ACT_FRM_SIZE));
748 dev_dbg(csi->ipu->dev, "CSI_OUT_FRM_CTRL: %08x\n",
749 ipu_csi_read(csi, CSI_OUT_FRM_CTRL));
750 dev_dbg(csi->ipu->dev, "CSI_TST_CTRL: %08x\n",
751 ipu_csi_read(csi, CSI_TST_CTRL));
752 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_1: %08x\n",
753 ipu_csi_read(csi, CSI_CCIR_CODE_1));
754 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_2: %08x\n",
755 ipu_csi_read(csi, CSI_CCIR_CODE_2));
756 dev_dbg(csi->ipu->dev, "CSI_CCIR_CODE_3: %08x\n",
757 ipu_csi_read(csi, CSI_CCIR_CODE_3));
758 dev_dbg(csi->ipu->dev, "CSI_MIPI_DI: %08x\n",
759 ipu_csi_read(csi, CSI_MIPI_DI));
760 dev_dbg(csi->ipu->dev, "CSI_SKIP: %08x\n",
761 ipu_csi_read(csi, CSI_SKIP));
762}
763EXPORT_SYMBOL_GPL(ipu_csi_dump);
764
