linux/drivers/hwtracing/coresight/coresight-tmc.c
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   1/* Copyright (c) 2012, The Linux Foundation. All rights reserved.
   2 *
   3 * Description: CoreSight Trace Memory Controller driver
   4 *
   5 * This program is free software; you can redistribute it and/or modify
   6 * it under the terms of the GNU General Public License version 2 and
   7 * only version 2 as published by the Free Software Foundation.
   8 *
   9 * This program is distributed in the hope that it will be useful,
  10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12 * GNU General Public License for more details.
  13 */
  14
  15#include <linux/kernel.h>
  16#include <linux/init.h>
  17#include <linux/types.h>
  18#include <linux/device.h>
  19#include <linux/io.h>
  20#include <linux/err.h>
  21#include <linux/fs.h>
  22#include <linux/miscdevice.h>
  23#include <linux/uaccess.h>
  24#include <linux/slab.h>
  25#include <linux/dma-mapping.h>
  26#include <linux/spinlock.h>
  27#include <linux/pm_runtime.h>
  28#include <linux/of.h>
  29#include <linux/coresight.h>
  30#include <linux/amba/bus.h>
  31
  32#include "coresight-priv.h"
  33#include "coresight-tmc.h"
  34
  35void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
  36{
  37        /* Ensure formatter, unformatter and hardware fifo are empty */
  38        if (coresight_timeout(drvdata->base,
  39                              TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
  40                dev_err(drvdata->dev,
  41                        "timeout while waiting for TMC to be Ready\n");
  42        }
  43}
  44
  45void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
  46{
  47        u32 ffcr;
  48
  49        ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
  50        ffcr |= TMC_FFCR_STOP_ON_FLUSH;
  51        writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  52        ffcr |= BIT(TMC_FFCR_FLUSHMAN_BIT);
  53        writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
  54        /* Ensure flush completes */
  55        if (coresight_timeout(drvdata->base,
  56                              TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
  57                dev_err(drvdata->dev,
  58                "timeout while waiting for completion of Manual Flush\n");
  59        }
  60
  61        tmc_wait_for_tmcready(drvdata);
  62}
  63
  64void tmc_enable_hw(struct tmc_drvdata *drvdata)
  65{
  66        writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
  67}
  68
  69void tmc_disable_hw(struct tmc_drvdata *drvdata)
  70{
  71        writel_relaxed(0x0, drvdata->base + TMC_CTL);
  72}
  73
  74static int tmc_read_prepare(struct tmc_drvdata *drvdata)
  75{
  76        int ret = 0;
  77
  78        switch (drvdata->config_type) {
  79        case TMC_CONFIG_TYPE_ETB:
  80        case TMC_CONFIG_TYPE_ETF:
  81                ret = tmc_read_prepare_etb(drvdata);
  82                break;
  83        case TMC_CONFIG_TYPE_ETR:
  84                ret = tmc_read_prepare_etr(drvdata);
  85                break;
  86        default:
  87                ret = -EINVAL;
  88        }
  89
  90        if (!ret)
  91                dev_info(drvdata->dev, "TMC read start\n");
  92
  93        return ret;
  94}
  95
  96static int tmc_read_unprepare(struct tmc_drvdata *drvdata)
  97{
  98        int ret = 0;
  99
 100        switch (drvdata->config_type) {
 101        case TMC_CONFIG_TYPE_ETB:
 102        case TMC_CONFIG_TYPE_ETF:
 103                ret = tmc_read_unprepare_etb(drvdata);
 104                break;
 105        case TMC_CONFIG_TYPE_ETR:
 106                ret = tmc_read_unprepare_etr(drvdata);
 107                break;
 108        default:
 109                ret = -EINVAL;
 110        }
 111
 112        if (!ret)
 113                dev_info(drvdata->dev, "TMC read end\n");
 114
 115        return ret;
 116}
 117
 118static int tmc_open(struct inode *inode, struct file *file)
 119{
 120        int ret;
 121        struct tmc_drvdata *drvdata = container_of(file->private_data,
 122                                                   struct tmc_drvdata, miscdev);
 123
 124        ret = tmc_read_prepare(drvdata);
 125        if (ret)
 126                return ret;
 127
 128        nonseekable_open(inode, file);
 129
 130        dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 131        return 0;
 132}
 133
 134static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
 135                        loff_t *ppos)
 136{
 137        struct tmc_drvdata *drvdata = container_of(file->private_data,
 138                                                   struct tmc_drvdata, miscdev);
 139        char *bufp = drvdata->buf + *ppos;
 140
 141        if (*ppos + len > drvdata->len)
 142                len = drvdata->len - *ppos;
 143
 144        if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 145                if (bufp == (char *)(drvdata->vaddr + drvdata->size))
 146                        bufp = drvdata->vaddr;
 147                else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
 148                        bufp -= drvdata->size;
 149                if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
 150                        len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
 151        }
 152
 153        if (copy_to_user(data, bufp, len)) {
 154                dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 155                return -EFAULT;
 156        }
 157
 158        *ppos += len;
 159
 160        dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 161                __func__, len, (int)(drvdata->len - *ppos));
 162        return len;
 163}
 164
 165static int tmc_release(struct inode *inode, struct file *file)
 166{
 167        int ret;
 168        struct tmc_drvdata *drvdata = container_of(file->private_data,
 169                                                   struct tmc_drvdata, miscdev);
 170
 171        ret = tmc_read_unprepare(drvdata);
 172        if (ret)
 173                return ret;
 174
 175        dev_dbg(drvdata->dev, "%s: released\n", __func__);
 176        return 0;
 177}
 178
 179static const struct file_operations tmc_fops = {
 180        .owner          = THIS_MODULE,
 181        .open           = tmc_open,
 182        .read           = tmc_read,
 183        .release        = tmc_release,
 184        .llseek         = no_llseek,
 185};
 186
 187static enum tmc_mem_intf_width tmc_get_memwidth(u32 devid)
 188{
 189        enum tmc_mem_intf_width memwidth;
 190
 191        /*
 192         * Excerpt from the TRM:
 193         *
 194         * DEVID::MEMWIDTH[10:8]
 195         * 0x2 Memory interface databus is 32 bits wide.
 196         * 0x3 Memory interface databus is 64 bits wide.
 197         * 0x4 Memory interface databus is 128 bits wide.
 198         * 0x5 Memory interface databus is 256 bits wide.
 199         */
 200        switch (BMVAL(devid, 8, 10)) {
 201        case 0x2:
 202                memwidth = TMC_MEM_INTF_WIDTH_32BITS;
 203                break;
 204        case 0x3:
 205                memwidth = TMC_MEM_INTF_WIDTH_64BITS;
 206                break;
 207        case 0x4:
 208                memwidth = TMC_MEM_INTF_WIDTH_128BITS;
 209                break;
 210        case 0x5:
 211                memwidth = TMC_MEM_INTF_WIDTH_256BITS;
 212                break;
 213        default:
 214                memwidth = 0;
 215        }
 216
 217        return memwidth;
 218}
 219
 220#define coresight_tmc_reg(name, offset)                 \
 221        coresight_simple_reg32(struct tmc_drvdata, name, offset)
 222#define coresight_tmc_reg64(name, lo_off, hi_off)       \
 223        coresight_simple_reg64(struct tmc_drvdata, name, lo_off, hi_off)
 224
 225coresight_tmc_reg(rsz, TMC_RSZ);
 226coresight_tmc_reg(sts, TMC_STS);
 227coresight_tmc_reg(trg, TMC_TRG);
 228coresight_tmc_reg(ctl, TMC_CTL);
 229coresight_tmc_reg(ffsr, TMC_FFSR);
 230coresight_tmc_reg(ffcr, TMC_FFCR);
 231coresight_tmc_reg(mode, TMC_MODE);
 232coresight_tmc_reg(pscr, TMC_PSCR);
 233coresight_tmc_reg(axictl, TMC_AXICTL);
 234coresight_tmc_reg(devid, CORESIGHT_DEVID);
 235coresight_tmc_reg64(rrp, TMC_RRP, TMC_RRPHI);
 236coresight_tmc_reg64(rwp, TMC_RWP, TMC_RWPHI);
 237coresight_tmc_reg64(dba, TMC_DBALO, TMC_DBAHI);
 238
 239static struct attribute *coresight_tmc_mgmt_attrs[] = {
 240        &dev_attr_rsz.attr,
 241        &dev_attr_sts.attr,
 242        &dev_attr_rrp.attr,
 243        &dev_attr_rwp.attr,
 244        &dev_attr_trg.attr,
 245        &dev_attr_ctl.attr,
 246        &dev_attr_ffsr.attr,
 247        &dev_attr_ffcr.attr,
 248        &dev_attr_mode.attr,
 249        &dev_attr_pscr.attr,
 250        &dev_attr_devid.attr,
 251        &dev_attr_dba.attr,
 252        &dev_attr_axictl.attr,
 253        NULL,
 254};
 255
 256static ssize_t trigger_cntr_show(struct device *dev,
 257                                 struct device_attribute *attr, char *buf)
 258{
 259        struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 260        unsigned long val = drvdata->trigger_cntr;
 261
 262        return sprintf(buf, "%#lx\n", val);
 263}
 264
 265static ssize_t trigger_cntr_store(struct device *dev,
 266                             struct device_attribute *attr,
 267                             const char *buf, size_t size)
 268{
 269        int ret;
 270        unsigned long val;
 271        struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 272
 273        ret = kstrtoul(buf, 16, &val);
 274        if (ret)
 275                return ret;
 276
 277        drvdata->trigger_cntr = val;
 278        return size;
 279}
 280static DEVICE_ATTR_RW(trigger_cntr);
 281
 282static struct attribute *coresight_tmc_attrs[] = {
 283        &dev_attr_trigger_cntr.attr,
 284        NULL,
 285};
 286
 287static const struct attribute_group coresight_tmc_group = {
 288        .attrs = coresight_tmc_attrs,
 289};
 290
 291static const struct attribute_group coresight_tmc_mgmt_group = {
 292        .attrs = coresight_tmc_mgmt_attrs,
 293        .name = "mgmt",
 294};
 295
 296const struct attribute_group *coresight_tmc_groups[] = {
 297        &coresight_tmc_group,
 298        &coresight_tmc_mgmt_group,
 299        NULL,
 300};
 301
 302/* Detect and initialise the capabilities of a TMC ETR */
 303static int tmc_etr_setup_caps(struct tmc_drvdata *drvdata,
 304                             u32 devid, void *dev_caps)
 305{
 306        u32 dma_mask = 0;
 307
 308        /* Set the unadvertised capabilities */
 309        tmc_etr_init_caps(drvdata, (u32)(unsigned long)dev_caps);
 310
 311        if (!(devid & TMC_DEVID_NOSCAT))
 312                tmc_etr_set_cap(drvdata, TMC_ETR_SG);
 313
 314        /* Check if the AXI address width is available */
 315        if (devid & TMC_DEVID_AXIAW_VALID)
 316                dma_mask = ((devid >> TMC_DEVID_AXIAW_SHIFT) &
 317                                TMC_DEVID_AXIAW_MASK);
 318
 319        /*
 320         * Unless specified in the device configuration, ETR uses a 40-bit
 321         * AXI master in place of the embedded SRAM of ETB/ETF.
 322         */
 323        switch (dma_mask) {
 324        case 32:
 325        case 40:
 326        case 44:
 327        case 48:
 328        case 52:
 329                dev_info(drvdata->dev, "Detected dma mask %dbits\n", dma_mask);
 330                break;
 331        default:
 332                dma_mask = 40;
 333        }
 334
 335        return dma_set_mask_and_coherent(drvdata->dev, DMA_BIT_MASK(dma_mask));
 336}
 337
 338static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 339{
 340        int ret = 0;
 341        u32 devid;
 342        void __iomem *base;
 343        struct device *dev = &adev->dev;
 344        struct coresight_platform_data *pdata = NULL;
 345        struct tmc_drvdata *drvdata;
 346        struct resource *res = &adev->res;
 347        struct coresight_desc desc = { 0 };
 348        struct device_node *np = adev->dev.of_node;
 349
 350        if (np) {
 351                pdata = of_get_coresight_platform_data(dev, np);
 352                if (IS_ERR(pdata)) {
 353                        ret = PTR_ERR(pdata);
 354                        goto out;
 355                }
 356                adev->dev.platform_data = pdata;
 357        }
 358
 359        ret = -ENOMEM;
 360        drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 361        if (!drvdata)
 362                goto out;
 363
 364        drvdata->dev = &adev->dev;
 365        dev_set_drvdata(dev, drvdata);
 366
 367        /* Validity for the resource is already checked by the AMBA core */
 368        base = devm_ioremap_resource(dev, res);
 369        if (IS_ERR(base)) {
 370                ret = PTR_ERR(base);
 371                goto out;
 372        }
 373
 374        drvdata->base = base;
 375
 376        spin_lock_init(&drvdata->spinlock);
 377
 378        devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 379        drvdata->config_type = BMVAL(devid, 6, 7);
 380        drvdata->memwidth = tmc_get_memwidth(devid);
 381
 382        if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 383                if (np)
 384                        ret = of_property_read_u32(np,
 385                                                   "arm,buffer-size",
 386                                                   &drvdata->size);
 387                if (ret)
 388                        drvdata->size = SZ_1M;
 389        } else {
 390                drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
 391        }
 392
 393        pm_runtime_put(&adev->dev);
 394
 395        desc.pdata = pdata;
 396        desc.dev = dev;
 397        desc.groups = coresight_tmc_groups;
 398
 399        switch (drvdata->config_type) {
 400        case TMC_CONFIG_TYPE_ETB:
 401                desc.type = CORESIGHT_DEV_TYPE_SINK;
 402                desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 403                desc.ops = &tmc_etb_cs_ops;
 404                break;
 405        case TMC_CONFIG_TYPE_ETR:
 406                desc.type = CORESIGHT_DEV_TYPE_SINK;
 407                desc.subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 408                desc.ops = &tmc_etr_cs_ops;
 409                ret = tmc_etr_setup_caps(drvdata, devid, id->data);
 410                if (ret)
 411                        goto out;
 412                break;
 413        case TMC_CONFIG_TYPE_ETF:
 414                desc.type = CORESIGHT_DEV_TYPE_LINKSINK;
 415                desc.subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 416                desc.ops = &tmc_etf_cs_ops;
 417                break;
 418        default:
 419                pr_err("%s: Unsupported TMC config\n", pdata->name);
 420                ret = -EINVAL;
 421                goto out;
 422        }
 423
 424        drvdata->csdev = coresight_register(&desc);
 425        if (IS_ERR(drvdata->csdev)) {
 426                ret = PTR_ERR(drvdata->csdev);
 427                goto out;
 428        }
 429
 430        drvdata->miscdev.name = pdata->name;
 431        drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 432        drvdata->miscdev.fops = &tmc_fops;
 433        ret = misc_register(&drvdata->miscdev);
 434        if (ret)
 435                coresight_unregister(drvdata->csdev);
 436out:
 437        return ret;
 438}
 439
 440static const struct amba_id tmc_ids[] = {
 441        {
 442                .id     = 0x000bb961,
 443                .mask   = 0x000fffff,
 444        },
 445        {
 446                /* Coresight SoC 600 TMC-ETR/ETS */
 447                .id     = 0x000bb9e8,
 448                .mask   = 0x000fffff,
 449                .data   = (void *)(unsigned long)CORESIGHT_SOC_600_ETR_CAPS,
 450        },
 451        {
 452                /* Coresight SoC 600 TMC-ETB */
 453                .id     = 0x000bb9e9,
 454                .mask   = 0x000fffff,
 455        },
 456        {
 457                /* Coresight SoC 600 TMC-ETF */
 458                .id     = 0x000bb9ea,
 459                .mask   = 0x000fffff,
 460        },
 461        { 0, 0},
 462};
 463
 464static struct amba_driver tmc_driver = {
 465        .drv = {
 466                .name   = "coresight-tmc",
 467                .owner  = THIS_MODULE,
 468                .suppress_bind_attrs = true,
 469        },
 470        .probe          = tmc_probe,
 471        .id_table       = tmc_ids,
 472};
 473builtin_amba_driver(tmc_driver);
 474