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22#include <linux/module.h>
23#include <linux/i2c.h>
24#include <linux/interrupt.h>
25#include <linux/delay.h>
26#include <linux/slab.h>
27#include <linux/acpi.h>
28#include <linux/pm.h>
29#include <linux/pm_runtime.h>
30#include <linux/iio/iio.h>
31#include <linux/iio/sysfs.h>
32#include <linux/iio/buffer.h>
33#include <linux/iio/events.h>
34#include <linux/iio/trigger.h>
35#include <linux/iio/trigger_consumer.h>
36#include <linux/iio/triggered_buffer.h>
37#include <linux/regmap.h>
38
39#include "bmc150-accel.h"
40
41#define BMC150_ACCEL_DRV_NAME "bmc150_accel"
42#define BMC150_ACCEL_IRQ_NAME "bmc150_accel_event"
43
44#define BMC150_ACCEL_REG_CHIP_ID 0x00
45
46#define BMC150_ACCEL_REG_INT_STATUS_2 0x0B
47#define BMC150_ACCEL_ANY_MOTION_MASK 0x07
48#define BMC150_ACCEL_ANY_MOTION_BIT_X BIT(0)
49#define BMC150_ACCEL_ANY_MOTION_BIT_Y BIT(1)
50#define BMC150_ACCEL_ANY_MOTION_BIT_Z BIT(2)
51#define BMC150_ACCEL_ANY_MOTION_BIT_SIGN BIT(3)
52
53#define BMC150_ACCEL_REG_PMU_LPW 0x11
54#define BMC150_ACCEL_PMU_MODE_MASK 0xE0
55#define BMC150_ACCEL_PMU_MODE_SHIFT 5
56#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_MASK 0x17
57#define BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT 1
58
59#define BMC150_ACCEL_REG_PMU_RANGE 0x0F
60
61#define BMC150_ACCEL_DEF_RANGE_2G 0x03
62#define BMC150_ACCEL_DEF_RANGE_4G 0x05
63#define BMC150_ACCEL_DEF_RANGE_8G 0x08
64#define BMC150_ACCEL_DEF_RANGE_16G 0x0C
65
66
67#define BMC150_ACCEL_REG_PMU_BW 0x10
68#define BMC150_ACCEL_DEF_BW 125
69
70#define BMC150_ACCEL_REG_RESET 0x14
71#define BMC150_ACCEL_RESET_VAL 0xB6
72
73#define BMC150_ACCEL_REG_INT_MAP_0 0x19
74#define BMC150_ACCEL_INT_MAP_0_BIT_SLOPE BIT(2)
75
76#define BMC150_ACCEL_REG_INT_MAP_1 0x1A
77#define BMC150_ACCEL_INT_MAP_1_BIT_DATA BIT(0)
78#define BMC150_ACCEL_INT_MAP_1_BIT_FWM BIT(1)
79#define BMC150_ACCEL_INT_MAP_1_BIT_FFULL BIT(2)
80
81#define BMC150_ACCEL_REG_INT_RST_LATCH 0x21
82#define BMC150_ACCEL_INT_MODE_LATCH_RESET 0x80
83#define BMC150_ACCEL_INT_MODE_LATCH_INT 0x0F
84#define BMC150_ACCEL_INT_MODE_NON_LATCH_INT 0x00
85
86#define BMC150_ACCEL_REG_INT_EN_0 0x16
87#define BMC150_ACCEL_INT_EN_BIT_SLP_X BIT(0)
88#define BMC150_ACCEL_INT_EN_BIT_SLP_Y BIT(1)
89#define BMC150_ACCEL_INT_EN_BIT_SLP_Z BIT(2)
90
91#define BMC150_ACCEL_REG_INT_EN_1 0x17
92#define BMC150_ACCEL_INT_EN_BIT_DATA_EN BIT(4)
93#define BMC150_ACCEL_INT_EN_BIT_FFULL_EN BIT(5)
94#define BMC150_ACCEL_INT_EN_BIT_FWM_EN BIT(6)
95
96#define BMC150_ACCEL_REG_INT_OUT_CTRL 0x20
97#define BMC150_ACCEL_INT_OUT_CTRL_INT1_LVL BIT(0)
98
99#define BMC150_ACCEL_REG_INT_5 0x27
100#define BMC150_ACCEL_SLOPE_DUR_MASK 0x03
101
102#define BMC150_ACCEL_REG_INT_6 0x28
103#define BMC150_ACCEL_SLOPE_THRES_MASK 0xFF
104
105
106#define BMC150_ACCEL_DEF_SLOPE_DURATION 1
107
108#define BMC150_ACCEL_DEF_SLOPE_THRESHOLD 1
109
110#define BMC150_ACCEL_REG_XOUT_L 0x02
111
112#define BMC150_ACCEL_MAX_STARTUP_TIME_MS 100
113
114
115#define BMC150_ACCEL_SLEEP_500_MICRO 0x05
116#define BMC150_ACCEL_SLEEP_1_MS 0x06
117#define BMC150_ACCEL_SLEEP_2_MS 0x07
118#define BMC150_ACCEL_SLEEP_4_MS 0x08
119#define BMC150_ACCEL_SLEEP_6_MS 0x09
120#define BMC150_ACCEL_SLEEP_10_MS 0x0A
121#define BMC150_ACCEL_SLEEP_25_MS 0x0B
122#define BMC150_ACCEL_SLEEP_50_MS 0x0C
123#define BMC150_ACCEL_SLEEP_100_MS 0x0D
124#define BMC150_ACCEL_SLEEP_500_MS 0x0E
125#define BMC150_ACCEL_SLEEP_1_SEC 0x0F
126
127#define BMC150_ACCEL_REG_TEMP 0x08
128#define BMC150_ACCEL_TEMP_CENTER_VAL 24
129
130#define BMC150_ACCEL_AXIS_TO_REG(axis) (BMC150_ACCEL_REG_XOUT_L + (axis * 2))
131#define BMC150_AUTO_SUSPEND_DELAY_MS 2000
132
133#define BMC150_ACCEL_REG_FIFO_STATUS 0x0E
134#define BMC150_ACCEL_REG_FIFO_CONFIG0 0x30
135#define BMC150_ACCEL_REG_FIFO_CONFIG1 0x3E
136#define BMC150_ACCEL_REG_FIFO_DATA 0x3F
137#define BMC150_ACCEL_FIFO_LENGTH 32
138
139enum bmc150_accel_axis {
140 AXIS_X,
141 AXIS_Y,
142 AXIS_Z,
143 AXIS_MAX,
144};
145
146enum bmc150_power_modes {
147 BMC150_ACCEL_SLEEP_MODE_NORMAL,
148 BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND,
149 BMC150_ACCEL_SLEEP_MODE_LPM,
150 BMC150_ACCEL_SLEEP_MODE_SUSPEND = 0x04,
151};
152
153struct bmc150_scale_info {
154 int scale;
155 u8 reg_range;
156};
157
158struct bmc150_accel_chip_info {
159 const char *name;
160 u8 chip_id;
161 const struct iio_chan_spec *channels;
162 int num_channels;
163 const struct bmc150_scale_info scale_table[4];
164};
165
166struct bmc150_accel_interrupt {
167 const struct bmc150_accel_interrupt_info *info;
168 atomic_t users;
169};
170
171struct bmc150_accel_trigger {
172 struct bmc150_accel_data *data;
173 struct iio_trigger *indio_trig;
174 int (*setup)(struct bmc150_accel_trigger *t, bool state);
175 int intr;
176 bool enabled;
177};
178
179enum bmc150_accel_interrupt_id {
180 BMC150_ACCEL_INT_DATA_READY,
181 BMC150_ACCEL_INT_ANY_MOTION,
182 BMC150_ACCEL_INT_WATERMARK,
183 BMC150_ACCEL_INTERRUPTS,
184};
185
186enum bmc150_accel_trigger_id {
187 BMC150_ACCEL_TRIGGER_DATA_READY,
188 BMC150_ACCEL_TRIGGER_ANY_MOTION,
189 BMC150_ACCEL_TRIGGERS,
190};
191
192struct bmc150_accel_data {
193 struct regmap *regmap;
194 int irq;
195 struct bmc150_accel_interrupt interrupts[BMC150_ACCEL_INTERRUPTS];
196 struct bmc150_accel_trigger triggers[BMC150_ACCEL_TRIGGERS];
197 struct mutex mutex;
198 u8 fifo_mode, watermark;
199 s16 buffer[8];
200 u8 bw_bits;
201 u32 slope_dur;
202 u32 slope_thres;
203 u32 range;
204 int ev_enable_state;
205 int64_t timestamp, old_timestamp;
206 const struct bmc150_accel_chip_info *chip_info;
207};
208
209static const struct {
210 int val;
211 int val2;
212 u8 bw_bits;
213} bmc150_accel_samp_freq_table[] = { {15, 620000, 0x08},
214 {31, 260000, 0x09},
215 {62, 500000, 0x0A},
216 {125, 0, 0x0B},
217 {250, 0, 0x0C},
218 {500, 0, 0x0D},
219 {1000, 0, 0x0E},
220 {2000, 0, 0x0F} };
221
222static const struct {
223 int bw_bits;
224 int msec;
225} bmc150_accel_sample_upd_time[] = { {0x08, 64},
226 {0x09, 32},
227 {0x0A, 16},
228 {0x0B, 8},
229 {0x0C, 4},
230 {0x0D, 2},
231 {0x0E, 1},
232 {0x0F, 1} };
233
234static const struct {
235 int sleep_dur;
236 u8 reg_value;
237} bmc150_accel_sleep_value_table[] = { {0, 0},
238 {500, BMC150_ACCEL_SLEEP_500_MICRO},
239 {1000, BMC150_ACCEL_SLEEP_1_MS},
240 {2000, BMC150_ACCEL_SLEEP_2_MS},
241 {4000, BMC150_ACCEL_SLEEP_4_MS},
242 {6000, BMC150_ACCEL_SLEEP_6_MS},
243 {10000, BMC150_ACCEL_SLEEP_10_MS},
244 {25000, BMC150_ACCEL_SLEEP_25_MS},
245 {50000, BMC150_ACCEL_SLEEP_50_MS},
246 {100000, BMC150_ACCEL_SLEEP_100_MS},
247 {500000, BMC150_ACCEL_SLEEP_500_MS},
248 {1000000, BMC150_ACCEL_SLEEP_1_SEC} };
249
250const struct regmap_config bmc150_regmap_conf = {
251 .reg_bits = 8,
252 .val_bits = 8,
253 .max_register = 0x3f,
254};
255EXPORT_SYMBOL_GPL(bmc150_regmap_conf);
256
257static int bmc150_accel_set_mode(struct bmc150_accel_data *data,
258 enum bmc150_power_modes mode,
259 int dur_us)
260{
261 struct device *dev = regmap_get_device(data->regmap);
262 int i;
263 int ret;
264 u8 lpw_bits;
265 int dur_val = -1;
266
267 if (dur_us > 0) {
268 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sleep_value_table);
269 ++i) {
270 if (bmc150_accel_sleep_value_table[i].sleep_dur ==
271 dur_us)
272 dur_val =
273 bmc150_accel_sleep_value_table[i].reg_value;
274 }
275 } else {
276 dur_val = 0;
277 }
278
279 if (dur_val < 0)
280 return -EINVAL;
281
282 lpw_bits = mode << BMC150_ACCEL_PMU_MODE_SHIFT;
283 lpw_bits |= (dur_val << BMC150_ACCEL_PMU_BIT_SLEEP_DUR_SHIFT);
284
285 dev_dbg(dev, "Set Mode bits %x\n", lpw_bits);
286
287 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_LPW, lpw_bits);
288 if (ret < 0) {
289 dev_err(dev, "Error writing reg_pmu_lpw\n");
290 return ret;
291 }
292
293 return 0;
294}
295
296static int bmc150_accel_set_bw(struct bmc150_accel_data *data, int val,
297 int val2)
298{
299 int i;
300 int ret;
301
302 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
303 if (bmc150_accel_samp_freq_table[i].val == val &&
304 bmc150_accel_samp_freq_table[i].val2 == val2) {
305 ret = regmap_write(data->regmap,
306 BMC150_ACCEL_REG_PMU_BW,
307 bmc150_accel_samp_freq_table[i].bw_bits);
308 if (ret < 0)
309 return ret;
310
311 data->bw_bits =
312 bmc150_accel_samp_freq_table[i].bw_bits;
313 return 0;
314 }
315 }
316
317 return -EINVAL;
318}
319
320static int bmc150_accel_update_slope(struct bmc150_accel_data *data)
321{
322 struct device *dev = regmap_get_device(data->regmap);
323 int ret;
324
325 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_6,
326 data->slope_thres);
327 if (ret < 0) {
328 dev_err(dev, "Error writing reg_int_6\n");
329 return ret;
330 }
331
332 ret = regmap_update_bits(data->regmap, BMC150_ACCEL_REG_INT_5,
333 BMC150_ACCEL_SLOPE_DUR_MASK, data->slope_dur);
334 if (ret < 0) {
335 dev_err(dev, "Error updating reg_int_5\n");
336 return ret;
337 }
338
339 dev_dbg(dev, "%x %x\n", data->slope_thres, data->slope_dur);
340
341 return ret;
342}
343
344static int bmc150_accel_any_motion_setup(struct bmc150_accel_trigger *t,
345 bool state)
346{
347 if (state)
348 return bmc150_accel_update_slope(t->data);
349
350 return 0;
351}
352
353static int bmc150_accel_get_bw(struct bmc150_accel_data *data, int *val,
354 int *val2)
355{
356 int i;
357
358 for (i = 0; i < ARRAY_SIZE(bmc150_accel_samp_freq_table); ++i) {
359 if (bmc150_accel_samp_freq_table[i].bw_bits == data->bw_bits) {
360 *val = bmc150_accel_samp_freq_table[i].val;
361 *val2 = bmc150_accel_samp_freq_table[i].val2;
362 return IIO_VAL_INT_PLUS_MICRO;
363 }
364 }
365
366 return -EINVAL;
367}
368
369#ifdef CONFIG_PM
370static int bmc150_accel_get_startup_times(struct bmc150_accel_data *data)
371{
372 int i;
373
374 for (i = 0; i < ARRAY_SIZE(bmc150_accel_sample_upd_time); ++i) {
375 if (bmc150_accel_sample_upd_time[i].bw_bits == data->bw_bits)
376 return bmc150_accel_sample_upd_time[i].msec;
377 }
378
379 return BMC150_ACCEL_MAX_STARTUP_TIME_MS;
380}
381
382static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
383{
384 struct device *dev = regmap_get_device(data->regmap);
385 int ret;
386
387 if (on) {
388 ret = pm_runtime_get_sync(dev);
389 } else {
390 pm_runtime_mark_last_busy(dev);
391 ret = pm_runtime_put_autosuspend(dev);
392 }
393
394 if (ret < 0) {
395 dev_err(dev,
396 "Failed: bmc150_accel_set_power_state for %d\n", on);
397 if (on)
398 pm_runtime_put_noidle(dev);
399
400 return ret;
401 }
402
403 return 0;
404}
405#else
406static int bmc150_accel_set_power_state(struct bmc150_accel_data *data, bool on)
407{
408 return 0;
409}
410#endif
411
412static const struct bmc150_accel_interrupt_info {
413 u8 map_reg;
414 u8 map_bitmask;
415 u8 en_reg;
416 u8 en_bitmask;
417} bmc150_accel_interrupts[BMC150_ACCEL_INTERRUPTS] = {
418 {
419 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
420 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_DATA,
421 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
422 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_DATA_EN,
423 },
424 {
425 .map_reg = BMC150_ACCEL_REG_INT_MAP_0,
426 .map_bitmask = BMC150_ACCEL_INT_MAP_0_BIT_SLOPE,
427 .en_reg = BMC150_ACCEL_REG_INT_EN_0,
428 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_SLP_X |
429 BMC150_ACCEL_INT_EN_BIT_SLP_Y |
430 BMC150_ACCEL_INT_EN_BIT_SLP_Z
431 },
432 {
433 .map_reg = BMC150_ACCEL_REG_INT_MAP_1,
434 .map_bitmask = BMC150_ACCEL_INT_MAP_1_BIT_FWM,
435 .en_reg = BMC150_ACCEL_REG_INT_EN_1,
436 .en_bitmask = BMC150_ACCEL_INT_EN_BIT_FWM_EN,
437 },
438};
439
440static void bmc150_accel_interrupts_setup(struct iio_dev *indio_dev,
441 struct bmc150_accel_data *data)
442{
443 int i;
444
445 for (i = 0; i < BMC150_ACCEL_INTERRUPTS; i++)
446 data->interrupts[i].info = &bmc150_accel_interrupts[i];
447}
448
449static int bmc150_accel_set_interrupt(struct bmc150_accel_data *data, int i,
450 bool state)
451{
452 struct device *dev = regmap_get_device(data->regmap);
453 struct bmc150_accel_interrupt *intr = &data->interrupts[i];
454 const struct bmc150_accel_interrupt_info *info = intr->info;
455 int ret;
456
457 if (state) {
458 if (atomic_inc_return(&intr->users) > 1)
459 return 0;
460 } else {
461 if (atomic_dec_return(&intr->users) > 0)
462 return 0;
463 }
464
465
466
467
468
469
470
471
472
473
474 ret = bmc150_accel_set_power_state(data, state);
475 if (ret < 0)
476 return ret;
477
478
479 ret = regmap_update_bits(data->regmap, info->map_reg, info->map_bitmask,
480 (state ? info->map_bitmask : 0));
481 if (ret < 0) {
482 dev_err(dev, "Error updating reg_int_map\n");
483 goto out_fix_power_state;
484 }
485
486
487 ret = regmap_update_bits(data->regmap, info->en_reg, info->en_bitmask,
488 (state ? info->en_bitmask : 0));
489 if (ret < 0) {
490 dev_err(dev, "Error updating reg_int_en\n");
491 goto out_fix_power_state;
492 }
493
494 return 0;
495
496out_fix_power_state:
497 bmc150_accel_set_power_state(data, false);
498 return ret;
499}
500
501static int bmc150_accel_set_scale(struct bmc150_accel_data *data, int val)
502{
503 struct device *dev = regmap_get_device(data->regmap);
504 int ret, i;
505
506 for (i = 0; i < ARRAY_SIZE(data->chip_info->scale_table); ++i) {
507 if (data->chip_info->scale_table[i].scale == val) {
508 ret = regmap_write(data->regmap,
509 BMC150_ACCEL_REG_PMU_RANGE,
510 data->chip_info->scale_table[i].reg_range);
511 if (ret < 0) {
512 dev_err(dev, "Error writing pmu_range\n");
513 return ret;
514 }
515
516 data->range = data->chip_info->scale_table[i].reg_range;
517 return 0;
518 }
519 }
520
521 return -EINVAL;
522}
523
524static int bmc150_accel_get_temp(struct bmc150_accel_data *data, int *val)
525{
526 struct device *dev = regmap_get_device(data->regmap);
527 int ret;
528 unsigned int value;
529
530 mutex_lock(&data->mutex);
531
532 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_TEMP, &value);
533 if (ret < 0) {
534 dev_err(dev, "Error reading reg_temp\n");
535 mutex_unlock(&data->mutex);
536 return ret;
537 }
538 *val = sign_extend32(value, 7);
539
540 mutex_unlock(&data->mutex);
541
542 return IIO_VAL_INT;
543}
544
545static int bmc150_accel_get_axis(struct bmc150_accel_data *data,
546 struct iio_chan_spec const *chan,
547 int *val)
548{
549 struct device *dev = regmap_get_device(data->regmap);
550 int ret;
551 int axis = chan->scan_index;
552 __le16 raw_val;
553
554 mutex_lock(&data->mutex);
555 ret = bmc150_accel_set_power_state(data, true);
556 if (ret < 0) {
557 mutex_unlock(&data->mutex);
558 return ret;
559 }
560
561 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_AXIS_TO_REG(axis),
562 &raw_val, sizeof(raw_val));
563 if (ret < 0) {
564 dev_err(dev, "Error reading axis %d\n", axis);
565 bmc150_accel_set_power_state(data, false);
566 mutex_unlock(&data->mutex);
567 return ret;
568 }
569 *val = sign_extend32(le16_to_cpu(raw_val) >> chan->scan_type.shift,
570 chan->scan_type.realbits - 1);
571 ret = bmc150_accel_set_power_state(data, false);
572 mutex_unlock(&data->mutex);
573 if (ret < 0)
574 return ret;
575
576 return IIO_VAL_INT;
577}
578
579static int bmc150_accel_read_raw(struct iio_dev *indio_dev,
580 struct iio_chan_spec const *chan,
581 int *val, int *val2, long mask)
582{
583 struct bmc150_accel_data *data = iio_priv(indio_dev);
584 int ret;
585
586 switch (mask) {
587 case IIO_CHAN_INFO_RAW:
588 switch (chan->type) {
589 case IIO_TEMP:
590 return bmc150_accel_get_temp(data, val);
591 case IIO_ACCEL:
592 if (iio_buffer_enabled(indio_dev))
593 return -EBUSY;
594 else
595 return bmc150_accel_get_axis(data, chan, val);
596 default:
597 return -EINVAL;
598 }
599 case IIO_CHAN_INFO_OFFSET:
600 if (chan->type == IIO_TEMP) {
601 *val = BMC150_ACCEL_TEMP_CENTER_VAL;
602 return IIO_VAL_INT;
603 } else {
604 return -EINVAL;
605 }
606 case IIO_CHAN_INFO_SCALE:
607 *val = 0;
608 switch (chan->type) {
609 case IIO_TEMP:
610 *val2 = 500000;
611 return IIO_VAL_INT_PLUS_MICRO;
612 case IIO_ACCEL:
613 {
614 int i;
615 const struct bmc150_scale_info *si;
616 int st_size = ARRAY_SIZE(data->chip_info->scale_table);
617
618 for (i = 0; i < st_size; ++i) {
619 si = &data->chip_info->scale_table[i];
620 if (si->reg_range == data->range) {
621 *val2 = si->scale;
622 return IIO_VAL_INT_PLUS_MICRO;
623 }
624 }
625 return -EINVAL;
626 }
627 default:
628 return -EINVAL;
629 }
630 case IIO_CHAN_INFO_SAMP_FREQ:
631 mutex_lock(&data->mutex);
632 ret = bmc150_accel_get_bw(data, val, val2);
633 mutex_unlock(&data->mutex);
634 return ret;
635 default:
636 return -EINVAL;
637 }
638}
639
640static int bmc150_accel_write_raw(struct iio_dev *indio_dev,
641 struct iio_chan_spec const *chan,
642 int val, int val2, long mask)
643{
644 struct bmc150_accel_data *data = iio_priv(indio_dev);
645 int ret;
646
647 switch (mask) {
648 case IIO_CHAN_INFO_SAMP_FREQ:
649 mutex_lock(&data->mutex);
650 ret = bmc150_accel_set_bw(data, val, val2);
651 mutex_unlock(&data->mutex);
652 break;
653 case IIO_CHAN_INFO_SCALE:
654 if (val)
655 return -EINVAL;
656
657 mutex_lock(&data->mutex);
658 ret = bmc150_accel_set_scale(data, val2);
659 mutex_unlock(&data->mutex);
660 return ret;
661 default:
662 ret = -EINVAL;
663 }
664
665 return ret;
666}
667
668static int bmc150_accel_read_event(struct iio_dev *indio_dev,
669 const struct iio_chan_spec *chan,
670 enum iio_event_type type,
671 enum iio_event_direction dir,
672 enum iio_event_info info,
673 int *val, int *val2)
674{
675 struct bmc150_accel_data *data = iio_priv(indio_dev);
676
677 *val2 = 0;
678 switch (info) {
679 case IIO_EV_INFO_VALUE:
680 *val = data->slope_thres;
681 break;
682 case IIO_EV_INFO_PERIOD:
683 *val = data->slope_dur;
684 break;
685 default:
686 return -EINVAL;
687 }
688
689 return IIO_VAL_INT;
690}
691
692static int bmc150_accel_write_event(struct iio_dev *indio_dev,
693 const struct iio_chan_spec *chan,
694 enum iio_event_type type,
695 enum iio_event_direction dir,
696 enum iio_event_info info,
697 int val, int val2)
698{
699 struct bmc150_accel_data *data = iio_priv(indio_dev);
700
701 if (data->ev_enable_state)
702 return -EBUSY;
703
704 switch (info) {
705 case IIO_EV_INFO_VALUE:
706 data->slope_thres = val & BMC150_ACCEL_SLOPE_THRES_MASK;
707 break;
708 case IIO_EV_INFO_PERIOD:
709 data->slope_dur = val & BMC150_ACCEL_SLOPE_DUR_MASK;
710 break;
711 default:
712 return -EINVAL;
713 }
714
715 return 0;
716}
717
718static int bmc150_accel_read_event_config(struct iio_dev *indio_dev,
719 const struct iio_chan_spec *chan,
720 enum iio_event_type type,
721 enum iio_event_direction dir)
722{
723 struct bmc150_accel_data *data = iio_priv(indio_dev);
724
725 return data->ev_enable_state;
726}
727
728static int bmc150_accel_write_event_config(struct iio_dev *indio_dev,
729 const struct iio_chan_spec *chan,
730 enum iio_event_type type,
731 enum iio_event_direction dir,
732 int state)
733{
734 struct bmc150_accel_data *data = iio_priv(indio_dev);
735 int ret;
736
737 if (state == data->ev_enable_state)
738 return 0;
739
740 mutex_lock(&data->mutex);
741
742 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_ANY_MOTION,
743 state);
744 if (ret < 0) {
745 mutex_unlock(&data->mutex);
746 return ret;
747 }
748
749 data->ev_enable_state = state;
750 mutex_unlock(&data->mutex);
751
752 return 0;
753}
754
755static int bmc150_accel_validate_trigger(struct iio_dev *indio_dev,
756 struct iio_trigger *trig)
757{
758 struct bmc150_accel_data *data = iio_priv(indio_dev);
759 int i;
760
761 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
762 if (data->triggers[i].indio_trig == trig)
763 return 0;
764 }
765
766 return -EINVAL;
767}
768
769static ssize_t bmc150_accel_get_fifo_watermark(struct device *dev,
770 struct device_attribute *attr,
771 char *buf)
772{
773 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
774 struct bmc150_accel_data *data = iio_priv(indio_dev);
775 int wm;
776
777 mutex_lock(&data->mutex);
778 wm = data->watermark;
779 mutex_unlock(&data->mutex);
780
781 return sprintf(buf, "%d\n", wm);
782}
783
784static ssize_t bmc150_accel_get_fifo_state(struct device *dev,
785 struct device_attribute *attr,
786 char *buf)
787{
788 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
789 struct bmc150_accel_data *data = iio_priv(indio_dev);
790 bool state;
791
792 mutex_lock(&data->mutex);
793 state = data->fifo_mode;
794 mutex_unlock(&data->mutex);
795
796 return sprintf(buf, "%d\n", state);
797}
798
799static IIO_CONST_ATTR(hwfifo_watermark_min, "1");
800static IIO_CONST_ATTR(hwfifo_watermark_max,
801 __stringify(BMC150_ACCEL_FIFO_LENGTH));
802static IIO_DEVICE_ATTR(hwfifo_enabled, S_IRUGO,
803 bmc150_accel_get_fifo_state, NULL, 0);
804static IIO_DEVICE_ATTR(hwfifo_watermark, S_IRUGO,
805 bmc150_accel_get_fifo_watermark, NULL, 0);
806
807static const struct attribute *bmc150_accel_fifo_attributes[] = {
808 &iio_const_attr_hwfifo_watermark_min.dev_attr.attr,
809 &iio_const_attr_hwfifo_watermark_max.dev_attr.attr,
810 &iio_dev_attr_hwfifo_watermark.dev_attr.attr,
811 &iio_dev_attr_hwfifo_enabled.dev_attr.attr,
812 NULL,
813};
814
815static int bmc150_accel_set_watermark(struct iio_dev *indio_dev, unsigned val)
816{
817 struct bmc150_accel_data *data = iio_priv(indio_dev);
818
819 if (val > BMC150_ACCEL_FIFO_LENGTH)
820 val = BMC150_ACCEL_FIFO_LENGTH;
821
822 mutex_lock(&data->mutex);
823 data->watermark = val;
824 mutex_unlock(&data->mutex);
825
826 return 0;
827}
828
829
830
831
832
833static int bmc150_accel_fifo_transfer(struct bmc150_accel_data *data,
834 char *buffer, int samples)
835{
836 struct device *dev = regmap_get_device(data->regmap);
837 int sample_length = 3 * 2;
838 int ret;
839 int total_length = samples * sample_length;
840 int i;
841 size_t step = regmap_get_raw_read_max(data->regmap);
842
843 if (!step || step > total_length)
844 step = total_length;
845 else if (step < total_length)
846 step = sample_length;
847
848
849
850
851
852 for (i = 0; i < total_length; i += step) {
853 ret = regmap_raw_read(data->regmap, BMC150_ACCEL_REG_FIFO_DATA,
854 &buffer[i], step);
855 if (ret)
856 break;
857 }
858
859 if (ret)
860 dev_err(dev,
861 "Error transferring data from fifo in single steps of %zu\n",
862 step);
863
864 return ret;
865}
866
867static int __bmc150_accel_fifo_flush(struct iio_dev *indio_dev,
868 unsigned samples, bool irq)
869{
870 struct bmc150_accel_data *data = iio_priv(indio_dev);
871 struct device *dev = regmap_get_device(data->regmap);
872 int ret, i;
873 u8 count;
874 u16 buffer[BMC150_ACCEL_FIFO_LENGTH * 3];
875 int64_t tstamp;
876 uint64_t sample_period;
877 unsigned int val;
878
879 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_FIFO_STATUS, &val);
880 if (ret < 0) {
881 dev_err(dev, "Error reading reg_fifo_status\n");
882 return ret;
883 }
884
885 count = val & 0x7F;
886
887 if (!count)
888 return 0;
889
890
891
892
893
894
895
896
897
898 if (!irq) {
899 data->old_timestamp = data->timestamp;
900 data->timestamp = iio_get_time_ns(indio_dev);
901 }
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917 sample_period = (data->timestamp - data->old_timestamp);
918 do_div(sample_period, count);
919 tstamp = data->timestamp - (count - 1) * sample_period;
920
921 if (samples && count > samples)
922 count = samples;
923
924 ret = bmc150_accel_fifo_transfer(data, (u8 *)buffer, count);
925 if (ret)
926 return ret;
927
928
929
930
931
932
933
934 for (i = 0; i < count; i++) {
935 u16 sample[8];
936 int j, bit;
937
938 j = 0;
939 for_each_set_bit(bit, indio_dev->active_scan_mask,
940 indio_dev->masklength)
941 memcpy(&sample[j++], &buffer[i * 3 + bit], 2);
942
943 iio_push_to_buffers_with_timestamp(indio_dev, sample, tstamp);
944
945 tstamp += sample_period;
946 }
947
948 return count;
949}
950
951static int bmc150_accel_fifo_flush(struct iio_dev *indio_dev, unsigned samples)
952{
953 struct bmc150_accel_data *data = iio_priv(indio_dev);
954 int ret;
955
956 mutex_lock(&data->mutex);
957 ret = __bmc150_accel_fifo_flush(indio_dev, samples, false);
958 mutex_unlock(&data->mutex);
959
960 return ret;
961}
962
963static IIO_CONST_ATTR_SAMP_FREQ_AVAIL(
964 "15.620000 31.260000 62.50000 125 250 500 1000 2000");
965
966static struct attribute *bmc150_accel_attributes[] = {
967 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
968 NULL,
969};
970
971static const struct attribute_group bmc150_accel_attrs_group = {
972 .attrs = bmc150_accel_attributes,
973};
974
975static const struct iio_event_spec bmc150_accel_event = {
976 .type = IIO_EV_TYPE_ROC,
977 .dir = IIO_EV_DIR_EITHER,
978 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
979 BIT(IIO_EV_INFO_ENABLE) |
980 BIT(IIO_EV_INFO_PERIOD)
981};
982
983#define BMC150_ACCEL_CHANNEL(_axis, bits) { \
984 .type = IIO_ACCEL, \
985 .modified = 1, \
986 .channel2 = IIO_MOD_##_axis, \
987 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
988 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | \
989 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
990 .scan_index = AXIS_##_axis, \
991 .scan_type = { \
992 .sign = 's', \
993 .realbits = (bits), \
994 .storagebits = 16, \
995 .shift = 16 - (bits), \
996 .endianness = IIO_LE, \
997 }, \
998 .event_spec = &bmc150_accel_event, \
999 .num_event_specs = 1 \
1000}
1001
1002#define BMC150_ACCEL_CHANNELS(bits) { \
1003 { \
1004 .type = IIO_TEMP, \
1005 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
1006 BIT(IIO_CHAN_INFO_SCALE) | \
1007 BIT(IIO_CHAN_INFO_OFFSET), \
1008 .scan_index = -1, \
1009 }, \
1010 BMC150_ACCEL_CHANNEL(X, bits), \
1011 BMC150_ACCEL_CHANNEL(Y, bits), \
1012 BMC150_ACCEL_CHANNEL(Z, bits), \
1013 IIO_CHAN_SOFT_TIMESTAMP(3), \
1014}
1015
1016static const struct iio_chan_spec bma222e_accel_channels[] =
1017 BMC150_ACCEL_CHANNELS(8);
1018static const struct iio_chan_spec bma250e_accel_channels[] =
1019 BMC150_ACCEL_CHANNELS(10);
1020static const struct iio_chan_spec bmc150_accel_channels[] =
1021 BMC150_ACCEL_CHANNELS(12);
1022static const struct iio_chan_spec bma280_accel_channels[] =
1023 BMC150_ACCEL_CHANNELS(14);
1024
1025static const struct bmc150_accel_chip_info bmc150_accel_chip_info_tbl[] = {
1026 [bmc150] = {
1027 .name = "BMC150A",
1028 .chip_id = 0xFA,
1029 .channels = bmc150_accel_channels,
1030 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1031 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1032 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1033 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1034 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1035 },
1036 [bmi055] = {
1037 .name = "BMI055A",
1038 .chip_id = 0xFA,
1039 .channels = bmc150_accel_channels,
1040 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1041 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1042 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1043 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1044 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1045 },
1046 [bma255] = {
1047 .name = "BMA0255",
1048 .chip_id = 0xFA,
1049 .channels = bmc150_accel_channels,
1050 .num_channels = ARRAY_SIZE(bmc150_accel_channels),
1051 .scale_table = { {9610, BMC150_ACCEL_DEF_RANGE_2G},
1052 {19122, BMC150_ACCEL_DEF_RANGE_4G},
1053 {38344, BMC150_ACCEL_DEF_RANGE_8G},
1054 {76590, BMC150_ACCEL_DEF_RANGE_16G} },
1055 },
1056 [bma250e] = {
1057 .name = "BMA250E",
1058 .chip_id = 0xF9,
1059 .channels = bma250e_accel_channels,
1060 .num_channels = ARRAY_SIZE(bma250e_accel_channels),
1061 .scale_table = { {38344, BMC150_ACCEL_DEF_RANGE_2G},
1062 {76590, BMC150_ACCEL_DEF_RANGE_4G},
1063 {153277, BMC150_ACCEL_DEF_RANGE_8G},
1064 {306457, BMC150_ACCEL_DEF_RANGE_16G} },
1065 },
1066 [bma222e] = {
1067 .name = "BMA222E",
1068 .chip_id = 0xF8,
1069 .channels = bma222e_accel_channels,
1070 .num_channels = ARRAY_SIZE(bma222e_accel_channels),
1071 .scale_table = { {153277, BMC150_ACCEL_DEF_RANGE_2G},
1072 {306457, BMC150_ACCEL_DEF_RANGE_4G},
1073 {612915, BMC150_ACCEL_DEF_RANGE_8G},
1074 {1225831, BMC150_ACCEL_DEF_RANGE_16G} },
1075 },
1076 [bma280] = {
1077 .name = "BMA0280",
1078 .chip_id = 0xFB,
1079 .channels = bma280_accel_channels,
1080 .num_channels = ARRAY_SIZE(bma280_accel_channels),
1081 .scale_table = { {2392, BMC150_ACCEL_DEF_RANGE_2G},
1082 {4785, BMC150_ACCEL_DEF_RANGE_4G},
1083 {9581, BMC150_ACCEL_DEF_RANGE_8G},
1084 {19152, BMC150_ACCEL_DEF_RANGE_16G} },
1085 },
1086};
1087
1088static const struct iio_info bmc150_accel_info = {
1089 .attrs = &bmc150_accel_attrs_group,
1090 .read_raw = bmc150_accel_read_raw,
1091 .write_raw = bmc150_accel_write_raw,
1092 .read_event_value = bmc150_accel_read_event,
1093 .write_event_value = bmc150_accel_write_event,
1094 .write_event_config = bmc150_accel_write_event_config,
1095 .read_event_config = bmc150_accel_read_event_config,
1096};
1097
1098static const struct iio_info bmc150_accel_info_fifo = {
1099 .attrs = &bmc150_accel_attrs_group,
1100 .read_raw = bmc150_accel_read_raw,
1101 .write_raw = bmc150_accel_write_raw,
1102 .read_event_value = bmc150_accel_read_event,
1103 .write_event_value = bmc150_accel_write_event,
1104 .write_event_config = bmc150_accel_write_event_config,
1105 .read_event_config = bmc150_accel_read_event_config,
1106 .validate_trigger = bmc150_accel_validate_trigger,
1107 .hwfifo_set_watermark = bmc150_accel_set_watermark,
1108 .hwfifo_flush_to_buffer = bmc150_accel_fifo_flush,
1109};
1110
1111static const unsigned long bmc150_accel_scan_masks[] = {
1112 BIT(AXIS_X) | BIT(AXIS_Y) | BIT(AXIS_Z),
1113 0};
1114
1115static irqreturn_t bmc150_accel_trigger_handler(int irq, void *p)
1116{
1117 struct iio_poll_func *pf = p;
1118 struct iio_dev *indio_dev = pf->indio_dev;
1119 struct bmc150_accel_data *data = iio_priv(indio_dev);
1120 int ret;
1121
1122 mutex_lock(&data->mutex);
1123 ret = regmap_bulk_read(data->regmap, BMC150_ACCEL_REG_XOUT_L,
1124 data->buffer, AXIS_MAX * 2);
1125 mutex_unlock(&data->mutex);
1126 if (ret < 0)
1127 goto err_read;
1128
1129 iio_push_to_buffers_with_timestamp(indio_dev, data->buffer,
1130 pf->timestamp);
1131err_read:
1132 iio_trigger_notify_done(indio_dev->trig);
1133
1134 return IRQ_HANDLED;
1135}
1136
1137static int bmc150_accel_trig_try_reen(struct iio_trigger *trig)
1138{
1139 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1140 struct bmc150_accel_data *data = t->data;
1141 struct device *dev = regmap_get_device(data->regmap);
1142 int ret;
1143
1144
1145 if (t == &t->data->triggers[BMC150_ACCEL_TRIGGER_DATA_READY])
1146 return 0;
1147
1148 mutex_lock(&data->mutex);
1149
1150 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1151 BMC150_ACCEL_INT_MODE_LATCH_INT |
1152 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1153 mutex_unlock(&data->mutex);
1154 if (ret < 0) {
1155 dev_err(dev, "Error writing reg_int_rst_latch\n");
1156 return ret;
1157 }
1158
1159 return 0;
1160}
1161
1162static int bmc150_accel_trigger_set_state(struct iio_trigger *trig,
1163 bool state)
1164{
1165 struct bmc150_accel_trigger *t = iio_trigger_get_drvdata(trig);
1166 struct bmc150_accel_data *data = t->data;
1167 int ret;
1168
1169 mutex_lock(&data->mutex);
1170
1171 if (t->enabled == state) {
1172 mutex_unlock(&data->mutex);
1173 return 0;
1174 }
1175
1176 if (t->setup) {
1177 ret = t->setup(t, state);
1178 if (ret < 0) {
1179 mutex_unlock(&data->mutex);
1180 return ret;
1181 }
1182 }
1183
1184 ret = bmc150_accel_set_interrupt(data, t->intr, state);
1185 if (ret < 0) {
1186 mutex_unlock(&data->mutex);
1187 return ret;
1188 }
1189
1190 t->enabled = state;
1191
1192 mutex_unlock(&data->mutex);
1193
1194 return ret;
1195}
1196
1197static const struct iio_trigger_ops bmc150_accel_trigger_ops = {
1198 .set_trigger_state = bmc150_accel_trigger_set_state,
1199 .try_reenable = bmc150_accel_trig_try_reen,
1200};
1201
1202static int bmc150_accel_handle_roc_event(struct iio_dev *indio_dev)
1203{
1204 struct bmc150_accel_data *data = iio_priv(indio_dev);
1205 struct device *dev = regmap_get_device(data->regmap);
1206 int dir;
1207 int ret;
1208 unsigned int val;
1209
1210 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_INT_STATUS_2, &val);
1211 if (ret < 0) {
1212 dev_err(dev, "Error reading reg_int_status_2\n");
1213 return ret;
1214 }
1215
1216 if (val & BMC150_ACCEL_ANY_MOTION_BIT_SIGN)
1217 dir = IIO_EV_DIR_FALLING;
1218 else
1219 dir = IIO_EV_DIR_RISING;
1220
1221 if (val & BMC150_ACCEL_ANY_MOTION_BIT_X)
1222 iio_push_event(indio_dev,
1223 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1224 0,
1225 IIO_MOD_X,
1226 IIO_EV_TYPE_ROC,
1227 dir),
1228 data->timestamp);
1229
1230 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Y)
1231 iio_push_event(indio_dev,
1232 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1233 0,
1234 IIO_MOD_Y,
1235 IIO_EV_TYPE_ROC,
1236 dir),
1237 data->timestamp);
1238
1239 if (val & BMC150_ACCEL_ANY_MOTION_BIT_Z)
1240 iio_push_event(indio_dev,
1241 IIO_MOD_EVENT_CODE(IIO_ACCEL,
1242 0,
1243 IIO_MOD_Z,
1244 IIO_EV_TYPE_ROC,
1245 dir),
1246 data->timestamp);
1247
1248 return ret;
1249}
1250
1251static irqreturn_t bmc150_accel_irq_thread_handler(int irq, void *private)
1252{
1253 struct iio_dev *indio_dev = private;
1254 struct bmc150_accel_data *data = iio_priv(indio_dev);
1255 struct device *dev = regmap_get_device(data->regmap);
1256 bool ack = false;
1257 int ret;
1258
1259 mutex_lock(&data->mutex);
1260
1261 if (data->fifo_mode) {
1262 ret = __bmc150_accel_fifo_flush(indio_dev,
1263 BMC150_ACCEL_FIFO_LENGTH, true);
1264 if (ret > 0)
1265 ack = true;
1266 }
1267
1268 if (data->ev_enable_state) {
1269 ret = bmc150_accel_handle_roc_event(indio_dev);
1270 if (ret > 0)
1271 ack = true;
1272 }
1273
1274 if (ack) {
1275 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1276 BMC150_ACCEL_INT_MODE_LATCH_INT |
1277 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1278 if (ret)
1279 dev_err(dev, "Error writing reg_int_rst_latch\n");
1280
1281 ret = IRQ_HANDLED;
1282 } else {
1283 ret = IRQ_NONE;
1284 }
1285
1286 mutex_unlock(&data->mutex);
1287
1288 return ret;
1289}
1290
1291static irqreturn_t bmc150_accel_irq_handler(int irq, void *private)
1292{
1293 struct iio_dev *indio_dev = private;
1294 struct bmc150_accel_data *data = iio_priv(indio_dev);
1295 bool ack = false;
1296 int i;
1297
1298 data->old_timestamp = data->timestamp;
1299 data->timestamp = iio_get_time_ns(indio_dev);
1300
1301 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1302 if (data->triggers[i].enabled) {
1303 iio_trigger_poll(data->triggers[i].indio_trig);
1304 ack = true;
1305 break;
1306 }
1307 }
1308
1309 if (data->ev_enable_state || data->fifo_mode)
1310 return IRQ_WAKE_THREAD;
1311
1312 if (ack)
1313 return IRQ_HANDLED;
1314
1315 return IRQ_NONE;
1316}
1317
1318static const struct {
1319 int intr;
1320 const char *name;
1321 int (*setup)(struct bmc150_accel_trigger *t, bool state);
1322} bmc150_accel_triggers[BMC150_ACCEL_TRIGGERS] = {
1323 {
1324 .intr = 0,
1325 .name = "%s-dev%d",
1326 },
1327 {
1328 .intr = 1,
1329 .name = "%s-any-motion-dev%d",
1330 .setup = bmc150_accel_any_motion_setup,
1331 },
1332};
1333
1334static void bmc150_accel_unregister_triggers(struct bmc150_accel_data *data,
1335 int from)
1336{
1337 int i;
1338
1339 for (i = from; i >= 0; i--) {
1340 if (data->triggers[i].indio_trig) {
1341 iio_trigger_unregister(data->triggers[i].indio_trig);
1342 data->triggers[i].indio_trig = NULL;
1343 }
1344 }
1345}
1346
1347static int bmc150_accel_triggers_setup(struct iio_dev *indio_dev,
1348 struct bmc150_accel_data *data)
1349{
1350 struct device *dev = regmap_get_device(data->regmap);
1351 int i, ret;
1352
1353 for (i = 0; i < BMC150_ACCEL_TRIGGERS; i++) {
1354 struct bmc150_accel_trigger *t = &data->triggers[i];
1355
1356 t->indio_trig = devm_iio_trigger_alloc(dev,
1357 bmc150_accel_triggers[i].name,
1358 indio_dev->name,
1359 indio_dev->id);
1360 if (!t->indio_trig) {
1361 ret = -ENOMEM;
1362 break;
1363 }
1364
1365 t->indio_trig->dev.parent = dev;
1366 t->indio_trig->ops = &bmc150_accel_trigger_ops;
1367 t->intr = bmc150_accel_triggers[i].intr;
1368 t->data = data;
1369 t->setup = bmc150_accel_triggers[i].setup;
1370 iio_trigger_set_drvdata(t->indio_trig, t);
1371
1372 ret = iio_trigger_register(t->indio_trig);
1373 if (ret)
1374 break;
1375 }
1376
1377 if (ret)
1378 bmc150_accel_unregister_triggers(data, i - 1);
1379
1380 return ret;
1381}
1382
1383#define BMC150_ACCEL_FIFO_MODE_STREAM 0x80
1384#define BMC150_ACCEL_FIFO_MODE_FIFO 0x40
1385#define BMC150_ACCEL_FIFO_MODE_BYPASS 0x00
1386
1387static int bmc150_accel_fifo_set_mode(struct bmc150_accel_data *data)
1388{
1389 struct device *dev = regmap_get_device(data->regmap);
1390 u8 reg = BMC150_ACCEL_REG_FIFO_CONFIG1;
1391 int ret;
1392
1393 ret = regmap_write(data->regmap, reg, data->fifo_mode);
1394 if (ret < 0) {
1395 dev_err(dev, "Error writing reg_fifo_config1\n");
1396 return ret;
1397 }
1398
1399 if (!data->fifo_mode)
1400 return 0;
1401
1402 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_FIFO_CONFIG0,
1403 data->watermark);
1404 if (ret < 0)
1405 dev_err(dev, "Error writing reg_fifo_config0\n");
1406
1407 return ret;
1408}
1409
1410static int bmc150_accel_buffer_preenable(struct iio_dev *indio_dev)
1411{
1412 struct bmc150_accel_data *data = iio_priv(indio_dev);
1413
1414 return bmc150_accel_set_power_state(data, true);
1415}
1416
1417static int bmc150_accel_buffer_postenable(struct iio_dev *indio_dev)
1418{
1419 struct bmc150_accel_data *data = iio_priv(indio_dev);
1420 int ret = 0;
1421
1422 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1423 return iio_triggered_buffer_postenable(indio_dev);
1424
1425 mutex_lock(&data->mutex);
1426
1427 if (!data->watermark)
1428 goto out;
1429
1430 ret = bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1431 true);
1432 if (ret)
1433 goto out;
1434
1435 data->fifo_mode = BMC150_ACCEL_FIFO_MODE_FIFO;
1436
1437 ret = bmc150_accel_fifo_set_mode(data);
1438 if (ret) {
1439 data->fifo_mode = 0;
1440 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK,
1441 false);
1442 }
1443
1444out:
1445 mutex_unlock(&data->mutex);
1446
1447 return ret;
1448}
1449
1450static int bmc150_accel_buffer_predisable(struct iio_dev *indio_dev)
1451{
1452 struct bmc150_accel_data *data = iio_priv(indio_dev);
1453
1454 if (indio_dev->currentmode == INDIO_BUFFER_TRIGGERED)
1455 return iio_triggered_buffer_predisable(indio_dev);
1456
1457 mutex_lock(&data->mutex);
1458
1459 if (!data->fifo_mode)
1460 goto out;
1461
1462 bmc150_accel_set_interrupt(data, BMC150_ACCEL_INT_WATERMARK, false);
1463 __bmc150_accel_fifo_flush(indio_dev, BMC150_ACCEL_FIFO_LENGTH, false);
1464 data->fifo_mode = 0;
1465 bmc150_accel_fifo_set_mode(data);
1466
1467out:
1468 mutex_unlock(&data->mutex);
1469
1470 return 0;
1471}
1472
1473static int bmc150_accel_buffer_postdisable(struct iio_dev *indio_dev)
1474{
1475 struct bmc150_accel_data *data = iio_priv(indio_dev);
1476
1477 return bmc150_accel_set_power_state(data, false);
1478}
1479
1480static const struct iio_buffer_setup_ops bmc150_accel_buffer_ops = {
1481 .preenable = bmc150_accel_buffer_preenable,
1482 .postenable = bmc150_accel_buffer_postenable,
1483 .predisable = bmc150_accel_buffer_predisable,
1484 .postdisable = bmc150_accel_buffer_postdisable,
1485};
1486
1487static int bmc150_accel_chip_init(struct bmc150_accel_data *data)
1488{
1489 struct device *dev = regmap_get_device(data->regmap);
1490 int ret, i;
1491 unsigned int val;
1492
1493
1494
1495
1496
1497 regmap_write(data->regmap, BMC150_ACCEL_REG_RESET,
1498 BMC150_ACCEL_RESET_VAL);
1499 usleep_range(1800, 2500);
1500
1501 ret = regmap_read(data->regmap, BMC150_ACCEL_REG_CHIP_ID, &val);
1502 if (ret < 0) {
1503 dev_err(dev, "Error: Reading chip id\n");
1504 return ret;
1505 }
1506
1507 dev_dbg(dev, "Chip Id %x\n", val);
1508 for (i = 0; i < ARRAY_SIZE(bmc150_accel_chip_info_tbl); i++) {
1509 if (bmc150_accel_chip_info_tbl[i].chip_id == val) {
1510 data->chip_info = &bmc150_accel_chip_info_tbl[i];
1511 break;
1512 }
1513 }
1514
1515 if (!data->chip_info) {
1516 dev_err(dev, "Invalid chip %x\n", val);
1517 return -ENODEV;
1518 }
1519
1520 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1521 if (ret < 0)
1522 return ret;
1523
1524
1525 ret = bmc150_accel_set_bw(data, BMC150_ACCEL_DEF_BW, 0);
1526 if (ret < 0)
1527 return ret;
1528
1529
1530 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_PMU_RANGE,
1531 BMC150_ACCEL_DEF_RANGE_4G);
1532 if (ret < 0) {
1533 dev_err(dev, "Error writing reg_pmu_range\n");
1534 return ret;
1535 }
1536
1537 data->range = BMC150_ACCEL_DEF_RANGE_4G;
1538
1539
1540 data->slope_thres = BMC150_ACCEL_DEF_SLOPE_THRESHOLD;
1541 data->slope_dur = BMC150_ACCEL_DEF_SLOPE_DURATION;
1542 ret = bmc150_accel_update_slope(data);
1543 if (ret < 0)
1544 return ret;
1545
1546
1547 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1548 BMC150_ACCEL_INT_MODE_LATCH_INT |
1549 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1550 if (ret < 0) {
1551 dev_err(dev, "Error writing reg_int_rst_latch\n");
1552 return ret;
1553 }
1554
1555 return 0;
1556}
1557
1558int bmc150_accel_core_probe(struct device *dev, struct regmap *regmap, int irq,
1559 const char *name, bool block_supported)
1560{
1561 struct bmc150_accel_data *data;
1562 struct iio_dev *indio_dev;
1563 int ret;
1564
1565 indio_dev = devm_iio_device_alloc(dev, sizeof(*data));
1566 if (!indio_dev)
1567 return -ENOMEM;
1568
1569 data = iio_priv(indio_dev);
1570 dev_set_drvdata(dev, indio_dev);
1571 data->irq = irq;
1572
1573 data->regmap = regmap;
1574
1575 ret = bmc150_accel_chip_init(data);
1576 if (ret < 0)
1577 return ret;
1578
1579 mutex_init(&data->mutex);
1580
1581 indio_dev->dev.parent = dev;
1582 indio_dev->channels = data->chip_info->channels;
1583 indio_dev->num_channels = data->chip_info->num_channels;
1584 indio_dev->name = name ? name : data->chip_info->name;
1585 indio_dev->available_scan_masks = bmc150_accel_scan_masks;
1586 indio_dev->modes = INDIO_DIRECT_MODE;
1587 indio_dev->info = &bmc150_accel_info;
1588
1589 ret = iio_triggered_buffer_setup(indio_dev,
1590 &iio_pollfunc_store_time,
1591 bmc150_accel_trigger_handler,
1592 &bmc150_accel_buffer_ops);
1593 if (ret < 0) {
1594 dev_err(dev, "Failed: iio triggered buffer setup\n");
1595 return ret;
1596 }
1597
1598 if (data->irq > 0) {
1599 ret = devm_request_threaded_irq(
1600 dev, data->irq,
1601 bmc150_accel_irq_handler,
1602 bmc150_accel_irq_thread_handler,
1603 IRQF_TRIGGER_RISING,
1604 BMC150_ACCEL_IRQ_NAME,
1605 indio_dev);
1606 if (ret)
1607 goto err_buffer_cleanup;
1608
1609
1610
1611
1612
1613
1614
1615 ret = regmap_write(data->regmap, BMC150_ACCEL_REG_INT_RST_LATCH,
1616 BMC150_ACCEL_INT_MODE_LATCH_RESET);
1617 if (ret < 0) {
1618 dev_err(dev, "Error writing reg_int_rst_latch\n");
1619 goto err_buffer_cleanup;
1620 }
1621
1622 bmc150_accel_interrupts_setup(indio_dev, data);
1623
1624 ret = bmc150_accel_triggers_setup(indio_dev, data);
1625 if (ret)
1626 goto err_buffer_cleanup;
1627
1628 if (block_supported) {
1629 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1630 indio_dev->info = &bmc150_accel_info_fifo;
1631 iio_buffer_set_attrs(indio_dev->buffer,
1632 bmc150_accel_fifo_attributes);
1633 }
1634 }
1635
1636 ret = pm_runtime_set_active(dev);
1637 if (ret)
1638 goto err_trigger_unregister;
1639
1640 pm_runtime_enable(dev);
1641 pm_runtime_set_autosuspend_delay(dev, BMC150_AUTO_SUSPEND_DELAY_MS);
1642 pm_runtime_use_autosuspend(dev);
1643
1644 ret = iio_device_register(indio_dev);
1645 if (ret < 0) {
1646 dev_err(dev, "Unable to register iio device\n");
1647 goto err_trigger_unregister;
1648 }
1649
1650 return 0;
1651
1652err_trigger_unregister:
1653 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1654err_buffer_cleanup:
1655 iio_triggered_buffer_cleanup(indio_dev);
1656
1657 return ret;
1658}
1659EXPORT_SYMBOL_GPL(bmc150_accel_core_probe);
1660
1661int bmc150_accel_core_remove(struct device *dev)
1662{
1663 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1664 struct bmc150_accel_data *data = iio_priv(indio_dev);
1665
1666 iio_device_unregister(indio_dev);
1667
1668 pm_runtime_disable(dev);
1669 pm_runtime_set_suspended(dev);
1670 pm_runtime_put_noidle(dev);
1671
1672 bmc150_accel_unregister_triggers(data, BMC150_ACCEL_TRIGGERS - 1);
1673
1674 iio_triggered_buffer_cleanup(indio_dev);
1675
1676 mutex_lock(&data->mutex);
1677 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_DEEP_SUSPEND, 0);
1678 mutex_unlock(&data->mutex);
1679
1680 return 0;
1681}
1682EXPORT_SYMBOL_GPL(bmc150_accel_core_remove);
1683
1684#ifdef CONFIG_PM_SLEEP
1685static int bmc150_accel_suspend(struct device *dev)
1686{
1687 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1688 struct bmc150_accel_data *data = iio_priv(indio_dev);
1689
1690 mutex_lock(&data->mutex);
1691 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1692 mutex_unlock(&data->mutex);
1693
1694 return 0;
1695}
1696
1697static int bmc150_accel_resume(struct device *dev)
1698{
1699 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1700 struct bmc150_accel_data *data = iio_priv(indio_dev);
1701
1702 mutex_lock(&data->mutex);
1703 bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1704 bmc150_accel_fifo_set_mode(data);
1705 mutex_unlock(&data->mutex);
1706
1707 return 0;
1708}
1709#endif
1710
1711#ifdef CONFIG_PM
1712static int bmc150_accel_runtime_suspend(struct device *dev)
1713{
1714 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1715 struct bmc150_accel_data *data = iio_priv(indio_dev);
1716 int ret;
1717
1718 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_SUSPEND, 0);
1719 if (ret < 0)
1720 return -EAGAIN;
1721
1722 return 0;
1723}
1724
1725static int bmc150_accel_runtime_resume(struct device *dev)
1726{
1727 struct iio_dev *indio_dev = dev_get_drvdata(dev);
1728 struct bmc150_accel_data *data = iio_priv(indio_dev);
1729 int ret;
1730 int sleep_val;
1731
1732 ret = bmc150_accel_set_mode(data, BMC150_ACCEL_SLEEP_MODE_NORMAL, 0);
1733 if (ret < 0)
1734 return ret;
1735 ret = bmc150_accel_fifo_set_mode(data);
1736 if (ret < 0)
1737 return ret;
1738
1739 sleep_val = bmc150_accel_get_startup_times(data);
1740 if (sleep_val < 20)
1741 usleep_range(sleep_val * 1000, 20000);
1742 else
1743 msleep_interruptible(sleep_val);
1744
1745 return 0;
1746}
1747#endif
1748
1749const struct dev_pm_ops bmc150_accel_pm_ops = {
1750 SET_SYSTEM_SLEEP_PM_OPS(bmc150_accel_suspend, bmc150_accel_resume)
1751 SET_RUNTIME_PM_OPS(bmc150_accel_runtime_suspend,
1752 bmc150_accel_runtime_resume, NULL)
1753};
1754EXPORT_SYMBOL_GPL(bmc150_accel_pm_ops);
1755
1756MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
1757MODULE_LICENSE("GPL v2");
1758MODULE_DESCRIPTION("BMC150 accelerometer driver");
1759
