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9#include <linux/dmaengine.h>
10#include <linux/dma-mapping.h>
11#include <linux/interrupt.h>
12#include <linux/iio/buffer.h>
13#include <linux/iio/hw-consumer.h>
14#include <linux/iio/iio.h>
15#include <linux/iio/sysfs.h>
16#include <linux/module.h>
17#include <linux/of_device.h>
18#include <linux/platform_device.h>
19#include <linux/regmap.h>
20#include <linux/slab.h>
21
22#include "stm32-dfsdm.h"
23
24#define DFSDM_DMA_BUFFER_SIZE (4 * PAGE_SIZE)
25
26
27#define DFSDM_TIMEOUT_US 100000
28#define DFSDM_TIMEOUT (msecs_to_jiffies(DFSDM_TIMEOUT_US / 1000))
29
30
31#define DFSDM_DEFAULT_OVERSAMPLING 100
32
33
34#define DFSDM_MAX_INT_OVERSAMPLING 256
35#define DFSDM_MAX_FL_OVERSAMPLING 1024
36
37
38#define DFSDM_MAX_RES BIT(31)
39#define DFSDM_DATA_RES BIT(23)
40
41enum sd_converter_type {
42 DFSDM_AUDIO,
43 DFSDM_IIO,
44};
45
46struct stm32_dfsdm_dev_data {
47 int type;
48 int (*init)(struct iio_dev *indio_dev);
49 unsigned int num_channels;
50 const struct regmap_config *regmap_cfg;
51};
52
53struct stm32_dfsdm_adc {
54 struct stm32_dfsdm *dfsdm;
55 const struct stm32_dfsdm_dev_data *dev_data;
56 unsigned int fl_id;
57
58
59 unsigned int oversamp;
60 struct iio_hw_consumer *hwc;
61 struct completion completion;
62 u32 *buffer;
63
64
65 unsigned int spi_freq;
66 unsigned int sample_freq;
67 int (*cb)(const void *data, size_t size, void *cb_priv);
68 void *cb_priv;
69
70
71 u8 *rx_buf;
72 unsigned int bufi;
73 unsigned int buf_sz;
74 struct dma_chan *dma_chan;
75 dma_addr_t dma_buf;
76};
77
78struct stm32_dfsdm_str2field {
79 const char *name;
80 unsigned int val;
81};
82
83
84static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_type[] = {
85 { "SPI_R", 0 },
86 { "SPI_F", 1 },
87 { "MANCH_R", 2 },
88 { "MANCH_F", 3 },
89 {},
90};
91
92
93static const struct stm32_dfsdm_str2field stm32_dfsdm_chan_src[] = {
94
95 { "CLKIN", DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL },
96
97 { "CLKOUT", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL },
98
99 { "CLKOUT_F", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING },
100
101 { "CLKOUT_R", DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING },
102 {},
103};
104
105static int stm32_dfsdm_str2val(const char *str,
106 const struct stm32_dfsdm_str2field *list)
107{
108 const struct stm32_dfsdm_str2field *p = list;
109
110 for (p = list; p && p->name; p++)
111 if (!strcmp(p->name, str))
112 return p->val;
113
114 return -EINVAL;
115}
116
117static int stm32_dfsdm_set_osrs(struct stm32_dfsdm_filter *fl,
118 unsigned int fast, unsigned int oversamp)
119{
120 unsigned int i, d, fosr, iosr;
121 u64 res;
122 s64 delta;
123 unsigned int m = 1;
124 unsigned int p = fl->ford;
125
126 pr_debug("%s: Requested oversampling: %d\n", __func__, oversamp);
127
128
129
130
131
132
133
134
135
136 if (fl->ford == DFSDM_FASTSINC_ORDER) {
137 m = 2;
138 p = 2;
139 }
140
141
142
143
144
145
146
147 fl->res = 0;
148 for (fosr = 1; fosr <= DFSDM_MAX_FL_OVERSAMPLING; fosr++) {
149 for (iosr = 1; iosr <= DFSDM_MAX_INT_OVERSAMPLING; iosr++) {
150 if (fast)
151 d = fosr * iosr;
152 else if (fl->ford == DFSDM_FASTSINC_ORDER)
153 d = fosr * (iosr + 3) + 2;
154 else
155 d = fosr * (iosr - 1 + p) + p;
156
157 if (d > oversamp)
158 break;
159 else if (d != oversamp)
160 continue;
161
162
163
164
165
166
167
168
169 res = fosr;
170 for (i = p - 1; i > 0; i--) {
171 res = res * (u64)fosr;
172 if (res > DFSDM_MAX_RES)
173 break;
174 }
175 if (res > DFSDM_MAX_RES)
176 continue;
177 res = res * (u64)m * (u64)iosr;
178 if (res > DFSDM_MAX_RES)
179 continue;
180
181 delta = res - DFSDM_DATA_RES;
182
183 if (res >= fl->res) {
184 fl->res = res;
185 fl->fosr = fosr;
186 fl->iosr = iosr;
187 fl->fast = fast;
188 pr_debug("%s: fosr = %d, iosr = %d\n",
189 __func__, fl->fosr, fl->iosr);
190 }
191
192 if (!delta)
193 return 0;
194 }
195 }
196
197 if (!fl->res)
198 return -EINVAL;
199
200 return 0;
201}
202
203static int stm32_dfsdm_start_channel(struct stm32_dfsdm *dfsdm,
204 unsigned int ch_id)
205{
206 return regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
207 DFSDM_CHCFGR1_CHEN_MASK,
208 DFSDM_CHCFGR1_CHEN(1));
209}
210
211static void stm32_dfsdm_stop_channel(struct stm32_dfsdm *dfsdm,
212 unsigned int ch_id)
213{
214 regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(ch_id),
215 DFSDM_CHCFGR1_CHEN_MASK, DFSDM_CHCFGR1_CHEN(0));
216}
217
218static int stm32_dfsdm_chan_configure(struct stm32_dfsdm *dfsdm,
219 struct stm32_dfsdm_channel *ch)
220{
221 unsigned int id = ch->id;
222 struct regmap *regmap = dfsdm->regmap;
223 int ret;
224
225 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
226 DFSDM_CHCFGR1_SITP_MASK,
227 DFSDM_CHCFGR1_SITP(ch->type));
228 if (ret < 0)
229 return ret;
230 ret = regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
231 DFSDM_CHCFGR1_SPICKSEL_MASK,
232 DFSDM_CHCFGR1_SPICKSEL(ch->src));
233 if (ret < 0)
234 return ret;
235 return regmap_update_bits(regmap, DFSDM_CHCFGR1(id),
236 DFSDM_CHCFGR1_CHINSEL_MASK,
237 DFSDM_CHCFGR1_CHINSEL(ch->alt_si));
238}
239
240static int stm32_dfsdm_start_filter(struct stm32_dfsdm *dfsdm,
241 unsigned int fl_id)
242{
243 int ret;
244
245
246 ret = regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
247 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(1));
248 if (ret < 0)
249 return ret;
250
251
252 return regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
253 DFSDM_CR1_RSWSTART_MASK,
254 DFSDM_CR1_RSWSTART(1));
255}
256
257static void stm32_dfsdm_stop_filter(struct stm32_dfsdm *dfsdm, unsigned int fl_id)
258{
259
260 regmap_update_bits(dfsdm->regmap, DFSDM_CR1(fl_id),
261 DFSDM_CR1_DFEN_MASK, DFSDM_CR1_DFEN(0));
262}
263
264static int stm32_dfsdm_filter_configure(struct stm32_dfsdm *dfsdm,
265 unsigned int fl_id, unsigned int ch_id)
266{
267 struct regmap *regmap = dfsdm->regmap;
268 struct stm32_dfsdm_filter *fl = &dfsdm->fl_list[fl_id];
269 int ret;
270
271
272 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_IOSR_MASK,
273 DFSDM_FCR_IOSR(fl->iosr - 1));
274 if (ret)
275 return ret;
276
277
278 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FOSR_MASK,
279 DFSDM_FCR_FOSR(fl->fosr - 1));
280 if (ret)
281 return ret;
282
283 ret = regmap_update_bits(regmap, DFSDM_FCR(fl_id), DFSDM_FCR_FORD_MASK,
284 DFSDM_FCR_FORD(fl->ford));
285 if (ret)
286 return ret;
287
288
289 ret = regmap_update_bits(regmap, DFSDM_CR1(fl_id), DFSDM_CR1_RCH_MASK,
290 DFSDM_CR1_RCH(ch_id));
291 if (ret)
292 return ret;
293
294 return regmap_update_bits(regmap, DFSDM_CR1(fl_id),
295 DFSDM_CR1_RSYNC_MASK,
296 DFSDM_CR1_RSYNC(fl->sync_mode));
297}
298
299static int stm32_dfsdm_channel_parse_of(struct stm32_dfsdm *dfsdm,
300 struct iio_dev *indio_dev,
301 struct iio_chan_spec *ch)
302{
303 struct stm32_dfsdm_channel *df_ch;
304 const char *of_str;
305 int chan_idx = ch->scan_index;
306 int ret, val;
307
308 ret = of_property_read_u32_index(indio_dev->dev.of_node,
309 "st,adc-channels", chan_idx,
310 &ch->channel);
311 if (ret < 0) {
312 dev_err(&indio_dev->dev,
313 " Error parsing 'st,adc-channels' for idx %d\n",
314 chan_idx);
315 return ret;
316 }
317 if (ch->channel >= dfsdm->num_chs) {
318 dev_err(&indio_dev->dev,
319 " Error bad channel number %d (max = %d)\n",
320 ch->channel, dfsdm->num_chs);
321 return -EINVAL;
322 }
323
324 ret = of_property_read_string_index(indio_dev->dev.of_node,
325 "st,adc-channel-names", chan_idx,
326 &ch->datasheet_name);
327 if (ret < 0) {
328 dev_err(&indio_dev->dev,
329 " Error parsing 'st,adc-channel-names' for idx %d\n",
330 chan_idx);
331 return ret;
332 }
333
334 df_ch = &dfsdm->ch_list[ch->channel];
335 df_ch->id = ch->channel;
336
337 ret = of_property_read_string_index(indio_dev->dev.of_node,
338 "st,adc-channel-types", chan_idx,
339 &of_str);
340 if (!ret) {
341 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_type);
342 if (val < 0)
343 return val;
344 } else {
345 val = 0;
346 }
347 df_ch->type = val;
348
349 ret = of_property_read_string_index(indio_dev->dev.of_node,
350 "st,adc-channel-clk-src", chan_idx,
351 &of_str);
352 if (!ret) {
353 val = stm32_dfsdm_str2val(of_str, stm32_dfsdm_chan_src);
354 if (val < 0)
355 return val;
356 } else {
357 val = 0;
358 }
359 df_ch->src = val;
360
361 ret = of_property_read_u32_index(indio_dev->dev.of_node,
362 "st,adc-alt-channel", chan_idx,
363 &df_ch->alt_si);
364 if (ret < 0)
365 df_ch->alt_si = 0;
366
367 return 0;
368}
369
370static ssize_t dfsdm_adc_audio_get_spiclk(struct iio_dev *indio_dev,
371 uintptr_t priv,
372 const struct iio_chan_spec *chan,
373 char *buf)
374{
375 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
376
377 return snprintf(buf, PAGE_SIZE, "%d\n", adc->spi_freq);
378}
379
380static ssize_t dfsdm_adc_audio_set_spiclk(struct iio_dev *indio_dev,
381 uintptr_t priv,
382 const struct iio_chan_spec *chan,
383 const char *buf, size_t len)
384{
385 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
386 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
387 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
388 unsigned int sample_freq = adc->sample_freq;
389 unsigned int spi_freq;
390 int ret;
391
392 dev_err(&indio_dev->dev, "enter %s\n", __func__);
393
394 if (ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
395 return -EPERM;
396
397 ret = kstrtoint(buf, 0, &spi_freq);
398 if (ret)
399 return ret;
400
401 if (!spi_freq)
402 return -EINVAL;
403
404 if (sample_freq) {
405 if (spi_freq % sample_freq)
406 dev_warn(&indio_dev->dev,
407 "Sampling rate not accurate (%d)\n",
408 spi_freq / (spi_freq / sample_freq));
409
410 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / sample_freq));
411 if (ret < 0) {
412 dev_err(&indio_dev->dev,
413 "No filter parameters that match!\n");
414 return ret;
415 }
416 }
417 adc->spi_freq = spi_freq;
418
419 return len;
420}
421
422static int stm32_dfsdm_start_conv(struct stm32_dfsdm_adc *adc,
423 const struct iio_chan_spec *chan,
424 bool dma)
425{
426 struct regmap *regmap = adc->dfsdm->regmap;
427 int ret;
428 unsigned int dma_en = 0, cont_en = 0;
429
430 ret = stm32_dfsdm_start_channel(adc->dfsdm, chan->channel);
431 if (ret < 0)
432 return ret;
433
434 ret = stm32_dfsdm_filter_configure(adc->dfsdm, adc->fl_id,
435 chan->channel);
436 if (ret < 0)
437 goto stop_channels;
438
439 if (dma) {
440
441 dma_en = DFSDM_CR1_RDMAEN(1);
442
443 cont_en = DFSDM_CR1_RCONT(1);
444 }
445
446 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
447 DFSDM_CR1_RDMAEN_MASK, dma_en);
448 if (ret < 0)
449 goto stop_channels;
450
451
452 ret = regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
453 DFSDM_CR1_RCONT_MASK, cont_en);
454 if (ret < 0)
455 goto stop_channels;
456
457 ret = stm32_dfsdm_start_filter(adc->dfsdm, adc->fl_id);
458 if (ret < 0)
459 goto stop_channels;
460
461 return 0;
462
463stop_channels:
464 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
465 DFSDM_CR1_RDMAEN_MASK, 0);
466
467 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
468 DFSDM_CR1_RCONT_MASK, 0);
469 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
470
471 return ret;
472}
473
474static void stm32_dfsdm_stop_conv(struct stm32_dfsdm_adc *adc,
475 const struct iio_chan_spec *chan)
476{
477 struct regmap *regmap = adc->dfsdm->regmap;
478
479 stm32_dfsdm_stop_filter(adc->dfsdm, adc->fl_id);
480
481
482 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
483 DFSDM_CR1_RDMAEN_MASK, 0);
484
485 regmap_update_bits(regmap, DFSDM_CR1(adc->fl_id),
486 DFSDM_CR1_RCONT_MASK, 0);
487
488 stm32_dfsdm_stop_channel(adc->dfsdm, chan->channel);
489}
490
491static int stm32_dfsdm_set_watermark(struct iio_dev *indio_dev,
492 unsigned int val)
493{
494 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
495 unsigned int watermark = DFSDM_DMA_BUFFER_SIZE / 2;
496
497
498
499
500
501
502
503 watermark = min(watermark, val * (unsigned int)(sizeof(u32)));
504 adc->buf_sz = watermark * 2;
505
506 return 0;
507}
508
509static unsigned int stm32_dfsdm_adc_dma_residue(struct stm32_dfsdm_adc *adc)
510{
511 struct dma_tx_state state;
512 enum dma_status status;
513
514 status = dmaengine_tx_status(adc->dma_chan,
515 adc->dma_chan->cookie,
516 &state);
517 if (status == DMA_IN_PROGRESS) {
518
519 unsigned int i = adc->buf_sz - state.residue;
520 unsigned int size;
521
522
523 if (i >= adc->bufi)
524 size = i - adc->bufi;
525 else
526 size = adc->buf_sz + i - adc->bufi;
527
528 return size;
529 }
530
531 return 0;
532}
533
534static void stm32_dfsdm_audio_dma_buffer_done(void *data)
535{
536 struct iio_dev *indio_dev = data;
537 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
538 int available = stm32_dfsdm_adc_dma_residue(adc);
539 size_t old_pos;
540
541
542
543
544
545
546
547
548
549
550 dev_dbg(&indio_dev->dev, "%s: pos = %d, available = %d\n", __func__,
551 adc->bufi, available);
552 old_pos = adc->bufi;
553
554 while (available >= indio_dev->scan_bytes) {
555 u32 *buffer = (u32 *)&adc->rx_buf[adc->bufi];
556
557
558 *buffer = (*buffer & 0xFFFFFF00) << 8;
559 available -= indio_dev->scan_bytes;
560 adc->bufi += indio_dev->scan_bytes;
561 if (adc->bufi >= adc->buf_sz) {
562 if (adc->cb)
563 adc->cb(&adc->rx_buf[old_pos],
564 adc->buf_sz - old_pos, adc->cb_priv);
565 adc->bufi = 0;
566 old_pos = 0;
567 }
568 }
569 if (adc->cb)
570 adc->cb(&adc->rx_buf[old_pos], adc->bufi - old_pos,
571 adc->cb_priv);
572}
573
574static int stm32_dfsdm_adc_dma_start(struct iio_dev *indio_dev)
575{
576 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
577 struct dma_async_tx_descriptor *desc;
578 dma_cookie_t cookie;
579 int ret;
580
581 if (!adc->dma_chan)
582 return -EINVAL;
583
584 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__,
585 adc->buf_sz, adc->buf_sz / 2);
586
587
588 desc = dmaengine_prep_dma_cyclic(adc->dma_chan,
589 adc->dma_buf,
590 adc->buf_sz, adc->buf_sz / 2,
591 DMA_DEV_TO_MEM,
592 DMA_PREP_INTERRUPT);
593 if (!desc)
594 return -EBUSY;
595
596 desc->callback = stm32_dfsdm_audio_dma_buffer_done;
597 desc->callback_param = indio_dev;
598
599 cookie = dmaengine_submit(desc);
600 ret = dma_submit_error(cookie);
601 if (ret) {
602 dmaengine_terminate_all(adc->dma_chan);
603 return ret;
604 }
605
606
607 dma_async_issue_pending(adc->dma_chan);
608
609 return 0;
610}
611
612static int stm32_dfsdm_postenable(struct iio_dev *indio_dev)
613{
614 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
615 const struct iio_chan_spec *chan = &indio_dev->channels[0];
616 int ret;
617
618
619 adc->bufi = 0;
620
621 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
622 if (ret < 0)
623 return ret;
624
625 ret = stm32_dfsdm_start_conv(adc, chan, true);
626 if (ret) {
627 dev_err(&indio_dev->dev, "Can't start conversion\n");
628 goto stop_dfsdm;
629 }
630
631 if (adc->dma_chan) {
632 ret = stm32_dfsdm_adc_dma_start(indio_dev);
633 if (ret) {
634 dev_err(&indio_dev->dev, "Can't start DMA\n");
635 goto err_stop_conv;
636 }
637 }
638
639 return 0;
640
641err_stop_conv:
642 stm32_dfsdm_stop_conv(adc, chan);
643stop_dfsdm:
644 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
645
646 return ret;
647}
648
649static int stm32_dfsdm_predisable(struct iio_dev *indio_dev)
650{
651 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
652 const struct iio_chan_spec *chan = &indio_dev->channels[0];
653
654 if (adc->dma_chan)
655 dmaengine_terminate_all(adc->dma_chan);
656
657 stm32_dfsdm_stop_conv(adc, chan);
658
659 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
660
661 return 0;
662}
663
664static const struct iio_buffer_setup_ops stm32_dfsdm_buffer_setup_ops = {
665 .postenable = &stm32_dfsdm_postenable,
666 .predisable = &stm32_dfsdm_predisable,
667};
668
669
670
671
672
673
674
675
676
677
678
679
680int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
681 int (*cb)(const void *data, size_t size,
682 void *private),
683 void *private)
684{
685 struct stm32_dfsdm_adc *adc;
686
687 if (!iio_dev)
688 return -EINVAL;
689 adc = iio_priv(iio_dev);
690
691 adc->cb = cb;
692 adc->cb_priv = private;
693
694 return 0;
695}
696EXPORT_SYMBOL_GPL(stm32_dfsdm_get_buff_cb);
697
698
699
700
701
702
703int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev)
704{
705 struct stm32_dfsdm_adc *adc;
706
707 if (!iio_dev)
708 return -EINVAL;
709 adc = iio_priv(iio_dev);
710
711 adc->cb = NULL;
712 adc->cb_priv = NULL;
713
714 return 0;
715}
716EXPORT_SYMBOL_GPL(stm32_dfsdm_release_buff_cb);
717
718static int stm32_dfsdm_single_conv(struct iio_dev *indio_dev,
719 const struct iio_chan_spec *chan, int *res)
720{
721 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
722 long timeout;
723 int ret;
724
725 reinit_completion(&adc->completion);
726
727 adc->buffer = res;
728
729 ret = stm32_dfsdm_start_dfsdm(adc->dfsdm);
730 if (ret < 0)
731 return ret;
732
733 ret = regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
734 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(1));
735 if (ret < 0)
736 goto stop_dfsdm;
737
738 ret = stm32_dfsdm_start_conv(adc, chan, false);
739 if (ret < 0) {
740 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
741 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
742 goto stop_dfsdm;
743 }
744
745 timeout = wait_for_completion_interruptible_timeout(&adc->completion,
746 DFSDM_TIMEOUT);
747
748
749 regmap_update_bits(adc->dfsdm->regmap, DFSDM_CR2(adc->fl_id),
750 DFSDM_CR2_REOCIE_MASK, DFSDM_CR2_REOCIE(0));
751
752 if (timeout == 0)
753 ret = -ETIMEDOUT;
754 else if (timeout < 0)
755 ret = timeout;
756 else
757 ret = IIO_VAL_INT;
758
759 stm32_dfsdm_stop_conv(adc, chan);
760
761stop_dfsdm:
762 stm32_dfsdm_stop_dfsdm(adc->dfsdm);
763
764 return ret;
765}
766
767static int stm32_dfsdm_write_raw(struct iio_dev *indio_dev,
768 struct iio_chan_spec const *chan,
769 int val, int val2, long mask)
770{
771 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
772 struct stm32_dfsdm_filter *fl = &adc->dfsdm->fl_list[adc->fl_id];
773 struct stm32_dfsdm_channel *ch = &adc->dfsdm->ch_list[chan->channel];
774 unsigned int spi_freq;
775 int ret = -EINVAL;
776
777 switch (mask) {
778 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
779 ret = stm32_dfsdm_set_osrs(fl, 0, val);
780 if (!ret)
781 adc->oversamp = val;
782
783 return ret;
784
785 case IIO_CHAN_INFO_SAMP_FREQ:
786 if (!val)
787 return -EINVAL;
788
789 switch (ch->src) {
790 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL:
791 spi_freq = adc->dfsdm->spi_master_freq;
792 break;
793 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING:
794 case DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING:
795 spi_freq = adc->dfsdm->spi_master_freq / 2;
796 break;
797 default:
798 spi_freq = adc->spi_freq;
799 }
800
801 if (spi_freq % val)
802 dev_warn(&indio_dev->dev,
803 "Sampling rate not accurate (%d)\n",
804 spi_freq / (spi_freq / val));
805
806 ret = stm32_dfsdm_set_osrs(fl, 0, (spi_freq / val));
807 if (ret < 0) {
808 dev_err(&indio_dev->dev,
809 "Not able to find parameter that match!\n");
810 return ret;
811 }
812 adc->sample_freq = val;
813
814 return 0;
815 }
816
817 return -EINVAL;
818}
819
820static int stm32_dfsdm_read_raw(struct iio_dev *indio_dev,
821 struct iio_chan_spec const *chan, int *val,
822 int *val2, long mask)
823{
824 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
825 int ret;
826
827 switch (mask) {
828 case IIO_CHAN_INFO_RAW:
829 ret = iio_hw_consumer_enable(adc->hwc);
830 if (ret < 0) {
831 dev_err(&indio_dev->dev,
832 "%s: IIO enable failed (channel %d)\n",
833 __func__, chan->channel);
834 return ret;
835 }
836 ret = stm32_dfsdm_single_conv(indio_dev, chan, val);
837 iio_hw_consumer_disable(adc->hwc);
838 if (ret < 0) {
839 dev_err(&indio_dev->dev,
840 "%s: Conversion failed (channel %d)\n",
841 __func__, chan->channel);
842 return ret;
843 }
844 return IIO_VAL_INT;
845
846 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
847 *val = adc->oversamp;
848
849 return IIO_VAL_INT;
850
851 case IIO_CHAN_INFO_SAMP_FREQ:
852 *val = adc->sample_freq;
853
854 return IIO_VAL_INT;
855 }
856
857 return -EINVAL;
858}
859
860static const struct iio_info stm32_dfsdm_info_audio = {
861 .hwfifo_set_watermark = stm32_dfsdm_set_watermark,
862 .read_raw = stm32_dfsdm_read_raw,
863 .write_raw = stm32_dfsdm_write_raw,
864};
865
866static const struct iio_info stm32_dfsdm_info_adc = {
867 .read_raw = stm32_dfsdm_read_raw,
868 .write_raw = stm32_dfsdm_write_raw,
869};
870
871static irqreturn_t stm32_dfsdm_irq(int irq, void *arg)
872{
873 struct stm32_dfsdm_adc *adc = arg;
874 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
875 struct regmap *regmap = adc->dfsdm->regmap;
876 unsigned int status, int_en;
877
878 regmap_read(regmap, DFSDM_ISR(adc->fl_id), &status);
879 regmap_read(regmap, DFSDM_CR2(adc->fl_id), &int_en);
880
881 if (status & DFSDM_ISR_REOCF_MASK) {
882
883 regmap_read(regmap, DFSDM_RDATAR(adc->fl_id), adc->buffer);
884 complete(&adc->completion);
885 }
886
887 if (status & DFSDM_ISR_ROVRF_MASK) {
888 if (int_en & DFSDM_CR2_ROVRIE_MASK)
889 dev_warn(&indio_dev->dev, "Overrun detected\n");
890 regmap_update_bits(regmap, DFSDM_ICR(adc->fl_id),
891 DFSDM_ICR_CLRROVRF_MASK,
892 DFSDM_ICR_CLRROVRF_MASK);
893 }
894
895 return IRQ_HANDLED;
896}
897
898
899
900
901
902static const struct iio_chan_spec_ext_info dfsdm_adc_audio_ext_info[] = {
903
904 {
905 .name = "spi_clk_freq",
906 .shared = IIO_SHARED_BY_TYPE,
907 .read = dfsdm_adc_audio_get_spiclk,
908 .write = dfsdm_adc_audio_set_spiclk,
909 },
910 {},
911};
912
913static void stm32_dfsdm_dma_release(struct iio_dev *indio_dev)
914{
915 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
916
917 if (adc->dma_chan) {
918 dma_free_coherent(adc->dma_chan->device->dev,
919 DFSDM_DMA_BUFFER_SIZE,
920 adc->rx_buf, adc->dma_buf);
921 dma_release_channel(adc->dma_chan);
922 }
923}
924
925static int stm32_dfsdm_dma_request(struct iio_dev *indio_dev)
926{
927 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
928 struct dma_slave_config config = {
929 .src_addr = (dma_addr_t)adc->dfsdm->phys_base +
930 DFSDM_RDATAR(adc->fl_id),
931 .src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES,
932 };
933 int ret;
934
935 adc->dma_chan = dma_request_slave_channel(&indio_dev->dev, "rx");
936 if (!adc->dma_chan)
937 return -EINVAL;
938
939 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev,
940 DFSDM_DMA_BUFFER_SIZE,
941 &adc->dma_buf, GFP_KERNEL);
942 if (!adc->rx_buf) {
943 ret = -ENOMEM;
944 goto err_release;
945 }
946
947 ret = dmaengine_slave_config(adc->dma_chan, &config);
948 if (ret)
949 goto err_free;
950
951 return 0;
952
953err_free:
954 dma_free_coherent(adc->dma_chan->device->dev, DFSDM_DMA_BUFFER_SIZE,
955 adc->rx_buf, adc->dma_buf);
956err_release:
957 dma_release_channel(adc->dma_chan);
958
959 return ret;
960}
961
962static int stm32_dfsdm_adc_chan_init_one(struct iio_dev *indio_dev,
963 struct iio_chan_spec *ch)
964{
965 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
966 int ret;
967
968 ret = stm32_dfsdm_channel_parse_of(adc->dfsdm, indio_dev, ch);
969 if (ret < 0)
970 return ret;
971
972 ch->type = IIO_VOLTAGE;
973 ch->indexed = 1;
974
975
976
977
978
979 ch->info_mask_separate = BIT(IIO_CHAN_INFO_RAW);
980 ch->info_mask_shared_by_all = BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO);
981
982 if (adc->dev_data->type == DFSDM_AUDIO) {
983 ch->scan_type.sign = 's';
984 ch->ext_info = dfsdm_adc_audio_ext_info;
985 } else {
986 ch->scan_type.sign = 'u';
987 }
988 ch->scan_type.realbits = 24;
989 ch->scan_type.storagebits = 32;
990
991 return stm32_dfsdm_chan_configure(adc->dfsdm,
992 &adc->dfsdm->ch_list[ch->channel]);
993}
994
995static int stm32_dfsdm_audio_init(struct iio_dev *indio_dev)
996{
997 struct iio_chan_spec *ch;
998 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
999 struct stm32_dfsdm_channel *d_ch;
1000 int ret;
1001
1002 indio_dev->modes |= INDIO_BUFFER_SOFTWARE;
1003 indio_dev->setup_ops = &stm32_dfsdm_buffer_setup_ops;
1004
1005 ch = devm_kzalloc(&indio_dev->dev, sizeof(*ch), GFP_KERNEL);
1006 if (!ch)
1007 return -ENOMEM;
1008
1009 ch->scan_index = 0;
1010
1011 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, ch);
1012 if (ret < 0) {
1013 dev_err(&indio_dev->dev, "Channels init failed\n");
1014 return ret;
1015 }
1016 ch->info_mask_separate = BIT(IIO_CHAN_INFO_SAMP_FREQ);
1017
1018 d_ch = &adc->dfsdm->ch_list[ch->channel];
1019 if (d_ch->src != DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL)
1020 adc->spi_freq = adc->dfsdm->spi_master_freq;
1021
1022 indio_dev->num_channels = 1;
1023 indio_dev->channels = ch;
1024
1025 return stm32_dfsdm_dma_request(indio_dev);
1026}
1027
1028static int stm32_dfsdm_adc_init(struct iio_dev *indio_dev)
1029{
1030 struct iio_chan_spec *ch;
1031 struct stm32_dfsdm_adc *adc = iio_priv(indio_dev);
1032 int num_ch;
1033 int ret, chan_idx;
1034
1035 adc->oversamp = DFSDM_DEFAULT_OVERSAMPLING;
1036 ret = stm32_dfsdm_set_osrs(&adc->dfsdm->fl_list[adc->fl_id], 0,
1037 adc->oversamp);
1038 if (ret < 0)
1039 return ret;
1040
1041 num_ch = of_property_count_u32_elems(indio_dev->dev.of_node,
1042 "st,adc-channels");
1043 if (num_ch < 0 || num_ch > adc->dfsdm->num_chs) {
1044 dev_err(&indio_dev->dev, "Bad st,adc-channels\n");
1045 return num_ch < 0 ? num_ch : -EINVAL;
1046 }
1047
1048
1049 adc->hwc = devm_iio_hw_consumer_alloc(&indio_dev->dev);
1050 if (IS_ERR(adc->hwc))
1051 return -EPROBE_DEFER;
1052
1053 ch = devm_kcalloc(&indio_dev->dev, num_ch, sizeof(*ch),
1054 GFP_KERNEL);
1055 if (!ch)
1056 return -ENOMEM;
1057
1058 for (chan_idx = 0; chan_idx < num_ch; chan_idx++) {
1059 ch[chan_idx].scan_index = chan_idx;
1060 ret = stm32_dfsdm_adc_chan_init_one(indio_dev, &ch[chan_idx]);
1061 if (ret < 0) {
1062 dev_err(&indio_dev->dev, "Channels init failed\n");
1063 return ret;
1064 }
1065 }
1066
1067 indio_dev->num_channels = num_ch;
1068 indio_dev->channels = ch;
1069
1070 init_completion(&adc->completion);
1071
1072 return 0;
1073}
1074
1075static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_adc_data = {
1076 .type = DFSDM_IIO,
1077 .init = stm32_dfsdm_adc_init,
1078};
1079
1080static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_audio_data = {
1081 .type = DFSDM_AUDIO,
1082 .init = stm32_dfsdm_audio_init,
1083};
1084
1085static const struct of_device_id stm32_dfsdm_adc_match[] = {
1086 {
1087 .compatible = "st,stm32-dfsdm-adc",
1088 .data = &stm32h7_dfsdm_adc_data,
1089 },
1090 {
1091 .compatible = "st,stm32-dfsdm-dmic",
1092 .data = &stm32h7_dfsdm_audio_data,
1093 },
1094 {}
1095};
1096
1097static int stm32_dfsdm_adc_probe(struct platform_device *pdev)
1098{
1099 struct device *dev = &pdev->dev;
1100 struct stm32_dfsdm_adc *adc;
1101 struct device_node *np = dev->of_node;
1102 const struct stm32_dfsdm_dev_data *dev_data;
1103 struct iio_dev *iio;
1104 char *name;
1105 int ret, irq, val;
1106
1107
1108 dev_data = of_device_get_match_data(dev);
1109 iio = devm_iio_device_alloc(dev, sizeof(*adc));
1110 if (!iio) {
1111 dev_err(dev, "%s: Failed to allocate IIO\n", __func__);
1112 return -ENOMEM;
1113 }
1114
1115 adc = iio_priv(iio);
1116 adc->dfsdm = dev_get_drvdata(dev->parent);
1117
1118 iio->dev.parent = dev;
1119 iio->dev.of_node = np;
1120 iio->modes = INDIO_DIRECT_MODE | INDIO_BUFFER_SOFTWARE;
1121
1122 platform_set_drvdata(pdev, adc);
1123
1124 ret = of_property_read_u32(dev->of_node, "reg", &adc->fl_id);
1125 if (ret != 0) {
1126 dev_err(dev, "Missing reg property\n");
1127 return -EINVAL;
1128 }
1129
1130 name = devm_kzalloc(dev, sizeof("dfsdm-adc0"), GFP_KERNEL);
1131 if (!name)
1132 return -ENOMEM;
1133 if (dev_data->type == DFSDM_AUDIO) {
1134 iio->info = &stm32_dfsdm_info_audio;
1135 snprintf(name, sizeof("dfsdm-pdm0"), "dfsdm-pdm%d", adc->fl_id);
1136 } else {
1137 iio->info = &stm32_dfsdm_info_adc;
1138 snprintf(name, sizeof("dfsdm-adc0"), "dfsdm-adc%d", adc->fl_id);
1139 }
1140 iio->name = name;
1141
1142
1143
1144
1145
1146 irq = platform_get_irq(pdev, 0);
1147 ret = devm_request_irq(dev, irq, stm32_dfsdm_irq,
1148 0, pdev->name, adc);
1149 if (ret < 0) {
1150 dev_err(dev, "Failed to request IRQ\n");
1151 return ret;
1152 }
1153
1154 ret = of_property_read_u32(dev->of_node, "st,filter-order", &val);
1155 if (ret < 0) {
1156 dev_err(dev, "Failed to set filter order\n");
1157 return ret;
1158 }
1159
1160 adc->dfsdm->fl_list[adc->fl_id].ford = val;
1161
1162 ret = of_property_read_u32(dev->of_node, "st,filter0-sync", &val);
1163 if (!ret)
1164 adc->dfsdm->fl_list[adc->fl_id].sync_mode = val;
1165
1166 adc->dev_data = dev_data;
1167 ret = dev_data->init(iio);
1168 if (ret < 0)
1169 return ret;
1170
1171 ret = iio_device_register(iio);
1172 if (ret < 0)
1173 goto err_cleanup;
1174
1175 dev_err(dev, "of_platform_populate\n");
1176 if (dev_data->type == DFSDM_AUDIO) {
1177 ret = of_platform_populate(np, NULL, NULL, dev);
1178 if (ret < 0) {
1179 dev_err(dev, "Failed to find an audio DAI\n");
1180 goto err_unregister;
1181 }
1182 }
1183
1184 return 0;
1185
1186err_unregister:
1187 iio_device_unregister(iio);
1188err_cleanup:
1189 stm32_dfsdm_dma_release(iio);
1190
1191 return ret;
1192}
1193
1194static int stm32_dfsdm_adc_remove(struct platform_device *pdev)
1195{
1196 struct stm32_dfsdm_adc *adc = platform_get_drvdata(pdev);
1197 struct iio_dev *indio_dev = iio_priv_to_dev(adc);
1198
1199 if (adc->dev_data->type == DFSDM_AUDIO)
1200 of_platform_depopulate(&pdev->dev);
1201 iio_device_unregister(indio_dev);
1202 stm32_dfsdm_dma_release(indio_dev);
1203
1204 return 0;
1205}
1206
1207static struct platform_driver stm32_dfsdm_adc_driver = {
1208 .driver = {
1209 .name = "stm32-dfsdm-adc",
1210 .of_match_table = stm32_dfsdm_adc_match,
1211 },
1212 .probe = stm32_dfsdm_adc_probe,
1213 .remove = stm32_dfsdm_adc_remove,
1214};
1215module_platform_driver(stm32_dfsdm_adc_driver);
1216
1217MODULE_DESCRIPTION("STM32 sigma delta ADC");
1218MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
1219MODULE_LICENSE("GPL v2");
1220
