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17#include <linux/module.h>
18#include <linux/of_device.h>
19#include <linux/init.h>
20#include <linux/irq.h>
21#include <linux/i2c.h>
22#include <linux/regmap.h>
23#include <linux/pm_runtime.h>
24#include <linux/mutex.h>
25#include <linux/delay.h>
26
27#include <linux/platform_data/ads1015.h>
28
29#include <linux/iio/iio.h>
30#include <linux/iio/types.h>
31#include <linux/iio/sysfs.h>
32#include <linux/iio/events.h>
33#include <linux/iio/buffer.h>
34#include <linux/iio/triggered_buffer.h>
35#include <linux/iio/trigger_consumer.h>
36
37#define ADS1015_DRV_NAME "ads1015"
38
39#define ADS1015_CONV_REG 0x00
40#define ADS1015_CFG_REG 0x01
41#define ADS1015_LO_THRESH_REG 0x02
42#define ADS1015_HI_THRESH_REG 0x03
43
44#define ADS1015_CFG_COMP_QUE_SHIFT 0
45#define ADS1015_CFG_COMP_LAT_SHIFT 2
46#define ADS1015_CFG_COMP_POL_SHIFT 3
47#define ADS1015_CFG_COMP_MODE_SHIFT 4
48#define ADS1015_CFG_DR_SHIFT 5
49#define ADS1015_CFG_MOD_SHIFT 8
50#define ADS1015_CFG_PGA_SHIFT 9
51#define ADS1015_CFG_MUX_SHIFT 12
52
53#define ADS1015_CFG_COMP_QUE_MASK GENMASK(1, 0)
54#define ADS1015_CFG_COMP_LAT_MASK BIT(2)
55#define ADS1015_CFG_COMP_POL_MASK BIT(3)
56#define ADS1015_CFG_COMP_MODE_MASK BIT(4)
57#define ADS1015_CFG_DR_MASK GENMASK(7, 5)
58#define ADS1015_CFG_MOD_MASK BIT(8)
59#define ADS1015_CFG_PGA_MASK GENMASK(11, 9)
60#define ADS1015_CFG_MUX_MASK GENMASK(14, 12)
61
62
63#define ADS1015_CFG_COMP_DISABLE 3
64
65
66#define ADS1015_CFG_COMP_POL_LOW 0
67#define ADS1015_CFG_COMP_POL_HIGH 1
68
69
70#define ADS1015_CFG_COMP_MODE_TRAD 0
71#define ADS1015_CFG_COMP_MODE_WINDOW 1
72
73
74#define ADS1015_CONTINUOUS 0
75#define ADS1015_SINGLESHOT 1
76
77#define ADS1015_SLEEP_DELAY_MS 2000
78#define ADS1015_DEFAULT_PGA 2
79#define ADS1015_DEFAULT_DATA_RATE 4
80#define ADS1015_DEFAULT_CHAN 0
81
82enum chip_ids {
83 ADS1015,
84 ADS1115,
85};
86
87enum ads1015_channels {
88 ADS1015_AIN0_AIN1 = 0,
89 ADS1015_AIN0_AIN3,
90 ADS1015_AIN1_AIN3,
91 ADS1015_AIN2_AIN3,
92 ADS1015_AIN0,
93 ADS1015_AIN1,
94 ADS1015_AIN2,
95 ADS1015_AIN3,
96 ADS1015_TIMESTAMP,
97};
98
99static const unsigned int ads1015_data_rate[] = {
100 128, 250, 490, 920, 1600, 2400, 3300, 3300
101};
102
103static const unsigned int ads1115_data_rate[] = {
104 8, 16, 32, 64, 128, 250, 475, 860
105};
106
107
108
109
110
111static int ads1015_fullscale_range[] = {
112 6144, 4096, 2048, 1024, 512, 256, 256, 256
113};
114
115
116
117
118
119static const int ads1015_comp_queue[] = { 1, 2, 4 };
120
121static const struct iio_event_spec ads1015_events[] = {
122 {
123 .type = IIO_EV_TYPE_THRESH,
124 .dir = IIO_EV_DIR_RISING,
125 .mask_separate = BIT(IIO_EV_INFO_VALUE) |
126 BIT(IIO_EV_INFO_ENABLE),
127 }, {
128 .type = IIO_EV_TYPE_THRESH,
129 .dir = IIO_EV_DIR_FALLING,
130 .mask_separate = BIT(IIO_EV_INFO_VALUE),
131 }, {
132 .type = IIO_EV_TYPE_THRESH,
133 .dir = IIO_EV_DIR_EITHER,
134 .mask_separate = BIT(IIO_EV_INFO_ENABLE) |
135 BIT(IIO_EV_INFO_PERIOD),
136 },
137};
138
139#define ADS1015_V_CHAN(_chan, _addr) { \
140 .type = IIO_VOLTAGE, \
141 .indexed = 1, \
142 .address = _addr, \
143 .channel = _chan, \
144 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
145 BIT(IIO_CHAN_INFO_SCALE) | \
146 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
147 .scan_index = _addr, \
148 .scan_type = { \
149 .sign = 's', \
150 .realbits = 12, \
151 .storagebits = 16, \
152 .shift = 4, \
153 .endianness = IIO_CPU, \
154 }, \
155 .event_spec = ads1015_events, \
156 .num_event_specs = ARRAY_SIZE(ads1015_events), \
157 .datasheet_name = "AIN"#_chan, \
158}
159
160#define ADS1015_V_DIFF_CHAN(_chan, _chan2, _addr) { \
161 .type = IIO_VOLTAGE, \
162 .differential = 1, \
163 .indexed = 1, \
164 .address = _addr, \
165 .channel = _chan, \
166 .channel2 = _chan2, \
167 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
168 BIT(IIO_CHAN_INFO_SCALE) | \
169 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
170 .scan_index = _addr, \
171 .scan_type = { \
172 .sign = 's', \
173 .realbits = 12, \
174 .storagebits = 16, \
175 .shift = 4, \
176 .endianness = IIO_CPU, \
177 }, \
178 .event_spec = ads1015_events, \
179 .num_event_specs = ARRAY_SIZE(ads1015_events), \
180 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
181}
182
183#define ADS1115_V_CHAN(_chan, _addr) { \
184 .type = IIO_VOLTAGE, \
185 .indexed = 1, \
186 .address = _addr, \
187 .channel = _chan, \
188 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
189 BIT(IIO_CHAN_INFO_SCALE) | \
190 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
191 .scan_index = _addr, \
192 .scan_type = { \
193 .sign = 's', \
194 .realbits = 16, \
195 .storagebits = 16, \
196 .endianness = IIO_CPU, \
197 }, \
198 .event_spec = ads1015_events, \
199 .num_event_specs = ARRAY_SIZE(ads1015_events), \
200 .datasheet_name = "AIN"#_chan, \
201}
202
203#define ADS1115_V_DIFF_CHAN(_chan, _chan2, _addr) { \
204 .type = IIO_VOLTAGE, \
205 .differential = 1, \
206 .indexed = 1, \
207 .address = _addr, \
208 .channel = _chan, \
209 .channel2 = _chan2, \
210 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
211 BIT(IIO_CHAN_INFO_SCALE) | \
212 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
213 .scan_index = _addr, \
214 .scan_type = { \
215 .sign = 's', \
216 .realbits = 16, \
217 .storagebits = 16, \
218 .endianness = IIO_CPU, \
219 }, \
220 .event_spec = ads1015_events, \
221 .num_event_specs = ARRAY_SIZE(ads1015_events), \
222 .datasheet_name = "AIN"#_chan"-AIN"#_chan2, \
223}
224
225struct ads1015_thresh_data {
226 unsigned int comp_queue;
227 int high_thresh;
228 int low_thresh;
229};
230
231struct ads1015_data {
232 struct regmap *regmap;
233
234
235
236
237 struct mutex lock;
238 struct ads1015_channel_data channel_data[ADS1015_CHANNELS];
239
240 unsigned int event_channel;
241 unsigned int comp_mode;
242 struct ads1015_thresh_data thresh_data[ADS1015_CHANNELS];
243
244 unsigned int *data_rate;
245
246
247
248
249
250 bool conv_invalid;
251};
252
253static bool ads1015_event_channel_enabled(struct ads1015_data *data)
254{
255 return (data->event_channel != ADS1015_CHANNELS);
256}
257
258static void ads1015_event_channel_enable(struct ads1015_data *data, int chan,
259 int comp_mode)
260{
261 WARN_ON(ads1015_event_channel_enabled(data));
262
263 data->event_channel = chan;
264 data->comp_mode = comp_mode;
265}
266
267static void ads1015_event_channel_disable(struct ads1015_data *data, int chan)
268{
269 data->event_channel = ADS1015_CHANNELS;
270}
271
272static bool ads1015_is_writeable_reg(struct device *dev, unsigned int reg)
273{
274 switch (reg) {
275 case ADS1015_CFG_REG:
276 case ADS1015_LO_THRESH_REG:
277 case ADS1015_HI_THRESH_REG:
278 return true;
279 default:
280 return false;
281 }
282}
283
284static const struct regmap_config ads1015_regmap_config = {
285 .reg_bits = 8,
286 .val_bits = 16,
287 .max_register = ADS1015_HI_THRESH_REG,
288 .writeable_reg = ads1015_is_writeable_reg,
289};
290
291static const struct iio_chan_spec ads1015_channels[] = {
292 ADS1015_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
293 ADS1015_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
294 ADS1015_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
295 ADS1015_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
296 ADS1015_V_CHAN(0, ADS1015_AIN0),
297 ADS1015_V_CHAN(1, ADS1015_AIN1),
298 ADS1015_V_CHAN(2, ADS1015_AIN2),
299 ADS1015_V_CHAN(3, ADS1015_AIN3),
300 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
301};
302
303static const struct iio_chan_spec ads1115_channels[] = {
304 ADS1115_V_DIFF_CHAN(0, 1, ADS1015_AIN0_AIN1),
305 ADS1115_V_DIFF_CHAN(0, 3, ADS1015_AIN0_AIN3),
306 ADS1115_V_DIFF_CHAN(1, 3, ADS1015_AIN1_AIN3),
307 ADS1115_V_DIFF_CHAN(2, 3, ADS1015_AIN2_AIN3),
308 ADS1115_V_CHAN(0, ADS1015_AIN0),
309 ADS1115_V_CHAN(1, ADS1015_AIN1),
310 ADS1115_V_CHAN(2, ADS1015_AIN2),
311 ADS1115_V_CHAN(3, ADS1015_AIN3),
312 IIO_CHAN_SOFT_TIMESTAMP(ADS1015_TIMESTAMP),
313};
314
315static int ads1015_set_power_state(struct ads1015_data *data, bool on)
316{
317 int ret;
318 struct device *dev = regmap_get_device(data->regmap);
319
320 if (on) {
321 ret = pm_runtime_get_sync(dev);
322 if (ret < 0)
323 pm_runtime_put_noidle(dev);
324 } else {
325 pm_runtime_mark_last_busy(dev);
326 ret = pm_runtime_put_autosuspend(dev);
327 }
328
329 return ret < 0 ? ret : 0;
330}
331
332static
333int ads1015_get_adc_result(struct ads1015_data *data, int chan, int *val)
334{
335 int ret, pga, dr, dr_old, conv_time;
336 unsigned int old, mask, cfg;
337
338 if (chan < 0 || chan >= ADS1015_CHANNELS)
339 return -EINVAL;
340
341 ret = regmap_read(data->regmap, ADS1015_CFG_REG, &old);
342 if (ret)
343 return ret;
344
345 pga = data->channel_data[chan].pga;
346 dr = data->channel_data[chan].data_rate;
347 mask = ADS1015_CFG_MUX_MASK | ADS1015_CFG_PGA_MASK |
348 ADS1015_CFG_DR_MASK;
349 cfg = chan << ADS1015_CFG_MUX_SHIFT | pga << ADS1015_CFG_PGA_SHIFT |
350 dr << ADS1015_CFG_DR_SHIFT;
351
352 if (ads1015_event_channel_enabled(data)) {
353 mask |= ADS1015_CFG_COMP_QUE_MASK | ADS1015_CFG_COMP_MODE_MASK;
354 cfg |= data->thresh_data[chan].comp_queue <<
355 ADS1015_CFG_COMP_QUE_SHIFT |
356 data->comp_mode <<
357 ADS1015_CFG_COMP_MODE_SHIFT;
358 }
359
360 cfg = (old & ~mask) | (cfg & mask);
361 if (old != cfg) {
362 ret = regmap_write(data->regmap, ADS1015_CFG_REG, cfg);
363 if (ret)
364 return ret;
365 data->conv_invalid = true;
366 }
367 if (data->conv_invalid) {
368 dr_old = (old & ADS1015_CFG_DR_MASK) >> ADS1015_CFG_DR_SHIFT;
369 conv_time = DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr_old]);
370 conv_time += DIV_ROUND_UP(USEC_PER_SEC, data->data_rate[dr]);
371 conv_time += conv_time / 10;
372 usleep_range(conv_time, conv_time + 1);
373 data->conv_invalid = false;
374 }
375
376 return regmap_read(data->regmap, ADS1015_CONV_REG, val);
377}
378
379static irqreturn_t ads1015_trigger_handler(int irq, void *p)
380{
381 struct iio_poll_func *pf = p;
382 struct iio_dev *indio_dev = pf->indio_dev;
383 struct ads1015_data *data = iio_priv(indio_dev);
384 s16 buf[8];
385 int chan, ret, res;
386
387 memset(buf, 0, sizeof(buf));
388
389 mutex_lock(&data->lock);
390 chan = find_first_bit(indio_dev->active_scan_mask,
391 indio_dev->masklength);
392 ret = ads1015_get_adc_result(data, chan, &res);
393 if (ret < 0) {
394 mutex_unlock(&data->lock);
395 goto err;
396 }
397
398 buf[0] = res;
399 mutex_unlock(&data->lock);
400
401 iio_push_to_buffers_with_timestamp(indio_dev, buf,
402 iio_get_time_ns(indio_dev));
403
404err:
405 iio_trigger_notify_done(indio_dev->trig);
406
407 return IRQ_HANDLED;
408}
409
410static int ads1015_set_scale(struct ads1015_data *data,
411 struct iio_chan_spec const *chan,
412 int scale, int uscale)
413{
414 int i;
415 int fullscale = div_s64((scale * 1000000LL + uscale) <<
416 (chan->scan_type.realbits - 1), 1000000);
417
418 for (i = 0; i < ARRAY_SIZE(ads1015_fullscale_range); i++) {
419 if (ads1015_fullscale_range[i] == fullscale) {
420 data->channel_data[chan->address].pga = i;
421 return 0;
422 }
423 }
424
425 return -EINVAL;
426}
427
428static int ads1015_set_data_rate(struct ads1015_data *data, int chan, int rate)
429{
430 int i;
431
432 for (i = 0; i < ARRAY_SIZE(ads1015_data_rate); i++) {
433 if (data->data_rate[i] == rate) {
434 data->channel_data[chan].data_rate = i;
435 return 0;
436 }
437 }
438
439 return -EINVAL;
440}
441
442static int ads1015_read_raw(struct iio_dev *indio_dev,
443 struct iio_chan_spec const *chan, int *val,
444 int *val2, long mask)
445{
446 int ret, idx;
447 struct ads1015_data *data = iio_priv(indio_dev);
448
449 mutex_lock(&data->lock);
450 switch (mask) {
451 case IIO_CHAN_INFO_RAW: {
452 int shift = chan->scan_type.shift;
453
454 ret = iio_device_claim_direct_mode(indio_dev);
455 if (ret)
456 break;
457
458 if (ads1015_event_channel_enabled(data) &&
459 data->event_channel != chan->address) {
460 ret = -EBUSY;
461 goto release_direct;
462 }
463
464 ret = ads1015_set_power_state(data, true);
465 if (ret < 0)
466 goto release_direct;
467
468 ret = ads1015_get_adc_result(data, chan->address, val);
469 if (ret < 0) {
470 ads1015_set_power_state(data, false);
471 goto release_direct;
472 }
473
474 *val = sign_extend32(*val >> shift, 15 - shift);
475
476 ret = ads1015_set_power_state(data, false);
477 if (ret < 0)
478 goto release_direct;
479
480 ret = IIO_VAL_INT;
481release_direct:
482 iio_device_release_direct_mode(indio_dev);
483 break;
484 }
485 case IIO_CHAN_INFO_SCALE:
486 idx = data->channel_data[chan->address].pga;
487 *val = ads1015_fullscale_range[idx];
488 *val2 = chan->scan_type.realbits - 1;
489 ret = IIO_VAL_FRACTIONAL_LOG2;
490 break;
491 case IIO_CHAN_INFO_SAMP_FREQ:
492 idx = data->channel_data[chan->address].data_rate;
493 *val = data->data_rate[idx];
494 ret = IIO_VAL_INT;
495 break;
496 default:
497 ret = -EINVAL;
498 break;
499 }
500 mutex_unlock(&data->lock);
501
502 return ret;
503}
504
505static int ads1015_write_raw(struct iio_dev *indio_dev,
506 struct iio_chan_spec const *chan, int val,
507 int val2, long mask)
508{
509 struct ads1015_data *data = iio_priv(indio_dev);
510 int ret;
511
512 mutex_lock(&data->lock);
513 switch (mask) {
514 case IIO_CHAN_INFO_SCALE:
515 ret = ads1015_set_scale(data, chan, val, val2);
516 break;
517 case IIO_CHAN_INFO_SAMP_FREQ:
518 ret = ads1015_set_data_rate(data, chan->address, val);
519 break;
520 default:
521 ret = -EINVAL;
522 break;
523 }
524 mutex_unlock(&data->lock);
525
526 return ret;
527}
528
529static int ads1015_read_event(struct iio_dev *indio_dev,
530 const struct iio_chan_spec *chan, enum iio_event_type type,
531 enum iio_event_direction dir, enum iio_event_info info, int *val,
532 int *val2)
533{
534 struct ads1015_data *data = iio_priv(indio_dev);
535 int ret;
536 unsigned int comp_queue;
537 int period;
538 int dr;
539
540 mutex_lock(&data->lock);
541
542 switch (info) {
543 case IIO_EV_INFO_VALUE:
544 *val = (dir == IIO_EV_DIR_RISING) ?
545 data->thresh_data[chan->address].high_thresh :
546 data->thresh_data[chan->address].low_thresh;
547 ret = IIO_VAL_INT;
548 break;
549 case IIO_EV_INFO_PERIOD:
550 dr = data->channel_data[chan->address].data_rate;
551 comp_queue = data->thresh_data[chan->address].comp_queue;
552 period = ads1015_comp_queue[comp_queue] *
553 USEC_PER_SEC / data->data_rate[dr];
554
555 *val = period / USEC_PER_SEC;
556 *val2 = period % USEC_PER_SEC;
557 ret = IIO_VAL_INT_PLUS_MICRO;
558 break;
559 default:
560 ret = -EINVAL;
561 break;
562 }
563
564 mutex_unlock(&data->lock);
565
566 return ret;
567}
568
569static int ads1015_write_event(struct iio_dev *indio_dev,
570 const struct iio_chan_spec *chan, enum iio_event_type type,
571 enum iio_event_direction dir, enum iio_event_info info, int val,
572 int val2)
573{
574 struct ads1015_data *data = iio_priv(indio_dev);
575 int realbits = chan->scan_type.realbits;
576 int ret = 0;
577 long long period;
578 int i;
579 int dr;
580
581 mutex_lock(&data->lock);
582
583 switch (info) {
584 case IIO_EV_INFO_VALUE:
585 if (val >= 1 << (realbits - 1) || val < -1 << (realbits - 1)) {
586 ret = -EINVAL;
587 break;
588 }
589 if (dir == IIO_EV_DIR_RISING)
590 data->thresh_data[chan->address].high_thresh = val;
591 else
592 data->thresh_data[chan->address].low_thresh = val;
593 break;
594 case IIO_EV_INFO_PERIOD:
595 dr = data->channel_data[chan->address].data_rate;
596 period = val * USEC_PER_SEC + val2;
597
598 for (i = 0; i < ARRAY_SIZE(ads1015_comp_queue) - 1; i++) {
599 if (period <= ads1015_comp_queue[i] *
600 USEC_PER_SEC / data->data_rate[dr])
601 break;
602 }
603 data->thresh_data[chan->address].comp_queue = i;
604 break;
605 default:
606 ret = -EINVAL;
607 break;
608 }
609
610 mutex_unlock(&data->lock);
611
612 return ret;
613}
614
615static int ads1015_read_event_config(struct iio_dev *indio_dev,
616 const struct iio_chan_spec *chan, enum iio_event_type type,
617 enum iio_event_direction dir)
618{
619 struct ads1015_data *data = iio_priv(indio_dev);
620 int ret = 0;
621
622 mutex_lock(&data->lock);
623 if (data->event_channel == chan->address) {
624 switch (dir) {
625 case IIO_EV_DIR_RISING:
626 ret = 1;
627 break;
628 case IIO_EV_DIR_EITHER:
629 ret = (data->comp_mode == ADS1015_CFG_COMP_MODE_WINDOW);
630 break;
631 default:
632 ret = -EINVAL;
633 break;
634 }
635 }
636 mutex_unlock(&data->lock);
637
638 return ret;
639}
640
641static int ads1015_enable_event_config(struct ads1015_data *data,
642 const struct iio_chan_spec *chan, int comp_mode)
643{
644 int low_thresh = data->thresh_data[chan->address].low_thresh;
645 int high_thresh = data->thresh_data[chan->address].high_thresh;
646 int ret;
647 unsigned int val;
648
649 if (ads1015_event_channel_enabled(data)) {
650 if (data->event_channel != chan->address ||
651 (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
652 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW))
653 return -EBUSY;
654
655 return 0;
656 }
657
658 if (comp_mode == ADS1015_CFG_COMP_MODE_TRAD) {
659 low_thresh = max(-1 << (chan->scan_type.realbits - 1),
660 high_thresh - 1);
661 }
662 ret = regmap_write(data->regmap, ADS1015_LO_THRESH_REG,
663 low_thresh << chan->scan_type.shift);
664 if (ret)
665 return ret;
666
667 ret = regmap_write(data->regmap, ADS1015_HI_THRESH_REG,
668 high_thresh << chan->scan_type.shift);
669 if (ret)
670 return ret;
671
672 ret = ads1015_set_power_state(data, true);
673 if (ret < 0)
674 return ret;
675
676 ads1015_event_channel_enable(data, chan->address, comp_mode);
677
678 ret = ads1015_get_adc_result(data, chan->address, &val);
679 if (ret) {
680 ads1015_event_channel_disable(data, chan->address);
681 ads1015_set_power_state(data, false);
682 }
683
684 return ret;
685}
686
687static int ads1015_disable_event_config(struct ads1015_data *data,
688 const struct iio_chan_spec *chan, int comp_mode)
689{
690 int ret;
691
692 if (!ads1015_event_channel_enabled(data))
693 return 0;
694
695 if (data->event_channel != chan->address)
696 return 0;
697
698 if (data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD &&
699 comp_mode == ADS1015_CFG_COMP_MODE_WINDOW)
700 return 0;
701
702 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
703 ADS1015_CFG_COMP_QUE_MASK,
704 ADS1015_CFG_COMP_DISABLE <<
705 ADS1015_CFG_COMP_QUE_SHIFT);
706 if (ret)
707 return ret;
708
709 ads1015_event_channel_disable(data, chan->address);
710
711 return ads1015_set_power_state(data, false);
712}
713
714static int ads1015_write_event_config(struct iio_dev *indio_dev,
715 const struct iio_chan_spec *chan, enum iio_event_type type,
716 enum iio_event_direction dir, int state)
717{
718 struct ads1015_data *data = iio_priv(indio_dev);
719 int ret;
720 int comp_mode = (dir == IIO_EV_DIR_EITHER) ?
721 ADS1015_CFG_COMP_MODE_WINDOW : ADS1015_CFG_COMP_MODE_TRAD;
722
723 mutex_lock(&data->lock);
724
725
726 ret = iio_device_claim_direct_mode(indio_dev);
727 if (ret) {
728 mutex_unlock(&data->lock);
729 return ret;
730 }
731
732 if (state)
733 ret = ads1015_enable_event_config(data, chan, comp_mode);
734 else
735 ret = ads1015_disable_event_config(data, chan, comp_mode);
736
737 iio_device_release_direct_mode(indio_dev);
738 mutex_unlock(&data->lock);
739
740 return ret;
741}
742
743static irqreturn_t ads1015_event_handler(int irq, void *priv)
744{
745 struct iio_dev *indio_dev = priv;
746 struct ads1015_data *data = iio_priv(indio_dev);
747 int val;
748 int ret;
749
750
751 ret = regmap_read(data->regmap, ADS1015_CONV_REG, &val);
752 if (ret)
753 return IRQ_HANDLED;
754
755 if (ads1015_event_channel_enabled(data)) {
756 enum iio_event_direction dir;
757 u64 code;
758
759 dir = data->comp_mode == ADS1015_CFG_COMP_MODE_TRAD ?
760 IIO_EV_DIR_RISING : IIO_EV_DIR_EITHER;
761 code = IIO_UNMOD_EVENT_CODE(IIO_VOLTAGE, data->event_channel,
762 IIO_EV_TYPE_THRESH, dir);
763 iio_push_event(indio_dev, code, iio_get_time_ns(indio_dev));
764 }
765
766 return IRQ_HANDLED;
767}
768
769static int ads1015_buffer_preenable(struct iio_dev *indio_dev)
770{
771 struct ads1015_data *data = iio_priv(indio_dev);
772
773
774 if (ads1015_event_channel_enabled(data))
775 return -EBUSY;
776
777 return ads1015_set_power_state(iio_priv(indio_dev), true);
778}
779
780static int ads1015_buffer_postdisable(struct iio_dev *indio_dev)
781{
782 return ads1015_set_power_state(iio_priv(indio_dev), false);
783}
784
785static const struct iio_buffer_setup_ops ads1015_buffer_setup_ops = {
786 .preenable = ads1015_buffer_preenable,
787 .postenable = iio_triggered_buffer_postenable,
788 .predisable = iio_triggered_buffer_predisable,
789 .postdisable = ads1015_buffer_postdisable,
790 .validate_scan_mask = &iio_validate_scan_mask_onehot,
791};
792
793static IIO_CONST_ATTR_NAMED(ads1015_scale_available, scale_available,
794 "3 2 1 0.5 0.25 0.125");
795static IIO_CONST_ATTR_NAMED(ads1115_scale_available, scale_available,
796 "0.1875 0.125 0.0625 0.03125 0.015625 0.007813");
797
798static IIO_CONST_ATTR_NAMED(ads1015_sampling_frequency_available,
799 sampling_frequency_available, "128 250 490 920 1600 2400 3300");
800static IIO_CONST_ATTR_NAMED(ads1115_sampling_frequency_available,
801 sampling_frequency_available, "8 16 32 64 128 250 475 860");
802
803static struct attribute *ads1015_attributes[] = {
804 &iio_const_attr_ads1015_scale_available.dev_attr.attr,
805 &iio_const_attr_ads1015_sampling_frequency_available.dev_attr.attr,
806 NULL,
807};
808
809static const struct attribute_group ads1015_attribute_group = {
810 .attrs = ads1015_attributes,
811};
812
813static struct attribute *ads1115_attributes[] = {
814 &iio_const_attr_ads1115_scale_available.dev_attr.attr,
815 &iio_const_attr_ads1115_sampling_frequency_available.dev_attr.attr,
816 NULL,
817};
818
819static const struct attribute_group ads1115_attribute_group = {
820 .attrs = ads1115_attributes,
821};
822
823static const struct iio_info ads1015_info = {
824 .read_raw = ads1015_read_raw,
825 .write_raw = ads1015_write_raw,
826 .read_event_value = ads1015_read_event,
827 .write_event_value = ads1015_write_event,
828 .read_event_config = ads1015_read_event_config,
829 .write_event_config = ads1015_write_event_config,
830 .attrs = &ads1015_attribute_group,
831};
832
833static const struct iio_info ads1115_info = {
834 .read_raw = ads1015_read_raw,
835 .write_raw = ads1015_write_raw,
836 .read_event_value = ads1015_read_event,
837 .write_event_value = ads1015_write_event,
838 .read_event_config = ads1015_read_event_config,
839 .write_event_config = ads1015_write_event_config,
840 .attrs = &ads1115_attribute_group,
841};
842
843#ifdef CONFIG_OF
844static int ads1015_get_channels_config_of(struct i2c_client *client)
845{
846 struct iio_dev *indio_dev = i2c_get_clientdata(client);
847 struct ads1015_data *data = iio_priv(indio_dev);
848 struct device_node *node;
849
850 if (!client->dev.of_node ||
851 !of_get_next_child(client->dev.of_node, NULL))
852 return -EINVAL;
853
854 for_each_child_of_node(client->dev.of_node, node) {
855 u32 pval;
856 unsigned int channel;
857 unsigned int pga = ADS1015_DEFAULT_PGA;
858 unsigned int data_rate = ADS1015_DEFAULT_DATA_RATE;
859
860 if (of_property_read_u32(node, "reg", &pval)) {
861 dev_err(&client->dev, "invalid reg on %pOF\n",
862 node);
863 continue;
864 }
865
866 channel = pval;
867 if (channel >= ADS1015_CHANNELS) {
868 dev_err(&client->dev,
869 "invalid channel index %d on %pOF\n",
870 channel, node);
871 continue;
872 }
873
874 if (!of_property_read_u32(node, "ti,gain", &pval)) {
875 pga = pval;
876 if (pga > 6) {
877 dev_err(&client->dev, "invalid gain on %pOF\n",
878 node);
879 of_node_put(node);
880 return -EINVAL;
881 }
882 }
883
884 if (!of_property_read_u32(node, "ti,datarate", &pval)) {
885 data_rate = pval;
886 if (data_rate > 7) {
887 dev_err(&client->dev,
888 "invalid data_rate on %pOF\n",
889 node);
890 of_node_put(node);
891 return -EINVAL;
892 }
893 }
894
895 data->channel_data[channel].pga = pga;
896 data->channel_data[channel].data_rate = data_rate;
897 }
898
899 return 0;
900}
901#endif
902
903static void ads1015_get_channels_config(struct i2c_client *client)
904{
905 unsigned int k;
906
907 struct iio_dev *indio_dev = i2c_get_clientdata(client);
908 struct ads1015_data *data = iio_priv(indio_dev);
909 struct ads1015_platform_data *pdata = dev_get_platdata(&client->dev);
910
911
912 if (pdata) {
913 memcpy(data->channel_data, pdata->channel_data,
914 sizeof(data->channel_data));
915 return;
916 }
917
918#ifdef CONFIG_OF
919 if (!ads1015_get_channels_config_of(client))
920 return;
921#endif
922
923 for (k = 0; k < ADS1015_CHANNELS; ++k) {
924 data->channel_data[k].pga = ADS1015_DEFAULT_PGA;
925 data->channel_data[k].data_rate = ADS1015_DEFAULT_DATA_RATE;
926 }
927}
928
929static int ads1015_set_conv_mode(struct ads1015_data *data, int mode)
930{
931 return regmap_update_bits(data->regmap, ADS1015_CFG_REG,
932 ADS1015_CFG_MOD_MASK,
933 mode << ADS1015_CFG_MOD_SHIFT);
934}
935
936static int ads1015_probe(struct i2c_client *client,
937 const struct i2c_device_id *id)
938{
939 struct iio_dev *indio_dev;
940 struct ads1015_data *data;
941 int ret;
942 enum chip_ids chip;
943 int i;
944
945 indio_dev = devm_iio_device_alloc(&client->dev, sizeof(*data));
946 if (!indio_dev)
947 return -ENOMEM;
948
949 data = iio_priv(indio_dev);
950 i2c_set_clientdata(client, indio_dev);
951
952 mutex_init(&data->lock);
953
954 indio_dev->dev.parent = &client->dev;
955 indio_dev->dev.of_node = client->dev.of_node;
956 indio_dev->name = ADS1015_DRV_NAME;
957 indio_dev->modes = INDIO_DIRECT_MODE;
958
959 if (client->dev.of_node)
960 chip = (enum chip_ids)of_device_get_match_data(&client->dev);
961 else
962 chip = id->driver_data;
963 switch (chip) {
964 case ADS1015:
965 indio_dev->channels = ads1015_channels;
966 indio_dev->num_channels = ARRAY_SIZE(ads1015_channels);
967 indio_dev->info = &ads1015_info;
968 data->data_rate = (unsigned int *) &ads1015_data_rate;
969 break;
970 case ADS1115:
971 indio_dev->channels = ads1115_channels;
972 indio_dev->num_channels = ARRAY_SIZE(ads1115_channels);
973 indio_dev->info = &ads1115_info;
974 data->data_rate = (unsigned int *) &ads1115_data_rate;
975 break;
976 }
977
978 data->event_channel = ADS1015_CHANNELS;
979
980
981
982
983 for (i = 0; i < ADS1015_CHANNELS; i++) {
984 int realbits = indio_dev->channels[i].scan_type.realbits;
985
986 data->thresh_data[i].low_thresh = -1 << (realbits - 1);
987 data->thresh_data[i].high_thresh = (1 << (realbits - 1)) - 1;
988 }
989
990
991 ads1015_get_channels_config(client);
992
993 data->regmap = devm_regmap_init_i2c(client, &ads1015_regmap_config);
994 if (IS_ERR(data->regmap)) {
995 dev_err(&client->dev, "Failed to allocate register map\n");
996 return PTR_ERR(data->regmap);
997 }
998
999 ret = devm_iio_triggered_buffer_setup(&client->dev, indio_dev, NULL,
1000 ads1015_trigger_handler,
1001 &ads1015_buffer_setup_ops);
1002 if (ret < 0) {
1003 dev_err(&client->dev, "iio triggered buffer setup failed\n");
1004 return ret;
1005 }
1006
1007 if (client->irq) {
1008 unsigned long irq_trig =
1009 irqd_get_trigger_type(irq_get_irq_data(client->irq));
1010 unsigned int cfg_comp_mask = ADS1015_CFG_COMP_QUE_MASK |
1011 ADS1015_CFG_COMP_LAT_MASK | ADS1015_CFG_COMP_POL_MASK;
1012 unsigned int cfg_comp =
1013 ADS1015_CFG_COMP_DISABLE << ADS1015_CFG_COMP_QUE_SHIFT |
1014 1 << ADS1015_CFG_COMP_LAT_SHIFT;
1015
1016 switch (irq_trig) {
1017 case IRQF_TRIGGER_LOW:
1018 cfg_comp |= ADS1015_CFG_COMP_POL_LOW <<
1019 ADS1015_CFG_COMP_POL_SHIFT;
1020 break;
1021 case IRQF_TRIGGER_HIGH:
1022 cfg_comp |= ADS1015_CFG_COMP_POL_HIGH <<
1023 ADS1015_CFG_COMP_POL_SHIFT;
1024 break;
1025 default:
1026 return -EINVAL;
1027 }
1028
1029 ret = regmap_update_bits(data->regmap, ADS1015_CFG_REG,
1030 cfg_comp_mask, cfg_comp);
1031 if (ret)
1032 return ret;
1033
1034 ret = devm_request_threaded_irq(&client->dev, client->irq,
1035 NULL, ads1015_event_handler,
1036 irq_trig | IRQF_ONESHOT,
1037 client->name, indio_dev);
1038 if (ret)
1039 return ret;
1040 }
1041
1042 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1043 if (ret)
1044 return ret;
1045
1046 data->conv_invalid = true;
1047
1048 ret = pm_runtime_set_active(&client->dev);
1049 if (ret)
1050 return ret;
1051 pm_runtime_set_autosuspend_delay(&client->dev, ADS1015_SLEEP_DELAY_MS);
1052 pm_runtime_use_autosuspend(&client->dev);
1053 pm_runtime_enable(&client->dev);
1054
1055 ret = iio_device_register(indio_dev);
1056 if (ret < 0) {
1057 dev_err(&client->dev, "Failed to register IIO device\n");
1058 return ret;
1059 }
1060
1061 return 0;
1062}
1063
1064static int ads1015_remove(struct i2c_client *client)
1065{
1066 struct iio_dev *indio_dev = i2c_get_clientdata(client);
1067 struct ads1015_data *data = iio_priv(indio_dev);
1068
1069 iio_device_unregister(indio_dev);
1070
1071 pm_runtime_disable(&client->dev);
1072 pm_runtime_set_suspended(&client->dev);
1073 pm_runtime_put_noidle(&client->dev);
1074
1075
1076 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1077}
1078
1079#ifdef CONFIG_PM
1080static int ads1015_runtime_suspend(struct device *dev)
1081{
1082 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1083 struct ads1015_data *data = iio_priv(indio_dev);
1084
1085 return ads1015_set_conv_mode(data, ADS1015_SINGLESHOT);
1086}
1087
1088static int ads1015_runtime_resume(struct device *dev)
1089{
1090 struct iio_dev *indio_dev = i2c_get_clientdata(to_i2c_client(dev));
1091 struct ads1015_data *data = iio_priv(indio_dev);
1092 int ret;
1093
1094 ret = ads1015_set_conv_mode(data, ADS1015_CONTINUOUS);
1095 if (!ret)
1096 data->conv_invalid = true;
1097
1098 return ret;
1099}
1100#endif
1101
1102static const struct dev_pm_ops ads1015_pm_ops = {
1103 SET_RUNTIME_PM_OPS(ads1015_runtime_suspend,
1104 ads1015_runtime_resume, NULL)
1105};
1106
1107static const struct i2c_device_id ads1015_id[] = {
1108 {"ads1015", ADS1015},
1109 {"ads1115", ADS1115},
1110 {}
1111};
1112MODULE_DEVICE_TABLE(i2c, ads1015_id);
1113
1114static const struct of_device_id ads1015_of_match[] = {
1115 {
1116 .compatible = "ti,ads1015",
1117 .data = (void *)ADS1015
1118 },
1119 {
1120 .compatible = "ti,ads1115",
1121 .data = (void *)ADS1115
1122 },
1123 {}
1124};
1125MODULE_DEVICE_TABLE(of, ads1015_of_match);
1126
1127static struct i2c_driver ads1015_driver = {
1128 .driver = {
1129 .name = ADS1015_DRV_NAME,
1130 .of_match_table = ads1015_of_match,
1131 .pm = &ads1015_pm_ops,
1132 },
1133 .probe = ads1015_probe,
1134 .remove = ads1015_remove,
1135 .id_table = ads1015_id,
1136};
1137
1138module_i2c_driver(ads1015_driver);
1139
1140MODULE_AUTHOR("Daniel Baluta <daniel.baluta@intel.com>");
1141MODULE_DESCRIPTION("Texas Instruments ADS1015 ADC driver");
1142MODULE_LICENSE("GPL v2");
1143
