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14#include <linux/module.h>
15#include <linux/slab.h>
16#include <linux/i2c.h>
17#include <linux/err.h>
18#include <linux/delay.h>
19#include <linux/sysfs.h>
20#include <linux/jiffies.h>
21#include <linux/irq.h>
22#include <linux/interrupt.h>
23#include <linux/kfifo.h>
24#include <linux/spinlock.h>
25#include <linux/iio/iio.h>
26#include <linux/acpi.h>
27#include "inv_mpu_iio.h"
28
29
30
31
32
33static const int gyro_scale_6050[] = {133090, 266181, 532362, 1064724};
34
35
36
37
38
39static const int accel_scale[] = {598, 1196, 2392, 4785};
40
41static const struct inv_mpu6050_reg_map reg_set_6500 = {
42 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
43 .lpf = INV_MPU6050_REG_CONFIG,
44 .accel_lpf = INV_MPU6500_REG_ACCEL_CONFIG_2,
45 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
46 .fifo_en = INV_MPU6050_REG_FIFO_EN,
47 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
48 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
49 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
50 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
51 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
52 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
53 .temperature = INV_MPU6050_REG_TEMPERATURE,
54 .int_enable = INV_MPU6050_REG_INT_ENABLE,
55 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
56 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
57 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
58 .accl_offset = INV_MPU6500_REG_ACCEL_OFFSET,
59 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
60};
61
62static const struct inv_mpu6050_reg_map reg_set_6050 = {
63 .sample_rate_div = INV_MPU6050_REG_SAMPLE_RATE_DIV,
64 .lpf = INV_MPU6050_REG_CONFIG,
65 .user_ctrl = INV_MPU6050_REG_USER_CTRL,
66 .fifo_en = INV_MPU6050_REG_FIFO_EN,
67 .gyro_config = INV_MPU6050_REG_GYRO_CONFIG,
68 .accl_config = INV_MPU6050_REG_ACCEL_CONFIG,
69 .fifo_count_h = INV_MPU6050_REG_FIFO_COUNT_H,
70 .fifo_r_w = INV_MPU6050_REG_FIFO_R_W,
71 .raw_gyro = INV_MPU6050_REG_RAW_GYRO,
72 .raw_accl = INV_MPU6050_REG_RAW_ACCEL,
73 .temperature = INV_MPU6050_REG_TEMPERATURE,
74 .int_enable = INV_MPU6050_REG_INT_ENABLE,
75 .pwr_mgmt_1 = INV_MPU6050_REG_PWR_MGMT_1,
76 .pwr_mgmt_2 = INV_MPU6050_REG_PWR_MGMT_2,
77 .int_pin_cfg = INV_MPU6050_REG_INT_PIN_CFG,
78 .accl_offset = INV_MPU6050_REG_ACCEL_OFFSET,
79 .gyro_offset = INV_MPU6050_REG_GYRO_OFFSET,
80};
81
82static const struct inv_mpu6050_chip_config chip_config_6050 = {
83 .fsr = INV_MPU6050_FSR_2000DPS,
84 .lpf = INV_MPU6050_FILTER_20HZ,
85 .fifo_rate = INV_MPU6050_INIT_FIFO_RATE,
86 .gyro_fifo_enable = false,
87 .accl_fifo_enable = false,
88 .accl_fs = INV_MPU6050_FS_02G,
89};
90
91
92static const struct inv_mpu6050_hw hw_info[] = {
93 {
94 .whoami = INV_MPU6050_WHOAMI_VALUE,
95 .name = "MPU6050",
96 .reg = ®_set_6050,
97 .config = &chip_config_6050,
98 },
99 {
100 .whoami = INV_MPU6500_WHOAMI_VALUE,
101 .name = "MPU6500",
102 .reg = ®_set_6500,
103 .config = &chip_config_6050,
104 },
105 {
106 .whoami = INV_MPU6000_WHOAMI_VALUE,
107 .name = "MPU6000",
108 .reg = ®_set_6050,
109 .config = &chip_config_6050,
110 },
111 {
112 .whoami = INV_MPU9150_WHOAMI_VALUE,
113 .name = "MPU9150",
114 .reg = ®_set_6050,
115 .config = &chip_config_6050,
116 },
117 {
118 .whoami = INV_MPU9250_WHOAMI_VALUE,
119 .name = "MPU9250",
120 .reg = ®_set_6500,
121 .config = &chip_config_6050,
122 },
123 {
124 .whoami = INV_ICM20608_WHOAMI_VALUE,
125 .name = "ICM20608",
126 .reg = ®_set_6500,
127 .config = &chip_config_6050,
128 },
129};
130
131int inv_mpu6050_switch_engine(struct inv_mpu6050_state *st, bool en, u32 mask)
132{
133 unsigned int d, mgmt_1;
134 int result;
135
136
137
138
139
140 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
141 result = regmap_read(st->map, st->reg->pwr_mgmt_1, &mgmt_1);
142 if (result)
143 return result;
144
145 mgmt_1 &= ~INV_MPU6050_BIT_CLK_MASK;
146 }
147
148 if ((mask == INV_MPU6050_BIT_PWR_GYRO_STBY) && (!en)) {
149
150
151
152
153 mgmt_1 |= INV_CLK_INTERNAL;
154 result = regmap_write(st->map, st->reg->pwr_mgmt_1, mgmt_1);
155 if (result)
156 return result;
157 }
158
159 result = regmap_read(st->map, st->reg->pwr_mgmt_2, &d);
160 if (result)
161 return result;
162 if (en)
163 d &= ~mask;
164 else
165 d |= mask;
166 result = regmap_write(st->map, st->reg->pwr_mgmt_2, d);
167 if (result)
168 return result;
169
170 if (en) {
171
172 msleep(INV_MPU6050_TEMP_UP_TIME);
173 if (mask == INV_MPU6050_BIT_PWR_GYRO_STBY) {
174
175 mgmt_1 |= INV_CLK_PLL;
176 result = regmap_write(st->map,
177 st->reg->pwr_mgmt_1, mgmt_1);
178 if (result)
179 return result;
180 }
181 }
182
183 return 0;
184}
185
186int inv_mpu6050_set_power_itg(struct inv_mpu6050_state *st, bool power_on)
187{
188 int result = 0;
189
190 if (power_on) {
191 if (!st->powerup_count)
192 result = regmap_write(st->map, st->reg->pwr_mgmt_1, 0);
193 if (!result)
194 st->powerup_count++;
195 } else {
196 st->powerup_count--;
197 if (!st->powerup_count)
198 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
199 INV_MPU6050_BIT_SLEEP);
200 }
201
202 if (result)
203 return result;
204
205 if (power_on)
206 usleep_range(INV_MPU6050_REG_UP_TIME_MIN,
207 INV_MPU6050_REG_UP_TIME_MAX);
208
209 return 0;
210}
211EXPORT_SYMBOL_GPL(inv_mpu6050_set_power_itg);
212
213
214
215
216
217
218
219static int inv_mpu6050_set_lpf_regs(struct inv_mpu6050_state *st,
220 enum inv_mpu6050_filter_e val)
221{
222 int result;
223
224 result = regmap_write(st->map, st->reg->lpf, val);
225 if (result)
226 return result;
227
228 switch (st->chip_type) {
229 case INV_MPU6050:
230 case INV_MPU6000:
231 case INV_MPU9150:
232
233 result = 0;
234 break;
235 default:
236
237 result = regmap_write(st->map, st->reg->accel_lpf, val);
238 break;
239 }
240
241 return result;
242}
243
244
245
246
247
248
249
250
251
252
253static int inv_mpu6050_init_config(struct iio_dev *indio_dev)
254{
255 int result;
256 u8 d;
257 struct inv_mpu6050_state *st = iio_priv(indio_dev);
258
259 result = inv_mpu6050_set_power_itg(st, true);
260 if (result)
261 return result;
262 d = (INV_MPU6050_FSR_2000DPS << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
263 result = regmap_write(st->map, st->reg->gyro_config, d);
264 if (result)
265 return result;
266
267 result = inv_mpu6050_set_lpf_regs(st, INV_MPU6050_FILTER_20HZ);
268 if (result)
269 return result;
270
271 d = INV_MPU6050_ONE_K_HZ / INV_MPU6050_INIT_FIFO_RATE - 1;
272 result = regmap_write(st->map, st->reg->sample_rate_div, d);
273 if (result)
274 return result;
275
276 d = (INV_MPU6050_FS_02G << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
277 result = regmap_write(st->map, st->reg->accl_config, d);
278 if (result)
279 return result;
280
281 memcpy(&st->chip_config, hw_info[st->chip_type].config,
282 sizeof(struct inv_mpu6050_chip_config));
283 result = inv_mpu6050_set_power_itg(st, false);
284
285 return result;
286}
287
288static int inv_mpu6050_sensor_set(struct inv_mpu6050_state *st, int reg,
289 int axis, int val)
290{
291 int ind, result;
292 __be16 d = cpu_to_be16(val);
293
294 ind = (axis - IIO_MOD_X) * 2;
295 result = regmap_bulk_write(st->map, reg + ind, (u8 *)&d, 2);
296 if (result)
297 return -EINVAL;
298
299 return 0;
300}
301
302static int inv_mpu6050_sensor_show(struct inv_mpu6050_state *st, int reg,
303 int axis, int *val)
304{
305 int ind, result;
306 __be16 d;
307
308 ind = (axis - IIO_MOD_X) * 2;
309 result = regmap_bulk_read(st->map, reg + ind, (u8 *)&d, 2);
310 if (result)
311 return -EINVAL;
312 *val = (short)be16_to_cpup(&d);
313
314 return IIO_VAL_INT;
315}
316
317static int
318inv_mpu6050_read_raw(struct iio_dev *indio_dev,
319 struct iio_chan_spec const *chan,
320 int *val, int *val2, long mask)
321{
322 struct inv_mpu6050_state *st = iio_priv(indio_dev);
323 int ret = 0;
324
325 switch (mask) {
326 case IIO_CHAN_INFO_RAW:
327 {
328 int result;
329
330 ret = IIO_VAL_INT;
331 mutex_lock(&st->lock);
332 result = iio_device_claim_direct_mode(indio_dev);
333 if (result)
334 goto error_read_raw_unlock;
335 result = inv_mpu6050_set_power_itg(st, true);
336 if (result)
337 goto error_read_raw_release;
338 switch (chan->type) {
339 case IIO_ANGL_VEL:
340 result = inv_mpu6050_switch_engine(st, true,
341 INV_MPU6050_BIT_PWR_GYRO_STBY);
342 if (result)
343 goto error_read_raw_power_off;
344 ret = inv_mpu6050_sensor_show(st, st->reg->raw_gyro,
345 chan->channel2, val);
346 result = inv_mpu6050_switch_engine(st, false,
347 INV_MPU6050_BIT_PWR_GYRO_STBY);
348 if (result)
349 goto error_read_raw_power_off;
350 break;
351 case IIO_ACCEL:
352 result = inv_mpu6050_switch_engine(st, true,
353 INV_MPU6050_BIT_PWR_ACCL_STBY);
354 if (result)
355 goto error_read_raw_power_off;
356 ret = inv_mpu6050_sensor_show(st, st->reg->raw_accl,
357 chan->channel2, val);
358 result = inv_mpu6050_switch_engine(st, false,
359 INV_MPU6050_BIT_PWR_ACCL_STBY);
360 if (result)
361 goto error_read_raw_power_off;
362 break;
363 case IIO_TEMP:
364
365 msleep(INV_MPU6050_SENSOR_UP_TIME);
366 ret = inv_mpu6050_sensor_show(st, st->reg->temperature,
367 IIO_MOD_X, val);
368 break;
369 default:
370 ret = -EINVAL;
371 break;
372 }
373error_read_raw_power_off:
374 result |= inv_mpu6050_set_power_itg(st, false);
375error_read_raw_release:
376 iio_device_release_direct_mode(indio_dev);
377error_read_raw_unlock:
378 mutex_unlock(&st->lock);
379 if (result)
380 return result;
381
382 return ret;
383 }
384 case IIO_CHAN_INFO_SCALE:
385 switch (chan->type) {
386 case IIO_ANGL_VEL:
387 mutex_lock(&st->lock);
388 *val = 0;
389 *val2 = gyro_scale_6050[st->chip_config.fsr];
390 mutex_unlock(&st->lock);
391
392 return IIO_VAL_INT_PLUS_NANO;
393 case IIO_ACCEL:
394 mutex_lock(&st->lock);
395 *val = 0;
396 *val2 = accel_scale[st->chip_config.accl_fs];
397 mutex_unlock(&st->lock);
398
399 return IIO_VAL_INT_PLUS_MICRO;
400 case IIO_TEMP:
401 *val = 0;
402 *val2 = INV_MPU6050_TEMP_SCALE;
403
404 return IIO_VAL_INT_PLUS_MICRO;
405 default:
406 return -EINVAL;
407 }
408 case IIO_CHAN_INFO_OFFSET:
409 switch (chan->type) {
410 case IIO_TEMP:
411 *val = INV_MPU6050_TEMP_OFFSET;
412
413 return IIO_VAL_INT;
414 default:
415 return -EINVAL;
416 }
417 case IIO_CHAN_INFO_CALIBBIAS:
418 switch (chan->type) {
419 case IIO_ANGL_VEL:
420 mutex_lock(&st->lock);
421 ret = inv_mpu6050_sensor_show(st, st->reg->gyro_offset,
422 chan->channel2, val);
423 mutex_unlock(&st->lock);
424 return IIO_VAL_INT;
425 case IIO_ACCEL:
426 mutex_lock(&st->lock);
427 ret = inv_mpu6050_sensor_show(st, st->reg->accl_offset,
428 chan->channel2, val);
429 mutex_unlock(&st->lock);
430 return IIO_VAL_INT;
431
432 default:
433 return -EINVAL;
434 }
435 default:
436 return -EINVAL;
437 }
438}
439
440static int inv_mpu6050_write_gyro_scale(struct inv_mpu6050_state *st, int val)
441{
442 int result, i;
443 u8 d;
444
445 for (i = 0; i < ARRAY_SIZE(gyro_scale_6050); ++i) {
446 if (gyro_scale_6050[i] == val) {
447 d = (i << INV_MPU6050_GYRO_CONFIG_FSR_SHIFT);
448 result = regmap_write(st->map, st->reg->gyro_config, d);
449 if (result)
450 return result;
451
452 st->chip_config.fsr = i;
453 return 0;
454 }
455 }
456
457 return -EINVAL;
458}
459
460static int inv_write_raw_get_fmt(struct iio_dev *indio_dev,
461 struct iio_chan_spec const *chan, long mask)
462{
463 switch (mask) {
464 case IIO_CHAN_INFO_SCALE:
465 switch (chan->type) {
466 case IIO_ANGL_VEL:
467 return IIO_VAL_INT_PLUS_NANO;
468 default:
469 return IIO_VAL_INT_PLUS_MICRO;
470 }
471 default:
472 return IIO_VAL_INT_PLUS_MICRO;
473 }
474
475 return -EINVAL;
476}
477
478static int inv_mpu6050_write_accel_scale(struct inv_mpu6050_state *st, int val)
479{
480 int result, i;
481 u8 d;
482
483 for (i = 0; i < ARRAY_SIZE(accel_scale); ++i) {
484 if (accel_scale[i] == val) {
485 d = (i << INV_MPU6050_ACCL_CONFIG_FSR_SHIFT);
486 result = regmap_write(st->map, st->reg->accl_config, d);
487 if (result)
488 return result;
489
490 st->chip_config.accl_fs = i;
491 return 0;
492 }
493 }
494
495 return -EINVAL;
496}
497
498static int inv_mpu6050_write_raw(struct iio_dev *indio_dev,
499 struct iio_chan_spec const *chan,
500 int val, int val2, long mask)
501{
502 struct inv_mpu6050_state *st = iio_priv(indio_dev);
503 int result;
504
505 mutex_lock(&st->lock);
506
507
508
509
510 result = iio_device_claim_direct_mode(indio_dev);
511 if (result)
512 goto error_write_raw_unlock;
513 result = inv_mpu6050_set_power_itg(st, true);
514 if (result)
515 goto error_write_raw_release;
516
517 switch (mask) {
518 case IIO_CHAN_INFO_SCALE:
519 switch (chan->type) {
520 case IIO_ANGL_VEL:
521 result = inv_mpu6050_write_gyro_scale(st, val2);
522 break;
523 case IIO_ACCEL:
524 result = inv_mpu6050_write_accel_scale(st, val2);
525 break;
526 default:
527 result = -EINVAL;
528 break;
529 }
530 break;
531 case IIO_CHAN_INFO_CALIBBIAS:
532 switch (chan->type) {
533 case IIO_ANGL_VEL:
534 result = inv_mpu6050_sensor_set(st,
535 st->reg->gyro_offset,
536 chan->channel2, val);
537 break;
538 case IIO_ACCEL:
539 result = inv_mpu6050_sensor_set(st,
540 st->reg->accl_offset,
541 chan->channel2, val);
542 break;
543 default:
544 result = -EINVAL;
545 break;
546 }
547 break;
548 default:
549 result = -EINVAL;
550 break;
551 }
552
553 result |= inv_mpu6050_set_power_itg(st, false);
554error_write_raw_release:
555 iio_device_release_direct_mode(indio_dev);
556error_write_raw_unlock:
557 mutex_unlock(&st->lock);
558
559 return result;
560}
561
562
563
564
565
566
567
568
569
570
571
572
573static int inv_mpu6050_set_lpf(struct inv_mpu6050_state *st, int rate)
574{
575 static const int hz[] = {188, 98, 42, 20, 10, 5};
576 static const int d[] = {
577 INV_MPU6050_FILTER_188HZ, INV_MPU6050_FILTER_98HZ,
578 INV_MPU6050_FILTER_42HZ, INV_MPU6050_FILTER_20HZ,
579 INV_MPU6050_FILTER_10HZ, INV_MPU6050_FILTER_5HZ
580 };
581 int i, h, result;
582 u8 data;
583
584 h = (rate >> 1);
585 i = 0;
586 while ((h < hz[i]) && (i < ARRAY_SIZE(d) - 1))
587 i++;
588 data = d[i];
589 result = inv_mpu6050_set_lpf_regs(st, data);
590 if (result)
591 return result;
592 st->chip_config.lpf = data;
593
594 return 0;
595}
596
597
598
599
600static ssize_t
601inv_mpu6050_fifo_rate_store(struct device *dev, struct device_attribute *attr,
602 const char *buf, size_t count)
603{
604 s32 fifo_rate;
605 u8 d;
606 int result;
607 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
608 struct inv_mpu6050_state *st = iio_priv(indio_dev);
609
610 if (kstrtoint(buf, 10, &fifo_rate))
611 return -EINVAL;
612 if (fifo_rate < INV_MPU6050_MIN_FIFO_RATE ||
613 fifo_rate > INV_MPU6050_MAX_FIFO_RATE)
614 return -EINVAL;
615
616 mutex_lock(&st->lock);
617 if (fifo_rate == st->chip_config.fifo_rate) {
618 result = 0;
619 goto fifo_rate_fail_unlock;
620 }
621 result = iio_device_claim_direct_mode(indio_dev);
622 if (result)
623 goto fifo_rate_fail_unlock;
624 result = inv_mpu6050_set_power_itg(st, true);
625 if (result)
626 goto fifo_rate_fail_release;
627
628 d = INV_MPU6050_ONE_K_HZ / fifo_rate - 1;
629 result = regmap_write(st->map, st->reg->sample_rate_div, d);
630 if (result)
631 goto fifo_rate_fail_power_off;
632 st->chip_config.fifo_rate = fifo_rate;
633
634 result = inv_mpu6050_set_lpf(st, fifo_rate);
635 if (result)
636 goto fifo_rate_fail_power_off;
637
638fifo_rate_fail_power_off:
639 result |= inv_mpu6050_set_power_itg(st, false);
640fifo_rate_fail_release:
641 iio_device_release_direct_mode(indio_dev);
642fifo_rate_fail_unlock:
643 mutex_unlock(&st->lock);
644 if (result)
645 return result;
646
647 return count;
648}
649
650
651
652
653static ssize_t
654inv_fifo_rate_show(struct device *dev, struct device_attribute *attr,
655 char *buf)
656{
657 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
658 unsigned fifo_rate;
659
660 mutex_lock(&st->lock);
661 fifo_rate = st->chip_config.fifo_rate;
662 mutex_unlock(&st->lock);
663
664 return scnprintf(buf, PAGE_SIZE, "%u\n", fifo_rate);
665}
666
667
668
669
670
671
672
673
674
675static ssize_t inv_attr_show(struct device *dev, struct device_attribute *attr,
676 char *buf)
677{
678 struct inv_mpu6050_state *st = iio_priv(dev_to_iio_dev(dev));
679 struct iio_dev_attr *this_attr = to_iio_dev_attr(attr);
680 s8 *m;
681
682 switch (this_attr->address) {
683
684
685
686
687 case ATTR_GYRO_MATRIX:
688 case ATTR_ACCL_MATRIX:
689 m = st->plat_data.orientation;
690
691 return scnprintf(buf, PAGE_SIZE,
692 "%d, %d, %d; %d, %d, %d; %d, %d, %d\n",
693 m[0], m[1], m[2], m[3], m[4], m[5], m[6], m[7], m[8]);
694 default:
695 return -EINVAL;
696 }
697}
698
699
700
701
702
703
704
705
706
707
708static int inv_mpu6050_validate_trigger(struct iio_dev *indio_dev,
709 struct iio_trigger *trig)
710{
711 struct inv_mpu6050_state *st = iio_priv(indio_dev);
712
713 if (st->trig != trig)
714 return -EINVAL;
715
716 return 0;
717}
718
719static const struct iio_mount_matrix *
720inv_get_mount_matrix(const struct iio_dev *indio_dev,
721 const struct iio_chan_spec *chan)
722{
723 return &((struct inv_mpu6050_state *)iio_priv(indio_dev))->orientation;
724}
725
726static const struct iio_chan_spec_ext_info inv_ext_info[] = {
727 IIO_MOUNT_MATRIX(IIO_SHARED_BY_TYPE, inv_get_mount_matrix),
728 { },
729};
730
731#define INV_MPU6050_CHAN(_type, _channel2, _index) \
732 { \
733 .type = _type, \
734 .modified = 1, \
735 .channel2 = _channel2, \
736 .info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE), \
737 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \
738 BIT(IIO_CHAN_INFO_CALIBBIAS), \
739 .scan_index = _index, \
740 .scan_type = { \
741 .sign = 's', \
742 .realbits = 16, \
743 .storagebits = 16, \
744 .shift = 0, \
745 .endianness = IIO_BE, \
746 }, \
747 .ext_info = inv_ext_info, \
748 }
749
750static const struct iio_chan_spec inv_mpu_channels[] = {
751 IIO_CHAN_SOFT_TIMESTAMP(INV_MPU6050_SCAN_TIMESTAMP),
752
753
754
755
756 {
757 .type = IIO_TEMP,
758 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW)
759 | BIT(IIO_CHAN_INFO_OFFSET)
760 | BIT(IIO_CHAN_INFO_SCALE),
761 .scan_index = -1,
762 },
763 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_X, INV_MPU6050_SCAN_GYRO_X),
764 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Y, INV_MPU6050_SCAN_GYRO_Y),
765 INV_MPU6050_CHAN(IIO_ANGL_VEL, IIO_MOD_Z, INV_MPU6050_SCAN_GYRO_Z),
766
767 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_X, INV_MPU6050_SCAN_ACCL_X),
768 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Y, INV_MPU6050_SCAN_ACCL_Y),
769 INV_MPU6050_CHAN(IIO_ACCEL, IIO_MOD_Z, INV_MPU6050_SCAN_ACCL_Z),
770};
771
772
773static IIO_CONST_ATTR_SAMP_FREQ_AVAIL("10 20 50 100 200 500");
774static IIO_CONST_ATTR(in_anglvel_scale_available,
775 "0.000133090 0.000266181 0.000532362 0.001064724");
776static IIO_CONST_ATTR(in_accel_scale_available,
777 "0.000598 0.001196 0.002392 0.004785");
778static IIO_DEV_ATTR_SAMP_FREQ(S_IRUGO | S_IWUSR, inv_fifo_rate_show,
779 inv_mpu6050_fifo_rate_store);
780
781
782static IIO_DEVICE_ATTR(in_gyro_matrix, S_IRUGO, inv_attr_show, NULL,
783 ATTR_GYRO_MATRIX);
784static IIO_DEVICE_ATTR(in_accel_matrix, S_IRUGO, inv_attr_show, NULL,
785 ATTR_ACCL_MATRIX);
786
787static struct attribute *inv_attributes[] = {
788 &iio_dev_attr_in_gyro_matrix.dev_attr.attr,
789 &iio_dev_attr_in_accel_matrix.dev_attr.attr,
790 &iio_dev_attr_sampling_frequency.dev_attr.attr,
791 &iio_const_attr_sampling_frequency_available.dev_attr.attr,
792 &iio_const_attr_in_accel_scale_available.dev_attr.attr,
793 &iio_const_attr_in_anglvel_scale_available.dev_attr.attr,
794 NULL,
795};
796
797static const struct attribute_group inv_attribute_group = {
798 .attrs = inv_attributes
799};
800
801static const struct iio_info mpu_info = {
802 .read_raw = &inv_mpu6050_read_raw,
803 .write_raw = &inv_mpu6050_write_raw,
804 .write_raw_get_fmt = &inv_write_raw_get_fmt,
805 .attrs = &inv_attribute_group,
806 .validate_trigger = inv_mpu6050_validate_trigger,
807};
808
809
810
811
812static int inv_check_and_setup_chip(struct inv_mpu6050_state *st)
813{
814 int result;
815 unsigned int regval;
816 int i;
817
818 st->hw = &hw_info[st->chip_type];
819 st->reg = hw_info[st->chip_type].reg;
820
821
822 result = regmap_read(st->map, INV_MPU6050_REG_WHOAMI, ®val);
823 if (result)
824 return result;
825 if (regval != st->hw->whoami) {
826
827 for (i = 0; i < INV_NUM_PARTS; ++i) {
828 if (regval == hw_info[i].whoami) {
829 dev_warn(regmap_get_device(st->map),
830 "whoami mismatch got %#02x (%s)"
831 "expected %#02hhx (%s)\n",
832 regval, hw_info[i].name,
833 st->hw->whoami, st->hw->name);
834 break;
835 }
836 }
837 if (i >= INV_NUM_PARTS) {
838 dev_err(regmap_get_device(st->map),
839 "invalid whoami %#02x expected %#02hhx (%s)\n",
840 regval, st->hw->whoami, st->hw->name);
841 return -ENODEV;
842 }
843 }
844
845
846 result = regmap_write(st->map, st->reg->pwr_mgmt_1,
847 INV_MPU6050_BIT_H_RESET);
848 if (result)
849 return result;
850 msleep(INV_MPU6050_POWER_UP_TIME);
851
852
853
854
855
856
857
858 result = inv_mpu6050_set_power_itg(st, false);
859 if (result)
860 return result;
861 result = inv_mpu6050_set_power_itg(st, true);
862 if (result)
863 return result;
864
865 result = inv_mpu6050_switch_engine(st, false,
866 INV_MPU6050_BIT_PWR_ACCL_STBY);
867 if (result)
868 return result;
869 result = inv_mpu6050_switch_engine(st, false,
870 INV_MPU6050_BIT_PWR_GYRO_STBY);
871 if (result)
872 return result;
873
874 return 0;
875}
876
877int inv_mpu_core_probe(struct regmap *regmap, int irq, const char *name,
878 int (*inv_mpu_bus_setup)(struct iio_dev *), int chip_type)
879{
880 struct inv_mpu6050_state *st;
881 struct iio_dev *indio_dev;
882 struct inv_mpu6050_platform_data *pdata;
883 struct device *dev = regmap_get_device(regmap);
884 int result;
885
886 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
887 if (!indio_dev)
888 return -ENOMEM;
889
890 BUILD_BUG_ON(ARRAY_SIZE(hw_info) != INV_NUM_PARTS);
891 if (chip_type < 0 || chip_type >= INV_NUM_PARTS) {
892 dev_err(dev, "Bad invensense chip_type=%d name=%s\n",
893 chip_type, name);
894 return -ENODEV;
895 }
896 st = iio_priv(indio_dev);
897 mutex_init(&st->lock);
898 st->chip_type = chip_type;
899 st->powerup_count = 0;
900 st->irq = irq;
901 st->map = regmap;
902
903 pdata = dev_get_platdata(dev);
904 if (!pdata) {
905 result = of_iio_read_mount_matrix(dev, "mount-matrix",
906 &st->orientation);
907 if (result) {
908 dev_err(dev, "Failed to retrieve mounting matrix %d\n",
909 result);
910 return result;
911 }
912 } else {
913 st->plat_data = *pdata;
914 }
915
916
917 result = inv_check_and_setup_chip(st);
918 if (result)
919 return result;
920
921 if (inv_mpu_bus_setup)
922 inv_mpu_bus_setup(indio_dev);
923
924 result = inv_mpu6050_init_config(indio_dev);
925 if (result) {
926 dev_err(dev, "Could not initialize device.\n");
927 return result;
928 }
929
930 dev_set_drvdata(dev, indio_dev);
931 indio_dev->dev.parent = dev;
932
933 if (name)
934 indio_dev->name = name;
935 else
936 indio_dev->name = dev_name(dev);
937 indio_dev->channels = inv_mpu_channels;
938 indio_dev->num_channels = ARRAY_SIZE(inv_mpu_channels);
939
940 indio_dev->info = &mpu_info;
941 indio_dev->modes = INDIO_BUFFER_TRIGGERED;
942
943 result = iio_triggered_buffer_setup(indio_dev,
944 inv_mpu6050_irq_handler,
945 inv_mpu6050_read_fifo,
946 NULL);
947 if (result) {
948 dev_err(dev, "configure buffer fail %d\n", result);
949 return result;
950 }
951 result = inv_mpu6050_probe_trigger(indio_dev);
952 if (result) {
953 dev_err(dev, "trigger probe fail %d\n", result);
954 goto out_unreg_ring;
955 }
956
957 INIT_KFIFO(st->timestamps);
958 spin_lock_init(&st->time_stamp_lock);
959 result = iio_device_register(indio_dev);
960 if (result) {
961 dev_err(dev, "IIO register fail %d\n", result);
962 goto out_remove_trigger;
963 }
964
965 return 0;
966
967out_remove_trigger:
968 inv_mpu6050_remove_trigger(st);
969out_unreg_ring:
970 iio_triggered_buffer_cleanup(indio_dev);
971 return result;
972}
973EXPORT_SYMBOL_GPL(inv_mpu_core_probe);
974
975int inv_mpu_core_remove(struct device *dev)
976{
977 struct iio_dev *indio_dev = dev_get_drvdata(dev);
978
979 iio_device_unregister(indio_dev);
980 inv_mpu6050_remove_trigger(iio_priv(indio_dev));
981 iio_triggered_buffer_cleanup(indio_dev);
982
983 return 0;
984}
985EXPORT_SYMBOL_GPL(inv_mpu_core_remove);
986
987#ifdef CONFIG_PM_SLEEP
988
989static int inv_mpu_resume(struct device *dev)
990{
991 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
992 int result;
993
994 mutex_lock(&st->lock);
995 result = inv_mpu6050_set_power_itg(st, true);
996 mutex_unlock(&st->lock);
997
998 return result;
999}
1000
1001static int inv_mpu_suspend(struct device *dev)
1002{
1003 struct inv_mpu6050_state *st = iio_priv(dev_get_drvdata(dev));
1004 int result;
1005
1006 mutex_lock(&st->lock);
1007 result = inv_mpu6050_set_power_itg(st, false);
1008 mutex_unlock(&st->lock);
1009
1010 return result;
1011}
1012#endif
1013
1014SIMPLE_DEV_PM_OPS(inv_mpu_pmops, inv_mpu_suspend, inv_mpu_resume);
1015EXPORT_SYMBOL_GPL(inv_mpu_pmops);
1016
1017MODULE_AUTHOR("Invensense Corporation");
1018MODULE_DESCRIPTION("Invensense device MPU6050 driver");
1019MODULE_LICENSE("GPL");
1020
