1#ifndef DEF_CHIP_REG 2#define DEF_CHIP_REG 3 4/* 5 * Copyright(c) 2015, 2016 Intel Corporation. 6 * 7 * This file is provided under a dual BSD/GPLv2 license. When using or 8 * redistributing this file, you may do so under either license. 9 * 10 * GPL LICENSE SUMMARY 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of version 2 of the GNU General Public License as 14 * published by the Free Software Foundation. 15 * 16 * This program is distributed in the hope that it will be useful, but 17 * WITHOUT ANY WARRANTY; without even the implied warranty of 18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 19 * General Public License for more details. 20 * 21 * BSD LICENSE 22 * 23 * Redistribution and use in source and binary forms, with or without 24 * modification, are permitted provided that the following conditions 25 * are met: 26 * 27 * - Redistributions of source code must retain the above copyright 28 * notice, this list of conditions and the following disclaimer. 29 * - Redistributions in binary form must reproduce the above copyright 30 * notice, this list of conditions and the following disclaimer in 31 * the documentation and/or other materials provided with the 32 * distribution. 33 * - Neither the name of Intel Corporation nor the names of its 34 * contributors may be used to endorse or promote products derived 35 * from this software without specific prior written permission. 36 * 37 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 38 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 39 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 40 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 41 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 42 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 43 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 44 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 45 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 46 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 47 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 48 * 49 */ 50 51#define CORE 0x000000000000 52#define CCE (CORE + 0x000000000000) 53#define ASIC (CORE + 0x000000400000) 54#define MISC (CORE + 0x000000500000) 55#define DC_TOP_CSRS (CORE + 0x000000600000) 56#define CHIP_DEBUG (CORE + 0x000000700000) 57#define RXE (CORE + 0x000001000000) 58#define TXE (CORE + 0x000001800000) 59#define DCC_CSRS (DC_TOP_CSRS + 0x000000000000) 60#define DC_LCB_CSRS (DC_TOP_CSRS + 0x000000001000) 61#define DC_8051_CSRS (DC_TOP_CSRS + 0x000000002000) 62#define PCIE 0 63 64#define ASIC_NUM_SCRATCH 4 65#define CCE_ERR_INT_CNT 0 66#define CCE_MISC_INT_CNT 2 67#define CCE_NUM_32_BIT_COUNTERS 3 68#define CCE_NUM_32_BIT_INT_COUNTERS 6 69#define CCE_NUM_INT_CSRS 12 70#define CCE_NUM_INT_MAP_CSRS 96 71#define CCE_NUM_MSIX_PBAS 4 72#define CCE_NUM_MSIX_VECTORS 256 73#define CCE_NUM_SCRATCH 4 74#define CCE_PCIE_POSTED_CRDT_STALL_CNT 2 75#define CCE_PCIE_TRGT_STALL_CNT 0 76#define CCE_PIO_WR_STALL_CNT 1 77#define CCE_RCV_AVAIL_INT_CNT 3 78#define CCE_RCV_URGENT_INT_CNT 4 79#define CCE_SDMA_INT_CNT 1 80#define CCE_SEND_CREDIT_INT_CNT 5 81#define DCC_CFG_LED_CNTRL (DCC_CSRS + 0x000000000040) 82#define DCC_CFG_LED_CNTRL_LED_CNTRL_SMASK 0x10ull 83#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SHIFT 0 84#define DCC_CFG_LED_CNTRL_LED_SW_BLINK_RATE_SMASK 0xFull 85#define DCC_CFG_PORT_CONFIG (DCC_CSRS + 0x000000000008) 86#define DCC_CFG_PORT_CONFIG1 (DCC_CSRS + 0x000000000010) 87#define DCC_CFG_PORT_CONFIG1_DLID_MASK_MASK 0xFFFFull 88#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SHIFT 16 89#define DCC_CFG_PORT_CONFIG1_DLID_MASK_SMASK 0xFFFF0000ull 90#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_MASK 0xFFFFull 91#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SHIFT 0 92#define DCC_CFG_PORT_CONFIG1_TARGET_DLID_SMASK 0xFFFFull 93#define DCC_CFG_PORT_CONFIG_LINK_STATE_MASK 0x7ull 94#define DCC_CFG_PORT_CONFIG_LINK_STATE_SHIFT 48 95#define DCC_CFG_PORT_CONFIG_LINK_STATE_SMASK 0x7000000000000ull 96#define DCC_CFG_PORT_CONFIG_MTU_CAP_MASK 0x7ull 97#define DCC_CFG_PORT_CONFIG_MTU_CAP_SHIFT 32 98#define DCC_CFG_PORT_CONFIG_MTU_CAP_SMASK 0x700000000ull 99#define DCC_CFG_RESET (DCC_CSRS + 0x000000000000) 100#define DCC_CFG_RESET_RESET_LCB_SHIFT 0 101#define DCC_CFG_RESET_RESET_RX_FPE_SHIFT 2 102#define DCC_CFG_SC_VL_TABLE_15_0 (DCC_CSRS + 0x000000000028) 103#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY0_SHIFT 0 104#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY10_SHIFT 40 105#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY11_SHIFT 44 106#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY12_SHIFT 48 107#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY13_SHIFT 52 108#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY14_SHIFT 56 109#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY15_SHIFT 60 110#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY1_SHIFT 4 111#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY2_SHIFT 8 112#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY3_SHIFT 12 113#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY4_SHIFT 16 114#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY5_SHIFT 20 115#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY6_SHIFT 24 116#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY7_SHIFT 28 117#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY8_SHIFT 32 118#define DCC_CFG_SC_VL_TABLE_15_0_ENTRY9_SHIFT 36 119#define DCC_CFG_SC_VL_TABLE_31_16 (DCC_CSRS + 0x000000000030) 120#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY16_SHIFT 0 121#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY17_SHIFT 4 122#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY18_SHIFT 8 123#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY19_SHIFT 12 124#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY20_SHIFT 16 125#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY21_SHIFT 20 126#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY22_SHIFT 24 127#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY23_SHIFT 28 128#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY24_SHIFT 32 129#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY25_SHIFT 36 130#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY26_SHIFT 40 131#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY27_SHIFT 44 132#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY28_SHIFT 48 133#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY29_SHIFT 52 134#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY30_SHIFT 56 135#define DCC_CFG_SC_VL_TABLE_31_16_ENTRY31_SHIFT 60 136#define DCC_ERR_DROPPED_PKT_CNT (DCC_CSRS + 0x000000000120) 137#define DCC_ERR_FLG (DCC_CSRS + 0x000000000050) 138#define DCC_ERR_FLG_BAD_CRDT_ACK_ERR_SMASK 0x4000ull 139#define DCC_ERR_FLG_BAD_CTRL_DIST_ERR_SMASK 0x200000ull 140#define DCC_ERR_FLG_BAD_CTRL_FLIT_ERR_SMASK 0x10000ull 141#define DCC_ERR_FLG_BAD_DLID_TARGET_ERR_SMASK 0x200ull 142#define DCC_ERR_FLG_BAD_HEAD_DIST_ERR_SMASK 0x800000ull 143#define DCC_ERR_FLG_BAD_L2_ERR_SMASK 0x2ull 144#define DCC_ERR_FLG_BAD_LVER_ERR_SMASK 0x400ull 145#define DCC_ERR_FLG_BAD_MID_TAIL_ERR_SMASK 0x8ull 146#define DCC_ERR_FLG_BAD_PKT_LENGTH_ERR_SMASK 0x4000000ull 147#define DCC_ERR_FLG_BAD_PREEMPTION_ERR_SMASK 0x10ull 148#define DCC_ERR_FLG_BAD_SC_ERR_SMASK 0x4ull 149#define DCC_ERR_FLG_BAD_TAIL_DIST_ERR_SMASK 0x400000ull 150#define DCC_ERR_FLG_BAD_VL_MARKER_ERR_SMASK 0x80ull 151#define DCC_ERR_FLG_CLR (DCC_CSRS + 0x000000000060) 152#define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull 153#define DCC_ERR_FLG_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull 154#define DCC_ERR_FLG_CSR_INVAL_ADDR_SMASK 0x400000000000ull 155#define DCC_ERR_FLG_CSR_PARITY_ERR_SMASK 0x200000000000ull 156#define DCC_ERR_FLG_DLID_ZERO_ERR_SMASK 0x40000000ull 157#define DCC_ERR_FLG_EN (DCC_CSRS + 0x000000000058) 158#define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_HOST_SMASK 0x8000000000ull 159#define DCC_ERR_FLG_EN_CSR_ACCESS_BLOCKED_UC_SMASK 0x10000000000ull 160#define DCC_ERR_FLG_EVENT_CNTR_PARITY_ERR_SMASK 0x20000ull 161#define DCC_ERR_FLG_EVENT_CNTR_ROLLOVER_ERR_SMASK 0x40000ull 162#define DCC_ERR_FLG_FMCONFIG_ERR_SMASK 0x40000000000000ull 163#define DCC_ERR_FLG_FPE_TX_FIFO_OVFLW_ERR_SMASK 0x2000000000ull 164#define DCC_ERR_FLG_FPE_TX_FIFO_UNFLW_ERR_SMASK 0x4000000000ull 165#define DCC_ERR_FLG_LATE_EBP_ERR_SMASK 0x1000000000ull 166#define DCC_ERR_FLG_LATE_LONG_ERR_SMASK 0x800000000ull 167#define DCC_ERR_FLG_LATE_SHORT_ERR_SMASK 0x400000000ull 168#define DCC_ERR_FLG_LENGTH_MTU_ERR_SMASK 0x80000000ull 169#define DCC_ERR_FLG_LINK_ERR_SMASK 0x80000ull 170#define DCC_ERR_FLG_MISC_CNTR_ROLLOVER_ERR_SMASK 0x100000ull 171#define DCC_ERR_FLG_NONVL15_STATE_ERR_SMASK 0x1000000ull 172#define DCC_ERR_FLG_PERM_NVL15_ERR_SMASK 0x10000000ull 173#define DCC_ERR_FLG_PREEMPTION_ERR_SMASK 0x20ull 174#define DCC_ERR_FLG_PREEMPTIONVL15_ERR_SMASK 0x40ull 175#define DCC_ERR_FLG_RCVPORT_ERR_SMASK 0x80000000000000ull 176#define DCC_ERR_FLG_RX_BYTE_SHFT_PARITY_ERR_SMASK 0x1000000000000ull 177#define DCC_ERR_FLG_RX_CTRL_PARITY_MBE_ERR_SMASK 0x100000000000ull 178#define DCC_ERR_FLG_RX_EARLY_DROP_ERR_SMASK 0x200000000ull 179#define DCC_ERR_FLG_SLID_ZERO_ERR_SMASK 0x20000000ull 180#define DCC_ERR_FLG_TX_BYTE_SHFT_PARITY_ERR_SMASK 0x800000000000ull 181#define DCC_ERR_FLG_TX_CTRL_PARITY_ERR_SMASK 0x20000000000ull 182#define DCC_ERR_FLG_TX_CTRL_PARITY_MBE_ERR_SMASK 0x40000000000ull 183#define DCC_ERR_FLG_TX_SC_PARITY_ERR_SMASK 0x80000000000ull 184#define DCC_ERR_FLG_UNCORRECTABLE_ERR_SMASK 0x2000ull 185#define DCC_ERR_FLG_UNSUP_PKT_TYPE_SMASK 0x8000ull 186#define DCC_ERR_FLG_UNSUP_VL_ERR_SMASK 0x8000000ull 187#define DCC_ERR_FLG_VL15_MULTI_ERR_SMASK 0x2000000ull 188#define DCC_ERR_FMCONFIG_ERR_CNT (DCC_CSRS + 0x000000000110) 189#define DCC_ERR_INFO_FMCONFIG (DCC_CSRS + 0x000000000090) 190#define DCC_ERR_INFO_PORTRCV (DCC_CSRS + 0x000000000078) 191#define DCC_ERR_INFO_PORTRCV_HDR0 (DCC_CSRS + 0x000000000080) 192#define DCC_ERR_INFO_PORTRCV_HDR1 (DCC_CSRS + 0x000000000088) 193#define DCC_ERR_INFO_UNCORRECTABLE (DCC_CSRS + 0x000000000098) 194#define DCC_ERR_PORTRCV_ERR_CNT (DCC_CSRS + 0x000000000108) 195#define DCC_ERR_RCVREMOTE_PHY_ERR_CNT (DCC_CSRS + 0x000000000118) 196#define DCC_ERR_UNCORRECTABLE_CNT (DCC_CSRS + 0x000000000100) 197#define DCC_PRF_PORT_MARK_FECN_CNT (DCC_CSRS + 0x000000000330) 198#define DCC_PRF_PORT_RCV_BECN_CNT (DCC_CSRS + 0x000000000290) 199#define DCC_PRF_PORT_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E0) 200#define DCC_PRF_PORT_RCV_CORRECTABLE_CNT (DCC_CSRS + 0x000000000140) 201#define DCC_PRF_PORT_RCV_DATA_CNT (DCC_CSRS + 0x000000000198) 202#define DCC_PRF_PORT_RCV_FECN_CNT (DCC_CSRS + 0x000000000240) 203#define DCC_PRF_PORT_RCV_MULTICAST_PKT_CNT (DCC_CSRS + 0x000000000130) 204#define DCC_PRF_PORT_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001A8) 205#define DCC_PRF_PORT_VL_MARK_FECN_CNT (DCC_CSRS + 0x000000000338) 206#define DCC_PRF_PORT_VL_RCV_BECN_CNT (DCC_CSRS + 0x000000000298) 207#define DCC_PRF_PORT_VL_RCV_BUBBLE_CNT (DCC_CSRS + 0x0000000002E8) 208#define DCC_PRF_PORT_VL_RCV_DATA_CNT (DCC_CSRS + 0x0000000001B0) 209#define DCC_PRF_PORT_VL_RCV_FECN_CNT (DCC_CSRS + 0x000000000248) 210#define DCC_PRF_PORT_VL_RCV_PKTS_CNT (DCC_CSRS + 0x0000000001F8) 211#define DCC_PRF_PORT_XMIT_CORRECTABLE_CNT (DCC_CSRS + 0x000000000138) 212#define DCC_PRF_PORT_XMIT_DATA_CNT (DCC_CSRS + 0x000000000190) 213#define DCC_PRF_PORT_XMIT_MULTICAST_CNT (DCC_CSRS + 0x000000000128) 214#define DCC_PRF_PORT_XMIT_PKTS_CNT (DCC_CSRS + 0x0000000001A0) 215#define DCC_PRF_RX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000180) 216#define DCC_PRF_TX_FLOW_CRTL_CNT (DCC_CSRS + 0x000000000188) 217#define DC_DC8051_CFG_CSR_ACCESS_SEL (DC_8051_CSRS + 0x000000000110) 218#define DC_DC8051_CFG_CSR_ACCESS_SEL_DCC_SMASK 0x2ull 219#define DC_DC8051_CFG_CSR_ACCESS_SEL_LCB_SMASK 0x1ull 220#define DC_DC8051_CFG_EXT_DEV_0 (DC_8051_CSRS + 0x000000000118) 221#define DC_DC8051_CFG_EXT_DEV_0_COMPLETED_SMASK 0x1ull 222#define DC_DC8051_CFG_EXT_DEV_0_RETURN_CODE_SHIFT 8 223#define DC_DC8051_CFG_EXT_DEV_0_RSP_DATA_SHIFT 16 224#define DC_DC8051_CFG_EXT_DEV_1 (DC_8051_CSRS + 0x000000000120) 225#define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_MASK 0xFFFFull 226#define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SHIFT 16 227#define DC_DC8051_CFG_EXT_DEV_1_REQ_DATA_SMASK 0xFFFF0000ull 228#define DC_DC8051_CFG_EXT_DEV_1_REQ_NEW_SMASK 0x1ull 229#define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_MASK 0xFFull 230#define DC_DC8051_CFG_EXT_DEV_1_REQ_TYPE_SHIFT 8 231#define DC_DC8051_CFG_HOST_CMD_0 (DC_8051_CSRS + 0x000000000028) 232#define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_MASK 0xFFFFFFFFFFFFull 233#define DC_DC8051_CFG_HOST_CMD_0_REQ_DATA_SHIFT 16 234#define DC_DC8051_CFG_HOST_CMD_0_REQ_NEW_SMASK 0x1ull 235#define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_MASK 0xFFull 236#define DC_DC8051_CFG_HOST_CMD_0_REQ_TYPE_SHIFT 8 237#define DC_DC8051_CFG_HOST_CMD_1 (DC_8051_CSRS + 0x000000000030) 238#define DC_DC8051_CFG_HOST_CMD_1_COMPLETED_SMASK 0x1ull 239#define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_MASK 0xFFull 240#define DC_DC8051_CFG_HOST_CMD_1_RETURN_CODE_SHIFT 8 241#define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_MASK 0xFFFFFFFFFFFFull 242#define DC_DC8051_CFG_HOST_CMD_1_RSP_DATA_SHIFT 16 243#define DC_DC8051_CFG_LOCAL_GUID (DC_8051_CSRS + 0x000000000038) 244#define DC_DC8051_CFG_MODE (DC_8051_CSRS + 0x000000000070) 245#define DC_DC8051_CFG_RAM_ACCESS_CTRL (DC_8051_CSRS + 0x000000000008) 246#define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_MASK 0x7FFFull 247#define DC_DC8051_CFG_RAM_ACCESS_CTRL_ADDRESS_SHIFT 0 248#define DC_DC8051_CFG_RAM_ACCESS_CTRL_WRITE_ENA_SMASK 0x1000000ull 249#define DC_DC8051_CFG_RAM_ACCESS_CTRL_READ_ENA_SMASK 0x10000ull 250#define DC_DC8051_CFG_RAM_ACCESS_SETUP (DC_8051_CSRS + 0x000000000000) 251#define DC_DC8051_CFG_RAM_ACCESS_SETUP_AUTO_INCR_ADDR_SMASK 0x100ull 252#define DC_DC8051_CFG_RAM_ACCESS_SETUP_RAM_SEL_SMASK 0x1ull 253#define DC_DC8051_CFG_RAM_ACCESS_STATUS (DC_8051_CSRS + 0x000000000018) 254#define DC_DC8051_CFG_RAM_ACCESS_STATUS_ACCESS_COMPLETED_SMASK 0x10000ull 255#define DC_DC8051_CFG_RAM_ACCESS_WR_DATA (DC_8051_CSRS + 0x000000000010) 256#define DC_DC8051_CFG_RAM_ACCESS_RD_DATA (DC_8051_CSRS + 0x000000000020) 257#define DC_DC8051_CFG_RST (DC_8051_CSRS + 0x000000000068) 258#define DC_DC8051_CFG_RST_CRAM_SMASK 0x2ull 259#define DC_DC8051_CFG_RST_DRAM_SMASK 0x4ull 260#define DC_DC8051_CFG_RST_IRAM_SMASK 0x8ull 261#define DC_DC8051_CFG_RST_M8051W_SMASK 0x1ull 262#define DC_DC8051_CFG_RST_SFR_SMASK 0x10ull 263#define DC_DC8051_DBG_ERR_INFO_SET_BY_8051 (DC_8051_CSRS + 0x0000000000D8) 264#define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_MASK 0xFFFFFFFFull 265#define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_ERROR_SHIFT 16 266#define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_MASK 0xFFFFull 267#define DC_DC8051_DBG_ERR_INFO_SET_BY_8051_HOST_MSG_SHIFT 0 268#define DC_DC8051_ERR_CLR (DC_8051_CSRS + 0x0000000000E8) 269#define DC_DC8051_ERR_EN (DC_8051_CSRS + 0x0000000000F0) 270#define DC_DC8051_ERR_EN_LOST_8051_HEART_BEAT_SMASK 0x2ull 271#define DC_DC8051_ERR_FLG (DC_8051_CSRS + 0x0000000000E0) 272#define DC_DC8051_ERR_FLG_CRAM_MBE_SMASK 0x4ull 273#define DC_DC8051_ERR_FLG_CRAM_SBE_SMASK 0x8ull 274#define DC_DC8051_ERR_FLG_DRAM_MBE_SMASK 0x10ull 275#define DC_DC8051_ERR_FLG_DRAM_SBE_SMASK 0x20ull 276#define DC_DC8051_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x400ull 277#define DC_DC8051_ERR_FLG_IRAM_MBE_SMASK 0x40ull 278#define DC_DC8051_ERR_FLG_IRAM_SBE_SMASK 0x80ull 279#define DC_DC8051_ERR_FLG_LOST_8051_HEART_BEAT_SMASK 0x2ull 280#define DC_DC8051_ERR_FLG_SET_BY_8051_SMASK 0x1ull 281#define DC_DC8051_ERR_FLG_UNMATCHED_SECURE_MSG_ACROSS_BCC_LANES_SMASK 0x100ull 282#define DC_DC8051_STS_CUR_STATE (DC_8051_CSRS + 0x000000000060) 283#define DC_DC8051_STS_CUR_STATE_FIRMWARE_MASK 0xFFull 284#define DC_DC8051_STS_CUR_STATE_FIRMWARE_SHIFT 16 285#define DC_DC8051_STS_CUR_STATE_PORT_MASK 0xFFull 286#define DC_DC8051_STS_CUR_STATE_PORT_SHIFT 0 287#define DC_DC8051_STS_LOCAL_FM_SECURITY (DC_8051_CSRS + 0x000000000050) 288#define DC_DC8051_STS_LOCAL_FM_SECURITY_DISABLED_MASK 0x1ull 289#define DC_DC8051_STS_REMOTE_FM_SECURITY (DC_8051_CSRS + 0x000000000058) 290#define DC_DC8051_STS_REMOTE_GUID (DC_8051_CSRS + 0x000000000040) 291#define DC_DC8051_STS_REMOTE_NODE_TYPE (DC_8051_CSRS + 0x000000000048) 292#define DC_DC8051_STS_REMOTE_NODE_TYPE_VAL_MASK 0x3ull 293#define DC_DC8051_STS_REMOTE_PORT_NO (DC_8051_CSRS + 0x000000000130) 294#define DC_DC8051_STS_REMOTE_PORT_NO_VAL_SMASK 0xFFull 295#define DC_LCB_CFG_ALLOW_LINK_UP (DC_LCB_CSRS + 0x000000000128) 296#define DC_LCB_CFG_ALLOW_LINK_UP_VAL_SHIFT 0 297#define DC_LCB_CFG_CRC_MODE (DC_LCB_CSRS + 0x000000000058) 298#define DC_LCB_CFG_CRC_MODE_TX_VAL_SHIFT 0 299#define DC_LCB_CFG_IGNORE_LOST_RCLK (DC_LCB_CSRS + 0x000000000020) 300#define DC_LCB_CFG_IGNORE_LOST_RCLK_EN_SMASK 0x1ull 301#define DC_LCB_CFG_LANE_WIDTH (DC_LCB_CSRS + 0x000000000100) 302#define DC_LCB_CFG_LINK_KILL_EN (DC_LCB_CSRS + 0x000000000120) 303#define DC_LCB_CFG_LINK_KILL_EN_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull 304#define DC_LCB_CFG_LINK_KILL_EN_REPLAY_BUF_MBE_SMASK 0x400000ull 305#define DC_LCB_CFG_LN_DCLK (DC_LCB_CSRS + 0x000000000060) 306#define DC_LCB_CFG_LOOPBACK (DC_LCB_CSRS + 0x0000000000F8) 307#define DC_LCB_CFG_LOOPBACK_VAL_SHIFT 0 308#define DC_LCB_CFG_RUN (DC_LCB_CSRS + 0x000000000000) 309#define DC_LCB_CFG_RUN_EN_SHIFT 0 310#define DC_LCB_CFG_RX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000018) 311#define DC_LCB_CFG_RX_FIFOS_RADR_DO_NOT_JUMP_VAL_SHIFT 8 312#define DC_LCB_CFG_RX_FIFOS_RADR_OK_TO_JUMP_VAL_SHIFT 4 313#define DC_LCB_CFG_RX_FIFOS_RADR_RST_VAL_SHIFT 0 314#define DC_LCB_CFG_TX_FIFOS_RADR (DC_LCB_CSRS + 0x000000000010) 315#define DC_LCB_CFG_TX_FIFOS_RADR_RST_VAL_SHIFT 0 316#define DC_LCB_CFG_TX_FIFOS_RESET (DC_LCB_CSRS + 0x000000000008) 317#define DC_LCB_CFG_TX_FIFOS_RESET_VAL_SHIFT 0 318#define DC_LCB_CFG_REINIT_AS_SLAVE (DC_LCB_CSRS + 0x000000000030) 319#define DC_LCB_CFG_CNT_FOR_SKIP_STALL (DC_LCB_CSRS + 0x000000000040) 320#define DC_LCB_CFG_CLK_CNTR (DC_LCB_CSRS + 0x000000000110) 321#define DC_LCB_ERR_CLR (DC_LCB_CSRS + 0x000000000308) 322#define DC_LCB_ERR_EN (DC_LCB_CSRS + 0x000000000310) 323#define DC_LCB_ERR_FLG (DC_LCB_CSRS + 0x000000000300) 324#define DC_LCB_ERR_FLG_REDUNDANT_FLIT_PARITY_ERR_SMASK 0x20000000ull 325#define DC_LCB_ERR_FLG_NEG_EDGE_LINK_TRANSFER_ACTIVE_SMASK 0x10000000ull 326#define DC_LCB_ERR_FLG_HOLD_REINIT_SMASK 0x8000000ull 327#define DC_LCB_ERR_FLG_RST_FOR_INCOMPLT_RND_TRIP_SMASK 0x4000000ull 328#define DC_LCB_ERR_FLG_RST_FOR_LINK_TIMEOUT_SMASK 0x2000000ull 329#define DC_LCB_ERR_FLG_CREDIT_RETURN_FLIT_MBE_SMASK 0x1000000ull 330#define DC_LCB_ERR_FLG_REPLAY_BUF_SBE_SMASK 0x800000ull 331#define DC_LCB_ERR_FLG_REPLAY_BUF_MBE_SMASK 0x400000ull 332#define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_SBE_SMASK 0x200000ull 333#define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_MBE_SMASK 0x100000ull 334#define DC_LCB_ERR_FLG_VL_ACK_INPUT_WRONG_CRC_MODE_SMASK 0x80000ull 335#define DC_LCB_ERR_FLG_VL_ACK_INPUT_PARITY_ERR_SMASK 0x40000ull 336#define DC_LCB_ERR_FLG_VL_ACK_INPUT_BUF_OFLW_SMASK 0x20000ull 337#define DC_LCB_ERR_FLG_FLIT_INPUT_BUF_OFLW_SMASK 0x10000ull 338#define DC_LCB_ERR_FLG_ILLEGAL_FLIT_ENCODING_SMASK 0x8000ull 339#define DC_LCB_ERR_FLG_ILLEGAL_NULL_LTP_SMASK 0x4000ull 340#define DC_LCB_ERR_FLG_UNEXPECTED_ROUND_TRIP_MARKER_SMASK 0x2000ull 341#define DC_LCB_ERR_FLG_UNEXPECTED_REPLAY_MARKER_SMASK 0x1000ull 342#define DC_LCB_ERR_FLG_RCLK_STOPPED_SMASK 0x800ull 343#define DC_LCB_ERR_FLG_CRC_ERR_CNT_HIT_LIMIT_SMASK 0x400ull 344#define DC_LCB_ERR_FLG_REINIT_FOR_LN_DEGRADE_SMASK 0x200ull 345#define DC_LCB_ERR_FLG_REINIT_FROM_PEER_SMASK 0x100ull 346#define DC_LCB_ERR_FLG_SEQ_CRC_ERR_SMASK 0x80ull 347#define DC_LCB_ERR_FLG_RX_LESS_THAN_FOUR_LNS_SMASK 0x40ull 348#define DC_LCB_ERR_FLG_TX_LESS_THAN_FOUR_LNS_SMASK 0x20ull 349#define DC_LCB_ERR_FLG_LOST_REINIT_STALL_OR_TOS_SMASK 0x10ull 350#define DC_LCB_ERR_FLG_ALL_LNS_FAILED_REINIT_TEST_SMASK 0x8ull 351#define DC_LCB_ERR_FLG_RST_FOR_FAILED_DESKEW_SMASK 0x4ull 352#define DC_LCB_ERR_FLG_INVALID_CSR_ADDR_SMASK 0x2ull 353#define DC_LCB_ERR_FLG_CSR_PARITY_ERR_SMASK 0x1ull 354#define DC_LCB_ERR_INFO_CRC_ERR_LN0 (DC_LCB_CSRS + 0x000000000328) 355#define DC_LCB_ERR_INFO_CRC_ERR_LN1 (DC_LCB_CSRS + 0x000000000330) 356#define DC_LCB_ERR_INFO_CRC_ERR_LN2 (DC_LCB_CSRS + 0x000000000338) 357#define DC_LCB_ERR_INFO_CRC_ERR_LN3 (DC_LCB_CSRS + 0x000000000340) 358#define DC_LCB_ERR_INFO_CRC_ERR_MULTI_LN (DC_LCB_CSRS + 0x000000000348) 359#define DC_LCB_ERR_INFO_ESCAPE_0_ONLY_CNT (DC_LCB_CSRS + 0x000000000368) 360#define DC_LCB_ERR_INFO_ESCAPE_0_PLUS1_CNT (DC_LCB_CSRS + 0x000000000370) 361#define DC_LCB_ERR_INFO_ESCAPE_0_PLUS2_CNT (DC_LCB_CSRS + 0x000000000378) 362#define DC_LCB_ERR_INFO_MISC_FLG_CNT (DC_LCB_CSRS + 0x000000000390) 363#define DC_LCB_ERR_INFO_REINIT_FROM_PEER_CNT (DC_LCB_CSRS + 0x000000000380) 364#define DC_LCB_ERR_INFO_RX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000358) 365#define DC_LCB_ERR_INFO_SBE_CNT (DC_LCB_CSRS + 0x000000000388) 366#define DC_LCB_ERR_INFO_SEQ_CRC_CNT (DC_LCB_CSRS + 0x000000000360) 367#define DC_LCB_ERR_INFO_TOTAL_CRC_ERR (DC_LCB_CSRS + 0x000000000320) 368#define DC_LCB_ERR_INFO_TX_REPLAY_CNT (DC_LCB_CSRS + 0x000000000350) 369#define DC_LCB_PG_DBG_FLIT_CRDTS_CNT (DC_LCB_CSRS + 0x000000000580) 370#define DC_LCB_PG_STS_PAUSE_COMPLETE_CNT (DC_LCB_CSRS + 0x0000000005F8) 371#define DC_LCB_PG_STS_TX_MBE_CNT (DC_LCB_CSRS + 0x000000000608) 372#define DC_LCB_PG_STS_TX_SBE_CNT (DC_LCB_CSRS + 0x000000000600) 373#define DC_LCB_PRF_ACCEPTED_LTP_CNT (DC_LCB_CSRS + 0x000000000408) 374#define DC_LCB_PRF_CLK_CNTR (DC_LCB_CSRS + 0x000000000420) 375#define DC_LCB_PRF_GOOD_LTP_CNT (DC_LCB_CSRS + 0x000000000400) 376#define DC_LCB_PRF_RX_FLIT_CNT (DC_LCB_CSRS + 0x000000000410) 377#define DC_LCB_PRF_TX_FLIT_CNT (DC_LCB_CSRS + 0x000000000418) 378#define DC_LCB_STS_LINK_TRANSFER_ACTIVE (DC_LCB_CSRS + 0x000000000468) 379#define DC_LCB_STS_ROUND_TRIP_LTP_CNT (DC_LCB_CSRS + 0x0000000004B0) 380#define RCV_BUF_OVFL_CNT 10 381#define RCV_CONTEXT_EGR_STALL 22 382#define RCV_DATA_PKT_CNT 0 383#define RCV_DWORD_CNT 1 384#define RCV_TID_FLOW_GEN_MISMATCH_CNT 20 385#define RCV_TID_FLOW_SEQ_MISMATCH_CNT 23 386#define RCV_TID_FULL_ERR_CNT 18 387#define RCV_TID_VALID_ERR_CNT 19 388#define RXE_NUM_32_BIT_COUNTERS 24 389#define RXE_NUM_64_BIT_COUNTERS 2 390#define RXE_NUM_RSM_INSTANCES 4 391#define RXE_NUM_TID_FLOWS 32 392#define RXE_PER_CONTEXT_OFFSET 0x0300000 393#define SEND_DATA_PKT_CNT 0 394#define SEND_DATA_PKT_VL0_CNT 12 395#define SEND_DATA_VL0_CNT 3 396#define SEND_DROPPED_PKT_CNT 5 397#define SEND_DWORD_CNT 1 398#define SEND_FLOW_STALL_CNT 4 399#define SEND_HEADERS_ERR_CNT 6 400#define SEND_LEN_ERR_CNT 1 401#define SEND_MAX_MIN_LEN_ERR_CNT 2 402#define SEND_UNDERRUN_CNT 3 403#define SEND_UNSUP_VL_ERR_CNT 0 404#define SEND_WAIT_CNT 2 405#define SEND_WAIT_VL0_CNT 21 406#define TXE_PIO_SEND_OFFSET 0x0800000 407#define ASIC_CFG_DRV_STR (ASIC + 0x000000000048) 408#define ASIC_CFG_MUTEX (ASIC + 0x000000000040) 409#define ASIC_CFG_SBUS_EXECUTE (ASIC + 0x000000000008) 410#define ASIC_CFG_SBUS_EXECUTE_EXECUTE_SMASK 0x1ull 411#define ASIC_CFG_SBUS_EXECUTE_FAST_MODE_SMASK 0x2ull 412#define ASIC_CFG_SBUS_REQUEST (ASIC + 0x000000000000) 413#define ASIC_CFG_SBUS_REQUEST_COMMAND_SHIFT 16 414#define ASIC_CFG_SBUS_REQUEST_DATA_ADDR_SHIFT 8 415#define ASIC_CFG_SBUS_REQUEST_DATA_IN_SHIFT 32 416#define ASIC_CFG_SBUS_REQUEST_RECEIVER_ADDR_SHIFT 0 417#define ASIC_CFG_SCRATCH (ASIC + 0x000000000020) 418#define ASIC_CFG_SCRATCH_1 (ASIC_CFG_SCRATCH + 0x08) 419#define ASIC_CFG_SCRATCH_2 (ASIC_CFG_SCRATCH + 0x10) 420#define ASIC_CFG_SCRATCH_3 (ASIC_CFG_SCRATCH + 0x18) 421#define ASIC_CFG_THERM_POLL_EN (ASIC + 0x000000000050) 422#define ASIC_EEP_ADDR_CMD (ASIC + 0x000000000308) 423#define ASIC_EEP_ADDR_CMD_EP_ADDR_MASK 0xFFFFFFull 424#define ASIC_EEP_CTL_STAT (ASIC + 0x000000000300) 425#define ASIC_EEP_CTL_STAT_EP_RESET_SMASK 0x4ull 426#define ASIC_EEP_CTL_STAT_RATE_SPI_SHIFT 8 427#define ASIC_EEP_CTL_STAT_RESETCSR 0x0000000083818000ull 428#define ASIC_EEP_DATA (ASIC + 0x000000000310) 429#define ASIC_GPIO_CLEAR (ASIC + 0x000000000230) 430#define ASIC_GPIO_FORCE (ASIC + 0x000000000238) 431#define ASIC_GPIO_IN (ASIC + 0x000000000200) 432#define ASIC_GPIO_INVERT (ASIC + 0x000000000210) 433#define ASIC_GPIO_MASK (ASIC + 0x000000000220) 434#define ASIC_GPIO_OE (ASIC + 0x000000000208) 435#define ASIC_GPIO_OUT (ASIC + 0x000000000218) 436#define ASIC_PCIE_SD_HOST_CMD (ASIC + 0x000000000100) 437#define ASIC_PCIE_SD_HOST_CMD_INTRPT_CMD_SHIFT 0 438#define ASIC_PCIE_SD_HOST_CMD_SBR_MODE_SMASK 0x400ull 439#define ASIC_PCIE_SD_HOST_CMD_SBUS_RCVR_ADDR_SHIFT 2 440#define ASIC_PCIE_SD_HOST_CMD_TIMER_MASK 0xFFFFFull 441#define ASIC_PCIE_SD_HOST_CMD_TIMER_SHIFT 12 442#define ASIC_PCIE_SD_HOST_STATUS (ASIC + 0x000000000108) 443#define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_MASK 0x7ull 444#define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_ERR_SHIFT 2 445#define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_MASK 0x3ull 446#define ASIC_PCIE_SD_HOST_STATUS_FW_DNLD_STS_SHIFT 0 447#define ASIC_PCIE_SD_INTRPT_DATA_CODE (ASIC + 0x000000000110) 448#define ASIC_PCIE_SD_INTRPT_ENABLE (ASIC + 0x000000000118) 449#define ASIC_PCIE_SD_INTRPT_LIST (ASIC + 0x000000000180) 450#define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_CODE_SHIFT 16 451#define ASIC_PCIE_SD_INTRPT_LIST_INTRPT_DATA_SHIFT 0 452#define ASIC_PCIE_SD_INTRPT_STATUS (ASIC + 0x000000000128) 453#define ASIC_QSFP1_CLEAR (ASIC + 0x000000000270) 454#define ASIC_QSFP1_FORCE (ASIC + 0x000000000278) 455#define ASIC_QSFP1_IN (ASIC + 0x000000000240) 456#define ASIC_QSFP1_INVERT (ASIC + 0x000000000250) 457#define ASIC_QSFP1_MASK (ASIC + 0x000000000260) 458#define ASIC_QSFP1_OE (ASIC + 0x000000000248) 459#define ASIC_QSFP1_OUT (ASIC + 0x000000000258) 460#define ASIC_QSFP1_STATUS (ASIC + 0x000000000268) 461#define ASIC_QSFP2_CLEAR (ASIC + 0x0000000002B0) 462#define ASIC_QSFP2_FORCE (ASIC + 0x0000000002B8) 463#define ASIC_QSFP2_IN (ASIC + 0x000000000280) 464#define ASIC_QSFP2_INVERT (ASIC + 0x000000000290) 465#define ASIC_QSFP2_MASK (ASIC + 0x0000000002A0) 466#define ASIC_QSFP2_OE (ASIC + 0x000000000288) 467#define ASIC_QSFP2_OUT (ASIC + 0x000000000298) 468#define ASIC_QSFP2_STATUS (ASIC + 0x0000000002A8) 469#define ASIC_STS_SBUS_COUNTERS (ASIC + 0x000000000018) 470#define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_MASK 0xFFFFull 471#define ASIC_STS_SBUS_COUNTERS_EXECUTE_CNT_SHIFT 0 472#define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_MASK 0xFFFFull 473#define ASIC_STS_SBUS_COUNTERS_RCV_DATA_VALID_CNT_SHIFT 16 474#define ASIC_STS_SBUS_RESULT (ASIC + 0x000000000010) 475#define ASIC_STS_SBUS_RESULT_DONE_SMASK 0x1ull 476#define ASIC_STS_SBUS_RESULT_RCV_DATA_VALID_SMASK 0x2ull 477#define ASIC_STS_SBUS_RESULT_RESULT_CODE_SHIFT 2 478#define ASIC_STS_SBUS_RESULT_RESULT_CODE_MASK 0x7ull 479#define ASIC_STS_SBUS_RESULT_DATA_OUT_SHIFT 32 480#define ASIC_STS_SBUS_RESULT_DATA_OUT_MASK 0xFFFFFFFFull 481#define ASIC_STS_THERM (ASIC + 0x000000000058) 482#define ASIC_STS_THERM_CRIT_TEMP_MASK 0x7FFull 483#define ASIC_STS_THERM_CRIT_TEMP_SHIFT 18 484#define ASIC_STS_THERM_CURR_TEMP_MASK 0x7FFull 485#define ASIC_STS_THERM_CURR_TEMP_SHIFT 2 486#define ASIC_STS_THERM_HI_TEMP_MASK 0x7FFull 487#define ASIC_STS_THERM_HI_TEMP_SHIFT 50 488#define ASIC_STS_THERM_LO_TEMP_MASK 0x7FFull 489#define ASIC_STS_THERM_LO_TEMP_SHIFT 34 490#define ASIC_STS_THERM_LOW_SHIFT 13 491#define CCE_COUNTER_ARRAY32 (CCE + 0x000000000060) 492#define CCE_CTRL (CCE + 0x000000000010) 493#define CCE_CTRL_RXE_RESUME_SMASK 0x800ull 494#define CCE_CTRL_SPC_FREEZE_SMASK 0x100ull 495#define CCE_CTRL_SPC_UNFREEZE_SMASK 0x200ull 496#define CCE_CTRL_TXE_RESUME_SMASK 0x2000ull 497#define CCE_DC_CTRL (CCE + 0x0000000000B8) 498#define CCE_DC_CTRL_DC_RESET_SMASK 0x1ull 499#define CCE_DC_CTRL_RESETCSR 0x0000000000000001ull 500#define CCE_ERR_CLEAR (CCE + 0x000000000050) 501#define CCE_ERR_MASK (CCE + 0x000000000048) 502#define CCE_ERR_STATUS (CCE + 0x000000000040) 503#define CCE_ERR_STATUS_CCE_CLI0_ASYNC_FIFO_PARITY_ERR_SMASK 0x40ull 504#define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_DBG_PARITY_ERROR_SMASK 0x1000ull 505#define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_PIO_CRDT_PARITY_ERR_SMASK \ 506 0x200ull 507#define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_RXDMA_PARITY_ERROR_SMASK \ 508 0x800ull 509#define CCE_ERR_STATUS_CCE_CLI1_ASYNC_FIFO_SDMA_HD_PARITY_ERR_SMASK \ 510 0x400ull 511#define CCE_ERR_STATUS_CCE_CLI2_ASYNC_FIFO_PARITY_ERR_SMASK 0x100ull 512#define CCE_ERR_STATUS_CCE_CSR_CFG_BUS_PARITY_ERR_SMASK 0x80ull 513#define CCE_ERR_STATUS_CCE_CSR_PARITY_ERR_SMASK 0x1ull 514#define CCE_ERR_STATUS_CCE_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 515#define CCE_ERR_STATUS_CCE_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 516#define CCE_ERR_STATUS_CCE_INT_MAP_COR_ERR_SMASK 0x4000000000ull 517#define CCE_ERR_STATUS_CCE_INT_MAP_UNC_ERR_SMASK 0x8000000000ull 518#define CCE_ERR_STATUS_CCE_MSIX_CSR_PARITY_ERR_SMASK 0x10000000000ull 519#define CCE_ERR_STATUS_CCE_MSIX_TABLE_COR_ERR_SMASK 0x1000000000ull 520#define CCE_ERR_STATUS_CCE_MSIX_TABLE_UNC_ERR_SMASK 0x2000000000ull 521#define CCE_ERR_STATUS_CCE_RCPL_ASYNC_FIFO_PARITY_ERR_SMASK 0x400000000ull 522#define CCE_ERR_STATUS_CCE_RSPD_DATA_PARITY_ERR_SMASK 0x20ull 523#define CCE_ERR_STATUS_CCE_RXDMA_CONV_FIFO_PARITY_ERR_SMASK 0x800000000ull 524#define CCE_ERR_STATUS_CCE_SEG_READ_BAD_ADDR_ERR_SMASK 0x100000000ull 525#define CCE_ERR_STATUS_CCE_SEG_WRITE_BAD_ADDR_ERR_SMASK 0x200000000ull 526#define CCE_ERR_STATUS_CCE_TRGT_ACCESS_ERR_SMASK 0x10ull 527#define CCE_ERR_STATUS_CCE_TRGT_ASYNC_FIFO_PARITY_ERR_SMASK 0x8ull 528#define CCE_ERR_STATUS_CCE_TRGT_CPL_TIMEOUT_ERR_SMASK 0x40000000ull 529#define CCE_ERR_STATUS_LA_TRIGGERED_SMASK 0x80000000ull 530#define CCE_ERR_STATUS_PCIC_CPL_DAT_QCOR_ERR_SMASK 0x40000ull 531#define CCE_ERR_STATUS_PCIC_CPL_DAT_QUNC_ERR_SMASK 0x4000000ull 532#define CCE_ERR_STATUS_PCIC_CPL_HD_QCOR_ERR_SMASK 0x20000ull 533#define CCE_ERR_STATUS_PCIC_CPL_HD_QUNC_ERR_SMASK 0x2000000ull 534#define CCE_ERR_STATUS_PCIC_NPOST_DAT_QPARITY_ERR_SMASK 0x100000ull 535#define CCE_ERR_STATUS_PCIC_NPOST_HQ_PARITY_ERR_SMASK 0x80000ull 536#define CCE_ERR_STATUS_PCIC_POST_DAT_QCOR_ERR_SMASK 0x10000ull 537#define CCE_ERR_STATUS_PCIC_POST_DAT_QUNC_ERR_SMASK 0x1000000ull 538#define CCE_ERR_STATUS_PCIC_POST_HD_QCOR_ERR_SMASK 0x8000ull 539#define CCE_ERR_STATUS_PCIC_POST_HD_QUNC_ERR_SMASK 0x800000ull 540#define CCE_ERR_STATUS_PCIC_RECEIVE_PARITY_ERR_SMASK 0x20000000ull 541#define CCE_ERR_STATUS_PCIC_RETRY_MEM_COR_ERR_SMASK 0x2000ull 542#define CCE_ERR_STATUS_PCIC_RETRY_MEM_UNC_ERR_SMASK 0x200000ull 543#define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_COR_ERR_SMASK 0x4000ull 544#define CCE_ERR_STATUS_PCIC_RETRY_SOT_MEM_UNC_ERR_SMASK 0x400000ull 545#define CCE_ERR_STATUS_PCIC_TRANSMIT_BACK_PARITY_ERR_SMASK 0x10000000ull 546#define CCE_ERR_STATUS_PCIC_TRANSMIT_FRONT_PARITY_ERR_SMASK 0x8000000ull 547#define CCE_INT_CLEAR (CCE + 0x000000110A00) 548#define CCE_INT_COUNTER_ARRAY32 (CCE + 0x000000110D00) 549#define CCE_INT_FORCE (CCE + 0x000000110B00) 550#define CCE_INT_MAP (CCE + 0x000000110500) 551#define CCE_INT_MASK (CCE + 0x000000110900) 552#define CCE_INT_STATUS (CCE + 0x000000110800) 553#define CCE_MSIX_INT_GRANTED (CCE + 0x000000110200) 554#define CCE_MSIX_TABLE_LOWER (CCE + 0x000000100000) 555#define CCE_MSIX_TABLE_UPPER (CCE + 0x000000100008) 556#define CCE_MSIX_TABLE_UPPER_RESETCSR 0x0000000100000000ull 557#define CCE_MSIX_VEC_CLR_WITHOUT_INT (CCE + 0x000000110400) 558#define CCE_PCIE_CTRL (CCE + 0x0000000000C0) 559#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_MASK 0x3ull 560#define CCE_PCIE_CTRL_PCIE_LANE_BUNDLE_SHIFT 0 561#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_MASK 0xFull 562#define CCE_PCIE_CTRL_PCIE_LANE_DELAY_SHIFT 2 563#define CCE_PCIE_CTRL_XMT_MARGIN_OVERWRITE_ENABLE_SHIFT 8 564#define CCE_PCIE_CTRL_XMT_MARGIN_SHIFT 9 565#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_MASK 0x1ull 566#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_OVERWRITE_ENABLE_SHIFT 12 567#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_MASK 0x7ull 568#define CCE_PCIE_CTRL_XMT_MARGIN_GEN1_GEN2_SHIFT 13 569#define CCE_REVISION (CCE + 0x000000000000) 570#define CCE_REVISION2 (CCE + 0x000000000008) 571#define CCE_REVISION2_HFI_ID_MASK 0x1ull 572#define CCE_REVISION2_HFI_ID_SHIFT 0 573#define CCE_REVISION2_IMPL_CODE_SHIFT 8 574#define CCE_REVISION2_IMPL_REVISION_SHIFT 16 575#define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_MASK 0xFull 576#define CCE_REVISION_BOARD_ID_LOWER_NIBBLE_SHIFT 32 577#define CCE_REVISION_CHIP_REV_MAJOR_MASK 0xFFull 578#define CCE_REVISION_CHIP_REV_MAJOR_SHIFT 8 579#define CCE_REVISION_CHIP_REV_MINOR_MASK 0xFFull 580#define CCE_REVISION_CHIP_REV_MINOR_SHIFT 0 581#define CCE_REVISION_SW_MASK 0xFFull 582#define CCE_REVISION_SW_SHIFT 24 583#define CCE_SCRATCH (CCE + 0x000000000020) 584#define CCE_STATUS (CCE + 0x000000000018) 585#define CCE_STATUS_RXE_FROZE_SMASK 0x2ull 586#define CCE_STATUS_RXE_PAUSED_SMASK 0x20ull 587#define CCE_STATUS_SDMA_FROZE_SMASK 0x1ull 588#define CCE_STATUS_SDMA_PAUSED_SMASK 0x10ull 589#define CCE_STATUS_TXE_FROZE_SMASK 0x4ull 590#define CCE_STATUS_TXE_PAUSED_SMASK 0x40ull 591#define CCE_STATUS_TXE_PIO_FROZE_SMASK 0x8ull 592#define CCE_STATUS_TXE_PIO_PAUSED_SMASK 0x80ull 593#define MISC_CFG_FW_CTRL (MISC + 0x000000001000) 594#define MISC_CFG_FW_CTRL_FW_8051_LOADED_SMASK 0x2ull 595#define MISC_CFG_FW_CTRL_RSA_STATUS_SHIFT 2 596#define MISC_CFG_FW_CTRL_RSA_STATUS_SMASK 0xCull 597#define MISC_CFG_RSA_CMD (MISC + 0x000000000A08) 598#define MISC_CFG_RSA_MODULUS (MISC + 0x000000000400) 599#define MISC_CFG_RSA_MU (MISC + 0x000000000A10) 600#define MISC_CFG_RSA_R2 (MISC + 0x000000000000) 601#define MISC_CFG_RSA_SIGNATURE (MISC + 0x000000000200) 602#define MISC_CFG_SHA_PRELOAD (MISC + 0x000000000A00) 603#define MISC_ERR_CLEAR (MISC + 0x000000002010) 604#define MISC_ERR_MASK (MISC + 0x000000002008) 605#define MISC_ERR_STATUS (MISC + 0x000000002000) 606#define MISC_ERR_STATUS_MISC_PLL_LOCK_FAIL_ERR_SMASK 0x1000ull 607#define MISC_ERR_STATUS_MISC_MBIST_FAIL_ERR_SMASK 0x800ull 608#define MISC_ERR_STATUS_MISC_INVALID_EEP_CMD_ERR_SMASK 0x400ull 609#define MISC_ERR_STATUS_MISC_EFUSE_DONE_PARITY_ERR_SMASK 0x200ull 610#define MISC_ERR_STATUS_MISC_EFUSE_WRITE_ERR_SMASK 0x100ull 611#define MISC_ERR_STATUS_MISC_EFUSE_READ_BAD_ADDR_ERR_SMASK 0x80ull 612#define MISC_ERR_STATUS_MISC_EFUSE_CSR_PARITY_ERR_SMASK 0x40ull 613#define MISC_ERR_STATUS_MISC_FW_AUTH_FAILED_ERR_SMASK 0x20ull 614#define MISC_ERR_STATUS_MISC_KEY_MISMATCH_ERR_SMASK 0x10ull 615#define MISC_ERR_STATUS_MISC_SBUS_WRITE_FAILED_ERR_SMASK 0x8ull 616#define MISC_ERR_STATUS_MISC_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 617#define MISC_ERR_STATUS_MISC_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 618#define MISC_ERR_STATUS_MISC_CSR_PARITY_ERR_SMASK 0x1ull 619#define PCI_CFG_MSIX0 (PCIE + 0x0000000000B0) 620#define PCI_CFG_REG1 (PCIE + 0x000000000004) 621#define PCI_CFG_REG11 (PCIE + 0x00000000002C) 622#define PCIE_CFG_SPCIE1 (PCIE + 0x00000000014C) 623#define PCIE_CFG_SPCIE2 (PCIE + 0x000000000150) 624#define PCIE_CFG_TPH2 (PCIE + 0x000000000180) 625#define RCV_ARRAY (RXE + 0x000000200000) 626#define RCV_ARRAY_CNT (RXE + 0x000000000018) 627#define RCV_ARRAY_RT_ADDR_MASK 0xFFFFFFFFFull 628#define RCV_ARRAY_RT_ADDR_SHIFT 0 629#define RCV_ARRAY_RT_BUF_SIZE_SHIFT 36 630#define RCV_ARRAY_RT_WRITE_ENABLE_SMASK 0x8000000000000000ull 631#define RCV_AVAIL_TIME_OUT (RXE + 0x000000100050) 632#define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_MASK 0xFFull 633#define RCV_AVAIL_TIME_OUT_TIME_OUT_RELOAD_SHIFT 0 634#define RCV_BTH_QP (RXE + 0x000000000028) 635#define RCV_BTH_QP_KDETH_QP_MASK 0xFFull 636#define RCV_BTH_QP_KDETH_QP_SHIFT 16 637#define RCV_BYPASS (RXE + 0x000000000038) 638#define RCV_CONTEXTS (RXE + 0x000000000010) 639#define RCV_COUNTER_ARRAY32 (RXE + 0x000000000400) 640#define RCV_COUNTER_ARRAY64 (RXE + 0x000000000500) 641#define RCV_CTRL (RXE + 0x000000000000) 642#define RCV_CTRL_RCV_BYPASS_ENABLE_SMASK 0x10ull 643#define RCV_CTRL_RCV_EXTENDED_PSN_ENABLE_SMASK 0x40ull 644#define RCV_CTRL_RCV_PARTITION_KEY_ENABLE_SMASK 0x4ull 645#define RCV_CTRL_RCV_PORT_ENABLE_SMASK 0x1ull 646#define RCV_CTRL_RCV_QP_MAP_ENABLE_SMASK 0x2ull 647#define RCV_CTRL_RCV_RSM_ENABLE_SMASK 0x20ull 648#define RCV_CTRL_RX_RBUF_INIT_SMASK 0x200ull 649#define RCV_CTXT_CTRL (RXE + 0x000000100000) 650#define RCV_CTXT_CTRL_DONT_DROP_EGR_FULL_SMASK 0x4ull 651#define RCV_CTXT_CTRL_DONT_DROP_RHQ_FULL_SMASK 0x8ull 652#define RCV_CTXT_CTRL_EGR_BUF_SIZE_MASK 0x7ull 653#define RCV_CTXT_CTRL_EGR_BUF_SIZE_SHIFT 8 654#define RCV_CTXT_CTRL_EGR_BUF_SIZE_SMASK 0x700ull 655#define RCV_CTXT_CTRL_ENABLE_SMASK 0x1ull 656#define RCV_CTXT_CTRL_INTR_AVAIL_SMASK 0x20ull 657#define RCV_CTXT_CTRL_ONE_PACKET_PER_EGR_BUFFER_SMASK 0x2ull 658#define RCV_CTXT_CTRL_TAIL_UPD_SMASK 0x40ull 659#define RCV_CTXT_CTRL_TID_FLOW_ENABLE_SMASK 0x10ull 660#define RCV_CTXT_STATUS (RXE + 0x000000100008) 661#define RCV_EGR_CTRL (RXE + 0x000000100010) 662#define RCV_EGR_CTRL_EGR_BASE_INDEX_MASK 0x1FFFull 663#define RCV_EGR_CTRL_EGR_BASE_INDEX_SHIFT 0 664#define RCV_EGR_CTRL_EGR_CNT_MASK 0x1FFull 665#define RCV_EGR_CTRL_EGR_CNT_SHIFT 32 666#define RCV_EGR_INDEX_HEAD (RXE + 0x000000300018) 667#define RCV_EGR_INDEX_HEAD_HEAD_MASK 0x7FFull 668#define RCV_EGR_INDEX_HEAD_HEAD_SHIFT 0 669#define RCV_ERR_CLEAR (RXE + 0x000000000070) 670#define RCV_ERR_INFO (RXE + 0x000000000050) 671#define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SC_SMASK 0x1Full 672#define RCV_ERR_INFO_RCV_EXCESS_BUFFER_OVERRUN_SMASK 0x20ull 673#define RCV_ERR_MASK (RXE + 0x000000000068) 674#define RCV_ERR_STATUS (RXE + 0x000000000060) 675#define RCV_ERR_STATUS_RX_CSR_PARITY_ERR_SMASK 0x8000000000000000ull 676#define RCV_ERR_STATUS_RX_CSR_READ_BAD_ADDR_ERR_SMASK 0x2000000000000000ull 677#define RCV_ERR_STATUS_RX_CSR_WRITE_BAD_ADDR_ERR_SMASK \ 678 0x4000000000000000ull 679#define RCV_ERR_STATUS_RX_DC_INTF_PARITY_ERR_SMASK 0x2ull 680#define RCV_ERR_STATUS_RX_DC_SOP_EOP_PARITY_ERR_SMASK 0x200ull 681#define RCV_ERR_STATUS_RX_DMA_CSR_COR_ERR_SMASK 0x1ull 682#define RCV_ERR_STATUS_RX_DMA_CSR_PARITY_ERR_SMASK 0x200000000000000ull 683#define RCV_ERR_STATUS_RX_DMA_CSR_UNC_ERR_SMASK 0x1000000000000000ull 684#define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_COR_ERR_SMASK \ 685 0x40000000000000ull 686#define RCV_ERR_STATUS_RX_DMA_DATA_FIFO_RD_UNC_ERR_SMASK \ 687 0x20000000000000ull 688#define RCV_ERR_STATUS_RX_DMA_DQ_FSM_ENCODING_ERR_SMASK \ 689 0x800000000000000ull 690#define RCV_ERR_STATUS_RX_DMA_EQ_FSM_ENCODING_ERR_SMASK \ 691 0x400000000000000ull 692#define RCV_ERR_STATUS_RX_DMA_FLAG_COR_ERR_SMASK 0x800ull 693#define RCV_ERR_STATUS_RX_DMA_FLAG_UNC_ERR_SMASK 0x400ull 694#define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_COR_ERR_SMASK 0x10000000000000ull 695#define RCV_ERR_STATUS_RX_DMA_HDR_FIFO_RD_UNC_ERR_SMASK 0x8000000000000ull 696#define RCV_ERR_STATUS_RX_HQ_INTR_CSR_PARITY_ERR_SMASK 0x200000000000ull 697#define RCV_ERR_STATUS_RX_HQ_INTR_FSM_ERR_SMASK 0x400000000000ull 698#define RCV_ERR_STATUS_RX_LOOKUP_CSR_PARITY_ERR_SMASK 0x100000000000ull 699#define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_COR_ERR_SMASK \ 700 0x10000000000ull 701#define RCV_ERR_STATUS_RX_LOOKUP_DES_PART1_UNC_ERR_SMASK 0x8000000000ull 702#define RCV_ERR_STATUS_RX_LOOKUP_DES_PART2_PARITY_ERR_SMASK \ 703 0x20000000000ull 704#define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_COR_ERR_SMASK 0x80000000000ull 705#define RCV_ERR_STATUS_RX_LOOKUP_RCV_ARRAY_UNC_ERR_SMASK 0x40000000000ull 706#define RCV_ERR_STATUS_RX_RBUF_BAD_LOOKUP_ERR_SMASK 0x40000000ull 707#define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_COR_ERR_SMASK 0x100000ull 708#define RCV_ERR_STATUS_RX_RBUF_BLOCK_LIST_READ_UNC_ERR_SMASK 0x80000ull 709#define RCV_ERR_STATUS_RX_RBUF_CSR_QENT_CNT_PARITY_ERR_SMASK 0x400000ull 710#define RCV_ERR_STATUS_RX_RBUF_CSR_QEOPDW_PARITY_ERR_SMASK 0x10000000ull 711#define RCV_ERR_STATUS_RX_RBUF_CSR_QHD_PTR_PARITY_ERR_SMASK 0x2000000ull 712#define RCV_ERR_STATUS_RX_RBUF_CSR_QHEAD_BUF_NUM_PARITY_ERR_SMASK \ 713 0x200000ull 714#define RCV_ERR_STATUS_RX_RBUF_CSR_QNEXT_BUF_PARITY_ERR_SMASK 0x800000ull 715#define RCV_ERR_STATUS_RX_RBUF_CSR_QNUM_OF_PKT_PARITY_ERR_SMASK \ 716 0x8000000ull 717#define RCV_ERR_STATUS_RX_RBUF_CSR_QTL_PTR_PARITY_ERR_SMASK 0x4000000ull 718#define RCV_ERR_STATUS_RX_RBUF_CSR_QVLD_BIT_PARITY_ERR_SMASK 0x1000000ull 719#define RCV_ERR_STATUS_RX_RBUF_CTX_ID_PARITY_ERR_SMASK 0x20000000ull 720#define RCV_ERR_STATUS_RX_RBUF_DATA_COR_ERR_SMASK 0x100000000000000ull 721#define RCV_ERR_STATUS_RX_RBUF_DATA_UNC_ERR_SMASK 0x80000000000000ull 722#define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_COR_ERR_SMASK 0x1000000000000ull 723#define RCV_ERR_STATUS_RX_RBUF_DESC_PART1_UNC_ERR_SMASK 0x800000000000ull 724#define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_COR_ERR_SMASK 0x4000000000000ull 725#define RCV_ERR_STATUS_RX_RBUF_DESC_PART2_UNC_ERR_SMASK 0x2000000000000ull 726#define RCV_ERR_STATUS_RX_RBUF_EMPTY_ERR_SMASK 0x100000000ull 727#define RCV_ERR_STATUS_RX_RBUF_FL_INITDONE_PARITY_ERR_SMASK 0x800000000ull 728#define RCV_ERR_STATUS_RX_RBUF_FL_INIT_WR_ADDR_PARITY_ERR_SMASK \ 729 0x1000000000ull 730#define RCV_ERR_STATUS_RX_RBUF_FL_RD_ADDR_PARITY_ERR_SMASK 0x200000000ull 731#define RCV_ERR_STATUS_RX_RBUF_FL_WR_ADDR_PARITY_ERR_SMASK 0x400000000ull 732#define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_COR_ERR_SMASK 0x4000ull 733#define RCV_ERR_STATUS_RX_RBUF_FREE_LIST_UNC_ERR_SMASK 0x2000ull 734#define RCV_ERR_STATUS_RX_RBUF_FULL_ERR_SMASK 0x80000000ull 735#define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_COR_ERR_SMASK 0x40000ull 736#define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_COR_ERR_SMASK 0x10000ull 737#define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_REG_UNC_ERR_SMASK 0x8000ull 738#define RCV_ERR_STATUS_RX_RBUF_LOOKUP_DES_UNC_ERR_SMASK 0x20000ull 739#define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_COR_ERR_SMASK 0x4000000000ull 740#define RCV_ERR_STATUS_RX_RBUF_NEXT_FREE_BUF_UNC_ERR_SMASK 0x2000000000ull 741#define RCV_ERR_STATUS_RX_RCV_CSR_PARITY_ERR_SMASK 0x100ull 742#define RCV_ERR_STATUS_RX_RCV_DATA_COR_ERR_SMASK 0x20ull 743#define RCV_ERR_STATUS_RX_RCV_DATA_UNC_ERR_SMASK 0x10ull 744#define RCV_ERR_STATUS_RX_RCV_FSM_ENCODING_ERR_SMASK 0x1000ull 745#define RCV_ERR_STATUS_RX_RCV_HDR_COR_ERR_SMASK 0x8ull 746#define RCV_ERR_STATUS_RX_RCV_HDR_UNC_ERR_SMASK 0x4ull 747#define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_COR_ERR_SMASK 0x80ull 748#define RCV_ERR_STATUS_RX_RCV_QP_MAP_TABLE_UNC_ERR_SMASK 0x40ull 749#define RCV_HDR_ADDR (RXE + 0x000000100028) 750#define RCV_HDR_CNT (RXE + 0x000000100030) 751#define RCV_HDR_CNT_CNT_MASK 0x1FFull 752#define RCV_HDR_CNT_CNT_SHIFT 0 753#define RCV_HDR_ENT_SIZE (RXE + 0x000000100038) 754#define RCV_HDR_ENT_SIZE_ENT_SIZE_MASK 0x7ull 755#define RCV_HDR_ENT_SIZE_ENT_SIZE_SHIFT 0 756#define RCV_HDR_HEAD (RXE + 0x000000300008) 757#define RCV_HDR_HEAD_COUNTER_MASK 0xFFull 758#define RCV_HDR_HEAD_COUNTER_SHIFT 32 759#define RCV_HDR_HEAD_HEAD_MASK 0x7FFFFull 760#define RCV_HDR_HEAD_HEAD_SHIFT 0 761#define RCV_HDR_HEAD_HEAD_SMASK 0x7FFFFull 762#define RCV_HDR_OVFL_CNT (RXE + 0x000000100058) 763#define RCV_HDR_SIZE (RXE + 0x000000100040) 764#define RCV_HDR_SIZE_HDR_SIZE_MASK 0x1Full 765#define RCV_HDR_SIZE_HDR_SIZE_SHIFT 0 766#define RCV_HDR_TAIL (RXE + 0x000000300000) 767#define RCV_HDR_TAIL_ADDR (RXE + 0x000000100048) 768#define RCV_KEY_CTRL (RXE + 0x000000100020) 769#define RCV_KEY_CTRL_JOB_KEY_ENABLE_SMASK 0x200000000ull 770#define RCV_KEY_CTRL_JOB_KEY_VALUE_MASK 0xFFFFull 771#define RCV_KEY_CTRL_JOB_KEY_VALUE_SHIFT 0 772#define RCV_MULTICAST (RXE + 0x000000000030) 773#define RCV_PARTITION_KEY (RXE + 0x000000000200) 774#define RCV_PARTITION_KEY_PARTITION_KEY_A_MASK 0xFFFFull 775#define RCV_PARTITION_KEY_PARTITION_KEY_B_SHIFT 16 776#define RCV_QP_MAP_TABLE (RXE + 0x000000000100) 777#define RCV_RSM_CFG (RXE + 0x000000000600) 778#define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_MASK 0x1ull 779#define RCV_RSM_CFG_ENABLE_OR_CHAIN_RSM0_SHIFT 0 780#define RCV_RSM_CFG_PACKET_TYPE_SHIFT 60 781#define RCV_RSM_CFG_OFFSET_SHIFT 32 782#define RCV_RSM_MAP_TABLE (RXE + 0x000000000900) 783#define RCV_RSM_MAP_TABLE_RCV_CONTEXT_A_MASK 0xFFull 784#define RCV_RSM_MATCH (RXE + 0x000000000800) 785#define RCV_RSM_MATCH_MASK1_SHIFT 0 786#define RCV_RSM_MATCH_MASK2_SHIFT 16 787#define RCV_RSM_MATCH_VALUE1_SHIFT 8 788#define RCV_RSM_MATCH_VALUE2_SHIFT 24 789#define RCV_RSM_SELECT (RXE + 0x000000000700) 790#define RCV_RSM_SELECT_FIELD1_OFFSET_SHIFT 0 791#define RCV_RSM_SELECT_FIELD2_OFFSET_SHIFT 16 792#define RCV_RSM_SELECT_INDEX1_OFFSET_SHIFT 32 793#define RCV_RSM_SELECT_INDEX1_WIDTH_SHIFT 44 794#define RCV_RSM_SELECT_INDEX2_OFFSET_SHIFT 48 795#define RCV_RSM_SELECT_INDEX2_WIDTH_SHIFT 60 796#define RCV_STATUS (RXE + 0x000000000008) 797#define RCV_STATUS_RX_PKT_IN_PROGRESS_SMASK 0x1ull 798#define RCV_STATUS_RX_RBUF_INIT_DONE_SMASK 0x200ull 799#define RCV_STATUS_RX_RBUF_PKT_PENDING_SMASK 0x40ull 800#define RCV_TID_CTRL (RXE + 0x000000100018) 801#define RCV_TID_CTRL_TID_BASE_INDEX_MASK 0x1FFFull 802#define RCV_TID_CTRL_TID_BASE_INDEX_SHIFT 0 803#define RCV_TID_CTRL_TID_PAIR_CNT_MASK 0x1FFull 804#define RCV_TID_CTRL_TID_PAIR_CNT_SHIFT 32 805#define RCV_TID_FLOW_TABLE (RXE + 0x000000300800) 806#define RCV_VL15 (RXE + 0x000000000048) 807#define SEND_BTH_QP (TXE + 0x0000000000A0) 808#define SEND_BTH_QP_KDETH_QP_MASK 0xFFull 809#define SEND_BTH_QP_KDETH_QP_SHIFT 16 810#define SEND_CM_CREDIT_USED_STATUS (TXE + 0x000000000510) 811#define SEND_CM_CREDIT_USED_STATUS_VL0_RETURN_CREDIT_STATUS_SMASK \ 812 0x1000000000000ull 813#define SEND_CM_CREDIT_USED_STATUS_VL15_RETURN_CREDIT_STATUS_SMASK \ 814 0x8000000000000000ull 815#define SEND_CM_CREDIT_USED_STATUS_VL1_RETURN_CREDIT_STATUS_SMASK \ 816 0x2000000000000ull 817#define SEND_CM_CREDIT_USED_STATUS_VL2_RETURN_CREDIT_STATUS_SMASK \ 818 0x4000000000000ull 819#define SEND_CM_CREDIT_USED_STATUS_VL3_RETURN_CREDIT_STATUS_SMASK \ 820 0x8000000000000ull 821#define SEND_CM_CREDIT_USED_STATUS_VL4_RETURN_CREDIT_STATUS_SMASK \ 822 0x10000000000000ull 823#define SEND_CM_CREDIT_USED_STATUS_VL5_RETURN_CREDIT_STATUS_SMASK \ 824 0x20000000000000ull 825#define SEND_CM_CREDIT_USED_STATUS_VL6_RETURN_CREDIT_STATUS_SMASK \ 826 0x40000000000000ull 827#define SEND_CM_CREDIT_USED_STATUS_VL7_RETURN_CREDIT_STATUS_SMASK \ 828 0x80000000000000ull 829#define SEND_CM_CREDIT_VL (TXE + 0x000000000600) 830#define SEND_CM_CREDIT_VL15 (TXE + 0x000000000678) 831#define SEND_CM_CREDIT_VL15_DEDICATED_LIMIT_VL_SHIFT 0 832#define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_MASK 0xFFFFull 833#define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SHIFT 0 834#define SEND_CM_CREDIT_VL_DEDICATED_LIMIT_VL_SMASK 0xFFFFull 835#define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_MASK 0xFFFFull 836#define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SHIFT 16 837#define SEND_CM_CREDIT_VL_SHARED_LIMIT_VL_SMASK 0xFFFF0000ull 838#define SEND_CM_CTRL (TXE + 0x000000000500) 839#define SEND_CM_CTRL_FORCE_CREDIT_MODE_SMASK 0x8ull 840#define SEND_CM_CTRL_RESETCSR 0x0000000000000020ull 841#define SEND_CM_GLOBAL_CREDIT (TXE + 0x000000000508) 842#define SEND_CM_GLOBAL_CREDIT_AU_MASK 0x7ull 843#define SEND_CM_GLOBAL_CREDIT_AU_SHIFT 16 844#define SEND_CM_GLOBAL_CREDIT_AU_SMASK 0x70000ull 845#define SEND_CM_GLOBAL_CREDIT_RESETCSR 0x0000094000030000ull 846#define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_MASK 0xFFFFull 847#define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SHIFT 0 848#define SEND_CM_GLOBAL_CREDIT_SHARED_LIMIT_SMASK 0xFFFFull 849#define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_MASK 0xFFFFull 850#define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SHIFT 32 851#define SEND_CM_GLOBAL_CREDIT_TOTAL_CREDIT_LIMIT_SMASK 0xFFFF00000000ull 852#define SEND_CM_LOCAL_AU_TABLE0_TO3 (TXE + 0x000000000520) 853#define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE0_SHIFT 0 854#define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE1_SHIFT 16 855#define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE2_SHIFT 32 856#define SEND_CM_LOCAL_AU_TABLE0_TO3_LOCAL_AU_TABLE3_SHIFT 48 857#define SEND_CM_LOCAL_AU_TABLE4_TO7 (TXE + 0x000000000528) 858#define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE4_SHIFT 0 859#define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE5_SHIFT 16 860#define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE6_SHIFT 32 861#define SEND_CM_LOCAL_AU_TABLE4_TO7_LOCAL_AU_TABLE7_SHIFT 48 862#define SEND_CM_REMOTE_AU_TABLE0_TO3 (TXE + 0x000000000530) 863#define SEND_CM_REMOTE_AU_TABLE4_TO7 (TXE + 0x000000000538) 864#define SEND_CM_TIMER_CTRL (TXE + 0x000000000518) 865#define SEND_CONTEXTS (TXE + 0x000000000010) 866#define SEND_CONTEXT_SET_CTRL (TXE + 0x000000000200) 867#define SEND_COUNTER_ARRAY32 (TXE + 0x000000000300) 868#define SEND_COUNTER_ARRAY64 (TXE + 0x000000000400) 869#define SEND_CTRL (TXE + 0x000000000000) 870#define SEND_CTRL_CM_RESET_SMASK 0x4ull 871#define SEND_CTRL_SEND_ENABLE_SMASK 0x1ull 872#define SEND_CTRL_VL_ARBITER_ENABLE_SMASK 0x2ull 873#define SEND_CTXT_CHECK_ENABLE (TXE + 0x000000100080) 874#define SEND_CTXT_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull 875#define SEND_CTXT_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull 876#define SEND_CTXT_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull 877#define SEND_CTXT_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull 878#define SEND_CTXT_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull 879#define SEND_CTXT_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull 880#define SEND_CTXT_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull 881#define SEND_CTXT_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull 882#define SEND_CTXT_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull 883#define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK \ 884 0x200000ull 885#define SEND_CTXT_CHECK_ENABLE_DISALLOW_BYPASS_SMASK 0x800ull 886#define SEND_CTXT_CHECK_ENABLE_DISALLOW_GRH_SMASK 0x400ull 887#define SEND_CTXT_CHECK_ENABLE_DISALLOW_KDETH_PACKETS_SMASK 0x1000ull 888#define SEND_CTXT_CHECK_ENABLE_DISALLOW_NON_KDETH_PACKETS_SMASK 0x2000ull 889#define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \ 890 0x100000ull 891#define SEND_CTXT_CHECK_ENABLE_DISALLOW_PBC_TEST_SMASK 0x10000ull 892#define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull 893#define SEND_CTXT_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull 894#define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \ 895 0x80000ull 896#define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK \ 897 0x40000ull 898#define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \ 899 0x8000ull 900#define SEND_CTXT_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK \ 901 0x4000ull 902#define SEND_CTXT_CHECK_JOB_KEY (TXE + 0x000000100090) 903#define SEND_CTXT_CHECK_JOB_KEY_ALLOW_PERMISSIVE_SMASK 0x100000000ull 904#define SEND_CTXT_CHECK_JOB_KEY_MASK_SMASK 0xFFFF0000ull 905#define SEND_CTXT_CHECK_JOB_KEY_VALUE_MASK 0xFFFFull 906#define SEND_CTXT_CHECK_JOB_KEY_VALUE_SHIFT 0 907#define SEND_CTXT_CHECK_OPCODE (TXE + 0x0000001000A8) 908#define SEND_CTXT_CHECK_OPCODE_MASK_SHIFT 8 909#define SEND_CTXT_CHECK_OPCODE_VALUE_SHIFT 0 910#define SEND_CTXT_CHECK_PARTITION_KEY (TXE + 0x000000100098) 911#define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_MASK 0xFFFFull 912#define SEND_CTXT_CHECK_PARTITION_KEY_VALUE_SHIFT 0 913#define SEND_CTXT_CHECK_SLID (TXE + 0x0000001000A0) 914#define SEND_CTXT_CHECK_SLID_MASK_MASK 0xFFFFull 915#define SEND_CTXT_CHECK_SLID_MASK_SHIFT 16 916#define SEND_CTXT_CHECK_SLID_VALUE_MASK 0xFFFFull 917#define SEND_CTXT_CHECK_SLID_VALUE_SHIFT 0 918#define SEND_CTXT_CHECK_VL (TXE + 0x000000100088) 919#define SEND_CTXT_CREDIT_CTRL (TXE + 0x000000100010) 920#define SEND_CTXT_CREDIT_CTRL_CREDIT_INTR_SMASK 0x20000ull 921#define SEND_CTXT_CREDIT_CTRL_EARLY_RETURN_SMASK 0x10000ull 922#define SEND_CTXT_CREDIT_CTRL_THRESHOLD_MASK 0x7FFull 923#define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SHIFT 0 924#define SEND_CTXT_CREDIT_CTRL_THRESHOLD_SMASK 0x7FFull 925#define SEND_CTXT_CREDIT_FORCE (TXE + 0x000000100028) 926#define SEND_CTXT_CREDIT_FORCE_FORCE_RETURN_SMASK 0x1ull 927#define SEND_CTXT_CREDIT_RETURN_ADDR (TXE + 0x000000100020) 928#define SEND_CTXT_CREDIT_RETURN_ADDR_ADDRESS_SMASK 0xFFFFFFFFFFC0ull 929#define SEND_CTXT_CTRL (TXE + 0x000000100000) 930#define SEND_CTXT_CTRL_CTXT_BASE_MASK 0x3FFFull 931#define SEND_CTXT_CTRL_CTXT_BASE_SHIFT 32 932#define SEND_CTXT_CTRL_CTXT_DEPTH_MASK 0x7FFull 933#define SEND_CTXT_CTRL_CTXT_DEPTH_SHIFT 48 934#define SEND_CTXT_CTRL_CTXT_ENABLE_SMASK 0x1ull 935#define SEND_CTXT_ERR_CLEAR (TXE + 0x000000100050) 936#define SEND_CTXT_ERR_MASK (TXE + 0x000000100048) 937#define SEND_CTXT_ERR_STATUS (TXE + 0x000000100040) 938#define SEND_CTXT_ERR_STATUS_PIO_DISALLOWED_PACKET_ERR_SMASK 0x2ull 939#define SEND_CTXT_ERR_STATUS_PIO_INCONSISTENT_SOP_ERR_SMASK 0x1ull 940#define SEND_CTXT_ERR_STATUS_PIO_WRITE_CROSSES_BOUNDARY_ERR_SMASK 0x4ull 941#define SEND_CTXT_ERR_STATUS_PIO_WRITE_OUT_OF_BOUNDS_ERR_SMASK 0x10ull 942#define SEND_CTXT_ERR_STATUS_PIO_WRITE_OVERFLOW_ERR_SMASK 0x8ull 943#define SEND_CTXT_STATUS (TXE + 0x000000100008) 944#define SEND_CTXT_STATUS_CTXT_HALTED_SMASK 0x1ull 945#define SEND_DMA_BASE_ADDR (TXE + 0x000000200010) 946#define SEND_DMA_CHECK_ENABLE (TXE + 0x000000200080) 947#define SEND_DMA_CHECK_ENABLE_CHECK_BYPASS_VL_MAPPING_SMASK 0x80ull 948#define SEND_DMA_CHECK_ENABLE_CHECK_ENABLE_SMASK 0x1ull 949#define SEND_DMA_CHECK_ENABLE_CHECK_JOB_KEY_SMASK 0x4ull 950#define SEND_DMA_CHECK_ENABLE_CHECK_OPCODE_SMASK 0x20ull 951#define SEND_DMA_CHECK_ENABLE_CHECK_PARTITION_KEY_SMASK 0x8ull 952#define SEND_DMA_CHECK_ENABLE_CHECK_SLID_SMASK 0x10ull 953#define SEND_DMA_CHECK_ENABLE_CHECK_VL_MAPPING_SMASK 0x40ull 954#define SEND_DMA_CHECK_ENABLE_CHECK_VL_SMASK 0x2ull 955#define SEND_DMA_CHECK_ENABLE_DISALLOW_BAD_PKT_LEN_SMASK 0x20000ull 956#define SEND_DMA_CHECK_ENABLE_DISALLOW_BYPASS_BAD_PKT_LEN_SMASK 0x200000ull 957#define SEND_DMA_CHECK_ENABLE_DISALLOW_PBC_STATIC_RATE_CONTROL_SMASK \ 958 0x100000ull 959#define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_IPV6_SMASK 0x200ull 960#define SEND_DMA_CHECK_ENABLE_DISALLOW_RAW_SMASK 0x100ull 961#define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_BYPASS_PACKETS_SMASK \ 962 0x80000ull 963#define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_LONG_IB_PACKETS_SMASK 0x40000ull 964#define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_BYPASS_PACKETS_SMASK \ 965 0x8000ull 966#define SEND_DMA_CHECK_ENABLE_DISALLOW_TOO_SMALL_IB_PACKETS_SMASK 0x4000ull 967#define SEND_DMA_CHECK_JOB_KEY (TXE + 0x000000200090) 968#define SEND_DMA_CHECK_OPCODE (TXE + 0x0000002000A8) 969#define SEND_DMA_CHECK_PARTITION_KEY (TXE + 0x000000200098) 970#define SEND_DMA_CHECK_SLID (TXE + 0x0000002000A0) 971#define SEND_DMA_CHECK_SLID_MASK_MASK 0xFFFFull 972#define SEND_DMA_CHECK_SLID_MASK_SHIFT 16 973#define SEND_DMA_CHECK_SLID_VALUE_MASK 0xFFFFull 974#define SEND_DMA_CHECK_SLID_VALUE_SHIFT 0 975#define SEND_DMA_CHECK_VL (TXE + 0x000000200088) 976#define SEND_DMA_CTRL (TXE + 0x000000200000) 977#define SEND_DMA_CTRL_SDMA_CLEANUP_SMASK 0x4ull 978#define SEND_DMA_CTRL_SDMA_ENABLE_SMASK 0x1ull 979#define SEND_DMA_CTRL_SDMA_HALT_SMASK 0x2ull 980#define SEND_DMA_CTRL_SDMA_INT_ENABLE_SMASK 0x8ull 981#define SEND_DMA_DESC_CNT (TXE + 0x000000200050) 982#define SEND_DMA_DESC_CNT_CNT_MASK 0xFFFFull 983#define SEND_DMA_DESC_CNT_CNT_SHIFT 0 984#define SEND_DMA_ENG_ERR_CLEAR (TXE + 0x000000200070) 985#define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_MASK 0x1ull 986#define SEND_DMA_ENG_ERR_CLEAR_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SHIFT 18 987#define SEND_DMA_ENG_ERR_MASK (TXE + 0x000000200068) 988#define SEND_DMA_ENG_ERR_STATUS (TXE + 0x000000200060) 989#define SEND_DMA_ENG_ERR_STATUS_SDMA_ASSEMBLY_UNC_ERR_SMASK 0x8000ull 990#define SEND_DMA_ENG_ERR_STATUS_SDMA_DESC_TABLE_UNC_ERR_SMASK 0x4000ull 991#define SEND_DMA_ENG_ERR_STATUS_SDMA_FIRST_DESC_ERR_SMASK 0x10ull 992#define SEND_DMA_ENG_ERR_STATUS_SDMA_GEN_MISMATCH_ERR_SMASK 0x2ull 993#define SEND_DMA_ENG_ERR_STATUS_SDMA_HALT_ERR_SMASK 0x40ull 994#define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_ADDRESS_ERR_SMASK 0x800ull 995#define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_LENGTH_ERR_SMASK 0x1000ull 996#define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_REQUEST_FIFO_UNC_ERR_SMASK \ 997 0x40000ull 998#define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_SELECT_ERR_SMASK 0x400ull 999#define SEND_DMA_ENG_ERR_STATUS_SDMA_HEADER_STORAGE_UNC_ERR_SMASK \ 1000 0x20000ull
1001#define SEND_DMA_ENG_ERR_STATUS_SDMA_LENGTH_MISMATCH_ERR_SMASK 0x80ull 1002#define SEND_DMA_ENG_ERR_STATUS_SDMA_MEM_READ_ERR_SMASK 0x20ull 1003#define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_DESC_OVERFLOW_ERR_SMASK \ 1004 0x100ull 1005#define SEND_DMA_ENG_ERR_STATUS_SDMA_PACKET_TRACKING_UNC_ERR_SMASK \ 1006 0x10000ull 1007#define SEND_DMA_ENG_ERR_STATUS_SDMA_TAIL_OUT_OF_BOUNDS_ERR_SMASK 0x8ull 1008#define SEND_DMA_ENG_ERR_STATUS_SDMA_TIMEOUT_ERR_SMASK 0x2000ull 1009#define SEND_DMA_ENG_ERR_STATUS_SDMA_TOO_LONG_ERR_SMASK 0x4ull 1010#define SEND_DMA_ENG_ERR_STATUS_SDMA_WRONG_DW_ERR_SMASK 0x1ull 1011#define SEND_DMA_ENGINES (TXE + 0x000000000018) 1012#define SEND_DMA_ERR_CLEAR (TXE + 0x000000000070) 1013#define SEND_DMA_ERR_MASK (TXE + 0x000000000068) 1014#define SEND_DMA_ERR_STATUS (TXE + 0x000000000060) 1015#define SEND_DMA_ERR_STATUS_SDMA_CSR_PARITY_ERR_SMASK 0x2ull 1016#define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_COR_ERR_SMASK 0x8ull 1017#define SEND_DMA_ERR_STATUS_SDMA_PCIE_REQ_TRACKING_UNC_ERR_SMASK 0x4ull 1018#define SEND_DMA_ERR_STATUS_SDMA_RPY_TAG_ERR_SMASK 0x1ull 1019#define SEND_DMA_HEAD (TXE + 0x000000200028) 1020#define SEND_DMA_HEAD_ADDR (TXE + 0x000000200030) 1021#define SEND_DMA_LEN_GEN (TXE + 0x000000200018) 1022#define SEND_DMA_LEN_GEN_GENERATION_SHIFT 16 1023#define SEND_DMA_LEN_GEN_LENGTH_SHIFT 6 1024#define SEND_DMA_MEMORY (TXE + 0x0000002000B0) 1025#define SEND_DMA_MEMORY_SDMA_MEMORY_CNT_SHIFT 16 1026#define SEND_DMA_MEMORY_SDMA_MEMORY_INDEX_SHIFT 0 1027#define SEND_DMA_MEM_SIZE (TXE + 0x000000000028) 1028#define SEND_DMA_PRIORITY_THLD (TXE + 0x000000200038) 1029#define SEND_DMA_RELOAD_CNT (TXE + 0x000000200048) 1030#define SEND_DMA_STATUS (TXE + 0x000000200008) 1031#define SEND_DMA_STATUS_ENG_CLEANED_UP_SMASK 0x200000000000000ull 1032#define SEND_DMA_STATUS_ENG_HALTED_SMASK 0x100000000000000ull 1033#define SEND_DMA_TAIL (TXE + 0x000000200020) 1034#define SEND_EGRESS_CTXT_STATUS (TXE + 0x000000000800) 1035#define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_HALT_STATUS_SMASK 0x10000ull 1036#define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SHIFT 0 1037#define SEND_EGRESS_CTXT_STATUS_CTXT_EGRESS_PACKET_OCCUPANCY_SMASK \ 1038 0x3FFFull 1039#define SEND_EGRESS_ERR_CLEAR (TXE + 0x000000000090) 1040#define SEND_EGRESS_ERR_INFO (TXE + 0x000000000F00) 1041#define SEND_EGRESS_ERR_INFO_BAD_PKT_LEN_ERR_SMASK 0x20000ull 1042#define SEND_EGRESS_ERR_INFO_BYPASS_ERR_SMASK 0x800ull 1043#define SEND_EGRESS_ERR_INFO_GRH_ERR_SMASK 0x400ull 1044#define SEND_EGRESS_ERR_INFO_JOB_KEY_ERR_SMASK 0x4ull 1045#define SEND_EGRESS_ERR_INFO_KDETH_PACKETS_ERR_SMASK 0x1000ull 1046#define SEND_EGRESS_ERR_INFO_NON_KDETH_PACKETS_ERR_SMASK 0x2000ull 1047#define SEND_EGRESS_ERR_INFO_OPCODE_ERR_SMASK 0x20ull 1048#define SEND_EGRESS_ERR_INFO_PARTITION_KEY_ERR_SMASK 0x8ull 1049#define SEND_EGRESS_ERR_INFO_PBC_STATIC_RATE_CONTROL_ERR_SMASK 0x100000ull 1050#define SEND_EGRESS_ERR_INFO_PBC_TEST_ERR_SMASK 0x10000ull 1051#define SEND_EGRESS_ERR_INFO_RAW_ERR_SMASK 0x100ull 1052#define SEND_EGRESS_ERR_INFO_RAW_IPV6_ERR_SMASK 0x200ull 1053#define SEND_EGRESS_ERR_INFO_SLID_ERR_SMASK 0x10ull 1054#define SEND_EGRESS_ERR_INFO_TOO_LONG_BYPASS_PACKETS_ERR_SMASK 0x80000ull 1055#define SEND_EGRESS_ERR_INFO_TOO_LONG_IB_PACKET_ERR_SMASK 0x40000ull 1056#define SEND_EGRESS_ERR_INFO_TOO_SMALL_BYPASS_PACKETS_ERR_SMASK 0x8000ull 1057#define SEND_EGRESS_ERR_INFO_TOO_SMALL_IB_PACKETS_ERR_SMASK 0x4000ull 1058#define SEND_EGRESS_ERR_INFO_VL_ERR_SMASK 0x2ull 1059#define SEND_EGRESS_ERR_INFO_VL_MAPPING_ERR_SMASK 0x40ull 1060#define SEND_EGRESS_ERR_MASK (TXE + 0x000000000088) 1061#define SEND_EGRESS_ERR_SOURCE (TXE + 0x000000000F08) 1062#define SEND_EGRESS_ERR_STATUS (TXE + 0x000000000080) 1063#define SEND_EGRESS_ERR_STATUS_TX_CONFIG_PARITY_ERR_SMASK 0x8000ull 1064#define SEND_EGRESS_ERR_STATUS_TX_CREDIT_OVERRUN_ERR_SMASK \ 1065 0x200000000000000ull 1066#define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_PARITY_ERR_SMASK \ 1067 0x20000000000ull 1068#define SEND_EGRESS_ERR_STATUS_TX_CREDIT_RETURN_VL_ERR_SMASK \ 1069 0x800000000000ull 1070#define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_COR_ERR_SMASK \ 1071 0x2000000000000000ull 1072#define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNC_ERR_SMASK \ 1073 0x200000000000ull 1074#define SEND_EGRESS_ERR_STATUS_TX_EGRESS_FIFO_UNDERRUN_OR_PARITY_ERR_SMASK \ 1075 0x8ull 1076#define SEND_EGRESS_ERR_STATUS_TX_HCRC_INSERTION_ERR_SMASK \ 1077 0x400000000000ull 1078#define SEND_EGRESS_ERR_STATUS_TX_ILLEGAL_VL_ERR_SMASK 0x1000ull 1079#define SEND_EGRESS_ERR_STATUS_TX_INCORRECT_LINK_STATE_ERR_SMASK 0x20ull 1080#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_CSR_PARITY_ERR_SMASK 0x2000ull 1081#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_COR_ERR_SMASK \ 1082 0x1000000000000ull 1083#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO0_UNC_OR_PARITY_ERR_SMASK \ 1084 0x100000000ull 1085#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_COR_ERR_SMASK \ 1086 0x2000000000000ull 1087#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO1_UNC_OR_PARITY_ERR_SMASK \ 1088 0x200000000ull 1089#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_COR_ERR_SMASK \ 1090 0x4000000000000ull 1091#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO2_UNC_OR_PARITY_ERR_SMASK \ 1092 0x400000000ull 1093#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_COR_ERR_SMASK \ 1094 0x8000000000000ull 1095#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO3_UNC_OR_PARITY_ERR_SMASK \ 1096 0x800000000ull 1097#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_COR_ERR_SMASK \ 1098 0x10000000000000ull 1099#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO4_UNC_OR_PARITY_ERR_SMASK \ 1100 0x1000000000ull 1101#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_COR_ERR_SMASK \ 1102 0x20000000000000ull 1103#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO5_UNC_OR_PARITY_ERR_SMASK \ 1104 0x2000000000ull 1105#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_COR_ERR_SMASK \ 1106 0x40000000000000ull 1107#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO6_UNC_OR_PARITY_ERR_SMASK \ 1108 0x4000000000ull 1109#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_COR_ERR_SMASK \ 1110 0x80000000000000ull 1111#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO7_UNC_OR_PARITY_ERR_SMASK \ 1112 0x8000000000ull 1113#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_COR_ERR_SMASK \ 1114 0x100000000000000ull 1115#define SEND_EGRESS_ERR_STATUS_TX_LAUNCH_FIFO8_UNC_OR_PARITY_ERR_SMASK \ 1116 0x10000000000ull 1117#define SEND_EGRESS_ERR_STATUS_TX_LINKDOWN_ERR_SMASK 0x10ull 1118#define SEND_EGRESS_ERR_STATUS_TX_PIO_LAUNCH_INTF_PARITY_ERR_SMASK 0x80ull 1119#define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_COR_ERR_SMASK 0x1ull 1120#define SEND_EGRESS_ERR_STATUS_TX_PKT_INTEGRITY_MEM_UNC_ERR_SMASK 0x2ull 1121#define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_COR_ERR_SMASK \ 1122 0x1000000000000000ull 1123#define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_CSR_UNC_ERR_SMASK \ 1124 0x8000000000000000ull 1125#define SEND_EGRESS_ERR_STATUS_TX_READ_PIO_MEMORY_UNC_ERR_SMASK \ 1126 0x100000000000ull 1127#define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_COR_ERR_SMASK \ 1128 0x800000000000000ull 1129#define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_CSR_UNC_ERR_SMASK \ 1130 0x4000000000000000ull 1131#define SEND_EGRESS_ERR_STATUS_TX_READ_SDMA_MEMORY_UNC_ERR_SMASK \ 1132 0x80000000000ull 1133#define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_COR_ERR_SMASK 0x400000000000000ull 1134#define SEND_EGRESS_ERR_STATUS_TX_SB_HDR_UNC_ERR_SMASK 0x40000000000ull 1135#define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_CSR_PARITY_ERR_SMASK 0x4000ull 1136#define SEND_EGRESS_ERR_STATUS_TX_SBRD_CTL_STATE_MACHINE_PARITY_ERR_SMASK \ 1137 0x800ull 1138#define SEND_EGRESS_ERR_STATUS_TX_SDMA0_DISALLOWED_PACKET_ERR_SMASK \ 1139 0x10000ull 1140#define SEND_EGRESS_ERR_STATUS_TX_SDMA10_DISALLOWED_PACKET_ERR_SMASK \ 1141 0x4000000ull 1142#define SEND_EGRESS_ERR_STATUS_TX_SDMA11_DISALLOWED_PACKET_ERR_SMASK \ 1143 0x8000000ull 1144#define SEND_EGRESS_ERR_STATUS_TX_SDMA12_DISALLOWED_PACKET_ERR_SMASK \ 1145 0x10000000ull 1146#define SEND_EGRESS_ERR_STATUS_TX_SDMA13_DISALLOWED_PACKET_ERR_SMASK \ 1147 0x20000000ull 1148#define SEND_EGRESS_ERR_STATUS_TX_SDMA14_DISALLOWED_PACKET_ERR_SMASK \ 1149 0x40000000ull 1150#define SEND_EGRESS_ERR_STATUS_TX_SDMA15_DISALLOWED_PACKET_ERR_SMASK \ 1151 0x80000000ull 1152#define SEND_EGRESS_ERR_STATUS_TX_SDMA1_DISALLOWED_PACKET_ERR_SMASK \ 1153 0x20000ull 1154#define SEND_EGRESS_ERR_STATUS_TX_SDMA2_DISALLOWED_PACKET_ERR_SMASK \ 1155 0x40000ull 1156#define SEND_EGRESS_ERR_STATUS_TX_SDMA3_DISALLOWED_PACKET_ERR_SMASK \ 1157 0x80000ull 1158#define SEND_EGRESS_ERR_STATUS_TX_SDMA4_DISALLOWED_PACKET_ERR_SMASK \ 1159 0x100000ull 1160#define SEND_EGRESS_ERR_STATUS_TX_SDMA5_DISALLOWED_PACKET_ERR_SMASK \ 1161 0x200000ull 1162#define SEND_EGRESS_ERR_STATUS_TX_SDMA6_DISALLOWED_PACKET_ERR_SMASK \ 1163 0x400000ull 1164#define SEND_EGRESS_ERR_STATUS_TX_SDMA7_DISALLOWED_PACKET_ERR_SMASK \ 1165 0x800000ull 1166#define SEND_EGRESS_ERR_STATUS_TX_SDMA8_DISALLOWED_PACKET_ERR_SMASK \ 1167 0x1000000ull 1168#define SEND_EGRESS_ERR_STATUS_TX_SDMA9_DISALLOWED_PACKET_ERR_SMASK \ 1169 0x2000000ull 1170#define SEND_EGRESS_ERR_STATUS_TX_SDMA_LAUNCH_INTF_PARITY_ERR_SMASK \ 1171 0x100ull 1172#define SEND_EGRESS_SEND_DMA_STATUS (TXE + 0x000000000E00) 1173#define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SHIFT 0 1174#define SEND_EGRESS_SEND_DMA_STATUS_SDMA_EGRESS_PACKET_OCCUPANCY_SMASK \ 1175 0x3FFFull 1176#define SEND_ERR_CLEAR (TXE + 0x0000000000F0) 1177#define SEND_ERR_MASK (TXE + 0x0000000000E8) 1178#define SEND_ERR_STATUS (TXE + 0x0000000000E0) 1179#define SEND_ERR_STATUS_SEND_CSR_PARITY_ERR_SMASK 0x1ull 1180#define SEND_ERR_STATUS_SEND_CSR_READ_BAD_ADDR_ERR_SMASK 0x2ull 1181#define SEND_ERR_STATUS_SEND_CSR_WRITE_BAD_ADDR_ERR_SMASK 0x4ull 1182#define SEND_HIGH_PRIORITY_LIMIT (TXE + 0x000000000030) 1183#define SEND_HIGH_PRIORITY_LIMIT_LIMIT_MASK 0x3FFFull 1184#define SEND_HIGH_PRIORITY_LIMIT_LIMIT_SHIFT 0 1185#define SEND_HIGH_PRIORITY_LIST (TXE + 0x000000000180) 1186#define SEND_LEN_CHECK0 (TXE + 0x0000000000D0) 1187#define SEND_LEN_CHECK0_LEN_VL0_MASK 0xFFFull 1188#define SEND_LEN_CHECK0_LEN_VL1_SHIFT 12 1189#define SEND_LEN_CHECK1 (TXE + 0x0000000000D8) 1190#define SEND_LEN_CHECK1_LEN_VL15_MASK 0xFFFull 1191#define SEND_LEN_CHECK1_LEN_VL15_SHIFT 48 1192#define SEND_LEN_CHECK1_LEN_VL4_MASK 0xFFFull 1193#define SEND_LEN_CHECK1_LEN_VL5_SHIFT 12 1194#define SEND_LOW_PRIORITY_LIST (TXE + 0x000000000100) 1195#define SEND_LOW_PRIORITY_LIST_VL_MASK 0x7ull 1196#define SEND_LOW_PRIORITY_LIST_VL_SHIFT 16 1197#define SEND_LOW_PRIORITY_LIST_WEIGHT_MASK 0xFFull 1198#define SEND_LOW_PRIORITY_LIST_WEIGHT_SHIFT 0 1199#define SEND_PIO_ERR_CLEAR (TXE + 0x000000000050) 1200#define SEND_PIO_ERR_CLEAR_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull 1201#define SEND_PIO_ERR_MASK (TXE + 0x000000000048) 1202#define SEND_PIO_ERR_STATUS (TXE + 0x000000000040) 1203#define SEND_PIO_ERR_STATUS_PIO_BLOCK_QW_COUNT_PARITY_ERR_SMASK \ 1204 0x1000000ull 1205#define SEND_PIO_ERR_STATUS_PIO_CREDIT_RET_FIFO_PARITY_ERR_SMASK 0x8000ull 1206#define SEND_PIO_ERR_STATUS_PIO_CSR_PARITY_ERR_SMASK 0x4ull 1207#define SEND_PIO_ERR_STATUS_PIO_CURRENT_FREE_CNT_PARITY_ERR_SMASK \ 1208 0x100000000ull 1209#define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_COR_ERR_SMASK 0x100000ull 1210#define SEND_PIO_ERR_STATUS_PIO_HOST_ADDR_MEM_UNC_ERR_SMASK 0x80000ull 1211#define SEND_PIO_ERR_STATUS_PIO_INIT_SM_IN_ERR_SMASK 0x20000ull 1212#define SEND_PIO_ERR_STATUS_PIO_LAST_RETURNED_CNT_PARITY_ERR_SMASK \ 1213 0x200000000ull 1214#define SEND_PIO_ERR_STATUS_PIO_PCC_FIFO_PARITY_ERR_SMASK 0x20ull 1215#define SEND_PIO_ERR_STATUS_PIO_PCC_SOP_HEAD_PARITY_ERR_SMASK \ 1216 0x400000000ull 1217#define SEND_PIO_ERR_STATUS_PIO_PEC_FIFO_PARITY_ERR_SMASK 0x40ull 1218#define SEND_PIO_ERR_STATUS_PIO_PEC_SOP_HEAD_PARITY_ERR_SMASK \ 1219 0x800000000ull 1220#define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_FIFO_PARITY_ERR_SMASK 0x200ull 1221#define SEND_PIO_ERR_STATUS_PIO_PKT_EVICT_SM_OR_ARB_SM_ERR_SMASK 0x40000ull 1222#define SEND_PIO_ERR_STATUS_PIO_PPMC_BQC_MEM_PARITY_ERR_SMASK 0x10000000ull 1223#define SEND_PIO_ERR_STATUS_PIO_PPMC_PBL_FIFO_ERR_SMASK 0x10000ull 1224#define SEND_PIO_ERR_STATUS_PIO_PPMC_SOP_LEN_ERR_SMASK 0x20000000ull 1225#define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO0_ERR_SMASK 0x8ull 1226#define SEND_PIO_ERR_STATUS_PIO_SB_MEM_FIFO1_ERR_SMASK 0x10ull 1227#define SEND_PIO_ERR_STATUS_PIO_SBRDCTL_CRREL_PARITY_ERR_SMASK 0x80ull 1228#define SEND_PIO_ERR_STATUS_PIO_SBRDCTRL_CRREL_FIFO_PARITY_ERR_SMASK \ 1229 0x100ull 1230#define SEND_PIO_ERR_STATUS_PIO_SM_PKT_RESET_PARITY_ERR_SMASK 0x400ull 1231#define SEND_PIO_ERR_STATUS_PIO_STATE_MACHINE_ERR_SMASK 0x400000ull 1232#define SEND_PIO_ERR_STATUS_PIO_VL_FIFO_PARITY_ERR_SMASK 0x8000000ull 1233#define SEND_PIO_ERR_STATUS_PIO_VLF_SOP_PARITY_ERR_SMASK 0x4000000ull 1234#define SEND_PIO_ERR_STATUS_PIO_VLF_VL_LEN_PARITY_ERR_SMASK 0x2000000ull 1235#define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_COR_ERR_SMASK 0x2000ull 1236#define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK0_UNC_ERR_SMASK 0x800ull 1237#define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_COR_ERR_SMASK 0x4000ull 1238#define SEND_PIO_ERR_STATUS_PIO_VL_LEN_MEM_BANK1_UNC_ERR_SMASK 0x1000ull 1239#define SEND_PIO_ERR_STATUS_PIO_WRITE_ADDR_PARITY_ERR_SMASK 0x2ull 1240#define SEND_PIO_ERR_STATUS_PIO_WRITE_BAD_CTXT_ERR_SMASK 0x1ull 1241#define SEND_PIO_ERR_STATUS_PIO_WRITE_DATA_PARITY_ERR_SMASK 0x200000ull 1242#define SEND_PIO_ERR_STATUS_PIO_WRITE_QW_VALID_PARITY_ERR_SMASK 0x800000ull 1243#define SEND_PIO_INIT_CTXT (TXE + 0x000000000038) 1244#define SEND_PIO_INIT_CTXT_PIO_ALL_CTXT_INIT_SMASK 0x1ull 1245#define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_MASK 0xFFull 1246#define SEND_PIO_INIT_CTXT_PIO_CTXT_NUM_SHIFT 8 1247#define SEND_PIO_INIT_CTXT_PIO_INIT_ERR_SMASK 0x8ull 1248#define SEND_PIO_INIT_CTXT_PIO_INIT_IN_PROGRESS_SMASK 0x4ull 1249#define SEND_PIO_INIT_CTXT_PIO_SINGLE_CTXT_INIT_SMASK 0x2ull 1250#define SEND_PIO_MEM_SIZE (TXE + 0x000000000020) 1251#define SEND_SC2VLT0 (TXE + 0x0000000000B0) 1252#define SEND_SC2VLT0_SC0_SHIFT 0 1253#define SEND_SC2VLT0_SC1_SHIFT 8 1254#define SEND_SC2VLT0_SC2_SHIFT 16 1255#define SEND_SC2VLT0_SC3_SHIFT 24 1256#define SEND_SC2VLT0_SC4_SHIFT 32 1257#define SEND_SC2VLT0_SC5_SHIFT 40 1258#define SEND_SC2VLT0_SC6_SHIFT 48 1259#define SEND_SC2VLT0_SC7_SHIFT 56 1260#define SEND_SC2VLT1 (TXE + 0x0000000000B8) 1261#define SEND_SC2VLT1_SC10_SHIFT 16 1262#define SEND_SC2VLT1_SC11_SHIFT 24 1263#define SEND_SC2VLT1_SC12_SHIFT 32 1264#define SEND_SC2VLT1_SC13_SHIFT 40 1265#define SEND_SC2VLT1_SC14_SHIFT 48 1266#define SEND_SC2VLT1_SC15_SHIFT 56 1267#define SEND_SC2VLT1_SC8_SHIFT 0 1268#define SEND_SC2VLT1_SC9_SHIFT 8 1269#define SEND_SC2VLT2 (TXE + 0x0000000000C0) 1270#define SEND_SC2VLT2_SC16_SHIFT 0 1271#define SEND_SC2VLT2_SC17_SHIFT 8 1272#define SEND_SC2VLT2_SC18_SHIFT 16 1273#define SEND_SC2VLT2_SC19_SHIFT 24 1274#define SEND_SC2VLT2_SC20_SHIFT 32 1275#define SEND_SC2VLT2_SC21_SHIFT 40 1276#define SEND_SC2VLT2_SC22_SHIFT 48 1277#define SEND_SC2VLT2_SC23_SHIFT 56 1278#define SEND_SC2VLT3 (TXE + 0x0000000000C8) 1279#define SEND_SC2VLT3_SC24_SHIFT 0 1280#define SEND_SC2VLT3_SC25_SHIFT 8 1281#define SEND_SC2VLT3_SC26_SHIFT 16 1282#define SEND_SC2VLT3_SC27_SHIFT 24 1283#define SEND_SC2VLT3_SC28_SHIFT 32 1284#define SEND_SC2VLT3_SC29_SHIFT 40 1285#define SEND_SC2VLT3_SC30_SHIFT 48 1286#define SEND_SC2VLT3_SC31_SHIFT 56 1287#define SEND_STATIC_RATE_CONTROL (TXE + 0x0000000000A8) 1288#define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SHIFT 0 1289#define SEND_STATIC_RATE_CONTROL_CSR_SRC_RELOAD_SMASK 0xFFFFull 1290#define PCIE_CFG_REG_PL2 (PCIE + 0x000000000708) 1291#define PCIE_CFG_REG_PL3 (PCIE + 0x00000000070C) 1292#define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SHIFT 27 1293#define PCIE_CFG_REG_PL3_L1_ENT_LATENCY_SMASK 0x38000000 1294#define PCIE_CFG_REG_PL102 (PCIE + 0x000000000898) 1295#define PCIE_CFG_REG_PL102_GEN3_EQ_POST_CURSOR_PSET_SHIFT 12 1296#define PCIE_CFG_REG_PL102_GEN3_EQ_CURSOR_PSET_SHIFT 6 1297#define PCIE_CFG_REG_PL102_GEN3_EQ_PRE_CURSOR_PSET_SHIFT 0 1298#define PCIE_CFG_REG_PL103 (PCIE + 0x00000000089C) 1299#define PCIE_CFG_REG_PL105 (PCIE + 0x0000000008A4) 1300#define PCIE_CFG_REG_PL105_GEN3_EQ_VIOLATE_COEF_RULES_SMASK 0x1ull 1301#define PCIE_CFG_REG_PL2_LOW_PWR_ENT_CNT_SHIFT 24 1302#define PCIE_CFG_REG_PL100 (PCIE + 0x000000000890) 1303#define PCIE_CFG_REG_PL100_EQ_EIEOS_CNT_SMASK 0x400ull 1304#define PCIE_CFG_REG_PL101 (PCIE + 0x000000000894) 1305#define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_FS_SHIFT 6 1306#define PCIE_CFG_REG_PL101_GEN3_EQ_LOCAL_LF_SHIFT 0 1307#define PCIE_CFG_REG_PL106 (PCIE + 0x0000000008A8) 1308#define PCIE_CFG_REG_PL106_GEN3_EQ_PSET_REQ_VEC_SHIFT 8 1309#define PCIE_CFG_REG_PL106_GEN3_EQ_EVAL2MS_DISABLE_SMASK 0x20ull 1310#define PCIE_CFG_REG_PL106_GEN3_EQ_PHASE23_EXIT_MODE_SMASK 0x10ull 1311#define CCE_INT_BLOCKED (CCE + 0x000000110C00) 1312#define SEND_DMA_IDLE_CNT (TXE + 0x000000200040) 1313#define SEND_DMA_DESC_FETCHED_CNT (TXE + 0x000000200058) 1314#define CCE_MSIX_PBA_OFFSET 0X0110000 1315 1316#endif /* DEF_CHIP_REG */ 1317