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20#include <linux/init.h>
21#include <linux/of.h>
22#include <linux/platform_device.h>
23#include <linux/spinlock.h>
24#include <linux/interrupt.h>
25#include <linux/ioport.h>
26#include <linux/io.h>
27#include <linux/irq.h>
28#include <linux/irqdomain.h>
29#include <linux/err.h>
30#include <linux/slab.h>
31#include <linux/module.h>
32#include <linux/of_device.h>
33#include <linux/pm_runtime.h>
34
35#define INTC_IRQPIN_MAX 8
36
37#define INTC_IRQPIN_REG_SENSE 0
38#define INTC_IRQPIN_REG_PRIO 1
39#define INTC_IRQPIN_REG_SOURCE 2
40#define INTC_IRQPIN_REG_MASK 3
41#define INTC_IRQPIN_REG_CLEAR 4
42#define INTC_IRQPIN_REG_NR_MANDATORY 5
43#define INTC_IRQPIN_REG_IRLM 5
44#define INTC_IRQPIN_REG_NR 6
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59struct intc_irqpin_iomem {
60 void __iomem *iomem;
61 unsigned long (*read)(void __iomem *iomem);
62 void (*write)(void __iomem *iomem, unsigned long data);
63 int width;
64};
65
66struct intc_irqpin_irq {
67 int hw_irq;
68 int requested_irq;
69 int domain_irq;
70 struct intc_irqpin_priv *p;
71};
72
73struct intc_irqpin_priv {
74 struct intc_irqpin_iomem iomem[INTC_IRQPIN_REG_NR];
75 struct intc_irqpin_irq irq[INTC_IRQPIN_MAX];
76 unsigned int sense_bitfield_width;
77 struct platform_device *pdev;
78 struct irq_chip irq_chip;
79 struct irq_domain *irq_domain;
80 atomic_t wakeup_path;
81 unsigned shared_irqs:1;
82 u8 shared_irq_mask;
83};
84
85struct intc_irqpin_config {
86 unsigned int irlm_bit;
87 unsigned needs_irlm:1;
88};
89
90static unsigned long intc_irqpin_read32(void __iomem *iomem)
91{
92 return ioread32(iomem);
93}
94
95static unsigned long intc_irqpin_read8(void __iomem *iomem)
96{
97 return ioread8(iomem);
98}
99
100static void intc_irqpin_write32(void __iomem *iomem, unsigned long data)
101{
102 iowrite32(data, iomem);
103}
104
105static void intc_irqpin_write8(void __iomem *iomem, unsigned long data)
106{
107 iowrite8(data, iomem);
108}
109
110static inline unsigned long intc_irqpin_read(struct intc_irqpin_priv *p,
111 int reg)
112{
113 struct intc_irqpin_iomem *i = &p->iomem[reg];
114
115 return i->read(i->iomem);
116}
117
118static inline void intc_irqpin_write(struct intc_irqpin_priv *p,
119 int reg, unsigned long data)
120{
121 struct intc_irqpin_iomem *i = &p->iomem[reg];
122
123 i->write(i->iomem, data);
124}
125
126static inline unsigned long intc_irqpin_hwirq_mask(struct intc_irqpin_priv *p,
127 int reg, int hw_irq)
128{
129 return BIT((p->iomem[reg].width - 1) - hw_irq);
130}
131
132static inline void intc_irqpin_irq_write_hwirq(struct intc_irqpin_priv *p,
133 int reg, int hw_irq)
134{
135 intc_irqpin_write(p, reg, intc_irqpin_hwirq_mask(p, reg, hw_irq));
136}
137
138static DEFINE_RAW_SPINLOCK(intc_irqpin_lock);
139
140static void intc_irqpin_read_modify_write(struct intc_irqpin_priv *p,
141 int reg, int shift,
142 int width, int value)
143{
144 unsigned long flags;
145 unsigned long tmp;
146
147 raw_spin_lock_irqsave(&intc_irqpin_lock, flags);
148
149 tmp = intc_irqpin_read(p, reg);
150 tmp &= ~(((1 << width) - 1) << shift);
151 tmp |= value << shift;
152 intc_irqpin_write(p, reg, tmp);
153
154 raw_spin_unlock_irqrestore(&intc_irqpin_lock, flags);
155}
156
157static void intc_irqpin_mask_unmask_prio(struct intc_irqpin_priv *p,
158 int irq, int do_mask)
159{
160
161 int bitfield_width = 4;
162 int shift = 32 - (irq + 1) * bitfield_width;
163
164 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_PRIO,
165 shift, bitfield_width,
166 do_mask ? 0 : (1 << bitfield_width) - 1);
167}
168
169static int intc_irqpin_set_sense(struct intc_irqpin_priv *p, int irq, int value)
170{
171
172 int bitfield_width = p->sense_bitfield_width;
173 int shift = 32 - (irq + 1) * bitfield_width;
174
175 dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);
176
177 if (value >= (1 << bitfield_width))
178 return -EINVAL;
179
180 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_SENSE, shift,
181 bitfield_width, value);
182 return 0;
183}
184
185static void intc_irqpin_dbg(struct intc_irqpin_irq *i, char *str)
186{
187 dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",
188 str, i->requested_irq, i->hw_irq, i->domain_irq);
189}
190
191static void intc_irqpin_irq_enable(struct irq_data *d)
192{
193 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
194 int hw_irq = irqd_to_hwirq(d);
195
196 intc_irqpin_dbg(&p->irq[hw_irq], "enable");
197 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
198}
199
200static void intc_irqpin_irq_disable(struct irq_data *d)
201{
202 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
203 int hw_irq = irqd_to_hwirq(d);
204
205 intc_irqpin_dbg(&p->irq[hw_irq], "disable");
206 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
207}
208
209static void intc_irqpin_shared_irq_enable(struct irq_data *d)
210{
211 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
212 int hw_irq = irqd_to_hwirq(d);
213
214 intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");
215 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_CLEAR, hw_irq);
216
217 p->shared_irq_mask &= ~BIT(hw_irq);
218}
219
220static void intc_irqpin_shared_irq_disable(struct irq_data *d)
221{
222 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
223 int hw_irq = irqd_to_hwirq(d);
224
225 intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");
226 intc_irqpin_irq_write_hwirq(p, INTC_IRQPIN_REG_MASK, hw_irq);
227
228 p->shared_irq_mask |= BIT(hw_irq);
229}
230
231static void intc_irqpin_irq_enable_force(struct irq_data *d)
232{
233 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
234 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
235
236 intc_irqpin_irq_enable(d);
237
238
239
240
241
242 irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));
243}
244
245static void intc_irqpin_irq_disable_force(struct irq_data *d)
246{
247 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
248 int irq = p->irq[irqd_to_hwirq(d)].requested_irq;
249
250
251
252
253
254 irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));
255 intc_irqpin_irq_disable(d);
256}
257
258#define INTC_IRQ_SENSE_VALID 0x10
259#define INTC_IRQ_SENSE(x) (x + INTC_IRQ_SENSE_VALID)
260
261static unsigned char intc_irqpin_sense[IRQ_TYPE_SENSE_MASK + 1] = {
262 [IRQ_TYPE_EDGE_FALLING] = INTC_IRQ_SENSE(0x00),
263 [IRQ_TYPE_EDGE_RISING] = INTC_IRQ_SENSE(0x01),
264 [IRQ_TYPE_LEVEL_LOW] = INTC_IRQ_SENSE(0x02),
265 [IRQ_TYPE_LEVEL_HIGH] = INTC_IRQ_SENSE(0x03),
266 [IRQ_TYPE_EDGE_BOTH] = INTC_IRQ_SENSE(0x04),
267};
268
269static int intc_irqpin_irq_set_type(struct irq_data *d, unsigned int type)
270{
271 unsigned char value = intc_irqpin_sense[type & IRQ_TYPE_SENSE_MASK];
272 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
273
274 if (!(value & INTC_IRQ_SENSE_VALID))
275 return -EINVAL;
276
277 return intc_irqpin_set_sense(p, irqd_to_hwirq(d),
278 value ^ INTC_IRQ_SENSE_VALID);
279}
280
281static int intc_irqpin_irq_set_wake(struct irq_data *d, unsigned int on)
282{
283 struct intc_irqpin_priv *p = irq_data_get_irq_chip_data(d);
284 int hw_irq = irqd_to_hwirq(d);
285
286 irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);
287 if (on)
288 atomic_inc(&p->wakeup_path);
289 else
290 atomic_dec(&p->wakeup_path);
291
292 return 0;
293}
294
295static irqreturn_t intc_irqpin_irq_handler(int irq, void *dev_id)
296{
297 struct intc_irqpin_irq *i = dev_id;
298 struct intc_irqpin_priv *p = i->p;
299 unsigned long bit;
300
301 intc_irqpin_dbg(i, "demux1");
302 bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);
303
304 if (intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE) & bit) {
305 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, ~bit);
306 intc_irqpin_dbg(i, "demux2");
307 generic_handle_irq(i->domain_irq);
308 return IRQ_HANDLED;
309 }
310 return IRQ_NONE;
311}
312
313static irqreturn_t intc_irqpin_shared_irq_handler(int irq, void *dev_id)
314{
315 struct intc_irqpin_priv *p = dev_id;
316 unsigned int reg_source = intc_irqpin_read(p, INTC_IRQPIN_REG_SOURCE);
317 irqreturn_t status = IRQ_NONE;
318 int k;
319
320 for (k = 0; k < 8; k++) {
321 if (reg_source & BIT(7 - k)) {
322 if (BIT(k) & p->shared_irq_mask)
323 continue;
324
325 status |= intc_irqpin_irq_handler(irq, &p->irq[k]);
326 }
327 }
328
329 return status;
330}
331
332
333
334
335
336static struct lock_class_key intc_irqpin_irq_lock_class;
337
338
339static struct lock_class_key intc_irqpin_irq_request_class;
340
341static int intc_irqpin_irq_domain_map(struct irq_domain *h, unsigned int virq,
342 irq_hw_number_t hw)
343{
344 struct intc_irqpin_priv *p = h->host_data;
345
346 p->irq[hw].domain_irq = virq;
347 p->irq[hw].hw_irq = hw;
348
349 intc_irqpin_dbg(&p->irq[hw], "map");
350 irq_set_chip_data(virq, h->host_data);
351 irq_set_lockdep_class(virq, &intc_irqpin_irq_lock_class,
352 &intc_irqpin_irq_request_class);
353 irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);
354 return 0;
355}
356
357static const struct irq_domain_ops intc_irqpin_irq_domain_ops = {
358 .map = intc_irqpin_irq_domain_map,
359 .xlate = irq_domain_xlate_twocell,
360};
361
362static const struct intc_irqpin_config intc_irqpin_irlm_r8a777x = {
363 .irlm_bit = 23,
364 .needs_irlm = 1,
365};
366
367static const struct intc_irqpin_config intc_irqpin_rmobile = {
368 .needs_irlm = 0,
369};
370
371static const struct of_device_id intc_irqpin_dt_ids[] = {
372 { .compatible = "renesas,intc-irqpin", },
373 { .compatible = "renesas,intc-irqpin-r8a7778",
374 .data = &intc_irqpin_irlm_r8a777x },
375 { .compatible = "renesas,intc-irqpin-r8a7779",
376 .data = &intc_irqpin_irlm_r8a777x },
377 { .compatible = "renesas,intc-irqpin-r8a7740",
378 .data = &intc_irqpin_rmobile },
379 { .compatible = "renesas,intc-irqpin-sh73a0",
380 .data = &intc_irqpin_rmobile },
381 {},
382};
383MODULE_DEVICE_TABLE(of, intc_irqpin_dt_ids);
384
385static int intc_irqpin_probe(struct platform_device *pdev)
386{
387 const struct intc_irqpin_config *config;
388 struct device *dev = &pdev->dev;
389 struct intc_irqpin_priv *p;
390 struct intc_irqpin_iomem *i;
391 struct resource *io[INTC_IRQPIN_REG_NR];
392 struct resource *irq;
393 struct irq_chip *irq_chip;
394 void (*enable_fn)(struct irq_data *d);
395 void (*disable_fn)(struct irq_data *d);
396 const char *name = dev_name(dev);
397 bool control_parent;
398 unsigned int nirqs;
399 int ref_irq;
400 int ret;
401 int k;
402
403 p = devm_kzalloc(dev, sizeof(*p), GFP_KERNEL);
404 if (!p) {
405 dev_err(dev, "failed to allocate driver data\n");
406 return -ENOMEM;
407 }
408
409
410 of_property_read_u32(dev->of_node, "sense-bitfield-width",
411 &p->sense_bitfield_width);
412 control_parent = of_property_read_bool(dev->of_node, "control-parent");
413 if (!p->sense_bitfield_width)
414 p->sense_bitfield_width = 4;
415
416 p->pdev = pdev;
417 platform_set_drvdata(pdev, p);
418
419 config = of_device_get_match_data(dev);
420
421 pm_runtime_enable(dev);
422 pm_runtime_get_sync(dev);
423
424
425 memset(io, 0, sizeof(io));
426 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
427 io[k] = platform_get_resource(pdev, IORESOURCE_MEM, k);
428 if (!io[k] && k < INTC_IRQPIN_REG_NR_MANDATORY) {
429 dev_err(dev, "not enough IOMEM resources\n");
430 ret = -EINVAL;
431 goto err0;
432 }
433 }
434
435
436 for (k = 0; k < INTC_IRQPIN_MAX; k++) {
437 irq = platform_get_resource(pdev, IORESOURCE_IRQ, k);
438 if (!irq)
439 break;
440
441 p->irq[k].p = p;
442 p->irq[k].requested_irq = irq->start;
443 }
444
445 nirqs = k;
446 if (nirqs < 1) {
447 dev_err(dev, "not enough IRQ resources\n");
448 ret = -EINVAL;
449 goto err0;
450 }
451
452
453 for (k = 0; k < INTC_IRQPIN_REG_NR; k++) {
454 i = &p->iomem[k];
455
456
457 if (!io[k])
458 continue;
459
460 switch (resource_size(io[k])) {
461 case 1:
462 i->width = 8;
463 i->read = intc_irqpin_read8;
464 i->write = intc_irqpin_write8;
465 break;
466 case 4:
467 i->width = 32;
468 i->read = intc_irqpin_read32;
469 i->write = intc_irqpin_write32;
470 break;
471 default:
472 dev_err(dev, "IOMEM size mismatch\n");
473 ret = -EINVAL;
474 goto err0;
475 }
476
477 i->iomem = devm_ioremap_nocache(dev, io[k]->start,
478 resource_size(io[k]));
479 if (!i->iomem) {
480 dev_err(dev, "failed to remap IOMEM\n");
481 ret = -ENXIO;
482 goto err0;
483 }
484 }
485
486
487 if (config && config->needs_irlm) {
488 if (io[INTC_IRQPIN_REG_IRLM])
489 intc_irqpin_read_modify_write(p, INTC_IRQPIN_REG_IRLM,
490 config->irlm_bit, 1, 1);
491 else
492 dev_warn(dev, "unable to select IRLM mode\n");
493 }
494
495
496 for (k = 0; k < nirqs; k++)
497 intc_irqpin_mask_unmask_prio(p, k, 1);
498
499
500 intc_irqpin_write(p, INTC_IRQPIN_REG_SOURCE, 0x0);
501
502
503 ref_irq = p->irq[0].requested_irq;
504 p->shared_irqs = 1;
505 for (k = 1; k < nirqs; k++) {
506 if (ref_irq != p->irq[k].requested_irq) {
507 p->shared_irqs = 0;
508 break;
509 }
510 }
511
512
513 if (control_parent) {
514 enable_fn = intc_irqpin_irq_enable_force;
515 disable_fn = intc_irqpin_irq_disable_force;
516 } else if (!p->shared_irqs) {
517 enable_fn = intc_irqpin_irq_enable;
518 disable_fn = intc_irqpin_irq_disable;
519 } else {
520 enable_fn = intc_irqpin_shared_irq_enable;
521 disable_fn = intc_irqpin_shared_irq_disable;
522 }
523
524 irq_chip = &p->irq_chip;
525 irq_chip->name = name;
526 irq_chip->irq_mask = disable_fn;
527 irq_chip->irq_unmask = enable_fn;
528 irq_chip->irq_set_type = intc_irqpin_irq_set_type;
529 irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;
530 irq_chip->flags = IRQCHIP_MASK_ON_SUSPEND;
531
532 p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,
533 &intc_irqpin_irq_domain_ops, p);
534 if (!p->irq_domain) {
535 ret = -ENXIO;
536 dev_err(dev, "cannot initialize irq domain\n");
537 goto err0;
538 }
539
540 if (p->shared_irqs) {
541
542 if (devm_request_irq(dev, p->irq[0].requested_irq,
543 intc_irqpin_shared_irq_handler,
544 IRQF_SHARED, name, p)) {
545 dev_err(dev, "failed to request low IRQ\n");
546 ret = -ENOENT;
547 goto err1;
548 }
549 } else {
550
551 for (k = 0; k < nirqs; k++) {
552 if (devm_request_irq(dev, p->irq[k].requested_irq,
553 intc_irqpin_irq_handler, 0, name,
554 &p->irq[k])) {
555 dev_err(dev, "failed to request low IRQ\n");
556 ret = -ENOENT;
557 goto err1;
558 }
559 }
560 }
561
562
563 for (k = 0; k < nirqs; k++)
564 intc_irqpin_mask_unmask_prio(p, k, 0);
565
566 dev_info(dev, "driving %d irqs\n", nirqs);
567
568 return 0;
569
570err1:
571 irq_domain_remove(p->irq_domain);
572err0:
573 pm_runtime_put(dev);
574 pm_runtime_disable(dev);
575 return ret;
576}
577
578static int intc_irqpin_remove(struct platform_device *pdev)
579{
580 struct intc_irqpin_priv *p = platform_get_drvdata(pdev);
581
582 irq_domain_remove(p->irq_domain);
583 pm_runtime_put(&pdev->dev);
584 pm_runtime_disable(&pdev->dev);
585 return 0;
586}
587
588static int __maybe_unused intc_irqpin_suspend(struct device *dev)
589{
590 struct intc_irqpin_priv *p = dev_get_drvdata(dev);
591
592 if (atomic_read(&p->wakeup_path))
593 device_set_wakeup_path(dev);
594
595 return 0;
596}
597
598static SIMPLE_DEV_PM_OPS(intc_irqpin_pm_ops, intc_irqpin_suspend, NULL);
599
600static struct platform_driver intc_irqpin_device_driver = {
601 .probe = intc_irqpin_probe,
602 .remove = intc_irqpin_remove,
603 .driver = {
604 .name = "renesas_intc_irqpin",
605 .of_match_table = intc_irqpin_dt_ids,
606 .pm = &intc_irqpin_pm_ops,
607 }
608};
609
610static int __init intc_irqpin_init(void)
611{
612 return platform_driver_register(&intc_irqpin_device_driver);
613}
614postcore_initcall(intc_irqpin_init);
615
616static void __exit intc_irqpin_exit(void)
617{
618 platform_driver_unregister(&intc_irqpin_device_driver);
619}
620module_exit(intc_irqpin_exit);
621
622MODULE_AUTHOR("Magnus Damm");
623MODULE_DESCRIPTION("Renesas INTC External IRQ Pin Driver");
624MODULE_LICENSE("GPL v2");
625