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8#include <linux/bitops.h>
9#include <linux/interrupt.h>
10#include <linux/io.h>
11#include <linux/irq.h>
12#include <linux/irqchip.h>
13#include <linux/irqchip/chained_irq.h>
14#include <linux/irqdomain.h>
15#include <linux/of_address.h>
16#include <linux/of_irq.h>
17
18#define IRQS_PER_BANK 32
19
20struct stm32_exti_bank {
21 u32 imr_ofst;
22 u32 emr_ofst;
23 u32 rtsr_ofst;
24 u32 ftsr_ofst;
25 u32 swier_ofst;
26 u32 pr_ofst;
27};
28
29static const struct stm32_exti_bank stm32f4xx_exti_b1 = {
30 .imr_ofst = 0x00,
31 .emr_ofst = 0x04,
32 .rtsr_ofst = 0x08,
33 .ftsr_ofst = 0x0C,
34 .swier_ofst = 0x10,
35 .pr_ofst = 0x14,
36};
37
38static const struct stm32_exti_bank *stm32f4xx_exti_banks[] = {
39 &stm32f4xx_exti_b1,
40};
41
42static const struct stm32_exti_bank stm32h7xx_exti_b1 = {
43 .imr_ofst = 0x80,
44 .emr_ofst = 0x84,
45 .rtsr_ofst = 0x00,
46 .ftsr_ofst = 0x04,
47 .swier_ofst = 0x08,
48 .pr_ofst = 0x88,
49};
50
51static const struct stm32_exti_bank stm32h7xx_exti_b2 = {
52 .imr_ofst = 0x90,
53 .emr_ofst = 0x94,
54 .rtsr_ofst = 0x20,
55 .ftsr_ofst = 0x24,
56 .swier_ofst = 0x28,
57 .pr_ofst = 0x98,
58};
59
60static const struct stm32_exti_bank stm32h7xx_exti_b3 = {
61 .imr_ofst = 0xA0,
62 .emr_ofst = 0xA4,
63 .rtsr_ofst = 0x40,
64 .ftsr_ofst = 0x44,
65 .swier_ofst = 0x48,
66 .pr_ofst = 0xA8,
67};
68
69static const struct stm32_exti_bank *stm32h7xx_exti_banks[] = {
70 &stm32h7xx_exti_b1,
71 &stm32h7xx_exti_b2,
72 &stm32h7xx_exti_b3,
73};
74
75static unsigned long stm32_exti_pending(struct irq_chip_generic *gc)
76{
77 const struct stm32_exti_bank *stm32_bank = gc->private;
78
79 return irq_reg_readl(gc, stm32_bank->pr_ofst);
80}
81
82static void stm32_exti_irq_ack(struct irq_chip_generic *gc, u32 mask)
83{
84 const struct stm32_exti_bank *stm32_bank = gc->private;
85
86 irq_reg_writel(gc, mask, stm32_bank->pr_ofst);
87}
88
89static void stm32_irq_handler(struct irq_desc *desc)
90{
91 struct irq_domain *domain = irq_desc_get_handler_data(desc);
92 struct irq_chip *chip = irq_desc_get_chip(desc);
93 unsigned int virq, nbanks = domain->gc->num_chips;
94 struct irq_chip_generic *gc;
95 const struct stm32_exti_bank *stm32_bank;
96 unsigned long pending;
97 int n, i, irq_base = 0;
98
99 chained_irq_enter(chip, desc);
100
101 for (i = 0; i < nbanks; i++, irq_base += IRQS_PER_BANK) {
102 gc = irq_get_domain_generic_chip(domain, irq_base);
103 stm32_bank = gc->private;
104
105 while ((pending = stm32_exti_pending(gc))) {
106 for_each_set_bit(n, &pending, IRQS_PER_BANK) {
107 virq = irq_find_mapping(domain, irq_base + n);
108 generic_handle_irq(virq);
109 stm32_exti_irq_ack(gc, BIT(n));
110 }
111 }
112 }
113
114 chained_irq_exit(chip, desc);
115}
116
117static int stm32_irq_set_type(struct irq_data *data, unsigned int type)
118{
119 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
120 const struct stm32_exti_bank *stm32_bank = gc->private;
121 int pin = data->hwirq % IRQS_PER_BANK;
122 u32 rtsr, ftsr;
123
124 irq_gc_lock(gc);
125
126 rtsr = irq_reg_readl(gc, stm32_bank->rtsr_ofst);
127 ftsr = irq_reg_readl(gc, stm32_bank->ftsr_ofst);
128
129 switch (type) {
130 case IRQ_TYPE_EDGE_RISING:
131 rtsr |= BIT(pin);
132 ftsr &= ~BIT(pin);
133 break;
134 case IRQ_TYPE_EDGE_FALLING:
135 rtsr &= ~BIT(pin);
136 ftsr |= BIT(pin);
137 break;
138 case IRQ_TYPE_EDGE_BOTH:
139 rtsr |= BIT(pin);
140 ftsr |= BIT(pin);
141 break;
142 default:
143 irq_gc_unlock(gc);
144 return -EINVAL;
145 }
146
147 irq_reg_writel(gc, rtsr, stm32_bank->rtsr_ofst);
148 irq_reg_writel(gc, ftsr, stm32_bank->ftsr_ofst);
149
150 irq_gc_unlock(gc);
151
152 return 0;
153}
154
155static int stm32_irq_set_wake(struct irq_data *data, unsigned int on)
156{
157 struct irq_chip_generic *gc = irq_data_get_irq_chip_data(data);
158 const struct stm32_exti_bank *stm32_bank = gc->private;
159 int pin = data->hwirq % IRQS_PER_BANK;
160 u32 imr;
161
162 irq_gc_lock(gc);
163
164 imr = irq_reg_readl(gc, stm32_bank->imr_ofst);
165 if (on)
166 imr |= BIT(pin);
167 else
168 imr &= ~BIT(pin);
169 irq_reg_writel(gc, imr, stm32_bank->imr_ofst);
170
171 irq_gc_unlock(gc);
172
173 return 0;
174}
175
176static int stm32_exti_alloc(struct irq_domain *d, unsigned int virq,
177 unsigned int nr_irqs, void *data)
178{
179 struct irq_chip_generic *gc;
180 struct irq_fwspec *fwspec = data;
181 irq_hw_number_t hwirq;
182
183 hwirq = fwspec->param[0];
184 gc = irq_get_domain_generic_chip(d, hwirq);
185
186 irq_map_generic_chip(d, virq, hwirq);
187 irq_domain_set_info(d, virq, hwirq, &gc->chip_types->chip, gc,
188 handle_simple_irq, NULL, NULL);
189
190 return 0;
191}
192
193static void stm32_exti_free(struct irq_domain *d, unsigned int virq,
194 unsigned int nr_irqs)
195{
196 struct irq_data *data = irq_domain_get_irq_data(d, virq);
197
198 irq_domain_reset_irq_data(data);
199}
200
201struct irq_domain_ops irq_exti_domain_ops = {
202 .map = irq_map_generic_chip,
203 .xlate = irq_domain_xlate_onetwocell,
204 .alloc = stm32_exti_alloc,
205 .free = stm32_exti_free,
206};
207
208static int
209__init stm32_exti_init(const struct stm32_exti_bank **stm32_exti_banks,
210 int bank_nr, struct device_node *node)
211{
212 unsigned int clr = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
213 int nr_irqs, nr_exti, ret, i;
214 struct irq_chip_generic *gc;
215 struct irq_domain *domain;
216 void *base;
217
218 base = of_iomap(node, 0);
219 if (!base) {
220 pr_err("%pOF: Unable to map registers\n", node);
221 return -ENOMEM;
222 }
223
224 domain = irq_domain_add_linear(node, bank_nr * IRQS_PER_BANK,
225 &irq_exti_domain_ops, NULL);
226 if (!domain) {
227 pr_err("%s: Could not register interrupt domain.\n",
228 node->name);
229 ret = -ENOMEM;
230 goto out_unmap;
231 }
232
233 ret = irq_alloc_domain_generic_chips(domain, IRQS_PER_BANK, 1, "exti",
234 handle_edge_irq, clr, 0, 0);
235 if (ret) {
236 pr_err("%pOF: Could not allocate generic interrupt chip.\n",
237 node);
238 goto out_free_domain;
239 }
240
241 for (i = 0; i < bank_nr; i++) {
242 const struct stm32_exti_bank *stm32_bank = stm32_exti_banks[i];
243 u32 irqs_mask;
244
245 gc = irq_get_domain_generic_chip(domain, i * IRQS_PER_BANK);
246
247 gc->reg_base = base;
248 gc->chip_types->type = IRQ_TYPE_EDGE_BOTH;
249 gc->chip_types->chip.irq_ack = irq_gc_ack_set_bit;
250 gc->chip_types->chip.irq_mask = irq_gc_mask_clr_bit;
251 gc->chip_types->chip.irq_unmask = irq_gc_mask_set_bit;
252 gc->chip_types->chip.irq_set_type = stm32_irq_set_type;
253 gc->chip_types->chip.irq_set_wake = stm32_irq_set_wake;
254 gc->chip_types->regs.ack = stm32_bank->pr_ofst;
255 gc->chip_types->regs.mask = stm32_bank->imr_ofst;
256 gc->private = (void *)stm32_bank;
257
258
259 writel_relaxed(~0UL, base + stm32_bank->rtsr_ofst);
260 irqs_mask = readl_relaxed(base + stm32_bank->rtsr_ofst);
261 nr_exti = fls(readl_relaxed(base + stm32_bank->rtsr_ofst));
262
263
264
265
266
267 writel_relaxed(0, base + stm32_bank->imr_ofst);
268 writel_relaxed(0, base + stm32_bank->emr_ofst);
269 writel_relaxed(0, base + stm32_bank->rtsr_ofst);
270 writel_relaxed(0, base + stm32_bank->ftsr_ofst);
271 writel_relaxed(~0UL, base + stm32_bank->pr_ofst);
272
273 pr_info("%s: bank%d, External IRQs available:%#x\n",
274 node->full_name, i, irqs_mask);
275 }
276
277 nr_irqs = of_irq_count(node);
278 for (i = 0; i < nr_irqs; i++) {
279 unsigned int irq = irq_of_parse_and_map(node, i);
280
281 irq_set_handler_data(irq, domain);
282 irq_set_chained_handler(irq, stm32_irq_handler);
283 }
284
285 return 0;
286
287out_free_domain:
288 irq_domain_remove(domain);
289out_unmap:
290 iounmap(base);
291 return ret;
292}
293
294static int __init stm32f4_exti_of_init(struct device_node *np,
295 struct device_node *parent)
296{
297 return stm32_exti_init(stm32f4xx_exti_banks,
298 ARRAY_SIZE(stm32f4xx_exti_banks), np);
299}
300
301IRQCHIP_DECLARE(stm32f4_exti, "st,stm32-exti", stm32f4_exti_of_init);
302
303static int __init stm32h7_exti_of_init(struct device_node *np,
304 struct device_node *parent)
305{
306 return stm32_exti_init(stm32h7xx_exti_banks,
307 ARRAY_SIZE(stm32h7xx_exti_banks), np);
308}
309
310IRQCHIP_DECLARE(stm32h7_exti, "st,stm32h7-exti", stm32h7_exti_of_init);
311
