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26#include <linux/kernel.h>
27#include <linux/module.h>
28#include <linux/platform_device.h>
29#include <linux/err.h>
30#include <linux/clk.h>
31#include <linux/io.h>
32#include <linux/mtd/rawnand.h>
33#include <linux/mtd/partitions.h>
34#include <linux/slab.h>
35#include <linux/of_device.h>
36#include <linux/of.h>
37
38#include <linux/platform_data/mtd-davinci.h>
39#include <linux/platform_data/mtd-davinci-aemif.h>
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54struct davinci_nand_info {
55 struct nand_chip chip;
56
57 struct device *dev;
58 struct clk *clk;
59
60 bool is_readmode;
61
62 void __iomem *base;
63 void __iomem *vaddr;
64
65 uint32_t ioaddr;
66 uint32_t current_cs;
67
68 uint32_t mask_chipsel;
69 uint32_t mask_ale;
70 uint32_t mask_cle;
71
72 uint32_t core_chipsel;
73
74 struct davinci_aemif_timing *timing;
75};
76
77static DEFINE_SPINLOCK(davinci_nand_lock);
78static bool ecc4_busy;
79
80static inline struct davinci_nand_info *to_davinci_nand(struct mtd_info *mtd)
81{
82 return container_of(mtd_to_nand(mtd), struct davinci_nand_info, chip);
83}
84
85static inline unsigned int davinci_nand_readl(struct davinci_nand_info *info,
86 int offset)
87{
88 return __raw_readl(info->base + offset);
89}
90
91static inline void davinci_nand_writel(struct davinci_nand_info *info,
92 int offset, unsigned long value)
93{
94 __raw_writel(value, info->base + offset);
95}
96
97
98
99
100
101
102
103static void nand_davinci_hwcontrol(struct mtd_info *mtd, int cmd,
104 unsigned int ctrl)
105{
106 struct davinci_nand_info *info = to_davinci_nand(mtd);
107 uint32_t addr = info->current_cs;
108 struct nand_chip *nand = mtd_to_nand(mtd);
109
110
111 if (ctrl & NAND_CTRL_CHANGE) {
112 if ((ctrl & NAND_CTRL_CLE) == NAND_CTRL_CLE)
113 addr |= info->mask_cle;
114 else if ((ctrl & NAND_CTRL_ALE) == NAND_CTRL_ALE)
115 addr |= info->mask_ale;
116
117 nand->IO_ADDR_W = (void __iomem __force *)addr;
118 }
119
120 if (cmd != NAND_CMD_NONE)
121 iowrite8(cmd, nand->IO_ADDR_W);
122}
123
124static void nand_davinci_select_chip(struct mtd_info *mtd, int chip)
125{
126 struct davinci_nand_info *info = to_davinci_nand(mtd);
127 uint32_t addr = info->ioaddr;
128
129
130 if (chip > 0)
131 addr |= info->mask_chipsel;
132 info->current_cs = addr;
133
134 info->chip.IO_ADDR_W = (void __iomem __force *)addr;
135 info->chip.IO_ADDR_R = info->chip.IO_ADDR_W;
136}
137
138
139
140
141
142
143
144static inline uint32_t nand_davinci_readecc_1bit(struct mtd_info *mtd)
145{
146 struct davinci_nand_info *info = to_davinci_nand(mtd);
147
148 return davinci_nand_readl(info, NANDF1ECC_OFFSET
149 + 4 * info->core_chipsel);
150}
151
152static void nand_davinci_hwctl_1bit(struct mtd_info *mtd, int mode)
153{
154 struct davinci_nand_info *info;
155 uint32_t nandcfr;
156 unsigned long flags;
157
158 info = to_davinci_nand(mtd);
159
160
161 nand_davinci_readecc_1bit(mtd);
162
163 spin_lock_irqsave(&davinci_nand_lock, flags);
164
165
166 nandcfr = davinci_nand_readl(info, NANDFCR_OFFSET);
167 nandcfr |= BIT(8 + info->core_chipsel);
168 davinci_nand_writel(info, NANDFCR_OFFSET, nandcfr);
169
170 spin_unlock_irqrestore(&davinci_nand_lock, flags);
171}
172
173
174
175
176static int nand_davinci_calculate_1bit(struct mtd_info *mtd,
177 const u_char *dat, u_char *ecc_code)
178{
179 unsigned int ecc_val = nand_davinci_readecc_1bit(mtd);
180 unsigned int ecc24 = (ecc_val & 0x0fff) | ((ecc_val & 0x0fff0000) >> 4);
181
182
183 ecc24 = ~ecc24;
184 ecc_code[0] = (u_char)(ecc24);
185 ecc_code[1] = (u_char)(ecc24 >> 8);
186 ecc_code[2] = (u_char)(ecc24 >> 16);
187
188 return 0;
189}
190
191static int nand_davinci_correct_1bit(struct mtd_info *mtd, u_char *dat,
192 u_char *read_ecc, u_char *calc_ecc)
193{
194 struct nand_chip *chip = mtd_to_nand(mtd);
195 uint32_t eccNand = read_ecc[0] | (read_ecc[1] << 8) |
196 (read_ecc[2] << 16);
197 uint32_t eccCalc = calc_ecc[0] | (calc_ecc[1] << 8) |
198 (calc_ecc[2] << 16);
199 uint32_t diff = eccCalc ^ eccNand;
200
201 if (diff) {
202 if ((((diff >> 12) ^ diff) & 0xfff) == 0xfff) {
203
204 if ((diff >> (12 + 3)) < chip->ecc.size) {
205 dat[diff >> (12 + 3)] ^= BIT((diff >> 12) & 7);
206 return 1;
207 } else {
208 return -EBADMSG;
209 }
210 } else if (!(diff & (diff - 1))) {
211
212
213 return 1;
214 } else {
215
216 return -EBADMSG;
217 }
218
219 }
220 return 0;
221}
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237static void nand_davinci_hwctl_4bit(struct mtd_info *mtd, int mode)
238{
239 struct davinci_nand_info *info = to_davinci_nand(mtd);
240 unsigned long flags;
241 u32 val;
242
243
244 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
245
246 spin_lock_irqsave(&davinci_nand_lock, flags);
247
248
249 val = davinci_nand_readl(info, NANDFCR_OFFSET);
250 val &= ~(0x03 << 4);
251 val |= (info->core_chipsel << 4) | BIT(12);
252 davinci_nand_writel(info, NANDFCR_OFFSET, val);
253
254 info->is_readmode = (mode == NAND_ECC_READ);
255
256 spin_unlock_irqrestore(&davinci_nand_lock, flags);
257}
258
259
260static void
261nand_davinci_readecc_4bit(struct davinci_nand_info *info, u32 code[4])
262{
263 const u32 mask = 0x03ff03ff;
264
265 code[0] = davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET) & mask;
266 code[1] = davinci_nand_readl(info, NAND_4BIT_ECC2_OFFSET) & mask;
267 code[2] = davinci_nand_readl(info, NAND_4BIT_ECC3_OFFSET) & mask;
268 code[3] = davinci_nand_readl(info, NAND_4BIT_ECC4_OFFSET) & mask;
269}
270
271
272static int nand_davinci_calculate_4bit(struct mtd_info *mtd,
273 const u_char *dat, u_char *ecc_code)
274{
275 struct davinci_nand_info *info = to_davinci_nand(mtd);
276 u32 raw_ecc[4], *p;
277 unsigned i;
278
279
280
281
282
283
284 if (info->is_readmode) {
285 davinci_nand_readl(info, NAND_4BIT_ECC1_OFFSET);
286 return 0;
287 }
288
289
290
291
292
293
294 nand_davinci_readecc_4bit(info, raw_ecc);
295 for (i = 0, p = raw_ecc; i < 2; i++, p += 2) {
296 *ecc_code++ = p[0] & 0xff;
297 *ecc_code++ = ((p[0] >> 8) & 0x03) | ((p[0] >> 14) & 0xfc);
298 *ecc_code++ = ((p[0] >> 22) & 0x0f) | ((p[1] << 4) & 0xf0);
299 *ecc_code++ = ((p[1] >> 4) & 0x3f) | ((p[1] >> 10) & 0xc0);
300 *ecc_code++ = (p[1] >> 18) & 0xff;
301 }
302
303 return 0;
304}
305
306
307
308
309static int nand_davinci_correct_4bit(struct mtd_info *mtd,
310 u_char *data, u_char *ecc_code, u_char *null)
311{
312 int i;
313 struct davinci_nand_info *info = to_davinci_nand(mtd);
314 unsigned short ecc10[8];
315 unsigned short *ecc16;
316 u32 syndrome[4];
317 u32 ecc_state;
318 unsigned num_errors, corrected;
319 unsigned long timeo;
320
321
322
323
324 if (WARN_ON(0x01 & (unsigned) ecc_code))
325 return -EINVAL;
326 ecc16 = (unsigned short *)ecc_code;
327
328 ecc10[0] = (ecc16[0] >> 0) & 0x3ff;
329 ecc10[1] = ((ecc16[0] >> 10) & 0x3f) | ((ecc16[1] << 6) & 0x3c0);
330 ecc10[2] = (ecc16[1] >> 4) & 0x3ff;
331 ecc10[3] = ((ecc16[1] >> 14) & 0x3) | ((ecc16[2] << 2) & 0x3fc);
332 ecc10[4] = (ecc16[2] >> 8) | ((ecc16[3] << 8) & 0x300);
333 ecc10[5] = (ecc16[3] >> 2) & 0x3ff;
334 ecc10[6] = ((ecc16[3] >> 12) & 0xf) | ((ecc16[4] << 4) & 0x3f0);
335 ecc10[7] = (ecc16[4] >> 6) & 0x3ff;
336
337
338 for (i = 7; i >= 0; i--)
339 davinci_nand_writel(info, NAND_4BIT_ECC_LOAD_OFFSET, ecc10[i]);
340
341
342
343
344 davinci_nand_readl(info, NANDFSR_OFFSET);
345 nand_davinci_readecc_4bit(info, syndrome);
346 if (!(syndrome[0] | syndrome[1] | syndrome[2] | syndrome[3]))
347 return 0;
348
349
350
351
352
353 davinci_nand_readl(info, NAND_ERR_ADD1_OFFSET);
354
355
356
357
358
359 davinci_nand_writel(info, NANDFCR_OFFSET,
360 davinci_nand_readl(info, NANDFCR_OFFSET) | BIT(13));
361
362
363
364
365
366
367
368
369
370
371 timeo = jiffies + usecs_to_jiffies(100);
372 do {
373 ecc_state = (davinci_nand_readl(info,
374 NANDFSR_OFFSET) >> 8) & 0x0f;
375 cpu_relax();
376 } while ((ecc_state < 4) && time_before(jiffies, timeo));
377
378 for (;;) {
379 u32 fsr = davinci_nand_readl(info, NANDFSR_OFFSET);
380
381 switch ((fsr >> 8) & 0x0f) {
382 case 0:
383 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
384 return 0;
385 case 1:
386 davinci_nand_readl(info, NAND_ERR_ERRVAL1_OFFSET);
387 return -EBADMSG;
388 case 2:
389 case 3:
390 num_errors = 1 + ((fsr >> 16) & 0x03);
391 goto correct;
392 default:
393 cpu_relax();
394 continue;
395 }
396 }
397
398correct:
399
400 for (i = 0, corrected = 0; i < num_errors; i++) {
401 int error_address, error_value;
402
403 if (i > 1) {
404 error_address = davinci_nand_readl(info,
405 NAND_ERR_ADD2_OFFSET);
406 error_value = davinci_nand_readl(info,
407 NAND_ERR_ERRVAL2_OFFSET);
408 } else {
409 error_address = davinci_nand_readl(info,
410 NAND_ERR_ADD1_OFFSET);
411 error_value = davinci_nand_readl(info,
412 NAND_ERR_ERRVAL1_OFFSET);
413 }
414
415 if (i & 1) {
416 error_address >>= 16;
417 error_value >>= 16;
418 }
419 error_address &= 0x3ff;
420 error_address = (512 + 7) - error_address;
421
422 if (error_address < 512) {
423 data[error_address] ^= error_value;
424 corrected++;
425 }
426 }
427
428 return corrected;
429}
430
431
432
433
434
435
436
437
438
439
440
441
442static void nand_davinci_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
443{
444 struct nand_chip *chip = mtd_to_nand(mtd);
445
446 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
447 ioread32_rep(chip->IO_ADDR_R, buf, len >> 2);
448 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
449 ioread16_rep(chip->IO_ADDR_R, buf, len >> 1);
450 else
451 ioread8_rep(chip->IO_ADDR_R, buf, len);
452}
453
454static void nand_davinci_write_buf(struct mtd_info *mtd,
455 const uint8_t *buf, int len)
456{
457 struct nand_chip *chip = mtd_to_nand(mtd);
458
459 if ((0x03 & ((unsigned)buf)) == 0 && (0x03 & len) == 0)
460 iowrite32_rep(chip->IO_ADDR_R, buf, len >> 2);
461 else if ((0x01 & ((unsigned)buf)) == 0 && (0x01 & len) == 0)
462 iowrite16_rep(chip->IO_ADDR_R, buf, len >> 1);
463 else
464 iowrite8_rep(chip->IO_ADDR_R, buf, len);
465}
466
467
468
469
470
471static int nand_davinci_dev_ready(struct mtd_info *mtd)
472{
473 struct davinci_nand_info *info = to_davinci_nand(mtd);
474
475 return davinci_nand_readl(info, NANDFSR_OFFSET) & BIT(0);
476}
477
478
479
480
481
482
483
484static int hwecc4_ooblayout_small_ecc(struct mtd_info *mtd, int section,
485 struct mtd_oob_region *oobregion)
486{
487 if (section > 2)
488 return -ERANGE;
489
490 if (!section) {
491 oobregion->offset = 0;
492 oobregion->length = 5;
493 } else if (section == 1) {
494 oobregion->offset = 6;
495 oobregion->length = 2;
496 } else {
497 oobregion->offset = 13;
498 oobregion->length = 3;
499 }
500
501 return 0;
502}
503
504static int hwecc4_ooblayout_small_free(struct mtd_info *mtd, int section,
505 struct mtd_oob_region *oobregion)
506{
507 if (section > 1)
508 return -ERANGE;
509
510 if (!section) {
511 oobregion->offset = 8;
512 oobregion->length = 5;
513 } else {
514 oobregion->offset = 16;
515 oobregion->length = mtd->oobsize - 16;
516 }
517
518 return 0;
519}
520
521static const struct mtd_ooblayout_ops hwecc4_small_ooblayout_ops = {
522 .ecc = hwecc4_ooblayout_small_ecc,
523 .free = hwecc4_ooblayout_small_free,
524};
525
526#if defined(CONFIG_OF)
527static const struct of_device_id davinci_nand_of_match[] = {
528 {.compatible = "ti,davinci-nand", },
529 {.compatible = "ti,keystone-nand", },
530 {},
531};
532MODULE_DEVICE_TABLE(of, davinci_nand_of_match);
533
534static struct davinci_nand_pdata
535 *nand_davinci_get_pdata(struct platform_device *pdev)
536{
537 if (!dev_get_platdata(&pdev->dev) && pdev->dev.of_node) {
538 struct davinci_nand_pdata *pdata;
539 const char *mode;
540 u32 prop;
541
542 pdata = devm_kzalloc(&pdev->dev,
543 sizeof(struct davinci_nand_pdata),
544 GFP_KERNEL);
545 pdev->dev.platform_data = pdata;
546 if (!pdata)
547 return ERR_PTR(-ENOMEM);
548 if (!of_property_read_u32(pdev->dev.of_node,
549 "ti,davinci-chipselect", &prop))
550 pdev->id = prop;
551 else
552 return ERR_PTR(-EINVAL);
553
554 if (!of_property_read_u32(pdev->dev.of_node,
555 "ti,davinci-mask-ale", &prop))
556 pdata->mask_ale = prop;
557 if (!of_property_read_u32(pdev->dev.of_node,
558 "ti,davinci-mask-cle", &prop))
559 pdata->mask_cle = prop;
560 if (!of_property_read_u32(pdev->dev.of_node,
561 "ti,davinci-mask-chipsel", &prop))
562 pdata->mask_chipsel = prop;
563 if (!of_property_read_string(pdev->dev.of_node,
564 "ti,davinci-ecc-mode", &mode)) {
565 if (!strncmp("none", mode, 4))
566 pdata->ecc_mode = NAND_ECC_NONE;
567 if (!strncmp("soft", mode, 4))
568 pdata->ecc_mode = NAND_ECC_SOFT;
569 if (!strncmp("hw", mode, 2))
570 pdata->ecc_mode = NAND_ECC_HW;
571 }
572 if (!of_property_read_u32(pdev->dev.of_node,
573 "ti,davinci-ecc-bits", &prop))
574 pdata->ecc_bits = prop;
575
576 if (!of_property_read_u32(pdev->dev.of_node,
577 "ti,davinci-nand-buswidth", &prop) && prop == 16)
578 pdata->options |= NAND_BUSWIDTH_16;
579
580 if (of_property_read_bool(pdev->dev.of_node,
581 "ti,davinci-nand-use-bbt"))
582 pdata->bbt_options = NAND_BBT_USE_FLASH;
583
584
585
586
587
588
589
590
591
592
593
594
595 if (of_device_is_compatible(pdev->dev.of_node,
596 "ti,keystone-nand")) {
597 pdata->options |= NAND_NO_SUBPAGE_WRITE;
598 }
599 }
600
601 return dev_get_platdata(&pdev->dev);
602}
603#else
604static struct davinci_nand_pdata
605 *nand_davinci_get_pdata(struct platform_device *pdev)
606{
607 return dev_get_platdata(&pdev->dev);
608}
609#endif
610
611static int nand_davinci_probe(struct platform_device *pdev)
612{
613 struct davinci_nand_pdata *pdata;
614 struct davinci_nand_info *info;
615 struct resource *res1;
616 struct resource *res2;
617 void __iomem *vaddr;
618 void __iomem *base;
619 int ret;
620 uint32_t val;
621 struct mtd_info *mtd;
622
623 pdata = nand_davinci_get_pdata(pdev);
624 if (IS_ERR(pdata))
625 return PTR_ERR(pdata);
626
627
628 if (!pdata)
629 return -ENODEV;
630
631
632 if (pdev->id < 0 || pdev->id > 3)
633 return -ENODEV;
634
635 info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
636 if (!info)
637 return -ENOMEM;
638
639 platform_set_drvdata(pdev, info);
640
641 res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
642 res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
643 if (!res1 || !res2) {
644 dev_err(&pdev->dev, "resource missing\n");
645 return -EINVAL;
646 }
647
648 vaddr = devm_ioremap_resource(&pdev->dev, res1);
649 if (IS_ERR(vaddr))
650 return PTR_ERR(vaddr);
651
652
653
654
655
656
657
658 base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
659 if (!base) {
660 dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
661 return -EADDRNOTAVAIL;
662 }
663
664 info->dev = &pdev->dev;
665 info->base = base;
666 info->vaddr = vaddr;
667
668 mtd = nand_to_mtd(&info->chip);
669 mtd->dev.parent = &pdev->dev;
670 nand_set_flash_node(&info->chip, pdev->dev.of_node);
671
672 info->chip.IO_ADDR_R = vaddr;
673 info->chip.IO_ADDR_W = vaddr;
674 info->chip.chip_delay = 0;
675 info->chip.select_chip = nand_davinci_select_chip;
676
677
678 info->chip.bbt_options = pdata->bbt_options;
679
680 info->chip.options = pdata->options;
681 info->chip.bbt_td = pdata->bbt_td;
682 info->chip.bbt_md = pdata->bbt_md;
683 info->timing = pdata->timing;
684
685 info->ioaddr = (uint32_t __force) vaddr;
686
687 info->current_cs = info->ioaddr;
688 info->core_chipsel = pdev->id;
689 info->mask_chipsel = pdata->mask_chipsel;
690
691
692 info->mask_ale = pdata->mask_ale ? : MASK_ALE;
693 info->mask_cle = pdata->mask_cle ? : MASK_CLE;
694
695
696 info->chip.cmd_ctrl = nand_davinci_hwcontrol;
697 info->chip.dev_ready = nand_davinci_dev_ready;
698
699
700 info->chip.read_buf = nand_davinci_read_buf;
701 info->chip.write_buf = nand_davinci_write_buf;
702
703
704 info->chip.ecc.mode = pdata->ecc_mode;
705
706 ret = -EINVAL;
707
708 info->clk = devm_clk_get(&pdev->dev, "aemif");
709 if (IS_ERR(info->clk)) {
710 ret = PTR_ERR(info->clk);
711 dev_dbg(&pdev->dev, "unable to get AEMIF clock, err %d\n", ret);
712 return ret;
713 }
714
715 ret = clk_prepare_enable(info->clk);
716 if (ret < 0) {
717 dev_dbg(&pdev->dev, "unable to enable AEMIF clock, err %d\n",
718 ret);
719 goto err_clk_enable;
720 }
721
722 spin_lock_irq(&davinci_nand_lock);
723
724
725 val = davinci_nand_readl(info, NANDFCR_OFFSET);
726 val |= BIT(info->core_chipsel);
727 davinci_nand_writel(info, NANDFCR_OFFSET, val);
728
729 spin_unlock_irq(&davinci_nand_lock);
730
731
732 ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
733 if (ret < 0) {
734 dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
735 goto err;
736 }
737
738 switch (info->chip.ecc.mode) {
739 case NAND_ECC_NONE:
740 pdata->ecc_bits = 0;
741 break;
742 case NAND_ECC_SOFT:
743 pdata->ecc_bits = 0;
744
745
746
747
748
749
750 info->chip.ecc.algo = NAND_ECC_HAMMING;
751 break;
752 case NAND_ECC_HW:
753 if (pdata->ecc_bits == 4) {
754
755
756
757
758
759 spin_lock_irq(&davinci_nand_lock);
760 if (ecc4_busy)
761 ret = -EBUSY;
762 else
763 ecc4_busy = true;
764 spin_unlock_irq(&davinci_nand_lock);
765
766 if (ret == -EBUSY)
767 return ret;
768
769 info->chip.ecc.calculate = nand_davinci_calculate_4bit;
770 info->chip.ecc.correct = nand_davinci_correct_4bit;
771 info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
772 info->chip.ecc.bytes = 10;
773 info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
774 info->chip.ecc.algo = NAND_ECC_BCH;
775 } else {
776
777 info->chip.ecc.calculate = nand_davinci_calculate_1bit;
778 info->chip.ecc.correct = nand_davinci_correct_1bit;
779 info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
780 info->chip.ecc.bytes = 3;
781 info->chip.ecc.algo = NAND_ECC_HAMMING;
782 }
783 info->chip.ecc.size = 512;
784 info->chip.ecc.strength = pdata->ecc_bits;
785 break;
786 default:
787 return -EINVAL;
788 }
789
790
791
792
793
794
795 if (pdata->ecc_bits == 4) {
796 int chunks = mtd->writesize / 512;
797
798 if (!chunks || mtd->oobsize < 16) {
799 dev_dbg(&pdev->dev, "too small\n");
800 ret = -EINVAL;
801 goto err;
802 }
803
804
805
806
807
808 if (chunks == 1) {
809 mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
810 } else if (chunks == 4 || chunks == 8) {
811 mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
812 info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
813 } else {
814 ret = -EIO;
815 goto err;
816 }
817 }
818
819 ret = nand_scan_tail(mtd);
820 if (ret < 0)
821 goto err;
822
823 if (pdata->parts)
824 ret = mtd_device_parse_register(mtd, NULL, NULL,
825 pdata->parts, pdata->nr_parts);
826 else
827 ret = mtd_device_register(mtd, NULL, 0);
828 if (ret < 0)
829 goto err_cleanup_nand;
830
831 val = davinci_nand_readl(info, NRCSR_OFFSET);
832 dev_info(&pdev->dev, "controller rev. %d.%d\n",
833 (val >> 8) & 0xff, val & 0xff);
834
835 return 0;
836
837err_cleanup_nand:
838 nand_cleanup(&info->chip);
839
840err:
841 clk_disable_unprepare(info->clk);
842
843err_clk_enable:
844 spin_lock_irq(&davinci_nand_lock);
845 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
846 ecc4_busy = false;
847 spin_unlock_irq(&davinci_nand_lock);
848 return ret;
849}
850
851static int nand_davinci_remove(struct platform_device *pdev)
852{
853 struct davinci_nand_info *info = platform_get_drvdata(pdev);
854
855 spin_lock_irq(&davinci_nand_lock);
856 if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME)
857 ecc4_busy = false;
858 spin_unlock_irq(&davinci_nand_lock);
859
860 nand_release(nand_to_mtd(&info->chip));
861
862 clk_disable_unprepare(info->clk);
863
864 return 0;
865}
866
867static struct platform_driver nand_davinci_driver = {
868 .probe = nand_davinci_probe,
869 .remove = nand_davinci_remove,
870 .driver = {
871 .name = "davinci_nand",
872 .of_match_table = of_match_ptr(davinci_nand_of_match),
873 },
874};
875MODULE_ALIAS("platform:davinci_nand");
876
877module_platform_driver(nand_davinci_driver);
878
879MODULE_LICENSE("GPL");
880MODULE_AUTHOR("Texas Instruments");
881MODULE_DESCRIPTION("Davinci NAND flash driver");
882
883