1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23#include <linux/module.h>
24#include <linux/types.h>
25#include <linux/kernel.h>
26#include <linux/of_address.h>
27#include <linux/slab.h>
28#include <linux/mtd/mtd.h>
29#include <linux/mtd/rawnand.h>
30#include <linux/mtd/partitions.h>
31#include <linux/mtd/nand_ecc.h>
32#include <linux/fsl_ifc.h>
33
34#define ERR_BYTE 0xFF
35
36#define IFC_TIMEOUT_MSECS 500
37
38
39struct fsl_ifc_ctrl;
40
41
42struct fsl_ifc_mtd {
43 struct nand_chip chip;
44 struct fsl_ifc_ctrl *ctrl;
45
46 struct device *dev;
47 int bank;
48 unsigned int bufnum_mask;
49 u8 __iomem *vbase;
50};
51
52
53struct fsl_ifc_nand_ctrl {
54 struct nand_hw_control controller;
55 struct fsl_ifc_mtd *chips[FSL_IFC_BANK_COUNT];
56
57 void __iomem *addr;
58 unsigned int page;
59 unsigned int read_bytes;
60 unsigned int column;
61 unsigned int index;
62 unsigned int oob;
63 unsigned int eccread;
64 unsigned int counter;
65 unsigned int max_bitflips;
66};
67
68static struct fsl_ifc_nand_ctrl *ifc_nand_ctrl;
69
70
71
72
73static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
74static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
75
76static struct nand_bbt_descr bbt_main_descr = {
77 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
78 NAND_BBT_2BIT | NAND_BBT_VERSION,
79 .offs = 2,
80 .len = 4,
81 .veroffs = 6,
82 .maxblocks = 4,
83 .pattern = bbt_pattern,
84};
85
86static struct nand_bbt_descr bbt_mirror_descr = {
87 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
88 NAND_BBT_2BIT | NAND_BBT_VERSION,
89 .offs = 2,
90 .len = 4,
91 .veroffs = 6,
92 .maxblocks = 4,
93 .pattern = mirror_pattern,
94};
95
96static int fsl_ifc_ooblayout_ecc(struct mtd_info *mtd, int section,
97 struct mtd_oob_region *oobregion)
98{
99 struct nand_chip *chip = mtd_to_nand(mtd);
100
101 if (section)
102 return -ERANGE;
103
104 oobregion->offset = 8;
105 oobregion->length = chip->ecc.total;
106
107 return 0;
108}
109
110static int fsl_ifc_ooblayout_free(struct mtd_info *mtd, int section,
111 struct mtd_oob_region *oobregion)
112{
113 struct nand_chip *chip = mtd_to_nand(mtd);
114
115 if (section > 1)
116 return -ERANGE;
117
118 if (mtd->writesize == 512 &&
119 !(chip->options & NAND_BUSWIDTH_16)) {
120 if (!section) {
121 oobregion->offset = 0;
122 oobregion->length = 5;
123 } else {
124 oobregion->offset = 6;
125 oobregion->length = 2;
126 }
127
128 return 0;
129 }
130
131 if (!section) {
132 oobregion->offset = 2;
133 oobregion->length = 6;
134 } else {
135 oobregion->offset = chip->ecc.total + 8;
136 oobregion->length = mtd->oobsize - oobregion->offset;
137 }
138
139 return 0;
140}
141
142static const struct mtd_ooblayout_ops fsl_ifc_ooblayout_ops = {
143 .ecc = fsl_ifc_ooblayout_ecc,
144 .free = fsl_ifc_ooblayout_free,
145};
146
147
148
149
150
151static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
152{
153 struct nand_chip *chip = mtd_to_nand(mtd);
154 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
155 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
156 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
157 int buf_num;
158
159 ifc_nand_ctrl->page = page_addr;
160
161 ifc_out32(page_addr, &ifc->ifc_nand.row0);
162 ifc_out32((oob ? IFC_NAND_COL_MS : 0) | column, &ifc->ifc_nand.col0);
163
164 buf_num = page_addr & priv->bufnum_mask;
165
166 ifc_nand_ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
167 ifc_nand_ctrl->index = column;
168
169
170 if (oob)
171 ifc_nand_ctrl->index += mtd->writesize;
172}
173
174
175static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
176 u32 eccstat, unsigned int bufnum)
177{
178 return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
179}
180
181
182
183
184static void fsl_ifc_run_command(struct mtd_info *mtd)
185{
186 struct nand_chip *chip = mtd_to_nand(mtd);
187 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
188 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
189 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
190 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
191 u32 eccstat;
192 int i;
193
194
195 ifc_out32(priv->bank << IFC_NAND_CSEL_SHIFT,
196 &ifc->ifc_nand.nand_csel);
197
198 dev_vdbg(priv->dev,
199 "%s: fir0=%08x fcr0=%08x\n",
200 __func__,
201 ifc_in32(&ifc->ifc_nand.nand_fir0),
202 ifc_in32(&ifc->ifc_nand.nand_fcr0));
203
204 ctrl->nand_stat = 0;
205
206
207 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT, &ifc->ifc_nand.nandseq_strt);
208
209
210 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
211 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
212
213
214 if (!ctrl->nand_stat)
215 dev_err(priv->dev, "Controller is not responding\n");
216 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_FTOER)
217 dev_err(priv->dev, "NAND Flash Timeout Error\n");
218 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_WPER)
219 dev_err(priv->dev, "NAND Flash Write Protect Error\n");
220
221 nctrl->max_bitflips = 0;
222
223 if (nctrl->eccread) {
224 int errors;
225 int bufnum = nctrl->page & priv->bufnum_mask;
226 int sector_start = bufnum * chip->ecc.steps;
227 int sector_end = sector_start + chip->ecc.steps - 1;
228 __be32 *eccstat_regs;
229
230 eccstat_regs = ifc->ifc_nand.nand_eccstat;
231 eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
232
233 for (i = sector_start; i <= sector_end; i++) {
234 if (i != sector_start && !(i % 4))
235 eccstat = ifc_in32(&eccstat_regs[i / 4]);
236
237 errors = check_read_ecc(mtd, ctrl, eccstat, i);
238
239 if (errors == 15) {
240
241
242
243
244
245
246
247
248 ctrl->nand_stat |= IFC_NAND_EVTER_STAT_ECCER;
249 continue;
250 }
251
252 mtd->ecc_stats.corrected += errors;
253 nctrl->max_bitflips = max_t(unsigned int,
254 nctrl->max_bitflips,
255 errors);
256 }
257
258 nctrl->eccread = 0;
259 }
260}
261
262static void fsl_ifc_do_read(struct nand_chip *chip,
263 int oob,
264 struct mtd_info *mtd)
265{
266 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
267 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
268 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
269
270
271 if (mtd->writesize > 512) {
272 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
273 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
274 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
275 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
276 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT),
277 &ifc->ifc_nand.nand_fir0);
278 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
279
280 ifc_out32((NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
281 (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT),
282 &ifc->ifc_nand.nand_fcr0);
283 } else {
284 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
285 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
286 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
287 (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT),
288 &ifc->ifc_nand.nand_fir0);
289 ifc_out32(0x0, &ifc->ifc_nand.nand_fir1);
290
291 if (oob)
292 ifc_out32(NAND_CMD_READOOB <<
293 IFC_NAND_FCR0_CMD0_SHIFT,
294 &ifc->ifc_nand.nand_fcr0);
295 else
296 ifc_out32(NAND_CMD_READ0 <<
297 IFC_NAND_FCR0_CMD0_SHIFT,
298 &ifc->ifc_nand.nand_fcr0);
299 }
300}
301
302
303static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
304 int column, int page_addr) {
305 struct nand_chip *chip = mtd_to_nand(mtd);
306 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
307 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
308 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
309
310
311 ifc_nand_ctrl->read_bytes = 0;
312 if (command != NAND_CMD_PAGEPROG)
313 ifc_nand_ctrl->index = 0;
314
315 switch (command) {
316
317 case NAND_CMD_READ0:
318 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
319 set_addr(mtd, 0, page_addr, 0);
320
321 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
322 ifc_nand_ctrl->index += column;
323
324 if (chip->ecc.mode == NAND_ECC_HW)
325 ifc_nand_ctrl->eccread = 1;
326
327 fsl_ifc_do_read(chip, 0, mtd);
328 fsl_ifc_run_command(mtd);
329 return;
330
331
332 case NAND_CMD_READOOB:
333 ifc_out32(mtd->oobsize - column, &ifc->ifc_nand.nand_fbcr);
334 set_addr(mtd, column, page_addr, 1);
335
336 ifc_nand_ctrl->read_bytes = mtd->writesize + mtd->oobsize;
337
338 fsl_ifc_do_read(chip, 1, mtd);
339 fsl_ifc_run_command(mtd);
340
341 return;
342
343 case NAND_CMD_READID:
344 case NAND_CMD_PARAM: {
345 int timing = IFC_FIR_OP_RB;
346 if (command == NAND_CMD_PARAM)
347 timing = IFC_FIR_OP_RBCD;
348
349 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
350 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
351 (timing << IFC_NAND_FIR0_OP2_SHIFT),
352 &ifc->ifc_nand.nand_fir0);
353 ifc_out32(command << IFC_NAND_FCR0_CMD0_SHIFT,
354 &ifc->ifc_nand.nand_fcr0);
355 ifc_out32(column, &ifc->ifc_nand.row3);
356
357
358
359
360
361 ifc_out32(256, &ifc->ifc_nand.nand_fbcr);
362 ifc_nand_ctrl->read_bytes = 256;
363
364 set_addr(mtd, 0, 0, 0);
365 fsl_ifc_run_command(mtd);
366 return;
367 }
368
369
370 case NAND_CMD_ERASE1:
371 set_addr(mtd, 0, page_addr, 0);
372 return;
373
374
375 case NAND_CMD_ERASE2:
376 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
377 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
378 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT),
379 &ifc->ifc_nand.nand_fir0);
380
381 ifc_out32((NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
382 (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT),
383 &ifc->ifc_nand.nand_fcr0);
384
385 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
386 ifc_nand_ctrl->read_bytes = 0;
387 fsl_ifc_run_command(mtd);
388 return;
389
390
391 case NAND_CMD_SEQIN: {
392 u32 nand_fcr0;
393 ifc_nand_ctrl->column = column;
394 ifc_nand_ctrl->oob = 0;
395
396 if (mtd->writesize > 512) {
397 nand_fcr0 =
398 (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
399 (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
400 (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
401
402 ifc_out32(
403 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
404 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
405 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
406 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP3_SHIFT) |
407 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT),
408 &ifc->ifc_nand.nand_fir0);
409 ifc_out32(
410 (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
411 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP6_SHIFT) |
412 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT),
413 &ifc->ifc_nand.nand_fir1);
414 } else {
415 nand_fcr0 = ((NAND_CMD_PAGEPROG <<
416 IFC_NAND_FCR0_CMD1_SHIFT) |
417 (NAND_CMD_SEQIN <<
418 IFC_NAND_FCR0_CMD2_SHIFT) |
419 (NAND_CMD_STATUS <<
420 IFC_NAND_FCR0_CMD3_SHIFT));
421
422 ifc_out32(
423 (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
424 (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
425 (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
426 (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
427 (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT),
428 &ifc->ifc_nand.nand_fir0);
429 ifc_out32(
430 (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
431 (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
432 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR1_OP7_SHIFT) |
433 (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT),
434 &ifc->ifc_nand.nand_fir1);
435
436 if (column >= mtd->writesize)
437 nand_fcr0 |=
438 NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
439 else
440 nand_fcr0 |=
441 NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
442 }
443
444 if (column >= mtd->writesize) {
445
446 column -= mtd->writesize;
447 ifc_nand_ctrl->oob = 1;
448 }
449 ifc_out32(nand_fcr0, &ifc->ifc_nand.nand_fcr0);
450 set_addr(mtd, column, page_addr, ifc_nand_ctrl->oob);
451 return;
452 }
453
454
455 case NAND_CMD_PAGEPROG: {
456 if (ifc_nand_ctrl->oob) {
457 ifc_out32(ifc_nand_ctrl->index -
458 ifc_nand_ctrl->column,
459 &ifc->ifc_nand.nand_fbcr);
460 } else {
461 ifc_out32(0, &ifc->ifc_nand.nand_fbcr);
462 }
463
464 fsl_ifc_run_command(mtd);
465 return;
466 }
467
468 case NAND_CMD_STATUS: {
469 void __iomem *addr;
470
471 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
472 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT),
473 &ifc->ifc_nand.nand_fir0);
474 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
475 &ifc->ifc_nand.nand_fcr0);
476 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
477 set_addr(mtd, 0, 0, 0);
478 ifc_nand_ctrl->read_bytes = 1;
479
480 fsl_ifc_run_command(mtd);
481
482
483
484
485
486 addr = ifc_nand_ctrl->addr;
487 if (chip->options & NAND_BUSWIDTH_16)
488 ifc_out16(ifc_in16(addr) | (NAND_STATUS_WP), addr);
489 else
490 ifc_out8(ifc_in8(addr) | (NAND_STATUS_WP), addr);
491 return;
492 }
493
494 case NAND_CMD_RESET:
495 ifc_out32(IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT,
496 &ifc->ifc_nand.nand_fir0);
497 ifc_out32(NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT,
498 &ifc->ifc_nand.nand_fcr0);
499 fsl_ifc_run_command(mtd);
500 return;
501
502 default:
503 dev_err(priv->dev, "%s: error, unsupported command 0x%x.\n",
504 __func__, command);
505 }
506}
507
508static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
509{
510
511
512
513}
514
515
516
517
518static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
519{
520 struct nand_chip *chip = mtd_to_nand(mtd);
521 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
522 unsigned int bufsize = mtd->writesize + mtd->oobsize;
523
524 if (len <= 0) {
525 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
526 return;
527 }
528
529 if ((unsigned int)len > bufsize - ifc_nand_ctrl->index) {
530 dev_err(priv->dev,
531 "%s: beyond end of buffer (%d requested, %u available)\n",
532 __func__, len, bufsize - ifc_nand_ctrl->index);
533 len = bufsize - ifc_nand_ctrl->index;
534 }
535
536 memcpy_toio(ifc_nand_ctrl->addr + ifc_nand_ctrl->index, buf, len);
537 ifc_nand_ctrl->index += len;
538}
539
540
541
542
543
544static uint8_t fsl_ifc_read_byte(struct mtd_info *mtd)
545{
546 struct nand_chip *chip = mtd_to_nand(mtd);
547 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
548 unsigned int offset;
549
550
551
552
553
554 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
555 offset = ifc_nand_ctrl->index++;
556 return ifc_in8(ifc_nand_ctrl->addr + offset);
557 }
558
559 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
560 return ERR_BYTE;
561}
562
563
564
565
566
567static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
568{
569 struct nand_chip *chip = mtd_to_nand(mtd);
570 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
571 uint16_t data;
572
573
574
575
576
577 if (ifc_nand_ctrl->index < ifc_nand_ctrl->read_bytes) {
578 data = ifc_in16(ifc_nand_ctrl->addr + ifc_nand_ctrl->index);
579 ifc_nand_ctrl->index += 2;
580 return (uint8_t) data;
581 }
582
583 dev_err(priv->dev, "%s: beyond end of buffer\n", __func__);
584 return ERR_BYTE;
585}
586
587
588
589
590static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
591{
592 struct nand_chip *chip = mtd_to_nand(mtd);
593 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
594 int avail;
595
596 if (len < 0) {
597 dev_err(priv->dev, "%s: len %d bytes", __func__, len);
598 return;
599 }
600
601 avail = min((unsigned int)len,
602 ifc_nand_ctrl->read_bytes - ifc_nand_ctrl->index);
603 memcpy_fromio(buf, ifc_nand_ctrl->addr + ifc_nand_ctrl->index, avail);
604 ifc_nand_ctrl->index += avail;
605
606 if (len > avail)
607 dev_err(priv->dev,
608 "%s: beyond end of buffer (%d requested, %d available)\n",
609 __func__, len, avail);
610}
611
612
613
614
615
616static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
617{
618 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
619 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
620 struct fsl_ifc_runtime __iomem *ifc = ctrl->rregs;
621 u32 nand_fsr;
622 int status;
623
624
625 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
626 (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT),
627 &ifc->ifc_nand.nand_fir0);
628 ifc_out32(NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT,
629 &ifc->ifc_nand.nand_fcr0);
630 ifc_out32(1, &ifc->ifc_nand.nand_fbcr);
631 set_addr(mtd, 0, 0, 0);
632 ifc_nand_ctrl->read_bytes = 1;
633
634 fsl_ifc_run_command(mtd);
635
636 nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
637 status = nand_fsr >> 24;
638
639
640
641
642 return status | NAND_STATUS_WP;
643}
644
645
646
647
648
649static int check_erased_page(struct nand_chip *chip, u8 *buf)
650{
651 struct mtd_info *mtd = nand_to_mtd(chip);
652 u8 *ecc = chip->oob_poi;
653 const int ecc_size = chip->ecc.bytes;
654 const int pkt_size = chip->ecc.size;
655 int i, res, bitflips = 0;
656 struct mtd_oob_region oobregion = { };
657
658 mtd_ooblayout_ecc(mtd, 0, &oobregion);
659 ecc += oobregion.offset;
660
661 for (i = 0; i < chip->ecc.steps; ++i) {
662 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
663 NULL, 0,
664 chip->ecc.strength);
665 if (res < 0)
666 mtd->ecc_stats.failed++;
667 else
668 mtd->ecc_stats.corrected += res;
669
670 bitflips = max(res, bitflips);
671 buf += pkt_size;
672 ecc += ecc_size;
673 }
674
675 return bitflips;
676}
677
678static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
679 uint8_t *buf, int oob_required, int page)
680{
681 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
682 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
683 struct fsl_ifc_nand_ctrl *nctrl = ifc_nand_ctrl;
684
685 nand_read_page_op(chip, page, 0, buf, mtd->writesize);
686 if (oob_required)
687 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
688
689 if (ctrl->nand_stat & IFC_NAND_EVTER_STAT_ECCER) {
690 if (!oob_required)
691 fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
692
693 return check_erased_page(chip, buf);
694 }
695
696 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
697 mtd->ecc_stats.failed++;
698
699 return nctrl->max_bitflips;
700}
701
702
703
704
705static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
706 const uint8_t *buf, int oob_required, int page)
707{
708 nand_prog_page_begin_op(chip, page, 0, buf, mtd->writesize);
709 fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
710
711 return nand_prog_page_end_op(chip);
712}
713
714static int fsl_ifc_chip_init_tail(struct mtd_info *mtd)
715{
716 struct nand_chip *chip = mtd_to_nand(mtd);
717 struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
718
719 dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__,
720 chip->numchips);
721 dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__,
722 chip->chipsize);
723 dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__,
724 chip->pagemask);
725 dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__,
726 chip->chip_delay);
727 dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__,
728 chip->badblockpos);
729 dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__,
730 chip->chip_shift);
731 dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__,
732 chip->page_shift);
733 dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__,
734 chip->phys_erase_shift);
735 dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__,
736 chip->ecc.mode);
737 dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__,
738 chip->ecc.steps);
739 dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__,
740 chip->ecc.bytes);
741 dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__,
742 chip->ecc.total);
743 dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__,
744 mtd->ooblayout);
745 dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
746 dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
747 dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__,
748 mtd->erasesize);
749 dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__,
750 mtd->writesize);
751 dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__,
752 mtd->oobsize);
753
754 return 0;
755}
756
757static void fsl_ifc_sram_init(struct fsl_ifc_mtd *priv)
758{
759 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
760 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
761 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
762 uint32_t csor = 0, csor_8k = 0, csor_ext = 0;
763 uint32_t cs = priv->bank;
764
765
766 csor = ifc_in32(&ifc_global->csor_cs[cs].csor);
767 csor_ext = ifc_in32(&ifc_global->csor_cs[cs].csor_ext);
768
769
770 csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
771 ifc_out32(csor_8k, &ifc_global->csor_cs[cs].csor);
772 ifc_out32(0x0000400, &ifc_global->csor_cs[cs].csor_ext);
773
774
775 ifc_out32((IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
776 (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
777 (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT),
778 &ifc_runtime->ifc_nand.nand_fir0);
779 ifc_out32(NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT,
780 &ifc_runtime->ifc_nand.nand_fcr0);
781 ifc_out32(0x0, &ifc_runtime->ifc_nand.row3);
782
783 ifc_out32(0x0, &ifc_runtime->ifc_nand.nand_fbcr);
784
785
786 ifc_out32(0x0, &ifc_runtime->ifc_nand.row0);
787 ifc_out32(0x0, &ifc_runtime->ifc_nand.col0);
788
789
790 ifc_out32(cs << IFC_NAND_CSEL_SHIFT,
791 &ifc_runtime->ifc_nand.nand_csel);
792
793
794 ifc_out32(IFC_NAND_SEQ_STRT_FIR_STRT,
795 &ifc_runtime->ifc_nand.nandseq_strt);
796
797
798 wait_event_timeout(ctrl->nand_wait, ctrl->nand_stat,
799 msecs_to_jiffies(IFC_TIMEOUT_MSECS));
800
801 if (ctrl->nand_stat != IFC_NAND_EVTER_STAT_OPC)
802 pr_err("fsl-ifc: Failed to Initialise SRAM\n");
803
804
805 ifc_out32(csor, &ifc_global->csor_cs[cs].csor);
806 ifc_out32(csor_ext, &ifc_global->csor_cs[cs].csor_ext);
807}
808
809static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv)
810{
811 struct fsl_ifc_ctrl *ctrl = priv->ctrl;
812 struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
813 struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
814 struct nand_chip *chip = &priv->chip;
815 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
816 u32 csor;
817
818
819 mtd->dev.parent = priv->dev;
820 nand_set_flash_node(chip, priv->dev->of_node);
821
822
823
824 if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr))
825 & CSPR_PORT_SIZE_16)
826 chip->read_byte = fsl_ifc_read_byte16;
827 else
828 chip->read_byte = fsl_ifc_read_byte;
829
830 chip->write_buf = fsl_ifc_write_buf;
831 chip->read_buf = fsl_ifc_read_buf;
832 chip->select_chip = fsl_ifc_select_chip;
833 chip->cmdfunc = fsl_ifc_cmdfunc;
834 chip->waitfunc = fsl_ifc_wait;
835 chip->set_features = nand_get_set_features_notsupp;
836 chip->get_features = nand_get_set_features_notsupp;
837
838 chip->bbt_td = &bbt_main_descr;
839 chip->bbt_md = &bbt_mirror_descr;
840
841 ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
842
843
844 chip->bbt_options = NAND_BBT_USE_FLASH;
845 chip->options = NAND_NO_SUBPAGE_WRITE;
846
847 if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)
848 & CSPR_PORT_SIZE_16) {
849 chip->read_byte = fsl_ifc_read_byte16;
850 chip->options |= NAND_BUSWIDTH_16;
851 } else {
852 chip->read_byte = fsl_ifc_read_byte;
853 }
854
855 chip->controller = &ifc_nand_ctrl->controller;
856 nand_set_controller_data(chip, priv);
857
858 chip->ecc.read_page = fsl_ifc_read_page;
859 chip->ecc.write_page = fsl_ifc_write_page;
860
861 csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
862
863 switch (csor & CSOR_NAND_PGS_MASK) {
864 case CSOR_NAND_PGS_512:
865 if (!(chip->options & NAND_BUSWIDTH_16)) {
866
867 bbt_main_descr.offs = 0;
868 bbt_mirror_descr.offs = 0;
869 }
870
871 priv->bufnum_mask = 15;
872 break;
873
874 case CSOR_NAND_PGS_2K:
875 priv->bufnum_mask = 3;
876 break;
877
878 case CSOR_NAND_PGS_4K:
879 priv->bufnum_mask = 1;
880 break;
881
882 case CSOR_NAND_PGS_8K:
883 priv->bufnum_mask = 0;
884 break;
885
886 default:
887 dev_err(priv->dev, "bad csor %#x: bad page size\n", csor);
888 return -ENODEV;
889 }
890
891
892 if (csor & CSOR_NAND_ECC_DEC_EN) {
893 chip->ecc.mode = NAND_ECC_HW;
894 mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
895
896
897 chip->ecc.size = 512;
898 if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
899 chip->ecc.bytes = 8;
900 chip->ecc.strength = 4;
901 } else {
902 chip->ecc.bytes = 16;
903 chip->ecc.strength = 8;
904 }
905 } else {
906 chip->ecc.mode = NAND_ECC_SOFT;
907 chip->ecc.algo = NAND_ECC_HAMMING;
908 }
909
910 if (ctrl->version >= FSL_IFC_VERSION_1_1_0)
911 fsl_ifc_sram_init(priv);
912
913
914
915
916
917 if (ctrl->version >= FSL_IFC_VERSION_2_0_0)
918 priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
919
920 return 0;
921}
922
923static int fsl_ifc_chip_remove(struct fsl_ifc_mtd *priv)
924{
925 struct mtd_info *mtd = nand_to_mtd(&priv->chip);
926
927 nand_release(mtd);
928
929 kfree(mtd->name);
930
931 if (priv->vbase)
932 iounmap(priv->vbase);
933
934 ifc_nand_ctrl->chips[priv->bank] = NULL;
935
936 return 0;
937}
938
939static int match_bank(struct fsl_ifc_global __iomem *ifc_global, int bank,
940 phys_addr_t addr)
941{
942 u32 cspr = ifc_in32(&ifc_global->cspr_cs[bank].cspr);
943
944 if (!(cspr & CSPR_V))
945 return 0;
946 if ((cspr & CSPR_MSEL) != CSPR_MSEL_NAND)
947 return 0;
948
949 return (cspr & CSPR_BA) == convert_ifc_address(addr);
950}
951
952static DEFINE_MUTEX(fsl_ifc_nand_mutex);
953
954static int fsl_ifc_nand_probe(struct platform_device *dev)
955{
956 struct fsl_ifc_runtime __iomem *ifc;
957 struct fsl_ifc_mtd *priv;
958 struct resource res;
959 static const char *part_probe_types[]
960 = { "cmdlinepart", "RedBoot", "ofpart", NULL };
961 int ret;
962 int bank;
963 struct device_node *node = dev->dev.of_node;
964 struct mtd_info *mtd;
965
966 if (!fsl_ifc_ctrl_dev || !fsl_ifc_ctrl_dev->rregs)
967 return -ENODEV;
968 ifc = fsl_ifc_ctrl_dev->rregs;
969
970
971 ret = of_address_to_resource(node, 0, &res);
972 if (ret) {
973 dev_err(&dev->dev, "%s: failed to get resource\n", __func__);
974 return ret;
975 }
976
977
978 for (bank = 0; bank < fsl_ifc_ctrl_dev->banks; bank++) {
979 if (match_bank(fsl_ifc_ctrl_dev->gregs, bank, res.start))
980 break;
981 }
982
983 if (bank >= fsl_ifc_ctrl_dev->banks) {
984 dev_err(&dev->dev, "%s: address did not match any chip selects\n",
985 __func__);
986 return -ENODEV;
987 }
988
989 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
990 if (!priv)
991 return -ENOMEM;
992
993 mutex_lock(&fsl_ifc_nand_mutex);
994 if (!fsl_ifc_ctrl_dev->nand) {
995 ifc_nand_ctrl = kzalloc(sizeof(*ifc_nand_ctrl), GFP_KERNEL);
996 if (!ifc_nand_ctrl) {
997 mutex_unlock(&fsl_ifc_nand_mutex);
998 return -ENOMEM;
999 }
1000
1001 ifc_nand_ctrl->read_bytes = 0;
1002 ifc_nand_ctrl->index = 0;
1003 ifc_nand_ctrl->addr = NULL;
1004 fsl_ifc_ctrl_dev->nand = ifc_nand_ctrl;
1005
1006 nand_hw_control_init(&ifc_nand_ctrl->controller);
1007 } else {
1008 ifc_nand_ctrl = fsl_ifc_ctrl_dev->nand;
1009 }
1010 mutex_unlock(&fsl_ifc_nand_mutex);
1011
1012 ifc_nand_ctrl->chips[bank] = priv;
1013 priv->bank = bank;
1014 priv->ctrl = fsl_ifc_ctrl_dev;
1015 priv->dev = &dev->dev;
1016
1017 priv->vbase = ioremap(res.start, resource_size(&res));
1018 if (!priv->vbase) {
1019 dev_err(priv->dev, "%s: failed to map chip region\n", __func__);
1020 ret = -ENOMEM;
1021 goto err;
1022 }
1023
1024 dev_set_drvdata(priv->dev, priv);
1025
1026 ifc_out32(IFC_NAND_EVTER_EN_OPC_EN |
1027 IFC_NAND_EVTER_EN_FTOER_EN |
1028 IFC_NAND_EVTER_EN_WPER_EN,
1029 &ifc->ifc_nand.nand_evter_en);
1030
1031
1032 ifc_out32(IFC_NAND_EVTER_INTR_OPCIR_EN |
1033 IFC_NAND_EVTER_INTR_FTOERIR_EN |
1034 IFC_NAND_EVTER_INTR_WPERIR_EN,
1035 &ifc->ifc_nand.nand_evter_intr_en);
1036
1037 mtd = nand_to_mtd(&priv->chip);
1038 mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
1039 if (!mtd->name) {
1040 ret = -ENOMEM;
1041 goto err;
1042 }
1043
1044 ret = fsl_ifc_chip_init(priv);
1045 if (ret)
1046 goto err;
1047
1048 ret = nand_scan_ident(mtd, 1, NULL);
1049 if (ret)
1050 goto err;
1051
1052 ret = fsl_ifc_chip_init_tail(mtd);
1053 if (ret)
1054 goto err;
1055
1056 ret = nand_scan_tail(mtd);
1057 if (ret)
1058 goto err;
1059
1060
1061
1062 mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
1063
1064 dev_info(priv->dev, "IFC NAND device at 0x%llx, bank %d\n",
1065 (unsigned long long)res.start, priv->bank);
1066 return 0;
1067
1068err:
1069 fsl_ifc_chip_remove(priv);
1070 return ret;
1071}
1072
1073static int fsl_ifc_nand_remove(struct platform_device *dev)
1074{
1075 struct fsl_ifc_mtd *priv = dev_get_drvdata(&dev->dev);
1076
1077 fsl_ifc_chip_remove(priv);
1078
1079 mutex_lock(&fsl_ifc_nand_mutex);
1080 ifc_nand_ctrl->counter--;
1081 if (!ifc_nand_ctrl->counter) {
1082 fsl_ifc_ctrl_dev->nand = NULL;
1083 kfree(ifc_nand_ctrl);
1084 }
1085 mutex_unlock(&fsl_ifc_nand_mutex);
1086
1087 return 0;
1088}
1089
1090static const struct of_device_id fsl_ifc_nand_match[] = {
1091 {
1092 .compatible = "fsl,ifc-nand",
1093 },
1094 {}
1095};
1096MODULE_DEVICE_TABLE(of, fsl_ifc_nand_match);
1097
1098static struct platform_driver fsl_ifc_nand_driver = {
1099 .driver = {
1100 .name = "fsl,ifc-nand",
1101 .of_match_table = fsl_ifc_nand_match,
1102 },
1103 .probe = fsl_ifc_nand_probe,
1104 .remove = fsl_ifc_nand_remove,
1105};
1106
1107module_platform_driver(fsl_ifc_nand_driver);
1108
1109MODULE_LICENSE("GPL");
1110MODULE_AUTHOR("Freescale");
1111MODULE_DESCRIPTION("Freescale Integrated Flash Controller MTD NAND driver");
1112