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20#include <linux/delay.h>
21#include <linux/slab.h>
22#include <linux/init.h>
23#include <linux/module.h>
24#include <linux/mtd/mtd.h>
25#include <linux/mtd/rawnand.h>
26#include <linux/mtd/partitions.h>
27#include <linux/interrupt.h>
28#include <linux/device.h>
29#include <linux/platform_device.h>
30#include <linux/clk.h>
31#include <linux/err.h>
32#include <linux/io.h>
33#include <linux/irq.h>
34#include <linux/completion.h>
35#include <linux/of.h>
36#include <linux/of_device.h>
37
38#include <asm/mach/flash.h>
39#include <linux/platform_data/mtd-mxc_nand.h>
40
41#define DRIVER_NAME "mxc_nand"
42
43
44#define NFC_V1_V2_BUF_SIZE (host->regs + 0x00)
45#define NFC_V1_V2_BUF_ADDR (host->regs + 0x04)
46#define NFC_V1_V2_FLASH_ADDR (host->regs + 0x06)
47#define NFC_V1_V2_FLASH_CMD (host->regs + 0x08)
48#define NFC_V1_V2_CONFIG (host->regs + 0x0a)
49#define NFC_V1_V2_ECC_STATUS_RESULT (host->regs + 0x0c)
50#define NFC_V1_V2_RSLTMAIN_AREA (host->regs + 0x0e)
51#define NFC_V1_V2_RSLTSPARE_AREA (host->regs + 0x10)
52#define NFC_V1_V2_WRPROT (host->regs + 0x12)
53#define NFC_V1_UNLOCKSTART_BLKADDR (host->regs + 0x14)
54#define NFC_V1_UNLOCKEND_BLKADDR (host->regs + 0x16)
55#define NFC_V21_UNLOCKSTART_BLKADDR0 (host->regs + 0x20)
56#define NFC_V21_UNLOCKSTART_BLKADDR1 (host->regs + 0x24)
57#define NFC_V21_UNLOCKSTART_BLKADDR2 (host->regs + 0x28)
58#define NFC_V21_UNLOCKSTART_BLKADDR3 (host->regs + 0x2c)
59#define NFC_V21_UNLOCKEND_BLKADDR0 (host->regs + 0x22)
60#define NFC_V21_UNLOCKEND_BLKADDR1 (host->regs + 0x26)
61#define NFC_V21_UNLOCKEND_BLKADDR2 (host->regs + 0x2a)
62#define NFC_V21_UNLOCKEND_BLKADDR3 (host->regs + 0x2e)
63#define NFC_V1_V2_NF_WRPRST (host->regs + 0x18)
64#define NFC_V1_V2_CONFIG1 (host->regs + 0x1a)
65#define NFC_V1_V2_CONFIG2 (host->regs + 0x1c)
66
67#define NFC_V2_CONFIG1_ECC_MODE_4 (1 << 0)
68#define NFC_V1_V2_CONFIG1_SP_EN (1 << 2)
69#define NFC_V1_V2_CONFIG1_ECC_EN (1 << 3)
70#define NFC_V1_V2_CONFIG1_INT_MSK (1 << 4)
71#define NFC_V1_V2_CONFIG1_BIG (1 << 5)
72#define NFC_V1_V2_CONFIG1_RST (1 << 6)
73#define NFC_V1_V2_CONFIG1_CE (1 << 7)
74#define NFC_V2_CONFIG1_ONE_CYCLE (1 << 8)
75#define NFC_V2_CONFIG1_PPB(x) (((x) & 0x3) << 9)
76#define NFC_V2_CONFIG1_FP_INT (1 << 11)
77
78#define NFC_V1_V2_CONFIG2_INT (1 << 15)
79
80
81
82
83
84#define NFC_CMD (1 << 0)
85#define NFC_ADDR (1 << 1)
86#define NFC_INPUT (1 << 2)
87#define NFC_OUTPUT (1 << 3)
88#define NFC_ID (1 << 4)
89#define NFC_STATUS (1 << 5)
90
91#define NFC_V3_FLASH_CMD (host->regs_axi + 0x00)
92#define NFC_V3_FLASH_ADDR0 (host->regs_axi + 0x04)
93
94#define NFC_V3_CONFIG1 (host->regs_axi + 0x34)
95#define NFC_V3_CONFIG1_SP_EN (1 << 0)
96#define NFC_V3_CONFIG1_RBA(x) (((x) & 0x7 ) << 4)
97
98#define NFC_V3_ECC_STATUS_RESULT (host->regs_axi + 0x38)
99
100#define NFC_V3_LAUNCH (host->regs_axi + 0x40)
101
102#define NFC_V3_WRPROT (host->regs_ip + 0x0)
103#define NFC_V3_WRPROT_LOCK_TIGHT (1 << 0)
104#define NFC_V3_WRPROT_LOCK (1 << 1)
105#define NFC_V3_WRPROT_UNLOCK (1 << 2)
106#define NFC_V3_WRPROT_BLS_UNLOCK (2 << 6)
107
108#define NFC_V3_WRPROT_UNLOCK_BLK_ADD0 (host->regs_ip + 0x04)
109
110#define NFC_V3_CONFIG2 (host->regs_ip + 0x24)
111#define NFC_V3_CONFIG2_PS_512 (0 << 0)
112#define NFC_V3_CONFIG2_PS_2048 (1 << 0)
113#define NFC_V3_CONFIG2_PS_4096 (2 << 0)
114#define NFC_V3_CONFIG2_ONE_CYCLE (1 << 2)
115#define NFC_V3_CONFIG2_ECC_EN (1 << 3)
116#define NFC_V3_CONFIG2_2CMD_PHASES (1 << 4)
117#define NFC_V3_CONFIG2_NUM_ADDR_PHASE0 (1 << 5)
118#define NFC_V3_CONFIG2_ECC_MODE_8 (1 << 6)
119#define NFC_V3_CONFIG2_PPB(x, shift) (((x) & 0x3) << shift)
120#define NFC_V3_CONFIG2_NUM_ADDR_PHASE1(x) (((x) & 0x3) << 12)
121#define NFC_V3_CONFIG2_INT_MSK (1 << 15)
122#define NFC_V3_CONFIG2_ST_CMD(x) (((x) & 0xff) << 24)
123#define NFC_V3_CONFIG2_SPAS(x) (((x) & 0xff) << 16)
124
125#define NFC_V3_CONFIG3 (host->regs_ip + 0x28)
126#define NFC_V3_CONFIG3_ADD_OP(x) (((x) & 0x3) << 0)
127#define NFC_V3_CONFIG3_FW8 (1 << 3)
128#define NFC_V3_CONFIG3_SBB(x) (((x) & 0x7) << 8)
129#define NFC_V3_CONFIG3_NUM_OF_DEVICES(x) (((x) & 0x7) << 12)
130#define NFC_V3_CONFIG3_RBB_MODE (1 << 15)
131#define NFC_V3_CONFIG3_NO_SDMA (1 << 20)
132
133#define NFC_V3_IPC (host->regs_ip + 0x2C)
134#define NFC_V3_IPC_CREQ (1 << 0)
135#define NFC_V3_IPC_INT (1 << 31)
136
137#define NFC_V3_DELAY_LINE (host->regs_ip + 0x34)
138
139struct mxc_nand_host;
140
141struct mxc_nand_devtype_data {
142 void (*preset)(struct mtd_info *);
143 int (*read_page)(struct nand_chip *chip, void *buf, void *oob, bool ecc,
144 int page);
145 void (*send_cmd)(struct mxc_nand_host *, uint16_t, int);
146 void (*send_addr)(struct mxc_nand_host *, uint16_t, int);
147 void (*send_page)(struct mtd_info *, unsigned int);
148 void (*send_read_id)(struct mxc_nand_host *);
149 uint16_t (*get_dev_status)(struct mxc_nand_host *);
150 int (*check_int)(struct mxc_nand_host *);
151 void (*irq_control)(struct mxc_nand_host *, int);
152 u32 (*get_ecc_status)(struct mxc_nand_host *);
153 const struct mtd_ooblayout_ops *ooblayout;
154 void (*select_chip)(struct mtd_info *mtd, int chip);
155 int (*setup_data_interface)(struct mtd_info *mtd, int csline,
156 const struct nand_data_interface *conf);
157 void (*enable_hwecc)(struct nand_chip *chip, bool enable);
158
159
160
161
162
163
164 int irqpending_quirk;
165 int needs_ip;
166
167 size_t regs_offset;
168 size_t spare0_offset;
169 size_t axi_offset;
170
171 int spare_len;
172 int eccbytes;
173 int eccsize;
174 int ppb_shift;
175};
176
177struct mxc_nand_host {
178 struct nand_chip nand;
179 struct device *dev;
180
181 void __iomem *spare0;
182 void __iomem *main_area0;
183
184 void __iomem *base;
185 void __iomem *regs;
186 void __iomem *regs_axi;
187 void __iomem *regs_ip;
188 int status_request;
189 struct clk *clk;
190 int clk_act;
191 int irq;
192 int eccsize;
193 int used_oobsize;
194 int active_cs;
195
196 struct completion op_completion;
197
198 uint8_t *data_buf;
199 unsigned int buf_start;
200
201 const struct mxc_nand_devtype_data *devtype_data;
202 struct mxc_nand_platform_data pdata;
203};
204
205static const char * const part_probes[] = {
206 "cmdlinepart", "RedBoot", "ofpart", NULL };
207
208static void memcpy32_fromio(void *trg, const void __iomem *src, size_t size)
209{
210 int i;
211 u32 *t = trg;
212 const __iomem u32 *s = src;
213
214 for (i = 0; i < (size >> 2); i++)
215 *t++ = __raw_readl(s++);
216}
217
218static void memcpy16_fromio(void *trg, const void __iomem *src, size_t size)
219{
220 int i;
221 u16 *t = trg;
222 const __iomem u16 *s = src;
223
224
225 if (PTR_ALIGN(trg, 4) == trg && IS_ALIGNED(size, 4)) {
226 memcpy32_fromio(trg, src, size);
227 return;
228 }
229
230 for (i = 0; i < (size >> 1); i++)
231 *t++ = __raw_readw(s++);
232}
233
234static inline void memcpy32_toio(void __iomem *trg, const void *src, int size)
235{
236
237 __iowrite32_copy(trg, src, size / 4);
238}
239
240static void memcpy16_toio(void __iomem *trg, const void *src, int size)
241{
242 int i;
243 __iomem u16 *t = trg;
244 const u16 *s = src;
245
246
247 if (PTR_ALIGN(src, 4) == src && IS_ALIGNED(size, 4)) {
248 memcpy32_toio(trg, src, size);
249 return;
250 }
251
252 for (i = 0; i < (size >> 1); i++)
253 __raw_writew(*s++, t++);
254}
255
256
257
258
259
260
261
262
263
264
265static void copy_spare(struct mtd_info *mtd, bool bfrom, void *buf)
266{
267 struct nand_chip *this = mtd_to_nand(mtd);
268 struct mxc_nand_host *host = nand_get_controller_data(this);
269 u16 i, oob_chunk_size;
270 u16 num_chunks = mtd->writesize / 512;
271
272 u8 *d = buf;
273 u8 __iomem *s = host->spare0;
274 u16 sparebuf_size = host->devtype_data->spare_len;
275
276
277 oob_chunk_size = (host->used_oobsize / num_chunks) & ~1;
278
279 if (bfrom) {
280 for (i = 0; i < num_chunks - 1; i++)
281 memcpy16_fromio(d + i * oob_chunk_size,
282 s + i * sparebuf_size,
283 oob_chunk_size);
284
285
286 memcpy16_fromio(d + i * oob_chunk_size,
287 s + i * sparebuf_size,
288 host->used_oobsize - i * oob_chunk_size);
289 } else {
290 for (i = 0; i < num_chunks - 1; i++)
291 memcpy16_toio(&s[i * sparebuf_size],
292 &d[i * oob_chunk_size],
293 oob_chunk_size);
294
295
296 memcpy16_toio(&s[i * sparebuf_size],
297 &d[i * oob_chunk_size],
298 host->used_oobsize - i * oob_chunk_size);
299 }
300}
301
302
303
304
305
306
307
308static void mxc_do_addr_cycle(struct mtd_info *mtd, int column, int page_addr)
309{
310 struct nand_chip *nand_chip = mtd_to_nand(mtd);
311 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
312
313
314 if (column != -1) {
315 host->devtype_data->send_addr(host, column & 0xff,
316 page_addr == -1);
317 if (mtd->writesize > 512)
318
319 host->devtype_data->send_addr(host,
320 (column >> 8) & 0xff,
321 false);
322 }
323
324
325 if (page_addr != -1) {
326
327 host->devtype_data->send_addr(host, (page_addr & 0xff), false);
328
329 if (mtd->writesize > 512) {
330 if (mtd->size >= 0x10000000) {
331
332 host->devtype_data->send_addr(host,
333 (page_addr >> 8) & 0xff,
334 false);
335 host->devtype_data->send_addr(host,
336 (page_addr >> 16) & 0xff,
337 true);
338 } else
339
340 host->devtype_data->send_addr(host,
341 (page_addr >> 8) & 0xff, true);
342 } else {
343 if (nand_chip->options & NAND_ROW_ADDR_3) {
344
345 host->devtype_data->send_addr(host,
346 (page_addr >> 8) & 0xff,
347 false);
348 host->devtype_data->send_addr(host,
349 (page_addr >> 16) & 0xff,
350 true);
351 } else
352
353 host->devtype_data->send_addr(host,
354 (page_addr >> 8) & 0xff, true);
355 }
356 }
357}
358
359static int check_int_v3(struct mxc_nand_host *host)
360{
361 uint32_t tmp;
362
363 tmp = readl(NFC_V3_IPC);
364 if (!(tmp & NFC_V3_IPC_INT))
365 return 0;
366
367 tmp &= ~NFC_V3_IPC_INT;
368 writel(tmp, NFC_V3_IPC);
369
370 return 1;
371}
372
373static int check_int_v1_v2(struct mxc_nand_host *host)
374{
375 uint32_t tmp;
376
377 tmp = readw(NFC_V1_V2_CONFIG2);
378 if (!(tmp & NFC_V1_V2_CONFIG2_INT))
379 return 0;
380
381 if (!host->devtype_data->irqpending_quirk)
382 writew(tmp & ~NFC_V1_V2_CONFIG2_INT, NFC_V1_V2_CONFIG2);
383
384 return 1;
385}
386
387static void irq_control_v1_v2(struct mxc_nand_host *host, int activate)
388{
389 uint16_t tmp;
390
391 tmp = readw(NFC_V1_V2_CONFIG1);
392
393 if (activate)
394 tmp &= ~NFC_V1_V2_CONFIG1_INT_MSK;
395 else
396 tmp |= NFC_V1_V2_CONFIG1_INT_MSK;
397
398 writew(tmp, NFC_V1_V2_CONFIG1);
399}
400
401static void irq_control_v3(struct mxc_nand_host *host, int activate)
402{
403 uint32_t tmp;
404
405 tmp = readl(NFC_V3_CONFIG2);
406
407 if (activate)
408 tmp &= ~NFC_V3_CONFIG2_INT_MSK;
409 else
410 tmp |= NFC_V3_CONFIG2_INT_MSK;
411
412 writel(tmp, NFC_V3_CONFIG2);
413}
414
415static void irq_control(struct mxc_nand_host *host, int activate)
416{
417 if (host->devtype_data->irqpending_quirk) {
418 if (activate)
419 enable_irq(host->irq);
420 else
421 disable_irq_nosync(host->irq);
422 } else {
423 host->devtype_data->irq_control(host, activate);
424 }
425}
426
427static u32 get_ecc_status_v1(struct mxc_nand_host *host)
428{
429 return readw(NFC_V1_V2_ECC_STATUS_RESULT);
430}
431
432static u32 get_ecc_status_v2(struct mxc_nand_host *host)
433{
434 return readl(NFC_V1_V2_ECC_STATUS_RESULT);
435}
436
437static u32 get_ecc_status_v3(struct mxc_nand_host *host)
438{
439 return readl(NFC_V3_ECC_STATUS_RESULT);
440}
441
442static irqreturn_t mxc_nfc_irq(int irq, void *dev_id)
443{
444 struct mxc_nand_host *host = dev_id;
445
446 if (!host->devtype_data->check_int(host))
447 return IRQ_NONE;
448
449 irq_control(host, 0);
450
451 complete(&host->op_completion);
452
453 return IRQ_HANDLED;
454}
455
456
457
458
459static int wait_op_done(struct mxc_nand_host *host, int useirq)
460{
461 int ret = 0;
462
463
464
465
466
467 if (host->devtype_data->check_int(host))
468 return 0;
469
470 if (useirq) {
471 unsigned long timeout;
472
473 reinit_completion(&host->op_completion);
474
475 irq_control(host, 1);
476
477 timeout = wait_for_completion_timeout(&host->op_completion, HZ);
478 if (!timeout && !host->devtype_data->check_int(host)) {
479 dev_dbg(host->dev, "timeout waiting for irq\n");
480 ret = -ETIMEDOUT;
481 }
482 } else {
483 int max_retries = 8000;
484 int done;
485
486 do {
487 udelay(1);
488
489 done = host->devtype_data->check_int(host);
490 if (done)
491 break;
492
493 } while (--max_retries);
494
495 if (!done) {
496 dev_dbg(host->dev, "timeout polling for completion\n");
497 ret = -ETIMEDOUT;
498 }
499 }
500
501 WARN_ONCE(ret < 0, "timeout! useirq=%d\n", useirq);
502
503 return ret;
504}
505
506static void send_cmd_v3(struct mxc_nand_host *host, uint16_t cmd, int useirq)
507{
508
509 writel(cmd, NFC_V3_FLASH_CMD);
510
511
512 writel(NFC_CMD, NFC_V3_LAUNCH);
513
514
515 wait_op_done(host, useirq);
516}
517
518
519
520static void send_cmd_v1_v2(struct mxc_nand_host *host, uint16_t cmd, int useirq)
521{
522 dev_dbg(host->dev, "send_cmd(host, 0x%x, %d)\n", cmd, useirq);
523
524 writew(cmd, NFC_V1_V2_FLASH_CMD);
525 writew(NFC_CMD, NFC_V1_V2_CONFIG2);
526
527 if (host->devtype_data->irqpending_quirk && (cmd == NAND_CMD_RESET)) {
528 int max_retries = 100;
529
530
531 while (max_retries-- > 0) {
532 if (readw(NFC_V1_V2_CONFIG2) == 0) {
533 break;
534 }
535 udelay(1);
536 }
537 if (max_retries < 0)
538 dev_dbg(host->dev, "%s: RESET failed\n", __func__);
539 } else {
540
541 wait_op_done(host, useirq);
542 }
543}
544
545static void send_addr_v3(struct mxc_nand_host *host, uint16_t addr, int islast)
546{
547
548 writel(addr, NFC_V3_FLASH_ADDR0);
549
550
551 writel(NFC_ADDR, NFC_V3_LAUNCH);
552
553 wait_op_done(host, 0);
554}
555
556
557
558
559static void send_addr_v1_v2(struct mxc_nand_host *host, uint16_t addr, int islast)
560{
561 dev_dbg(host->dev, "send_addr(host, 0x%x %d)\n", addr, islast);
562
563 writew(addr, NFC_V1_V2_FLASH_ADDR);
564 writew(NFC_ADDR, NFC_V1_V2_CONFIG2);
565
566
567 wait_op_done(host, islast);
568}
569
570static void send_page_v3(struct mtd_info *mtd, unsigned int ops)
571{
572 struct nand_chip *nand_chip = mtd_to_nand(mtd);
573 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
574 uint32_t tmp;
575
576 tmp = readl(NFC_V3_CONFIG1);
577 tmp &= ~(7 << 4);
578 writel(tmp, NFC_V3_CONFIG1);
579
580
581 writel(ops, NFC_V3_LAUNCH);
582
583 wait_op_done(host, false);
584}
585
586static void send_page_v2(struct mtd_info *mtd, unsigned int ops)
587{
588 struct nand_chip *nand_chip = mtd_to_nand(mtd);
589 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
590
591
592 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
593
594 writew(ops, NFC_V1_V2_CONFIG2);
595
596
597 wait_op_done(host, true);
598}
599
600static void send_page_v1(struct mtd_info *mtd, unsigned int ops)
601{
602 struct nand_chip *nand_chip = mtd_to_nand(mtd);
603 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
604 int bufs, i;
605
606 if (mtd->writesize > 512)
607 bufs = 4;
608 else
609 bufs = 1;
610
611 for (i = 0; i < bufs; i++) {
612
613
614 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
615
616 writew(ops, NFC_V1_V2_CONFIG2);
617
618
619 wait_op_done(host, true);
620 }
621}
622
623static void send_read_id_v3(struct mxc_nand_host *host)
624{
625
626 writel(NFC_ID, NFC_V3_LAUNCH);
627
628 wait_op_done(host, true);
629
630 memcpy32_fromio(host->data_buf, host->main_area0, 16);
631}
632
633
634static void send_read_id_v1_v2(struct mxc_nand_host *host)
635{
636
637 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
638
639 writew(NFC_ID, NFC_V1_V2_CONFIG2);
640
641
642 wait_op_done(host, true);
643
644 memcpy32_fromio(host->data_buf, host->main_area0, 16);
645}
646
647static uint16_t get_dev_status_v3(struct mxc_nand_host *host)
648{
649 writew(NFC_STATUS, NFC_V3_LAUNCH);
650 wait_op_done(host, true);
651
652 return readl(NFC_V3_CONFIG1) >> 16;
653}
654
655
656
657static uint16_t get_dev_status_v1_v2(struct mxc_nand_host *host)
658{
659 void __iomem *main_buf = host->main_area0;
660 uint32_t store;
661 uint16_t ret;
662
663 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
664
665
666
667
668
669
670 store = readl(main_buf);
671
672 writew(NFC_STATUS, NFC_V1_V2_CONFIG2);
673 wait_op_done(host, true);
674
675 ret = readw(main_buf);
676
677 writel(store, main_buf);
678
679 return ret;
680}
681
682static void mxc_nand_enable_hwecc_v1_v2(struct nand_chip *chip, bool enable)
683{
684 struct mxc_nand_host *host = nand_get_controller_data(chip);
685 uint16_t config1;
686
687 if (chip->ecc.mode != NAND_ECC_HW)
688 return;
689
690 config1 = readw(NFC_V1_V2_CONFIG1);
691
692 if (enable)
693 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
694 else
695 config1 &= ~NFC_V1_V2_CONFIG1_ECC_EN;
696
697 writew(config1, NFC_V1_V2_CONFIG1);
698}
699
700static void mxc_nand_enable_hwecc_v3(struct nand_chip *chip, bool enable)
701{
702 struct mxc_nand_host *host = nand_get_controller_data(chip);
703 uint32_t config2;
704
705 if (chip->ecc.mode != NAND_ECC_HW)
706 return;
707
708 config2 = readl(NFC_V3_CONFIG2);
709
710 if (enable)
711 config2 |= NFC_V3_CONFIG2_ECC_EN;
712 else
713 config2 &= ~NFC_V3_CONFIG2_ECC_EN;
714
715 writel(config2, NFC_V3_CONFIG2);
716}
717
718
719static int mxc_nand_dev_ready(struct mtd_info *mtd)
720{
721
722
723
724
725 return 1;
726}
727
728static int mxc_nand_read_page_v1(struct nand_chip *chip, void *buf, void *oob,
729 bool ecc, int page)
730{
731 struct mtd_info *mtd = nand_to_mtd(chip);
732 struct mxc_nand_host *host = nand_get_controller_data(chip);
733 unsigned int bitflips_corrected = 0;
734 int no_subpages;
735 int i;
736
737 host->devtype_data->enable_hwecc(chip, ecc);
738
739 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
740 mxc_do_addr_cycle(mtd, 0, page);
741
742 if (mtd->writesize > 512)
743 host->devtype_data->send_cmd(host, NAND_CMD_READSTART, true);
744
745 no_subpages = mtd->writesize >> 9;
746
747 for (i = 0; i < no_subpages; i++) {
748 uint16_t ecc_stats;
749
750
751 writew((host->active_cs << 4) | i, NFC_V1_V2_BUF_ADDR);
752
753 writew(NFC_OUTPUT, NFC_V1_V2_CONFIG2);
754
755
756 wait_op_done(host, true);
757
758 ecc_stats = get_ecc_status_v1(host);
759
760 ecc_stats >>= 2;
761
762 if (buf && ecc) {
763 switch (ecc_stats & 0x3) {
764 case 0:
765 default:
766 break;
767 case 1:
768 mtd->ecc_stats.corrected++;
769 bitflips_corrected = 1;
770 break;
771 case 2:
772 mtd->ecc_stats.failed++;
773 break;
774 }
775 }
776 }
777
778 if (buf)
779 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
780 if (oob)
781 copy_spare(mtd, true, oob);
782
783 return bitflips_corrected;
784}
785
786static int mxc_nand_read_page_v2_v3(struct nand_chip *chip, void *buf,
787 void *oob, bool ecc, int page)
788{
789 struct mtd_info *mtd = nand_to_mtd(chip);
790 struct mxc_nand_host *host = nand_get_controller_data(chip);
791 unsigned int max_bitflips = 0;
792 u32 ecc_stat, err;
793 int no_subpages;
794 u8 ecc_bit_mask, err_limit;
795
796 host->devtype_data->enable_hwecc(chip, ecc);
797
798 host->devtype_data->send_cmd(host, NAND_CMD_READ0, false);
799 mxc_do_addr_cycle(mtd, 0, page);
800
801 if (mtd->writesize > 512)
802 host->devtype_data->send_cmd(host,
803 NAND_CMD_READSTART, true);
804
805 host->devtype_data->send_page(mtd, NFC_OUTPUT);
806
807 if (buf)
808 memcpy32_fromio(buf, host->main_area0, mtd->writesize);
809 if (oob)
810 copy_spare(mtd, true, oob);
811
812 ecc_bit_mask = (host->eccsize == 4) ? 0x7 : 0xf;
813 err_limit = (host->eccsize == 4) ? 0x4 : 0x8;
814
815 no_subpages = mtd->writesize >> 9;
816
817 ecc_stat = host->devtype_data->get_ecc_status(host);
818
819 do {
820 err = ecc_stat & ecc_bit_mask;
821 if (err > err_limit) {
822 mtd->ecc_stats.failed++;
823 } else {
824 mtd->ecc_stats.corrected += err;
825 max_bitflips = max_t(unsigned int, max_bitflips, err);
826 }
827
828 ecc_stat >>= 4;
829 } while (--no_subpages);
830
831 return max_bitflips;
832}
833
834static int mxc_nand_read_page(struct mtd_info *mtd, struct nand_chip *chip,
835 uint8_t *buf, int oob_required, int page)
836{
837 struct mxc_nand_host *host = nand_get_controller_data(chip);
838 void *oob_buf;
839
840 if (oob_required)
841 oob_buf = chip->oob_poi;
842 else
843 oob_buf = NULL;
844
845 return host->devtype_data->read_page(chip, buf, oob_buf, 1, page);
846}
847
848static int mxc_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
849 uint8_t *buf, int oob_required, int page)
850{
851 struct mxc_nand_host *host = nand_get_controller_data(chip);
852 void *oob_buf;
853
854 if (oob_required)
855 oob_buf = chip->oob_poi;
856 else
857 oob_buf = NULL;
858
859 return host->devtype_data->read_page(chip, buf, oob_buf, 0, page);
860}
861
862static int mxc_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
863 int page)
864{
865 struct mxc_nand_host *host = nand_get_controller_data(chip);
866
867 return host->devtype_data->read_page(chip, NULL, chip->oob_poi, 0,
868 page);
869}
870
871static int mxc_nand_write_page(struct nand_chip *chip, const uint8_t *buf,
872 bool ecc, int page)
873{
874 struct mtd_info *mtd = nand_to_mtd(chip);
875 struct mxc_nand_host *host = nand_get_controller_data(chip);
876
877 host->devtype_data->enable_hwecc(chip, ecc);
878
879 host->devtype_data->send_cmd(host, NAND_CMD_SEQIN, false);
880 mxc_do_addr_cycle(mtd, 0, page);
881
882 memcpy32_toio(host->main_area0, buf, mtd->writesize);
883 copy_spare(mtd, false, chip->oob_poi);
884
885 host->devtype_data->send_page(mtd, NFC_INPUT);
886 host->devtype_data->send_cmd(host, NAND_CMD_PAGEPROG, true);
887 mxc_do_addr_cycle(mtd, 0, page);
888
889 return 0;
890}
891
892static int mxc_nand_write_page_ecc(struct mtd_info *mtd, struct nand_chip *chip,
893 const uint8_t *buf, int oob_required,
894 int page)
895{
896 return mxc_nand_write_page(chip, buf, true, page);
897}
898
899static int mxc_nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
900 const uint8_t *buf, int oob_required, int page)
901{
902 return mxc_nand_write_page(chip, buf, false, page);
903}
904
905static int mxc_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
906 int page)
907{
908 struct mxc_nand_host *host = nand_get_controller_data(chip);
909
910 memset(host->data_buf, 0xff, mtd->writesize);
911
912 return mxc_nand_write_page(chip, host->data_buf, false, page);
913}
914
915static u_char mxc_nand_read_byte(struct mtd_info *mtd)
916{
917 struct nand_chip *nand_chip = mtd_to_nand(mtd);
918 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
919 uint8_t ret;
920
921
922 if (host->status_request)
923 return host->devtype_data->get_dev_status(host) & 0xFF;
924
925 if (nand_chip->options & NAND_BUSWIDTH_16) {
926
927 ret = *(uint16_t *)(host->data_buf + host->buf_start);
928
929 host->buf_start += 2;
930 } else {
931 ret = *(uint8_t *)(host->data_buf + host->buf_start);
932 host->buf_start++;
933 }
934
935 dev_dbg(host->dev, "%s: ret=0x%hhx (start=%u)\n", __func__, ret, host->buf_start);
936 return ret;
937}
938
939static uint16_t mxc_nand_read_word(struct mtd_info *mtd)
940{
941 struct nand_chip *nand_chip = mtd_to_nand(mtd);
942 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
943 uint16_t ret;
944
945 ret = *(uint16_t *)(host->data_buf + host->buf_start);
946 host->buf_start += 2;
947
948 return ret;
949}
950
951
952
953
954static void mxc_nand_write_buf(struct mtd_info *mtd,
955 const u_char *buf, int len)
956{
957 struct nand_chip *nand_chip = mtd_to_nand(mtd);
958 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
959 u16 col = host->buf_start;
960 int n = mtd->oobsize + mtd->writesize - col;
961
962 n = min(n, len);
963
964 memcpy(host->data_buf + col, buf, n);
965
966 host->buf_start += n;
967}
968
969
970
971
972
973static void mxc_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len)
974{
975 struct nand_chip *nand_chip = mtd_to_nand(mtd);
976 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
977 u16 col = host->buf_start;
978 int n = mtd->oobsize + mtd->writesize - col;
979
980 n = min(n, len);
981
982 memcpy(buf, host->data_buf + col, n);
983
984 host->buf_start += n;
985}
986
987
988
989static void mxc_nand_select_chip_v1_v3(struct mtd_info *mtd, int chip)
990{
991 struct nand_chip *nand_chip = mtd_to_nand(mtd);
992 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
993
994 if (chip == -1) {
995
996 if (host->clk_act) {
997 clk_disable_unprepare(host->clk);
998 host->clk_act = 0;
999 }
1000 return;
1001 }
1002
1003 if (!host->clk_act) {
1004
1005 clk_prepare_enable(host->clk);
1006 host->clk_act = 1;
1007 }
1008}
1009
1010static void mxc_nand_select_chip_v2(struct mtd_info *mtd, int chip)
1011{
1012 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1013 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1014
1015 if (chip == -1) {
1016
1017 if (host->clk_act) {
1018 clk_disable_unprepare(host->clk);
1019 host->clk_act = 0;
1020 }
1021 return;
1022 }
1023
1024 if (!host->clk_act) {
1025
1026 clk_prepare_enable(host->clk);
1027 host->clk_act = 1;
1028 }
1029
1030 host->active_cs = chip;
1031 writew(host->active_cs << 4, NFC_V1_V2_BUF_ADDR);
1032}
1033
1034#define MXC_V1_ECCBYTES 5
1035
1036static int mxc_v1_ooblayout_ecc(struct mtd_info *mtd, int section,
1037 struct mtd_oob_region *oobregion)
1038{
1039 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1040
1041 if (section >= nand_chip->ecc.steps)
1042 return -ERANGE;
1043
1044 oobregion->offset = (section * 16) + 6;
1045 oobregion->length = MXC_V1_ECCBYTES;
1046
1047 return 0;
1048}
1049
1050static int mxc_v1_ooblayout_free(struct mtd_info *mtd, int section,
1051 struct mtd_oob_region *oobregion)
1052{
1053 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1054
1055 if (section > nand_chip->ecc.steps)
1056 return -ERANGE;
1057
1058 if (!section) {
1059 if (mtd->writesize <= 512) {
1060 oobregion->offset = 0;
1061 oobregion->length = 5;
1062 } else {
1063 oobregion->offset = 2;
1064 oobregion->length = 4;
1065 }
1066 } else {
1067 oobregion->offset = ((section - 1) * 16) + MXC_V1_ECCBYTES + 6;
1068 if (section < nand_chip->ecc.steps)
1069 oobregion->length = (section * 16) + 6 -
1070 oobregion->offset;
1071 else
1072 oobregion->length = mtd->oobsize - oobregion->offset;
1073 }
1074
1075 return 0;
1076}
1077
1078static const struct mtd_ooblayout_ops mxc_v1_ooblayout_ops = {
1079 .ecc = mxc_v1_ooblayout_ecc,
1080 .free = mxc_v1_ooblayout_free,
1081};
1082
1083static int mxc_v2_ooblayout_ecc(struct mtd_info *mtd, int section,
1084 struct mtd_oob_region *oobregion)
1085{
1086 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1087 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1088
1089 if (section >= nand_chip->ecc.steps)
1090 return -ERANGE;
1091
1092 oobregion->offset = (section * stepsize) + 7;
1093 oobregion->length = nand_chip->ecc.bytes;
1094
1095 return 0;
1096}
1097
1098static int mxc_v2_ooblayout_free(struct mtd_info *mtd, int section,
1099 struct mtd_oob_region *oobregion)
1100{
1101 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1102 int stepsize = nand_chip->ecc.bytes == 9 ? 16 : 26;
1103
1104 if (section >= nand_chip->ecc.steps)
1105 return -ERANGE;
1106
1107 if (!section) {
1108 if (mtd->writesize <= 512) {
1109 oobregion->offset = 0;
1110 oobregion->length = 5;
1111 } else {
1112 oobregion->offset = 2;
1113 oobregion->length = 4;
1114 }
1115 } else {
1116 oobregion->offset = section * stepsize;
1117 oobregion->length = 7;
1118 }
1119
1120 return 0;
1121}
1122
1123static const struct mtd_ooblayout_ops mxc_v2_ooblayout_ops = {
1124 .ecc = mxc_v2_ooblayout_ecc,
1125 .free = mxc_v2_ooblayout_free,
1126};
1127
1128
1129
1130
1131
1132
1133static int get_eccsize(struct mtd_info *mtd)
1134{
1135 int oobbytes_per_512 = 0;
1136
1137 oobbytes_per_512 = mtd->oobsize * 512 / mtd->writesize;
1138
1139 if (oobbytes_per_512 < 26)
1140 return 4;
1141 else
1142 return 8;
1143}
1144
1145static void preset_v1(struct mtd_info *mtd)
1146{
1147 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1148 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1149 uint16_t config1 = 0;
1150
1151 if (nand_chip->ecc.mode == NAND_ECC_HW && mtd->writesize)
1152 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1153
1154 if (!host->devtype_data->irqpending_quirk)
1155 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1156
1157 host->eccsize = 1;
1158
1159 writew(config1, NFC_V1_V2_CONFIG1);
1160
1161
1162
1163 writew(0x2, NFC_V1_V2_CONFIG);
1164
1165
1166 writew(0x0, NFC_V1_UNLOCKSTART_BLKADDR);
1167 writew(0xffff, NFC_V1_UNLOCKEND_BLKADDR);
1168
1169
1170 writew(0x4, NFC_V1_V2_WRPROT);
1171}
1172
1173static int mxc_nand_v2_setup_data_interface(struct mtd_info *mtd, int csline,
1174 const struct nand_data_interface *conf)
1175{
1176 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1177 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1178 int tRC_min_ns, tRC_ps, ret;
1179 unsigned long rate, rate_round;
1180 const struct nand_sdr_timings *timings;
1181 u16 config1;
1182
1183 timings = nand_get_sdr_timings(conf);
1184 if (IS_ERR(timings))
1185 return -ENOTSUPP;
1186
1187 config1 = readw(NFC_V1_V2_CONFIG1);
1188
1189 tRC_min_ns = timings->tRC_min / 1000;
1190 rate = 1000000000 / tRC_min_ns;
1191
1192
1193
1194
1195
1196
1197
1198 if (tRC_min_ns < 30) {
1199 rate_round = clk_round_rate(host->clk, rate);
1200 config1 |= NFC_V2_CONFIG1_ONE_CYCLE;
1201 tRC_ps = 1000000000 / (rate_round / 1000);
1202 } else {
1203 rate *= 2;
1204 rate_round = clk_round_rate(host->clk, rate);
1205 config1 &= ~NFC_V2_CONFIG1_ONE_CYCLE;
1206 tRC_ps = 1000000000 / (rate_round / 1000 / 2);
1207 }
1208
1209
1210
1211
1212
1213 if (timings->tCLS_min > tRC_ps - 1000 ||
1214 timings->tCLH_min > tRC_ps - 2000 ||
1215 timings->tCS_min > tRC_ps - 1000 ||
1216 timings->tCH_min > tRC_ps - 2000 ||
1217 timings->tWP_min > tRC_ps - 1500 ||
1218 timings->tALS_min > tRC_ps ||
1219 timings->tALH_min > tRC_ps - 3000 ||
1220 timings->tDS_min > tRC_ps ||
1221 timings->tDH_min > tRC_ps - 5000 ||
1222 timings->tWC_min > 2 * tRC_ps ||
1223 timings->tWH_min > tRC_ps - 2500 ||
1224 timings->tRR_min > 6 * tRC_ps ||
1225 timings->tRP_min > 3 * tRC_ps / 2 ||
1226 timings->tRC_min > 2 * tRC_ps ||
1227 timings->tREH_min > (tRC_ps / 2) - 2500) {
1228 dev_dbg(host->dev, "Timing out of bounds\n");
1229 return -EINVAL;
1230 }
1231
1232 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
1233 return 0;
1234
1235 ret = clk_set_rate(host->clk, rate);
1236 if (ret)
1237 return ret;
1238
1239 writew(config1, NFC_V1_V2_CONFIG1);
1240
1241 dev_dbg(host->dev, "Setting rate to %ldHz, %s mode\n", rate_round,
1242 config1 & NFC_V2_CONFIG1_ONE_CYCLE ? "One cycle (EDO)" :
1243 "normal");
1244
1245 return 0;
1246}
1247
1248static void preset_v2(struct mtd_info *mtd)
1249{
1250 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1251 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1252 uint16_t config1 = 0;
1253
1254 config1 |= NFC_V2_CONFIG1_FP_INT;
1255
1256 if (!host->devtype_data->irqpending_quirk)
1257 config1 |= NFC_V1_V2_CONFIG1_INT_MSK;
1258
1259 if (mtd->writesize) {
1260 uint16_t pages_per_block = mtd->erasesize / mtd->writesize;
1261
1262 if (nand_chip->ecc.mode == NAND_ECC_HW)
1263 config1 |= NFC_V1_V2_CONFIG1_ECC_EN;
1264
1265 host->eccsize = get_eccsize(mtd);
1266 if (host->eccsize == 4)
1267 config1 |= NFC_V2_CONFIG1_ECC_MODE_4;
1268
1269 config1 |= NFC_V2_CONFIG1_PPB(ffs(pages_per_block) - 6);
1270 } else {
1271 host->eccsize = 1;
1272 }
1273
1274 writew(config1, NFC_V1_V2_CONFIG1);
1275
1276
1277
1278 writew(0x2, NFC_V1_V2_CONFIG);
1279
1280
1281 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR0);
1282 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR1);
1283 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR2);
1284 writew(0x0, NFC_V21_UNLOCKSTART_BLKADDR3);
1285 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR0);
1286 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR1);
1287 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR2);
1288 writew(0xffff, NFC_V21_UNLOCKEND_BLKADDR3);
1289
1290
1291 writew(0x4, NFC_V1_V2_WRPROT);
1292}
1293
1294static void preset_v3(struct mtd_info *mtd)
1295{
1296 struct nand_chip *chip = mtd_to_nand(mtd);
1297 struct mxc_nand_host *host = nand_get_controller_data(chip);
1298 uint32_t config2, config3;
1299 int i, addr_phases;
1300
1301 writel(NFC_V3_CONFIG1_RBA(0), NFC_V3_CONFIG1);
1302 writel(NFC_V3_IPC_CREQ, NFC_V3_IPC);
1303
1304
1305 writel(NFC_V3_WRPROT_BLS_UNLOCK | NFC_V3_WRPROT_UNLOCK,
1306 NFC_V3_WRPROT);
1307
1308
1309 for (i = 0; i < NAND_MAX_CHIPS; i++)
1310 writel(0xffff << 16, NFC_V3_WRPROT_UNLOCK_BLK_ADD0 + (i << 2));
1311
1312 writel(0, NFC_V3_IPC);
1313
1314 config2 = NFC_V3_CONFIG2_ONE_CYCLE |
1315 NFC_V3_CONFIG2_2CMD_PHASES |
1316 NFC_V3_CONFIG2_SPAS(mtd->oobsize >> 1) |
1317 NFC_V3_CONFIG2_ST_CMD(0x70) |
1318 NFC_V3_CONFIG2_INT_MSK |
1319 NFC_V3_CONFIG2_NUM_ADDR_PHASE0;
1320
1321 addr_phases = fls(chip->pagemask) >> 3;
1322
1323 if (mtd->writesize == 2048) {
1324 config2 |= NFC_V3_CONFIG2_PS_2048;
1325 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1326 } else if (mtd->writesize == 4096) {
1327 config2 |= NFC_V3_CONFIG2_PS_4096;
1328 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases);
1329 } else {
1330 config2 |= NFC_V3_CONFIG2_PS_512;
1331 config2 |= NFC_V3_CONFIG2_NUM_ADDR_PHASE1(addr_phases - 1);
1332 }
1333
1334 if (mtd->writesize) {
1335 if (chip->ecc.mode == NAND_ECC_HW)
1336 config2 |= NFC_V3_CONFIG2_ECC_EN;
1337
1338 config2 |= NFC_V3_CONFIG2_PPB(
1339 ffs(mtd->erasesize / mtd->writesize) - 6,
1340 host->devtype_data->ppb_shift);
1341 host->eccsize = get_eccsize(mtd);
1342 if (host->eccsize == 8)
1343 config2 |= NFC_V3_CONFIG2_ECC_MODE_8;
1344 }
1345
1346 writel(config2, NFC_V3_CONFIG2);
1347
1348 config3 = NFC_V3_CONFIG3_NUM_OF_DEVICES(0) |
1349 NFC_V3_CONFIG3_NO_SDMA |
1350 NFC_V3_CONFIG3_RBB_MODE |
1351 NFC_V3_CONFIG3_SBB(6) |
1352 NFC_V3_CONFIG3_ADD_OP(0);
1353
1354 if (!(chip->options & NAND_BUSWIDTH_16))
1355 config3 |= NFC_V3_CONFIG3_FW8;
1356
1357 writel(config3, NFC_V3_CONFIG3);
1358
1359 writel(0, NFC_V3_DELAY_LINE);
1360}
1361
1362
1363
1364static void mxc_nand_command(struct mtd_info *mtd, unsigned command,
1365 int column, int page_addr)
1366{
1367 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1368 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1369
1370 dev_dbg(host->dev, "mxc_nand_command (cmd = 0x%x, col = 0x%x, page = 0x%x)\n",
1371 command, column, page_addr);
1372
1373
1374 host->status_request = false;
1375
1376
1377 switch (command) {
1378 case NAND_CMD_RESET:
1379 host->devtype_data->preset(mtd);
1380 host->devtype_data->send_cmd(host, command, false);
1381 break;
1382
1383 case NAND_CMD_STATUS:
1384 host->buf_start = 0;
1385 host->status_request = true;
1386
1387 host->devtype_data->send_cmd(host, command, true);
1388 WARN_ONCE(column != -1 || page_addr != -1,
1389 "Unexpected column/row value (cmd=%u, col=%d, row=%d)\n",
1390 command, column, page_addr);
1391 mxc_do_addr_cycle(mtd, column, page_addr);
1392 break;
1393
1394 case NAND_CMD_READID:
1395 host->devtype_data->send_cmd(host, command, true);
1396 mxc_do_addr_cycle(mtd, column, page_addr);
1397 host->devtype_data->send_read_id(host);
1398 host->buf_start = 0;
1399 break;
1400
1401 case NAND_CMD_ERASE1:
1402 case NAND_CMD_ERASE2:
1403 host->devtype_data->send_cmd(host, command, false);
1404 WARN_ONCE(column != -1,
1405 "Unexpected column value (cmd=%u, col=%d)\n",
1406 command, column);
1407 mxc_do_addr_cycle(mtd, column, page_addr);
1408
1409 break;
1410 case NAND_CMD_PARAM:
1411 host->devtype_data->send_cmd(host, command, false);
1412 mxc_do_addr_cycle(mtd, column, page_addr);
1413 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1414 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1415 host->buf_start = 0;
1416 break;
1417 default:
1418 WARN_ONCE(1, "Unimplemented command (cmd=%u)\n",
1419 command);
1420 break;
1421 }
1422}
1423
1424static int mxc_nand_set_features(struct mtd_info *mtd, struct nand_chip *chip,
1425 int addr, u8 *subfeature_param)
1426{
1427 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1428 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1429 int i;
1430
1431 host->buf_start = 0;
1432
1433 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1434 chip->write_byte(mtd, subfeature_param[i]);
1435
1436 memcpy32_toio(host->main_area0, host->data_buf, mtd->writesize);
1437 host->devtype_data->send_cmd(host, NAND_CMD_SET_FEATURES, false);
1438 mxc_do_addr_cycle(mtd, addr, -1);
1439 host->devtype_data->send_page(mtd, NFC_INPUT);
1440
1441 return 0;
1442}
1443
1444static int mxc_nand_get_features(struct mtd_info *mtd, struct nand_chip *chip,
1445 int addr, u8 *subfeature_param)
1446{
1447 struct nand_chip *nand_chip = mtd_to_nand(mtd);
1448 struct mxc_nand_host *host = nand_get_controller_data(nand_chip);
1449 int i;
1450
1451 host->devtype_data->send_cmd(host, NAND_CMD_GET_FEATURES, false);
1452 mxc_do_addr_cycle(mtd, addr, -1);
1453 host->devtype_data->send_page(mtd, NFC_OUTPUT);
1454 memcpy32_fromio(host->data_buf, host->main_area0, 512);
1455 host->buf_start = 0;
1456
1457 for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
1458 *subfeature_param++ = chip->read_byte(mtd);
1459
1460 return 0;
1461}
1462
1463
1464
1465
1466
1467static uint8_t bbt_pattern[] = { 'B', 'b', 't', '0' };
1468static uint8_t mirror_pattern[] = { '1', 't', 'b', 'B' };
1469
1470static struct nand_bbt_descr bbt_main_descr = {
1471 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1472 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1473 .offs = 0,
1474 .len = 4,
1475 .veroffs = 4,
1476 .maxblocks = 4,
1477 .pattern = bbt_pattern,
1478};
1479
1480static struct nand_bbt_descr bbt_mirror_descr = {
1481 .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
1482 | NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
1483 .offs = 0,
1484 .len = 4,
1485 .veroffs = 4,
1486 .maxblocks = 4,
1487 .pattern = mirror_pattern,
1488};
1489
1490
1491static const struct mxc_nand_devtype_data imx21_nand_devtype_data = {
1492 .preset = preset_v1,
1493 .read_page = mxc_nand_read_page_v1,
1494 .send_cmd = send_cmd_v1_v2,
1495 .send_addr = send_addr_v1_v2,
1496 .send_page = send_page_v1,
1497 .send_read_id = send_read_id_v1_v2,
1498 .get_dev_status = get_dev_status_v1_v2,
1499 .check_int = check_int_v1_v2,
1500 .irq_control = irq_control_v1_v2,
1501 .get_ecc_status = get_ecc_status_v1,
1502 .ooblayout = &mxc_v1_ooblayout_ops,
1503 .select_chip = mxc_nand_select_chip_v1_v3,
1504 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1505 .irqpending_quirk = 1,
1506 .needs_ip = 0,
1507 .regs_offset = 0xe00,
1508 .spare0_offset = 0x800,
1509 .spare_len = 16,
1510 .eccbytes = 3,
1511 .eccsize = 1,
1512};
1513
1514
1515static const struct mxc_nand_devtype_data imx27_nand_devtype_data = {
1516 .preset = preset_v1,
1517 .read_page = mxc_nand_read_page_v1,
1518 .send_cmd = send_cmd_v1_v2,
1519 .send_addr = send_addr_v1_v2,
1520 .send_page = send_page_v1,
1521 .send_read_id = send_read_id_v1_v2,
1522 .get_dev_status = get_dev_status_v1_v2,
1523 .check_int = check_int_v1_v2,
1524 .irq_control = irq_control_v1_v2,
1525 .get_ecc_status = get_ecc_status_v1,
1526 .ooblayout = &mxc_v1_ooblayout_ops,
1527 .select_chip = mxc_nand_select_chip_v1_v3,
1528 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1529 .irqpending_quirk = 0,
1530 .needs_ip = 0,
1531 .regs_offset = 0xe00,
1532 .spare0_offset = 0x800,
1533 .axi_offset = 0,
1534 .spare_len = 16,
1535 .eccbytes = 3,
1536 .eccsize = 1,
1537};
1538
1539
1540static const struct mxc_nand_devtype_data imx25_nand_devtype_data = {
1541 .preset = preset_v2,
1542 .read_page = mxc_nand_read_page_v2_v3,
1543 .send_cmd = send_cmd_v1_v2,
1544 .send_addr = send_addr_v1_v2,
1545 .send_page = send_page_v2,
1546 .send_read_id = send_read_id_v1_v2,
1547 .get_dev_status = get_dev_status_v1_v2,
1548 .check_int = check_int_v1_v2,
1549 .irq_control = irq_control_v1_v2,
1550 .get_ecc_status = get_ecc_status_v2,
1551 .ooblayout = &mxc_v2_ooblayout_ops,
1552 .select_chip = mxc_nand_select_chip_v2,
1553 .setup_data_interface = mxc_nand_v2_setup_data_interface,
1554 .enable_hwecc = mxc_nand_enable_hwecc_v1_v2,
1555 .irqpending_quirk = 0,
1556 .needs_ip = 0,
1557 .regs_offset = 0x1e00,
1558 .spare0_offset = 0x1000,
1559 .axi_offset = 0,
1560 .spare_len = 64,
1561 .eccbytes = 9,
1562 .eccsize = 0,
1563};
1564
1565
1566static const struct mxc_nand_devtype_data imx51_nand_devtype_data = {
1567 .preset = preset_v3,
1568 .read_page = mxc_nand_read_page_v2_v3,
1569 .send_cmd = send_cmd_v3,
1570 .send_addr = send_addr_v3,
1571 .send_page = send_page_v3,
1572 .send_read_id = send_read_id_v3,
1573 .get_dev_status = get_dev_status_v3,
1574 .check_int = check_int_v3,
1575 .irq_control = irq_control_v3,
1576 .get_ecc_status = get_ecc_status_v3,
1577 .ooblayout = &mxc_v2_ooblayout_ops,
1578 .select_chip = mxc_nand_select_chip_v1_v3,
1579 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1580 .irqpending_quirk = 0,
1581 .needs_ip = 1,
1582 .regs_offset = 0,
1583 .spare0_offset = 0x1000,
1584 .axi_offset = 0x1e00,
1585 .spare_len = 64,
1586 .eccbytes = 0,
1587 .eccsize = 0,
1588 .ppb_shift = 7,
1589};
1590
1591
1592static const struct mxc_nand_devtype_data imx53_nand_devtype_data = {
1593 .preset = preset_v3,
1594 .read_page = mxc_nand_read_page_v2_v3,
1595 .send_cmd = send_cmd_v3,
1596 .send_addr = send_addr_v3,
1597 .send_page = send_page_v3,
1598 .send_read_id = send_read_id_v3,
1599 .get_dev_status = get_dev_status_v3,
1600 .check_int = check_int_v3,
1601 .irq_control = irq_control_v3,
1602 .get_ecc_status = get_ecc_status_v3,
1603 .ooblayout = &mxc_v2_ooblayout_ops,
1604 .select_chip = mxc_nand_select_chip_v1_v3,
1605 .enable_hwecc = mxc_nand_enable_hwecc_v3,
1606 .irqpending_quirk = 0,
1607 .needs_ip = 1,
1608 .regs_offset = 0,
1609 .spare0_offset = 0x1000,
1610 .axi_offset = 0x1e00,
1611 .spare_len = 64,
1612 .eccbytes = 0,
1613 .eccsize = 0,
1614 .ppb_shift = 8,
1615};
1616
1617static inline int is_imx21_nfc(struct mxc_nand_host *host)
1618{
1619 return host->devtype_data == &imx21_nand_devtype_data;
1620}
1621
1622static inline int is_imx27_nfc(struct mxc_nand_host *host)
1623{
1624 return host->devtype_data == &imx27_nand_devtype_data;
1625}
1626
1627static inline int is_imx25_nfc(struct mxc_nand_host *host)
1628{
1629 return host->devtype_data == &imx25_nand_devtype_data;
1630}
1631
1632static inline int is_imx51_nfc(struct mxc_nand_host *host)
1633{
1634 return host->devtype_data == &imx51_nand_devtype_data;
1635}
1636
1637static inline int is_imx53_nfc(struct mxc_nand_host *host)
1638{
1639 return host->devtype_data == &imx53_nand_devtype_data;
1640}
1641
1642static const struct platform_device_id mxcnd_devtype[] = {
1643 {
1644 .name = "imx21-nand",
1645 .driver_data = (kernel_ulong_t) &imx21_nand_devtype_data,
1646 }, {
1647 .name = "imx27-nand",
1648 .driver_data = (kernel_ulong_t) &imx27_nand_devtype_data,
1649 }, {
1650 .name = "imx25-nand",
1651 .driver_data = (kernel_ulong_t) &imx25_nand_devtype_data,
1652 }, {
1653 .name = "imx51-nand",
1654 .driver_data = (kernel_ulong_t) &imx51_nand_devtype_data,
1655 }, {
1656 .name = "imx53-nand",
1657 .driver_data = (kernel_ulong_t) &imx53_nand_devtype_data,
1658 }, {
1659
1660 }
1661};
1662MODULE_DEVICE_TABLE(platform, mxcnd_devtype);
1663
1664#ifdef CONFIG_OF
1665static const struct of_device_id mxcnd_dt_ids[] = {
1666 {
1667 .compatible = "fsl,imx21-nand",
1668 .data = &imx21_nand_devtype_data,
1669 }, {
1670 .compatible = "fsl,imx27-nand",
1671 .data = &imx27_nand_devtype_data,
1672 }, {
1673 .compatible = "fsl,imx25-nand",
1674 .data = &imx25_nand_devtype_data,
1675 }, {
1676 .compatible = "fsl,imx51-nand",
1677 .data = &imx51_nand_devtype_data,
1678 }, {
1679 .compatible = "fsl,imx53-nand",
1680 .data = &imx53_nand_devtype_data,
1681 },
1682 { }
1683};
1684MODULE_DEVICE_TABLE(of, mxcnd_dt_ids);
1685
1686static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1687{
1688 struct device_node *np = host->dev->of_node;
1689 const struct of_device_id *of_id =
1690 of_match_device(mxcnd_dt_ids, host->dev);
1691
1692 if (!np)
1693 return 1;
1694
1695 host->devtype_data = of_id->data;
1696
1697 return 0;
1698}
1699#else
1700static int __init mxcnd_probe_dt(struct mxc_nand_host *host)
1701{
1702 return 1;
1703}
1704#endif
1705
1706static int mxcnd_probe(struct platform_device *pdev)
1707{
1708 struct nand_chip *this;
1709 struct mtd_info *mtd;
1710 struct mxc_nand_host *host;
1711 struct resource *res;
1712 int err = 0;
1713
1714
1715 host = devm_kzalloc(&pdev->dev, sizeof(struct mxc_nand_host),
1716 GFP_KERNEL);
1717 if (!host)
1718 return -ENOMEM;
1719
1720
1721 host->data_buf = devm_kzalloc(&pdev->dev, PAGE_SIZE, GFP_KERNEL);
1722 if (!host->data_buf)
1723 return -ENOMEM;
1724
1725 host->dev = &pdev->dev;
1726
1727 this = &host->nand;
1728 mtd = nand_to_mtd(this);
1729 mtd->dev.parent = &pdev->dev;
1730 mtd->name = DRIVER_NAME;
1731
1732
1733 this->chip_delay = 5;
1734
1735 nand_set_controller_data(this, host);
1736 nand_set_flash_node(this, pdev->dev.of_node),
1737 this->dev_ready = mxc_nand_dev_ready;
1738 this->cmdfunc = mxc_nand_command;
1739 this->read_byte = mxc_nand_read_byte;
1740 this->read_word = mxc_nand_read_word;
1741 this->write_buf = mxc_nand_write_buf;
1742 this->read_buf = mxc_nand_read_buf;
1743 this->set_features = mxc_nand_set_features;
1744 this->get_features = mxc_nand_get_features;
1745
1746 host->clk = devm_clk_get(&pdev->dev, NULL);
1747 if (IS_ERR(host->clk))
1748 return PTR_ERR(host->clk);
1749
1750 err = mxcnd_probe_dt(host);
1751 if (err > 0) {
1752 struct mxc_nand_platform_data *pdata =
1753 dev_get_platdata(&pdev->dev);
1754 if (pdata) {
1755 host->pdata = *pdata;
1756 host->devtype_data = (struct mxc_nand_devtype_data *)
1757 pdev->id_entry->driver_data;
1758 } else {
1759 err = -ENODEV;
1760 }
1761 }
1762 if (err < 0)
1763 return err;
1764
1765 this->setup_data_interface = host->devtype_data->setup_data_interface;
1766
1767 if (host->devtype_data->needs_ip) {
1768 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1769 host->regs_ip = devm_ioremap_resource(&pdev->dev, res);
1770 if (IS_ERR(host->regs_ip))
1771 return PTR_ERR(host->regs_ip);
1772
1773 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
1774 } else {
1775 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1776 }
1777
1778 host->base = devm_ioremap_resource(&pdev->dev, res);
1779 if (IS_ERR(host->base))
1780 return PTR_ERR(host->base);
1781
1782 host->main_area0 = host->base;
1783
1784 if (host->devtype_data->regs_offset)
1785 host->regs = host->base + host->devtype_data->regs_offset;
1786 host->spare0 = host->base + host->devtype_data->spare0_offset;
1787 if (host->devtype_data->axi_offset)
1788 host->regs_axi = host->base + host->devtype_data->axi_offset;
1789
1790 this->ecc.bytes = host->devtype_data->eccbytes;
1791 host->eccsize = host->devtype_data->eccsize;
1792
1793 this->select_chip = host->devtype_data->select_chip;
1794 this->ecc.size = 512;
1795 mtd_set_ooblayout(mtd, host->devtype_data->ooblayout);
1796
1797 if (host->pdata.hw_ecc) {
1798 this->ecc.mode = NAND_ECC_HW;
1799 } else {
1800 this->ecc.mode = NAND_ECC_SOFT;
1801 this->ecc.algo = NAND_ECC_HAMMING;
1802 }
1803
1804
1805 if (host->pdata.width == 2)
1806 this->options |= NAND_BUSWIDTH_16;
1807
1808
1809 if (host->pdata.flash_bbt)
1810 this->bbt_options |= NAND_BBT_USE_FLASH;
1811
1812 init_completion(&host->op_completion);
1813
1814 host->irq = platform_get_irq(pdev, 0);
1815 if (host->irq < 0)
1816 return host->irq;
1817
1818
1819
1820
1821
1822
1823 host->devtype_data->irq_control(host, 0);
1824
1825 err = devm_request_irq(&pdev->dev, host->irq, mxc_nfc_irq,
1826 0, DRIVER_NAME, host);
1827 if (err)
1828 return err;
1829
1830 err = clk_prepare_enable(host->clk);
1831 if (err)
1832 return err;
1833 host->clk_act = 1;
1834
1835
1836
1837
1838
1839
1840 if (host->devtype_data->irqpending_quirk) {
1841 disable_irq_nosync(host->irq);
1842 host->devtype_data->irq_control(host, 1);
1843 }
1844
1845
1846 err = nand_scan_ident(mtd, is_imx25_nfc(host) ? 4 : 1, NULL);
1847 if (err)
1848 goto escan;
1849
1850 switch (this->ecc.mode) {
1851 case NAND_ECC_HW:
1852 this->ecc.read_page = mxc_nand_read_page;
1853 this->ecc.read_page_raw = mxc_nand_read_page_raw;
1854 this->ecc.read_oob = mxc_nand_read_oob;
1855 this->ecc.write_page = mxc_nand_write_page_ecc;
1856 this->ecc.write_page_raw = mxc_nand_write_page_raw;
1857 this->ecc.write_oob = mxc_nand_write_oob;
1858 break;
1859
1860 case NAND_ECC_SOFT:
1861 break;
1862
1863 default:
1864 err = -EINVAL;
1865 goto escan;
1866 }
1867
1868 if (this->bbt_options & NAND_BBT_USE_FLASH) {
1869 this->bbt_td = &bbt_main_descr;
1870 this->bbt_md = &bbt_mirror_descr;
1871 }
1872
1873
1874 devm_kfree(&pdev->dev, (void *)host->data_buf);
1875 host->data_buf = devm_kzalloc(&pdev->dev, mtd->writesize + mtd->oobsize,
1876 GFP_KERNEL);
1877 if (!host->data_buf) {
1878 err = -ENOMEM;
1879 goto escan;
1880 }
1881
1882
1883 host->devtype_data->preset(mtd);
1884
1885 if (!this->ecc.bytes) {
1886 if (host->eccsize == 8)
1887 this->ecc.bytes = 18;
1888 else if (host->eccsize == 4)
1889 this->ecc.bytes = 9;
1890 }
1891
1892
1893
1894
1895
1896
1897
1898
1899 host->used_oobsize = min(mtd->oobsize, 218U);
1900
1901 if (this->ecc.mode == NAND_ECC_HW) {
1902 if (is_imx21_nfc(host) || is_imx27_nfc(host))
1903 this->ecc.strength = 1;
1904 else
1905 this->ecc.strength = (host->eccsize == 4) ? 4 : 8;
1906 }
1907
1908
1909 err = nand_scan_tail(mtd);
1910 if (err)
1911 goto escan;
1912
1913
1914 err = mtd_device_parse_register(mtd, part_probes, NULL,
1915 host->pdata.parts,
1916 host->pdata.nr_parts);
1917 if (err)
1918 goto cleanup_nand;
1919
1920 platform_set_drvdata(pdev, host);
1921
1922 return 0;
1923
1924cleanup_nand:
1925 nand_cleanup(this);
1926escan:
1927 if (host->clk_act)
1928 clk_disable_unprepare(host->clk);
1929
1930 return err;
1931}
1932
1933static int mxcnd_remove(struct platform_device *pdev)
1934{
1935 struct mxc_nand_host *host = platform_get_drvdata(pdev);
1936
1937 nand_release(nand_to_mtd(&host->nand));
1938 if (host->clk_act)
1939 clk_disable_unprepare(host->clk);
1940
1941 return 0;
1942}
1943
1944static struct platform_driver mxcnd_driver = {
1945 .driver = {
1946 .name = DRIVER_NAME,
1947 .of_match_table = of_match_ptr(mxcnd_dt_ids),
1948 },
1949 .id_table = mxcnd_devtype,
1950 .probe = mxcnd_probe,
1951 .remove = mxcnd_remove,
1952};
1953module_platform_driver(mxcnd_driver);
1954
1955MODULE_AUTHOR("Freescale Semiconductor, Inc.");
1956MODULE_DESCRIPTION("MXC NAND MTD driver");
1957MODULE_LICENSE("GPL");
1958