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9#include <linux/io.h>
10#include <linux/of.h>
11#include <linux/clk.h>
12#include <linux/iopoll.h>
13#include <linux/module.h>
14#include <linux/mtd/rawnand.h>
15#include <linux/dmaengine.h>
16#include <linux/dma-mapping.h>
17#include <linux/platform_device.h>
18
19
20#define PBUS_CMD 0
21#define PBUS_ADDR 4
22#define PBUS_DATA 8
23
24
25#define NFC_STATUS 0x00
26#define NFC_FLASH_CMD 0x04
27#define NFC_DEVICE_CFG 0x08
28#define NFC_TIMING1 0x0c
29#define NFC_TIMING2 0x10
30#define NFC_XFER_CFG 0x14
31#define NFC_PKT_0_CFG 0x18
32#define NFC_PKT_N_CFG 0x1c
33#define NFC_BB_CFG 0x20
34#define NFC_ADDR_PAGE 0x24
35#define NFC_ADDR_OFFSET 0x28
36#define NFC_XFER_STATUS 0x2c
37
38
39#define CMD_READY BIT(31)
40
41
42#define NFC_READ 1
43#define NFC_WRITE 2
44
45
46#define PAGE_IS_EMPTY BIT(16)
47
48
49#define METADATA 0x000
50#define ERROR_REPORT 0x1c0
51
52
53
54
55
56
57
58#define ERR_COUNT_PKT_0(v) (((v) >> 0) & 0x3f)
59#define ERR_COUNT_PKT_N(v) (((v) >> 8) & 0x3f)
60#define DECODE_FAIL_PKT_0(v) (((v) & BIT(7)) == 0)
61#define DECODE_FAIL_PKT_N(v) (((v) & BIT(15)) == 0)
62
63
64#define PBUS_CS_CTRL 0x83c
65#define PBUS_PAD_MODE 0x8f0
66
67
68#define PBUS_IORDY BIT(31)
69
70
71
72
73
74
75
76#define MODE_RAW 0
77#define MODE_NFC BIT(31)
78
79#define METADATA_SIZE 4
80#define BBM_SIZE 6
81#define FIELD_ORDER 15
82
83#define MAX_CS 4
84
85struct tango_nfc {
86 struct nand_hw_control hw;
87 void __iomem *reg_base;
88 void __iomem *mem_base;
89 void __iomem *pbus_base;
90 struct tango_chip *chips[MAX_CS];
91 struct dma_chan *chan;
92 int freq_kHz;
93};
94
95#define to_tango_nfc(ptr) container_of(ptr, struct tango_nfc, hw)
96
97struct tango_chip {
98 struct nand_chip nand_chip;
99 void __iomem *base;
100 u32 timing1;
101 u32 timing2;
102 u32 xfer_cfg;
103 u32 pkt_0_cfg;
104 u32 pkt_n_cfg;
105 u32 bb_cfg;
106};
107
108#define to_tango_chip(ptr) container_of(ptr, struct tango_chip, nand_chip)
109
110#define XFER_CFG(cs, page_count, steps, metadata_size) \
111 ((cs) << 24 | (page_count) << 16 | (steps) << 8 | (metadata_size))
112
113#define PKT_CFG(size, strength) ((size) << 16 | (strength))
114
115#define BB_CFG(bb_offset, bb_size) ((bb_offset) << 16 | (bb_size))
116
117#define TIMING(t0, t1, t2, t3) ((t0) << 24 | (t1) << 16 | (t2) << 8 | (t3))
118
119static void tango_cmd_ctrl(struct mtd_info *mtd, int dat, unsigned int ctrl)
120{
121 struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
122
123 if (ctrl & NAND_CLE)
124 writeb_relaxed(dat, tchip->base + PBUS_CMD);
125
126 if (ctrl & NAND_ALE)
127 writeb_relaxed(dat, tchip->base + PBUS_ADDR);
128}
129
130static int tango_dev_ready(struct mtd_info *mtd)
131{
132 struct nand_chip *chip = mtd_to_nand(mtd);
133 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
134
135 return readl_relaxed(nfc->pbus_base + PBUS_CS_CTRL) & PBUS_IORDY;
136}
137
138static u8 tango_read_byte(struct mtd_info *mtd)
139{
140 struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
141
142 return readb_relaxed(tchip->base + PBUS_DATA);
143}
144
145static void tango_read_buf(struct mtd_info *mtd, u8 *buf, int len)
146{
147 struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
148
149 ioread8_rep(tchip->base + PBUS_DATA, buf, len);
150}
151
152static void tango_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
153{
154 struct tango_chip *tchip = to_tango_chip(mtd_to_nand(mtd));
155
156 iowrite8_rep(tchip->base + PBUS_DATA, buf, len);
157}
158
159static void tango_select_chip(struct mtd_info *mtd, int idx)
160{
161 struct nand_chip *chip = mtd_to_nand(mtd);
162 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
163 struct tango_chip *tchip = to_tango_chip(chip);
164
165 if (idx < 0)
166 return;
167
168 writel_relaxed(tchip->timing1, nfc->reg_base + NFC_TIMING1);
169 writel_relaxed(tchip->timing2, nfc->reg_base + NFC_TIMING2);
170 writel_relaxed(tchip->xfer_cfg, nfc->reg_base + NFC_XFER_CFG);
171 writel_relaxed(tchip->pkt_0_cfg, nfc->reg_base + NFC_PKT_0_CFG);
172 writel_relaxed(tchip->pkt_n_cfg, nfc->reg_base + NFC_PKT_N_CFG);
173 writel_relaxed(tchip->bb_cfg, nfc->reg_base + NFC_BB_CFG);
174}
175
176
177
178
179
180static int check_erased_page(struct nand_chip *chip, u8 *buf)
181{
182 struct mtd_info *mtd = nand_to_mtd(chip);
183 u8 *meta = chip->oob_poi + BBM_SIZE;
184 u8 *ecc = chip->oob_poi + BBM_SIZE + METADATA_SIZE;
185 const int ecc_size = chip->ecc.bytes;
186 const int pkt_size = chip->ecc.size;
187 int i, res, meta_len, bitflips = 0;
188
189 for (i = 0; i < chip->ecc.steps; ++i) {
190 meta_len = i ? 0 : METADATA_SIZE;
191 res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
192 meta, meta_len,
193 chip->ecc.strength);
194 if (res < 0)
195 mtd->ecc_stats.failed++;
196 else
197 mtd->ecc_stats.corrected += res;
198
199 bitflips = max(res, bitflips);
200 buf += pkt_size;
201 ecc += ecc_size;
202 }
203
204 return bitflips;
205}
206
207static int decode_error_report(struct nand_chip *chip)
208{
209 u32 status, res;
210 struct mtd_info *mtd = nand_to_mtd(chip);
211 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
212
213 status = readl_relaxed(nfc->reg_base + NFC_XFER_STATUS);
214 if (status & PAGE_IS_EMPTY)
215 return 0;
216
217 res = readl_relaxed(nfc->mem_base + ERROR_REPORT);
218
219 if (DECODE_FAIL_PKT_0(res) || DECODE_FAIL_PKT_N(res))
220 return -EBADMSG;
221
222
223 mtd->ecc_stats.corrected +=
224 ERR_COUNT_PKT_0(res) + ERR_COUNT_PKT_N(res);
225
226 return max(ERR_COUNT_PKT_0(res), ERR_COUNT_PKT_N(res));
227}
228
229static void tango_dma_callback(void *arg)
230{
231 complete(arg);
232}
233
234static int do_dma(struct tango_nfc *nfc, enum dma_data_direction dir, int cmd,
235 const void *buf, int len, int page)
236{
237 void __iomem *addr = nfc->reg_base + NFC_STATUS;
238 struct dma_chan *chan = nfc->chan;
239 struct dma_async_tx_descriptor *desc;
240 enum dma_transfer_direction tdir;
241 struct scatterlist sg;
242 struct completion tx_done;
243 int err = -EIO;
244 u32 res, val;
245
246 sg_init_one(&sg, buf, len);
247 if (dma_map_sg(chan->device->dev, &sg, 1, dir) != 1)
248 return -EIO;
249
250 tdir = dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM;
251 desc = dmaengine_prep_slave_sg(chan, &sg, 1, tdir, DMA_PREP_INTERRUPT);
252 if (!desc)
253 goto dma_unmap;
254
255 desc->callback = tango_dma_callback;
256 desc->callback_param = &tx_done;
257 init_completion(&tx_done);
258
259 writel_relaxed(MODE_NFC, nfc->pbus_base + PBUS_PAD_MODE);
260
261 writel_relaxed(page, nfc->reg_base + NFC_ADDR_PAGE);
262 writel_relaxed(0, nfc->reg_base + NFC_ADDR_OFFSET);
263 writel_relaxed(cmd, nfc->reg_base + NFC_FLASH_CMD);
264
265 dmaengine_submit(desc);
266 dma_async_issue_pending(chan);
267
268 res = wait_for_completion_timeout(&tx_done, HZ);
269 if (res > 0)
270 err = readl_poll_timeout(addr, val, val & CMD_READY, 0, 1000);
271
272 writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
273
274dma_unmap:
275 dma_unmap_sg(chan->device->dev, &sg, 1, dir);
276
277 return err;
278}
279
280static int tango_read_page(struct mtd_info *mtd, struct nand_chip *chip,
281 u8 *buf, int oob_required, int page)
282{
283 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
284 int err, res, len = mtd->writesize;
285
286 if (oob_required)
287 chip->ecc.read_oob(mtd, chip, page);
288
289 err = do_dma(nfc, DMA_FROM_DEVICE, NFC_READ, buf, len, page);
290 if (err)
291 return err;
292
293 res = decode_error_report(chip);
294 if (res < 0) {
295 chip->ecc.read_oob_raw(mtd, chip, page);
296 res = check_erased_page(chip, buf);
297 }
298
299 return res;
300}
301
302static int tango_write_page(struct mtd_info *mtd, struct nand_chip *chip,
303 const u8 *buf, int oob_required, int page)
304{
305 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
306 int err, status, len = mtd->writesize;
307
308
309 if (oob_required)
310 return -ENOTSUPP;
311
312 writel_relaxed(0xffffffff, nfc->mem_base + METADATA);
313 err = do_dma(nfc, DMA_TO_DEVICE, NFC_WRITE, buf, len, page);
314 if (err)
315 return err;
316
317 status = chip->waitfunc(mtd, chip);
318 if (status & NAND_STATUS_FAIL)
319 return -EIO;
320
321 return 0;
322}
323
324static void aux_read(struct nand_chip *chip, u8 **buf, int len, int *pos)
325{
326 struct mtd_info *mtd = nand_to_mtd(chip);
327
328 *pos += len;
329
330 if (!*buf) {
331
332 nand_change_read_column_op(chip, *pos, NULL, 0, false);
333 } else {
334 tango_read_buf(mtd, *buf, len);
335 *buf += len;
336 }
337}
338
339static void aux_write(struct nand_chip *chip, const u8 **buf, int len, int *pos)
340{
341 struct mtd_info *mtd = nand_to_mtd(chip);
342
343 *pos += len;
344
345 if (!*buf) {
346
347 nand_change_write_column_op(chip, *pos, NULL, 0, false);
348 } else {
349 tango_write_buf(mtd, *buf, len);
350 *buf += len;
351 }
352}
353
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371
372
373static void raw_read(struct nand_chip *chip, u8 *buf, u8 *oob)
374{
375 struct mtd_info *mtd = nand_to_mtd(chip);
376 u8 *oob_orig = oob;
377 const int page_size = mtd->writesize;
378 const int ecc_size = chip->ecc.bytes;
379 const int pkt_size = chip->ecc.size;
380 int pos = 0;
381 int rem = page_size;
382
383 if (oob)
384 oob += BBM_SIZE;
385
386 aux_read(chip, &oob, METADATA_SIZE, &pos);
387
388 while (rem > pkt_size) {
389 aux_read(chip, &buf, pkt_size, &pos);
390 aux_read(chip, &oob, ecc_size, &pos);
391 rem = page_size - pos;
392 }
393
394 aux_read(chip, &buf, rem, &pos);
395 aux_read(chip, &oob_orig, BBM_SIZE, &pos);
396 aux_read(chip, &buf, pkt_size - rem, &pos);
397 aux_read(chip, &oob, ecc_size, &pos);
398}
399
400static void raw_write(struct nand_chip *chip, const u8 *buf, const u8 *oob)
401{
402 struct mtd_info *mtd = nand_to_mtd(chip);
403 const u8 *oob_orig = oob;
404 const int page_size = mtd->writesize;
405 const int ecc_size = chip->ecc.bytes;
406 const int pkt_size = chip->ecc.size;
407 int pos = 0;
408 int rem = page_size;
409
410 if (oob)
411 oob += BBM_SIZE;
412
413 aux_write(chip, &oob, METADATA_SIZE, &pos);
414
415 while (rem > pkt_size) {
416 aux_write(chip, &buf, pkt_size, &pos);
417 aux_write(chip, &oob, ecc_size, &pos);
418 rem = page_size - pos;
419 }
420
421 aux_write(chip, &buf, rem, &pos);
422 aux_write(chip, &oob_orig, BBM_SIZE, &pos);
423 aux_write(chip, &buf, pkt_size - rem, &pos);
424 aux_write(chip, &oob, ecc_size, &pos);
425}
426
427static int tango_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
428 u8 *buf, int oob_required, int page)
429{
430 nand_read_page_op(chip, page, 0, NULL, 0);
431 raw_read(chip, buf, chip->oob_poi);
432 return 0;
433}
434
435static int tango_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
436 const u8 *buf, int oob_required, int page)
437{
438 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
439 raw_write(chip, buf, chip->oob_poi);
440 return nand_prog_page_end_op(chip);
441}
442
443static int tango_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
444 int page)
445{
446 nand_read_page_op(chip, page, 0, NULL, 0);
447 raw_read(chip, NULL, chip->oob_poi);
448 return 0;
449}
450
451static int tango_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
452 int page)
453{
454 nand_prog_page_begin_op(chip, page, 0, NULL, 0);
455 raw_write(chip, NULL, chip->oob_poi);
456 return nand_prog_page_end_op(chip);
457}
458
459static int oob_ecc(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
460{
461 struct nand_chip *chip = mtd_to_nand(mtd);
462 struct nand_ecc_ctrl *ecc = &chip->ecc;
463
464 if (idx >= ecc->steps)
465 return -ERANGE;
466
467 res->offset = BBM_SIZE + METADATA_SIZE + ecc->bytes * idx;
468 res->length = ecc->bytes;
469
470 return 0;
471}
472
473static int oob_free(struct mtd_info *mtd, int idx, struct mtd_oob_region *res)
474{
475 return -ERANGE;
476}
477
478static const struct mtd_ooblayout_ops tango_nand_ooblayout_ops = {
479 .ecc = oob_ecc,
480 .free = oob_free,
481};
482
483static u32 to_ticks(int kHz, int ps)
484{
485 return DIV_ROUND_UP_ULL((u64)kHz * ps, NSEC_PER_SEC);
486}
487
488static int tango_set_timings(struct mtd_info *mtd, int csline,
489 const struct nand_data_interface *conf)
490{
491 const struct nand_sdr_timings *sdr = nand_get_sdr_timings(conf);
492 struct nand_chip *chip = mtd_to_nand(mtd);
493 struct tango_nfc *nfc = to_tango_nfc(chip->controller);
494 struct tango_chip *tchip = to_tango_chip(chip);
495 u32 Trdy, Textw, Twc, Twpw, Tacc, Thold, Trpw, Textr;
496 int kHz = nfc->freq_kHz;
497
498 if (IS_ERR(sdr))
499 return PTR_ERR(sdr);
500
501 if (csline == NAND_DATA_IFACE_CHECK_ONLY)
502 return 0;
503
504 Trdy = to_ticks(kHz, sdr->tCEA_max - sdr->tREA_max);
505 Textw = to_ticks(kHz, sdr->tWB_max);
506 Twc = to_ticks(kHz, sdr->tWC_min);
507 Twpw = to_ticks(kHz, sdr->tWC_min - sdr->tWP_min);
508
509 Tacc = to_ticks(kHz, sdr->tREA_max);
510 Thold = to_ticks(kHz, sdr->tREH_min);
511 Trpw = to_ticks(kHz, sdr->tRC_min - sdr->tREH_min);
512 Textr = to_ticks(kHz, sdr->tRHZ_max);
513
514 tchip->timing1 = TIMING(Trdy, Textw, Twc, Twpw);
515 tchip->timing2 = TIMING(Tacc, Thold, Trpw, Textr);
516
517 return 0;
518}
519
520static int chip_init(struct device *dev, struct device_node *np)
521{
522 u32 cs;
523 int err, res;
524 struct mtd_info *mtd;
525 struct nand_chip *chip;
526 struct tango_chip *tchip;
527 struct nand_ecc_ctrl *ecc;
528 struct tango_nfc *nfc = dev_get_drvdata(dev);
529
530 tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
531 if (!tchip)
532 return -ENOMEM;
533
534 res = of_property_count_u32_elems(np, "reg");
535 if (res < 0)
536 return res;
537
538 if (res != 1)
539 return -ENOTSUPP;
540
541 err = of_property_read_u32_index(np, "reg", 0, &cs);
542 if (err)
543 return err;
544
545 if (cs >= MAX_CS)
546 return -EINVAL;
547
548 chip = &tchip->nand_chip;
549 ecc = &chip->ecc;
550 mtd = nand_to_mtd(chip);
551
552 chip->read_byte = tango_read_byte;
553 chip->write_buf = tango_write_buf;
554 chip->read_buf = tango_read_buf;
555 chip->select_chip = tango_select_chip;
556 chip->cmd_ctrl = tango_cmd_ctrl;
557 chip->dev_ready = tango_dev_ready;
558 chip->setup_data_interface = tango_set_timings;
559 chip->options = NAND_USE_BOUNCE_BUFFER |
560 NAND_NO_SUBPAGE_WRITE |
561 NAND_WAIT_TCCS;
562 chip->controller = &nfc->hw;
563 tchip->base = nfc->pbus_base + (cs * 256);
564
565 nand_set_flash_node(chip, np);
566 mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
567 mtd->dev.parent = dev;
568
569 err = nand_scan_ident(mtd, 1, NULL);
570 if (err)
571 return err;
572
573 ecc->mode = NAND_ECC_HW;
574 ecc->algo = NAND_ECC_BCH;
575 ecc->bytes = DIV_ROUND_UP(ecc->strength * FIELD_ORDER, BITS_PER_BYTE);
576
577 ecc->read_page_raw = tango_read_page_raw;
578 ecc->write_page_raw = tango_write_page_raw;
579 ecc->read_page = tango_read_page;
580 ecc->write_page = tango_write_page;
581 ecc->read_oob = tango_read_oob;
582 ecc->write_oob = tango_write_oob;
583
584 err = nand_scan_tail(mtd);
585 if (err)
586 return err;
587
588 tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
589 tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
590 tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
591 tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
592
593 err = mtd_device_register(mtd, NULL, 0);
594 if (err) {
595 nand_cleanup(chip);
596 return err;
597 }
598
599 nfc->chips[cs] = tchip;
600
601 return 0;
602}
603
604static int tango_nand_remove(struct platform_device *pdev)
605{
606 int cs;
607 struct tango_nfc *nfc = platform_get_drvdata(pdev);
608
609 dma_release_channel(nfc->chan);
610
611 for (cs = 0; cs < MAX_CS; ++cs) {
612 if (nfc->chips[cs])
613 nand_release(nand_to_mtd(&nfc->chips[cs]->nand_chip));
614 }
615
616 return 0;
617}
618
619static int tango_nand_probe(struct platform_device *pdev)
620{
621 int err;
622 struct clk *clk;
623 struct resource *res;
624 struct tango_nfc *nfc;
625 struct device_node *np;
626
627 nfc = devm_kzalloc(&pdev->dev, sizeof(*nfc), GFP_KERNEL);
628 if (!nfc)
629 return -ENOMEM;
630
631 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
632 nfc->reg_base = devm_ioremap_resource(&pdev->dev, res);
633 if (IS_ERR(nfc->reg_base))
634 return PTR_ERR(nfc->reg_base);
635
636 res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
637 nfc->mem_base = devm_ioremap_resource(&pdev->dev, res);
638 if (IS_ERR(nfc->mem_base))
639 return PTR_ERR(nfc->mem_base);
640
641 res = platform_get_resource(pdev, IORESOURCE_MEM, 2);
642 nfc->pbus_base = devm_ioremap_resource(&pdev->dev, res);
643 if (IS_ERR(nfc->pbus_base))
644 return PTR_ERR(nfc->pbus_base);
645
646 writel_relaxed(MODE_RAW, nfc->pbus_base + PBUS_PAD_MODE);
647
648 clk = devm_clk_get(&pdev->dev, NULL);
649 if (IS_ERR(clk))
650 return PTR_ERR(clk);
651
652 nfc->chan = dma_request_chan(&pdev->dev, "rxtx");
653 if (IS_ERR(nfc->chan))
654 return PTR_ERR(nfc->chan);
655
656 platform_set_drvdata(pdev, nfc);
657 nand_hw_control_init(&nfc->hw);
658 nfc->freq_kHz = clk_get_rate(clk) / 1000;
659
660 for_each_child_of_node(pdev->dev.of_node, np) {
661 err = chip_init(&pdev->dev, np);
662 if (err) {
663 tango_nand_remove(pdev);
664 return err;
665 }
666 }
667
668 return 0;
669}
670
671static const struct of_device_id tango_nand_ids[] = {
672 { .compatible = "sigma,smp8758-nand" },
673 { }
674};
675MODULE_DEVICE_TABLE(of, tango_nand_ids);
676
677static struct platform_driver tango_nand_driver = {
678 .probe = tango_nand_probe,
679 .remove = tango_nand_remove,
680 .driver = {
681 .name = "tango-nand",
682 .of_match_table = tango_nand_ids,
683 },
684};
685
686module_platform_driver(tango_nand_driver);
687
688MODULE_LICENSE("GPL");
689MODULE_AUTHOR("Sigma Designs");
690MODULE_DESCRIPTION("Tango4 NAND Flash controller driver");
691
