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32#define DRV_NAME "3c59x"
33
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36
37
38#define TX_RING_SIZE 16
39#define RX_RING_SIZE 32
40#define PKT_BUF_SZ 1536
41
42
43
44
45#ifndef __arm__
46static int rx_copybreak = 200;
47#else
48
49
50static int rx_copybreak = 1513;
51#endif
52
53static const int mtu = 1500;
54
55static int max_interrupt_work = 32;
56
57static int watchdog = 5000;
58
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61
62
63#define tx_interrupt_mitigation 1
64
65
66#define vortex_debug debug
67#ifdef VORTEX_DEBUG
68static int vortex_debug = VORTEX_DEBUG;
69#else
70static int vortex_debug = 1;
71#endif
72
73#include <linux/module.h>
74#include <linux/kernel.h>
75#include <linux/string.h>
76#include <linux/timer.h>
77#include <linux/errno.h>
78#include <linux/in.h>
79#include <linux/ioport.h>
80#include <linux/interrupt.h>
81#include <linux/pci.h>
82#include <linux/mii.h>
83#include <linux/init.h>
84#include <linux/netdevice.h>
85#include <linux/etherdevice.h>
86#include <linux/skbuff.h>
87#include <linux/ethtool.h>
88#include <linux/highmem.h>
89#include <linux/eisa.h>
90#include <linux/bitops.h>
91#include <linux/jiffies.h>
92#include <linux/gfp.h>
93#include <asm/irq.h>
94#include <asm/io.h>
95#include <linux/uaccess.h>
96
97
98
99
100#define RUN_AT(x) (jiffies + (x))
101
102#include <linux/delay.h>
103
104
105static const char version[] =
106 DRV_NAME ": Donald Becker and others.\n";
107
108MODULE_AUTHOR("Donald Becker <becker@scyld.com>");
109MODULE_DESCRIPTION("3Com 3c59x/3c9xx ethernet driver ");
110MODULE_LICENSE("GPL");
111
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118
119#define VORTEX_TOTAL_SIZE 0x20
120#define BOOMERANG_TOTAL_SIZE 0x40
121
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123
124
125static char mii_preamble_required;
126
127#define PFX DRV_NAME ": "
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210enum pci_flags_bit {
211 PCI_USES_MASTER=4,
212};
213
214enum { IS_VORTEX=1, IS_BOOMERANG=2, IS_CYCLONE=4, IS_TORNADO=8,
215 EEPROM_8BIT=0x10,
216 HAS_PWR_CTRL=0x20, HAS_MII=0x40, HAS_NWAY=0x80, HAS_CB_FNS=0x100,
217 INVERT_MII_PWR=0x200, INVERT_LED_PWR=0x400, MAX_COLLISION_RESET=0x800,
218 EEPROM_OFFSET=0x1000, HAS_HWCKSM=0x2000, WNO_XCVR_PWR=0x4000,
219 EXTRA_PREAMBLE=0x8000, EEPROM_RESET=0x10000, };
220
221enum vortex_chips {
222 CH_3C590 = 0,
223 CH_3C592,
224 CH_3C597,
225 CH_3C595_1,
226 CH_3C595_2,
227
228 CH_3C595_3,
229 CH_3C900_1,
230 CH_3C900_2,
231 CH_3C900_3,
232 CH_3C900_4,
233
234 CH_3C900_5,
235 CH_3C900B_FL,
236 CH_3C905_1,
237 CH_3C905_2,
238 CH_3C905B_TX,
239 CH_3C905B_1,
240
241 CH_3C905B_2,
242 CH_3C905B_FX,
243 CH_3C905C,
244 CH_3C9202,
245 CH_3C980,
246 CH_3C9805,
247
248 CH_3CSOHO100_TX,
249 CH_3C555,
250 CH_3C556,
251 CH_3C556B,
252 CH_3C575,
253
254 CH_3C575_1,
255 CH_3CCFE575,
256 CH_3CCFE575CT,
257 CH_3CCFE656,
258 CH_3CCFEM656,
259
260 CH_3CCFEM656_1,
261 CH_3C450,
262 CH_3C920,
263 CH_3C982A,
264 CH_3C982B,
265
266 CH_905BT4,
267 CH_920B_EMB_WNM,
268};
269
270
271
272
273
274
275static struct vortex_chip_info {
276 const char *name;
277 int flags;
278 int drv_flags;
279 int io_size;
280} vortex_info_tbl[] = {
281 {"3c590 Vortex 10Mbps",
282 PCI_USES_MASTER, IS_VORTEX, 32, },
283 {"3c592 EISA 10Mbps Demon/Vortex",
284 PCI_USES_MASTER, IS_VORTEX, 32, },
285 {"3c597 EISA Fast Demon/Vortex",
286 PCI_USES_MASTER, IS_VORTEX, 32, },
287 {"3c595 Vortex 100baseTx",
288 PCI_USES_MASTER, IS_VORTEX, 32, },
289 {"3c595 Vortex 100baseT4",
290 PCI_USES_MASTER, IS_VORTEX, 32, },
291
292 {"3c595 Vortex 100base-MII",
293 PCI_USES_MASTER, IS_VORTEX, 32, },
294 {"3c900 Boomerang 10baseT",
295 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
296 {"3c900 Boomerang 10Mbps Combo",
297 PCI_USES_MASTER, IS_BOOMERANG|EEPROM_RESET, 64, },
298 {"3c900 Cyclone 10Mbps TPO",
299 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
300 {"3c900 Cyclone 10Mbps Combo",
301 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
302
303 {"3c900 Cyclone 10Mbps TPC",
304 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
305 {"3c900B-FL Cyclone 10base-FL",
306 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
307 {"3c905 Boomerang 100baseTx",
308 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
309 {"3c905 Boomerang 100baseT4",
310 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_RESET, 64, },
311 {"3C905B-TX Fast Etherlink XL PCI",
312 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
313 {"3c905B Cyclone 100baseTx",
314 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
315
316 {"3c905B Cyclone 10/100/BNC",
317 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
318 {"3c905B-FX Cyclone 100baseFx",
319 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM, 128, },
320 {"3c905C Tornado",
321 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
322 {"3c920B-EMB-WNM (ATI Radeon 9100 IGP)",
323 PCI_USES_MASTER, IS_TORNADO|HAS_MII|HAS_HWCKSM, 128, },
324 {"3c980 Cyclone",
325 PCI_USES_MASTER, IS_CYCLONE|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
326
327 {"3c980C Python-T",
328 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM, 128, },
329 {"3cSOHO100-TX Hurricane",
330 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
331 {"3c555 Laptop Hurricane",
332 PCI_USES_MASTER, IS_CYCLONE|EEPROM_8BIT|HAS_HWCKSM, 128, },
333 {"3c556 Laptop Tornado",
334 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_8BIT|HAS_CB_FNS|INVERT_MII_PWR|
335 HAS_HWCKSM, 128, },
336 {"3c556B Laptop Hurricane",
337 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|EEPROM_OFFSET|HAS_CB_FNS|INVERT_MII_PWR|
338 WNO_XCVR_PWR|HAS_HWCKSM, 128, },
339
340 {"3c575 [Megahertz] 10/100 LAN CardBus",
341 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
342 {"3c575 Boomerang CardBus",
343 PCI_USES_MASTER, IS_BOOMERANG|HAS_MII|EEPROM_8BIT, 128, },
344 {"3CCFE575BT Cyclone CardBus",
345 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|
346 INVERT_LED_PWR|HAS_HWCKSM, 128, },
347 {"3CCFE575CT Tornado CardBus",
348 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
349 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
350 {"3CCFE656 Cyclone CardBus",
351 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
352 INVERT_LED_PWR|HAS_HWCKSM, 128, },
353
354 {"3CCFEM656B Cyclone+Winmodem CardBus",
355 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
356 INVERT_LED_PWR|HAS_HWCKSM, 128, },
357 {"3CXFEM656C Tornado+Winmodem CardBus",
358 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_CB_FNS|EEPROM_8BIT|INVERT_MII_PWR|
359 MAX_COLLISION_RESET|HAS_HWCKSM, 128, },
360 {"3c450 HomePNA Tornado",
361 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
362 {"3c920 Tornado",
363 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
364 {"3c982 Hydra Dual Port A",
365 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
366
367 {"3c982 Hydra Dual Port B",
368 PCI_USES_MASTER, IS_TORNADO|HAS_HWCKSM|HAS_NWAY, 128, },
369 {"3c905B-T4",
370 PCI_USES_MASTER, IS_CYCLONE|HAS_NWAY|HAS_HWCKSM|EXTRA_PREAMBLE, 128, },
371 {"3c920B-EMB-WNM Tornado",
372 PCI_USES_MASTER, IS_TORNADO|HAS_NWAY|HAS_HWCKSM, 128, },
373
374 {NULL,},
375};
376
377
378static const struct pci_device_id vortex_pci_tbl[] = {
379 { 0x10B7, 0x5900, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C590 },
380 { 0x10B7, 0x5920, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C592 },
381 { 0x10B7, 0x5970, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C597 },
382 { 0x10B7, 0x5950, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_1 },
383 { 0x10B7, 0x5951, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_2 },
384
385 { 0x10B7, 0x5952, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C595_3 },
386 { 0x10B7, 0x9000, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_1 },
387 { 0x10B7, 0x9001, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_2 },
388 { 0x10B7, 0x9004, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_3 },
389 { 0x10B7, 0x9005, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_4 },
390
391 { 0x10B7, 0x9006, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900_5 },
392 { 0x10B7, 0x900A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C900B_FL },
393 { 0x10B7, 0x9050, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_1 },
394 { 0x10B7, 0x9051, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905_2 },
395 { 0x10B7, 0x9054, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_TX },
396 { 0x10B7, 0x9055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_1 },
397
398 { 0x10B7, 0x9058, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_2 },
399 { 0x10B7, 0x905A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905B_FX },
400 { 0x10B7, 0x9200, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C905C },
401 { 0x10B7, 0x9202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9202 },
402 { 0x10B7, 0x9800, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C980 },
403 { 0x10B7, 0x9805, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C9805 },
404
405 { 0x10B7, 0x7646, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CSOHO100_TX },
406 { 0x10B7, 0x5055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C555 },
407 { 0x10B7, 0x6055, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556 },
408 { 0x10B7, 0x6056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C556B },
409 { 0x10B7, 0x5b57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575 },
410
411 { 0x10B7, 0x5057, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C575_1 },
412 { 0x10B7, 0x5157, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575 },
413 { 0x10B7, 0x5257, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE575CT },
414 { 0x10B7, 0x6560, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFE656 },
415 { 0x10B7, 0x6562, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656 },
416
417 { 0x10B7, 0x6564, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3CCFEM656_1 },
418 { 0x10B7, 0x4500, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C450 },
419 { 0x10B7, 0x9201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C920 },
420 { 0x10B7, 0x1201, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982A },
421 { 0x10B7, 0x1202, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_3C982B },
422
423 { 0x10B7, 0x9056, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_905BT4 },
424 { 0x10B7, 0x9210, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CH_920B_EMB_WNM },
425
426 {0,}
427};
428MODULE_DEVICE_TABLE(pci, vortex_pci_tbl);
429
430
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434
435
436
437
438#define EL3_CMD 0x0e
439#define EL3_STATUS 0x0e
440
441
442
443
444
445
446
447enum vortex_cmd {
448 TotalReset = 0<<11, SelectWindow = 1<<11, StartCoax = 2<<11,
449 RxDisable = 3<<11, RxEnable = 4<<11, RxReset = 5<<11,
450 UpStall = 6<<11, UpUnstall = (6<<11)+1,
451 DownStall = (6<<11)+2, DownUnstall = (6<<11)+3,
452 RxDiscard = 8<<11, TxEnable = 9<<11, TxDisable = 10<<11, TxReset = 11<<11,
453 FakeIntr = 12<<11, AckIntr = 13<<11, SetIntrEnb = 14<<11,
454 SetStatusEnb = 15<<11, SetRxFilter = 16<<11, SetRxThreshold = 17<<11,
455 SetTxThreshold = 18<<11, SetTxStart = 19<<11,
456 StartDMAUp = 20<<11, StartDMADown = (20<<11)+1, StatsEnable = 21<<11,
457 StatsDisable = 22<<11, StopCoax = 23<<11, SetFilterBit = 25<<11,};
458
459
460enum RxFilter {
461 RxStation = 1, RxMulticast = 2, RxBroadcast = 4, RxProm = 8 };
462
463
464enum vortex_status {
465 IntLatch = 0x0001, HostError = 0x0002, TxComplete = 0x0004,
466 TxAvailable = 0x0008, RxComplete = 0x0010, RxEarly = 0x0020,
467 IntReq = 0x0040, StatsFull = 0x0080,
468 DMADone = 1<<8, DownComplete = 1<<9, UpComplete = 1<<10,
469 DMAInProgress = 1<<11,
470 CmdInProgress = 1<<12,
471};
472
473
474
475enum Window1 {
476 TX_FIFO = 0x10, RX_FIFO = 0x10, RxErrors = 0x14,
477 RxStatus = 0x18, Timer=0x1A, TxStatus = 0x1B,
478 TxFree = 0x1C,
479};
480enum Window0 {
481 Wn0EepromCmd = 10,
482 Wn0EepromData = 12,
483 IntrStatus=0x0E,
484};
485enum Win0_EEPROM_bits {
486 EEPROM_Read = 0x80, EEPROM_WRITE = 0x40, EEPROM_ERASE = 0xC0,
487 EEPROM_EWENB = 0x30,
488 EEPROM_EWDIS = 0x00,
489};
490
491enum eeprom_offset {
492 PhysAddr01=0, PhysAddr23=1, PhysAddr45=2, ModelID=3,
493 EtherLink3ID=7, IFXcvrIO=8, IRQLine=9,
494 NodeAddr01=10, NodeAddr23=11, NodeAddr45=12,
495 DriverTune=13, Checksum=15};
496
497enum Window2 {
498 Wn2_ResetOptions=12,
499};
500enum Window3 {
501 Wn3_Config=0, Wn3_MaxPktSize=4, Wn3_MAC_Ctrl=6, Wn3_Options=8,
502};
503
504#define BFEXT(value, offset, bitcount) \
505 ((((unsigned long)(value)) >> (offset)) & ((1 << (bitcount)) - 1))
506
507#define BFINS(lhs, rhs, offset, bitcount) \
508 (((lhs) & ~((((1 << (bitcount)) - 1)) << (offset))) | \
509 (((rhs) & ((1 << (bitcount)) - 1)) << (offset)))
510
511#define RAM_SIZE(v) BFEXT(v, 0, 3)
512#define RAM_WIDTH(v) BFEXT(v, 3, 1)
513#define RAM_SPEED(v) BFEXT(v, 4, 2)
514#define ROM_SIZE(v) BFEXT(v, 6, 2)
515#define RAM_SPLIT(v) BFEXT(v, 16, 2)
516#define XCVR(v) BFEXT(v, 20, 4)
517#define AUTOSELECT(v) BFEXT(v, 24, 1)
518
519enum Window4 {
520 Wn4_FIFODiag = 4, Wn4_NetDiag = 6, Wn4_PhysicalMgmt=8, Wn4_Media = 10,
521};
522enum Win4_Media_bits {
523 Media_SQE = 0x0008,
524 Media_10TP = 0x00C0,
525 Media_Lnk = 0x0080,
526 Media_LnkBeat = 0x0800,
527};
528enum Window7 {
529 Wn7_MasterAddr = 0, Wn7_VlanEtherType=4, Wn7_MasterLen = 6,
530 Wn7_MasterStatus = 12,
531};
532
533enum MasterCtrl {
534 PktStatus = 0x20, DownListPtr = 0x24, FragAddr = 0x28, FragLen = 0x2c,
535 TxFreeThreshold = 0x2f, UpPktStatus = 0x30, UpListPtr = 0x38,
536};
537
538
539
540
541#define LAST_FRAG 0x80000000
542#define DN_COMPLETE 0x00010000
543struct boom_rx_desc {
544 __le32 next;
545 __le32 status;
546 __le32 addr;
547 __le32 length;
548};
549
550enum rx_desc_status {
551 RxDComplete=0x00008000, RxDError=0x4000,
552
553 IPChksumErr=1<<25, TCPChksumErr=1<<26, UDPChksumErr=1<<27,
554 IPChksumValid=1<<29, TCPChksumValid=1<<30, UDPChksumValid=1<<31,
555};
556
557#ifdef MAX_SKB_FRAGS
558#define DO_ZEROCOPY 1
559#else
560#define DO_ZEROCOPY 0
561#endif
562
563struct boom_tx_desc {
564 __le32 next;
565 __le32 status;
566#if DO_ZEROCOPY
567 struct {
568 __le32 addr;
569 __le32 length;
570 } frag[1+MAX_SKB_FRAGS];
571#else
572 __le32 addr;
573 __le32 length;
574#endif
575};
576
577
578enum tx_desc_status {
579 CRCDisable=0x2000, TxDComplete=0x8000,
580 AddIPChksum=0x02000000, AddTCPChksum=0x04000000, AddUDPChksum=0x08000000,
581 TxIntrUploaded=0x80000000,
582};
583
584
585enum ChipCaps { CapBusMaster=0x20, CapPwrMgmt=0x2000 };
586
587struct vortex_extra_stats {
588 unsigned long tx_deferred;
589 unsigned long tx_max_collisions;
590 unsigned long tx_multiple_collisions;
591 unsigned long tx_single_collisions;
592 unsigned long rx_bad_ssd;
593};
594
595struct vortex_private {
596
597 struct boom_rx_desc* rx_ring;
598 struct boom_tx_desc* tx_ring;
599 dma_addr_t rx_ring_dma;
600 dma_addr_t tx_ring_dma;
601
602 struct sk_buff* rx_skbuff[RX_RING_SIZE];
603 struct sk_buff* tx_skbuff[TX_RING_SIZE];
604 unsigned int cur_rx, cur_tx;
605 unsigned int dirty_tx;
606 struct vortex_extra_stats xstats;
607 struct sk_buff *tx_skb;
608 dma_addr_t tx_skb_dma;
609
610
611 struct device *gendev;
612 void __iomem *ioaddr;
613 void __iomem *cb_fn_base;
614
615
616 int rx_nocopy, rx_copy, queued_packet, rx_csumhits;
617 int card_idx;
618
619
620 struct timer_list timer;
621 int options;
622 unsigned int media_override:4,
623 default_media:4,
624 full_duplex:1, autoselect:1,
625 bus_master:1,
626 full_bus_master_tx:1, full_bus_master_rx:2,
627 flow_ctrl:1,
628 partner_flow_ctrl:1,
629 has_nway:1,
630 enable_wol:1,
631 pm_state_valid:1,
632 open:1,
633 medialock:1,
634 large_frames:1,
635 handling_irq:1;
636
637
638
639 int drv_flags;
640 u16 status_enable;
641 u16 intr_enable;
642 u16 available_media;
643 u16 capabilities, info1, info2;
644 u16 advertising;
645 unsigned char phys[2];
646 u16 deferred;
647
648 u16 io_size;
649
650
651
652 spinlock_t lock;
653
654 spinlock_t mii_lock;
655 struct mii_if_info mii;
656 spinlock_t window_lock;
657 int window;
658};
659
660static void window_set(struct vortex_private *vp, int window)
661{
662 if (window != vp->window) {
663 iowrite16(SelectWindow + window, vp->ioaddr + EL3_CMD);
664 vp->window = window;
665 }
666}
667
668#define DEFINE_WINDOW_IO(size) \
669static u ## size \
670window_read ## size(struct vortex_private *vp, int window, int addr) \
671{ \
672 unsigned long flags; \
673 u ## size ret; \
674 spin_lock_irqsave(&vp->window_lock, flags); \
675 window_set(vp, window); \
676 ret = ioread ## size(vp->ioaddr + addr); \
677 spin_unlock_irqrestore(&vp->window_lock, flags); \
678 return ret; \
679} \
680static void \
681window_write ## size(struct vortex_private *vp, u ## size value, \
682 int window, int addr) \
683{ \
684 unsigned long flags; \
685 spin_lock_irqsave(&vp->window_lock, flags); \
686 window_set(vp, window); \
687 iowrite ## size(value, vp->ioaddr + addr); \
688 spin_unlock_irqrestore(&vp->window_lock, flags); \
689}
690DEFINE_WINDOW_IO(8)
691DEFINE_WINDOW_IO(16)
692DEFINE_WINDOW_IO(32)
693
694#ifdef CONFIG_PCI
695#define DEVICE_PCI(dev) ((dev_is_pci(dev)) ? to_pci_dev((dev)) : NULL)
696#else
697#define DEVICE_PCI(dev) NULL
698#endif
699
700#define VORTEX_PCI(vp) \
701 ((struct pci_dev *) (((vp)->gendev) ? DEVICE_PCI((vp)->gendev) : NULL))
702
703#ifdef CONFIG_EISA
704#define DEVICE_EISA(dev) (((dev)->bus == &eisa_bus_type) ? to_eisa_device((dev)) : NULL)
705#else
706#define DEVICE_EISA(dev) NULL
707#endif
708
709#define VORTEX_EISA(vp) \
710 ((struct eisa_device *) (((vp)->gendev) ? DEVICE_EISA((vp)->gendev) : NULL))
711
712
713
714
715enum xcvr_types {
716 XCVR_10baseT=0, XCVR_AUI, XCVR_10baseTOnly, XCVR_10base2, XCVR_100baseTx,
717 XCVR_100baseFx, XCVR_MII=6, XCVR_NWAY=8, XCVR_ExtMII=9, XCVR_Default=10,
718};
719
720static const struct media_table {
721 char *name;
722 unsigned int media_bits:16,
723 mask:8,
724 next:8;
725 int wait;
726} media_tbl[] = {
727 { "10baseT", Media_10TP,0x08, XCVR_10base2, (14*HZ)/10},
728 { "10Mbs AUI", Media_SQE, 0x20, XCVR_Default, (1*HZ)/10},
729 { "undefined", 0, 0x80, XCVR_10baseT, 10000},
730 { "10base2", 0, 0x10, XCVR_AUI, (1*HZ)/10},
731 { "100baseTX", Media_Lnk, 0x02, XCVR_100baseFx, (14*HZ)/10},
732 { "100baseFX", Media_Lnk, 0x04, XCVR_MII, (14*HZ)/10},
733 { "MII", 0, 0x41, XCVR_10baseT, 3*HZ },
734 { "undefined", 0, 0x01, XCVR_10baseT, 10000},
735 { "Autonegotiate", 0, 0x41, XCVR_10baseT, 3*HZ},
736 { "MII-External", 0, 0x41, XCVR_10baseT, 3*HZ },
737 { "Default", 0, 0xFF, XCVR_10baseT, 10000},
738};
739
740static struct {
741 const char str[ETH_GSTRING_LEN];
742} ethtool_stats_keys[] = {
743 { "tx_deferred" },
744 { "tx_max_collisions" },
745 { "tx_multiple_collisions" },
746 { "tx_single_collisions" },
747 { "rx_bad_ssd" },
748};
749
750
751#define VORTEX_NUM_STATS 5
752
753static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
754 int chip_idx, int card_idx);
755static int vortex_up(struct net_device *dev);
756static void vortex_down(struct net_device *dev, int final);
757static int vortex_open(struct net_device *dev);
758static void mdio_sync(struct vortex_private *vp, int bits);
759static int mdio_read(struct net_device *dev, int phy_id, int location);
760static void mdio_write(struct net_device *vp, int phy_id, int location, int value);
761static void vortex_timer(struct timer_list *t);
762static netdev_tx_t vortex_start_xmit(struct sk_buff *skb,
763 struct net_device *dev);
764static netdev_tx_t boomerang_start_xmit(struct sk_buff *skb,
765 struct net_device *dev);
766static int vortex_rx(struct net_device *dev);
767static int boomerang_rx(struct net_device *dev);
768static irqreturn_t vortex_interrupt(int irq, void *dev_id);
769static irqreturn_t boomerang_interrupt(int irq, void *dev_id);
770static int vortex_close(struct net_device *dev);
771static void dump_tx_ring(struct net_device *dev);
772static void update_stats(void __iomem *ioaddr, struct net_device *dev);
773static struct net_device_stats *vortex_get_stats(struct net_device *dev);
774static void set_rx_mode(struct net_device *dev);
775#ifdef CONFIG_PCI
776static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);
777#endif
778static void vortex_tx_timeout(struct net_device *dev);
779static void acpi_set_WOL(struct net_device *dev);
780static const struct ethtool_ops vortex_ethtool_ops;
781static void set_8021q_mode(struct net_device *dev, int enable);
782
783
784
785#define MAX_UNITS 8
786static int options[MAX_UNITS] = { [0 ... MAX_UNITS-1] = -1 };
787static int full_duplex[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
788static int hw_checksums[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
789static int flow_ctrl[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
790static int enable_wol[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
791static int use_mmio[MAX_UNITS] = {[0 ... MAX_UNITS-1] = -1 };
792static int global_options = -1;
793static int global_full_duplex = -1;
794static int global_enable_wol = -1;
795static int global_use_mmio = -1;
796
797
798static int compaq_ioaddr, compaq_irq, compaq_device_id = 0x5900;
799static struct net_device *compaq_net_device;
800
801static int vortex_cards_found;
802
803module_param(debug, int, 0);
804module_param(global_options, int, 0);
805module_param_array(options, int, NULL, 0);
806module_param(global_full_duplex, int, 0);
807module_param_array(full_duplex, int, NULL, 0);
808module_param_array(hw_checksums, int, NULL, 0);
809module_param_array(flow_ctrl, int, NULL, 0);
810module_param(global_enable_wol, int, 0);
811module_param_array(enable_wol, int, NULL, 0);
812module_param(rx_copybreak, int, 0);
813module_param(max_interrupt_work, int, 0);
814module_param_hw(compaq_ioaddr, int, ioport, 0);
815module_param_hw(compaq_irq, int, irq, 0);
816module_param(compaq_device_id, int, 0);
817module_param(watchdog, int, 0);
818module_param(global_use_mmio, int, 0);
819module_param_array(use_mmio, int, NULL, 0);
820MODULE_PARM_DESC(debug, "3c59x debug level (0-6)");
821MODULE_PARM_DESC(options, "3c59x: Bits 0-3: media type, bit 4: bus mastering, bit 9: full duplex");
822MODULE_PARM_DESC(global_options, "3c59x: same as options, but applies to all NICs if options is unset");
823MODULE_PARM_DESC(full_duplex, "3c59x full duplex setting(s) (1)");
824MODULE_PARM_DESC(global_full_duplex, "3c59x: same as full_duplex, but applies to all NICs if full_duplex is unset");
825MODULE_PARM_DESC(hw_checksums, "3c59x Hardware checksum checking by adapter(s) (0-1)");
826MODULE_PARM_DESC(flow_ctrl, "3c59x 802.3x flow control usage (PAUSE only) (0-1)");
827MODULE_PARM_DESC(enable_wol, "3c59x: Turn on Wake-on-LAN for adapter(s) (0-1)");
828MODULE_PARM_DESC(global_enable_wol, "3c59x: same as enable_wol, but applies to all NICs if enable_wol is unset");
829MODULE_PARM_DESC(rx_copybreak, "3c59x copy breakpoint for copy-only-tiny-frames");
830MODULE_PARM_DESC(max_interrupt_work, "3c59x maximum events handled per interrupt");
831MODULE_PARM_DESC(compaq_ioaddr, "3c59x PCI I/O base address (Compaq BIOS problem workaround)");
832MODULE_PARM_DESC(compaq_irq, "3c59x PCI IRQ number (Compaq BIOS problem workaround)");
833MODULE_PARM_DESC(compaq_device_id, "3c59x PCI device ID (Compaq BIOS problem workaround)");
834MODULE_PARM_DESC(watchdog, "3c59x transmit timeout in milliseconds");
835MODULE_PARM_DESC(global_use_mmio, "3c59x: same as use_mmio, but applies to all NICs if options is unset");
836MODULE_PARM_DESC(use_mmio, "3c59x: use memory-mapped PCI I/O resource (0-1)");
837
838#ifdef CONFIG_NET_POLL_CONTROLLER
839static void poll_vortex(struct net_device *dev)
840{
841 struct vortex_private *vp = netdev_priv(dev);
842 unsigned long flags;
843 local_irq_save(flags);
844 (vp->full_bus_master_rx ? boomerang_interrupt:vortex_interrupt)(dev->irq,dev);
845 local_irq_restore(flags);
846}
847#endif
848
849#ifdef CONFIG_PM
850
851static int vortex_suspend(struct device *dev)
852{
853 struct pci_dev *pdev = to_pci_dev(dev);
854 struct net_device *ndev = pci_get_drvdata(pdev);
855
856 if (!ndev || !netif_running(ndev))
857 return 0;
858
859 netif_device_detach(ndev);
860 vortex_down(ndev, 1);
861
862 return 0;
863}
864
865static int vortex_resume(struct device *dev)
866{
867 struct pci_dev *pdev = to_pci_dev(dev);
868 struct net_device *ndev = pci_get_drvdata(pdev);
869 int err;
870
871 if (!ndev || !netif_running(ndev))
872 return 0;
873
874 err = vortex_up(ndev);
875 if (err)
876 return err;
877
878 netif_device_attach(ndev);
879
880 return 0;
881}
882
883static const struct dev_pm_ops vortex_pm_ops = {
884 .suspend = vortex_suspend,
885 .resume = vortex_resume,
886 .freeze = vortex_suspend,
887 .thaw = vortex_resume,
888 .poweroff = vortex_suspend,
889 .restore = vortex_resume,
890};
891
892#define VORTEX_PM_OPS (&vortex_pm_ops)
893
894#else
895
896#define VORTEX_PM_OPS NULL
897
898#endif
899
900#ifdef CONFIG_EISA
901static const struct eisa_device_id vortex_eisa_ids[] = {
902 { "TCM5920", CH_3C592 },
903 { "TCM5970", CH_3C597 },
904 { "" }
905};
906MODULE_DEVICE_TABLE(eisa, vortex_eisa_ids);
907
908static int vortex_eisa_probe(struct device *device)
909{
910 void __iomem *ioaddr;
911 struct eisa_device *edev;
912
913 edev = to_eisa_device(device);
914
915 if (!request_region(edev->base_addr, VORTEX_TOTAL_SIZE, DRV_NAME))
916 return -EBUSY;
917
918 ioaddr = ioport_map(edev->base_addr, VORTEX_TOTAL_SIZE);
919
920 if (vortex_probe1(device, ioaddr, ioread16(ioaddr + 0xC88) >> 12,
921 edev->id.driver_data, vortex_cards_found)) {
922 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
923 return -ENODEV;
924 }
925
926 vortex_cards_found++;
927
928 return 0;
929}
930
931static int vortex_eisa_remove(struct device *device)
932{
933 struct eisa_device *edev;
934 struct net_device *dev;
935 struct vortex_private *vp;
936 void __iomem *ioaddr;
937
938 edev = to_eisa_device(device);
939 dev = eisa_get_drvdata(edev);
940
941 if (!dev) {
942 pr_err("vortex_eisa_remove called for Compaq device!\n");
943 BUG();
944 }
945
946 vp = netdev_priv(dev);
947 ioaddr = vp->ioaddr;
948
949 unregister_netdev(dev);
950 iowrite16(TotalReset|0x14, ioaddr + EL3_CMD);
951 release_region(edev->base_addr, VORTEX_TOTAL_SIZE);
952
953 free_netdev(dev);
954 return 0;
955}
956
957static struct eisa_driver vortex_eisa_driver = {
958 .id_table = vortex_eisa_ids,
959 .driver = {
960 .name = "3c59x",
961 .probe = vortex_eisa_probe,
962 .remove = vortex_eisa_remove
963 }
964};
965
966#endif
967
968
969static int __init vortex_eisa_init(void)
970{
971 int eisa_found = 0;
972 int orig_cards_found = vortex_cards_found;
973
974#ifdef CONFIG_EISA
975 int err;
976
977 err = eisa_driver_register (&vortex_eisa_driver);
978 if (!err) {
979
980
981
982
983
984
985
986 eisa_found = 1;
987 }
988#endif
989
990
991 if (compaq_ioaddr) {
992 vortex_probe1(NULL, ioport_map(compaq_ioaddr, VORTEX_TOTAL_SIZE),
993 compaq_irq, compaq_device_id, vortex_cards_found++);
994 }
995
996 return vortex_cards_found - orig_cards_found + eisa_found;
997}
998
999
1000static int vortex_init_one(struct pci_dev *pdev,
1001 const struct pci_device_id *ent)
1002{
1003 int rc, unit, pci_bar;
1004 struct vortex_chip_info *vci;
1005 void __iomem *ioaddr;
1006
1007
1008 rc = pci_enable_device(pdev);
1009 if (rc < 0)
1010 goto out;
1011
1012 rc = pci_request_regions(pdev, DRV_NAME);
1013 if (rc < 0)
1014 goto out_disable;
1015
1016 unit = vortex_cards_found;
1017
1018 if (global_use_mmio < 0 && (unit >= MAX_UNITS || use_mmio[unit] < 0)) {
1019
1020 vci = &vortex_info_tbl[ent->driver_data];
1021 pci_bar = vci->drv_flags & (IS_CYCLONE | IS_TORNADO) ? 1 : 0;
1022 } else if (unit < MAX_UNITS && use_mmio[unit] >= 0)
1023 pci_bar = use_mmio[unit] ? 1 : 0;
1024 else
1025 pci_bar = global_use_mmio ? 1 : 0;
1026
1027 ioaddr = pci_iomap(pdev, pci_bar, 0);
1028 if (!ioaddr)
1029 ioaddr = pci_iomap(pdev, 0, 0);
1030 if (!ioaddr) {
1031 rc = -ENOMEM;
1032 goto out_release;
1033 }
1034
1035 rc = vortex_probe1(&pdev->dev, ioaddr, pdev->irq,
1036 ent->driver_data, unit);
1037 if (rc < 0)
1038 goto out_iounmap;
1039
1040 vortex_cards_found++;
1041 goto out;
1042
1043out_iounmap:
1044 pci_iounmap(pdev, ioaddr);
1045out_release:
1046 pci_release_regions(pdev);
1047out_disable:
1048 pci_disable_device(pdev);
1049out:
1050 return rc;
1051}
1052
1053static const struct net_device_ops boomrang_netdev_ops = {
1054 .ndo_open = vortex_open,
1055 .ndo_stop = vortex_close,
1056 .ndo_start_xmit = boomerang_start_xmit,
1057 .ndo_tx_timeout = vortex_tx_timeout,
1058 .ndo_get_stats = vortex_get_stats,
1059#ifdef CONFIG_PCI
1060 .ndo_do_ioctl = vortex_ioctl,
1061#endif
1062 .ndo_set_rx_mode = set_rx_mode,
1063 .ndo_set_mac_address = eth_mac_addr,
1064 .ndo_validate_addr = eth_validate_addr,
1065#ifdef CONFIG_NET_POLL_CONTROLLER
1066 .ndo_poll_controller = poll_vortex,
1067#endif
1068};
1069
1070static const struct net_device_ops vortex_netdev_ops = {
1071 .ndo_open = vortex_open,
1072 .ndo_stop = vortex_close,
1073 .ndo_start_xmit = vortex_start_xmit,
1074 .ndo_tx_timeout = vortex_tx_timeout,
1075 .ndo_get_stats = vortex_get_stats,
1076#ifdef CONFIG_PCI
1077 .ndo_do_ioctl = vortex_ioctl,
1078#endif
1079 .ndo_set_rx_mode = set_rx_mode,
1080 .ndo_set_mac_address = eth_mac_addr,
1081 .ndo_validate_addr = eth_validate_addr,
1082#ifdef CONFIG_NET_POLL_CONTROLLER
1083 .ndo_poll_controller = poll_vortex,
1084#endif
1085};
1086
1087
1088
1089
1090
1091
1092
1093static int vortex_probe1(struct device *gendev, void __iomem *ioaddr, int irq,
1094 int chip_idx, int card_idx)
1095{
1096 struct vortex_private *vp;
1097 int option;
1098 unsigned int eeprom[0x40], checksum = 0;
1099 int i, step;
1100 struct net_device *dev;
1101 static int printed_version;
1102 int retval, print_info;
1103 struct vortex_chip_info * const vci = &vortex_info_tbl[chip_idx];
1104 const char *print_name = "3c59x";
1105 struct pci_dev *pdev = NULL;
1106 struct eisa_device *edev = NULL;
1107
1108 if (!printed_version) {
1109 pr_info("%s", version);
1110 printed_version = 1;
1111 }
1112
1113 if (gendev) {
1114 if ((pdev = DEVICE_PCI(gendev))) {
1115 print_name = pci_name(pdev);
1116 }
1117
1118 if ((edev = DEVICE_EISA(gendev))) {
1119 print_name = dev_name(&edev->dev);
1120 }
1121 }
1122
1123 dev = alloc_etherdev(sizeof(*vp));
1124 retval = -ENOMEM;
1125 if (!dev)
1126 goto out;
1127
1128 SET_NETDEV_DEV(dev, gendev);
1129 vp = netdev_priv(dev);
1130
1131 option = global_options;
1132
1133
1134 if (dev->mem_start) {
1135
1136
1137
1138
1139 option = dev->mem_start;
1140 }
1141 else if (card_idx < MAX_UNITS) {
1142 if (options[card_idx] >= 0)
1143 option = options[card_idx];
1144 }
1145
1146 if (option > 0) {
1147 if (option & 0x8000)
1148 vortex_debug = 7;
1149 if (option & 0x4000)
1150 vortex_debug = 2;
1151 if (option & 0x0400)
1152 vp->enable_wol = 1;
1153 }
1154
1155 print_info = (vortex_debug > 1);
1156 if (print_info)
1157 pr_info("See Documentation/networking/vortex.txt\n");
1158
1159 pr_info("%s: 3Com %s %s at %p.\n",
1160 print_name,
1161 pdev ? "PCI" : "EISA",
1162 vci->name,
1163 ioaddr);
1164
1165 dev->base_addr = (unsigned long)ioaddr;
1166 dev->irq = irq;
1167 dev->mtu = mtu;
1168 vp->ioaddr = ioaddr;
1169 vp->large_frames = mtu > 1500;
1170 vp->drv_flags = vci->drv_flags;
1171 vp->has_nway = (vci->drv_flags & HAS_NWAY) ? 1 : 0;
1172 vp->io_size = vci->io_size;
1173 vp->card_idx = card_idx;
1174 vp->window = -1;
1175
1176
1177 if (gendev == NULL) {
1178 compaq_net_device = dev;
1179 }
1180
1181
1182 if (pdev) {
1183
1184 if (vci->flags & PCI_USES_MASTER)
1185 pci_set_master(pdev);
1186
1187 if (vci->drv_flags & IS_VORTEX) {
1188 u8 pci_latency;
1189 u8 new_latency = 248;
1190
1191
1192
1193
1194
1195 pci_read_config_byte(pdev, PCI_LATENCY_TIMER, &pci_latency);
1196 if (pci_latency < new_latency) {
1197 pr_info("%s: Overriding PCI latency timer (CFLT) setting of %d, new value is %d.\n",
1198 print_name, pci_latency, new_latency);
1199 pci_write_config_byte(pdev, PCI_LATENCY_TIMER, new_latency);
1200 }
1201 }
1202 }
1203
1204 spin_lock_init(&vp->lock);
1205 spin_lock_init(&vp->mii_lock);
1206 spin_lock_init(&vp->window_lock);
1207 vp->gendev = gendev;
1208 vp->mii.dev = dev;
1209 vp->mii.mdio_read = mdio_read;
1210 vp->mii.mdio_write = mdio_write;
1211 vp->mii.phy_id_mask = 0x1f;
1212 vp->mii.reg_num_mask = 0x1f;
1213
1214
1215 vp->rx_ring = dma_alloc_coherent(gendev, sizeof(struct boom_rx_desc) * RX_RING_SIZE
1216 + sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1217 &vp->rx_ring_dma, GFP_KERNEL);
1218 retval = -ENOMEM;
1219 if (!vp->rx_ring)
1220 goto free_device;
1221
1222 vp->tx_ring = (struct boom_tx_desc *)(vp->rx_ring + RX_RING_SIZE);
1223 vp->tx_ring_dma = vp->rx_ring_dma + sizeof(struct boom_rx_desc) * RX_RING_SIZE;
1224
1225
1226
1227 if (pdev)
1228 pci_set_drvdata(pdev, dev);
1229 if (edev)
1230 eisa_set_drvdata(edev, dev);
1231
1232 vp->media_override = 7;
1233 if (option >= 0) {
1234 vp->media_override = ((option & 7) == 2) ? 0 : option & 15;
1235 if (vp->media_override != 7)
1236 vp->medialock = 1;
1237 vp->full_duplex = (option & 0x200) ? 1 : 0;
1238 vp->bus_master = (option & 16) ? 1 : 0;
1239 }
1240
1241 if (global_full_duplex > 0)
1242 vp->full_duplex = 1;
1243 if (global_enable_wol > 0)
1244 vp->enable_wol = 1;
1245
1246 if (card_idx < MAX_UNITS) {
1247 if (full_duplex[card_idx] > 0)
1248 vp->full_duplex = 1;
1249 if (flow_ctrl[card_idx] > 0)
1250 vp->flow_ctrl = 1;
1251 if (enable_wol[card_idx] > 0)
1252 vp->enable_wol = 1;
1253 }
1254
1255 vp->mii.force_media = vp->full_duplex;
1256 vp->options = option;
1257
1258 {
1259 int base;
1260
1261 if (vci->drv_flags & EEPROM_8BIT)
1262 base = 0x230;
1263 else if (vci->drv_flags & EEPROM_OFFSET)
1264 base = EEPROM_Read + 0x30;
1265 else
1266 base = EEPROM_Read;
1267
1268 for (i = 0; i < 0x40; i++) {
1269 int timer;
1270 window_write16(vp, base + i, 0, Wn0EepromCmd);
1271
1272 for (timer = 10; timer >= 0; timer--) {
1273 udelay(162);
1274 if ((window_read16(vp, 0, Wn0EepromCmd) &
1275 0x8000) == 0)
1276 break;
1277 }
1278 eeprom[i] = window_read16(vp, 0, Wn0EepromData);
1279 }
1280 }
1281 for (i = 0; i < 0x18; i++)
1282 checksum ^= eeprom[i];
1283 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1284 if (checksum != 0x00) {
1285 while (i < 0x21)
1286 checksum ^= eeprom[i++];
1287 checksum = (checksum ^ (checksum >> 8)) & 0xff;
1288 }
1289 if ((checksum != 0x00) && !(vci->drv_flags & IS_TORNADO))
1290 pr_cont(" ***INVALID CHECKSUM %4.4x*** ", checksum);
1291 for (i = 0; i < 3; i++)
1292 ((__be16 *)dev->dev_addr)[i] = htons(eeprom[i + 10]);
1293 if (print_info)
1294 pr_cont(" %pM", dev->dev_addr);
1295
1296
1297 if (!is_valid_ether_addr(dev->dev_addr)) {
1298 retval = -EINVAL;
1299 pr_err("*** EEPROM MAC address is invalid.\n");
1300 goto free_ring;
1301 }
1302 for (i = 0; i < 6; i++)
1303 window_write8(vp, dev->dev_addr[i], 2, i);
1304
1305 if (print_info)
1306 pr_cont(", IRQ %d\n", dev->irq);
1307
1308 if (dev->irq <= 0 || dev->irq >= nr_irqs)
1309 pr_warn(" *** Warning: IRQ %d is unlikely to work! ***\n",
1310 dev->irq);
1311
1312 step = (window_read8(vp, 4, Wn4_NetDiag) & 0x1e) >> 1;
1313 if (print_info) {
1314 pr_info(" product code %02x%02x rev %02x.%d date %02d-%02d-%02d\n",
1315 eeprom[6]&0xff, eeprom[6]>>8, eeprom[0x14],
1316 step, (eeprom[4]>>5) & 15, eeprom[4] & 31, eeprom[4]>>9);
1317 }
1318
1319
1320 if (pdev && vci->drv_flags & HAS_CB_FNS) {
1321 unsigned short n;
1322
1323 vp->cb_fn_base = pci_iomap(pdev, 2, 0);
1324 if (!vp->cb_fn_base) {
1325 retval = -ENOMEM;
1326 goto free_ring;
1327 }
1328
1329 if (print_info) {
1330 pr_info("%s: CardBus functions mapped %16.16llx->%p\n",
1331 print_name,
1332 (unsigned long long)pci_resource_start(pdev, 2),
1333 vp->cb_fn_base);
1334 }
1335
1336 n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1337 if (vp->drv_flags & INVERT_LED_PWR)
1338 n |= 0x10;
1339 if (vp->drv_flags & INVERT_MII_PWR)
1340 n |= 0x4000;
1341 window_write16(vp, n, 2, Wn2_ResetOptions);
1342 if (vp->drv_flags & WNO_XCVR_PWR) {
1343 window_write16(vp, 0x0800, 0, 0);
1344 }
1345 }
1346
1347
1348 vp->info1 = eeprom[13];
1349 vp->info2 = eeprom[15];
1350 vp->capabilities = eeprom[16];
1351
1352 if (vp->info1 & 0x8000) {
1353 vp->full_duplex = 1;
1354 if (print_info)
1355 pr_info("Full duplex capable\n");
1356 }
1357
1358 {
1359 static const char * const ram_split[] = {"5:3", "3:1", "1:1", "3:5"};
1360 unsigned int config;
1361 vp->available_media = window_read16(vp, 3, Wn3_Options);
1362 if ((vp->available_media & 0xff) == 0)
1363 vp->available_media = 0x40;
1364 config = window_read32(vp, 3, Wn3_Config);
1365 if (print_info) {
1366 pr_debug(" Internal config register is %4.4x, transceivers %#x.\n",
1367 config, window_read16(vp, 3, Wn3_Options));
1368 pr_info(" %dK %s-wide RAM %s Rx:Tx split, %s%s interface.\n",
1369 8 << RAM_SIZE(config),
1370 RAM_WIDTH(config) ? "word" : "byte",
1371 ram_split[RAM_SPLIT(config)],
1372 AUTOSELECT(config) ? "autoselect/" : "",
1373 XCVR(config) > XCVR_ExtMII ? "<invalid transceiver>" :
1374 media_tbl[XCVR(config)].name);
1375 }
1376 vp->default_media = XCVR(config);
1377 if (vp->default_media == XCVR_NWAY)
1378 vp->has_nway = 1;
1379 vp->autoselect = AUTOSELECT(config);
1380 }
1381
1382 if (vp->media_override != 7) {
1383 pr_info("%s: Media override to transceiver type %d (%s).\n",
1384 print_name, vp->media_override,
1385 media_tbl[vp->media_override].name);
1386 dev->if_port = vp->media_override;
1387 } else
1388 dev->if_port = vp->default_media;
1389
1390 if ((vp->available_media & 0x40) || (vci->drv_flags & HAS_NWAY) ||
1391 dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1392 int phy, phy_idx = 0;
1393 mii_preamble_required++;
1394 if (vp->drv_flags & EXTRA_PREAMBLE)
1395 mii_preamble_required++;
1396 mdio_sync(vp, 32);
1397 mdio_read(dev, 24, MII_BMSR);
1398 for (phy = 0; phy < 32 && phy_idx < 1; phy++) {
1399 int mii_status, phyx;
1400
1401
1402
1403
1404
1405 if (phy == 0)
1406 phyx = 24;
1407 else if (phy <= 24)
1408 phyx = phy - 1;
1409 else
1410 phyx = phy;
1411 mii_status = mdio_read(dev, phyx, MII_BMSR);
1412 if (mii_status && mii_status != 0xffff) {
1413 vp->phys[phy_idx++] = phyx;
1414 if (print_info) {
1415 pr_info(" MII transceiver found at address %d, status %4x.\n",
1416 phyx, mii_status);
1417 }
1418 if ((mii_status & 0x0040) == 0)
1419 mii_preamble_required++;
1420 }
1421 }
1422 mii_preamble_required--;
1423 if (phy_idx == 0) {
1424 pr_warn(" ***WARNING*** No MII transceivers found!\n");
1425 vp->phys[0] = 24;
1426 } else {
1427 vp->advertising = mdio_read(dev, vp->phys[0], MII_ADVERTISE);
1428 if (vp->full_duplex) {
1429
1430 vp->advertising &= ~0x02A0;
1431 mdio_write(dev, vp->phys[0], 4, vp->advertising);
1432 }
1433 }
1434 vp->mii.phy_id = vp->phys[0];
1435 }
1436
1437 if (vp->capabilities & CapBusMaster) {
1438 vp->full_bus_master_tx = 1;
1439 if (print_info) {
1440 pr_info(" Enabling bus-master transmits and %s receives.\n",
1441 (vp->info2 & 1) ? "early" : "whole-frame" );
1442 }
1443 vp->full_bus_master_rx = (vp->info2 & 1) ? 1 : 2;
1444 vp->bus_master = 0;
1445 }
1446
1447
1448 if (vp->full_bus_master_tx) {
1449 dev->netdev_ops = &boomrang_netdev_ops;
1450
1451 if (card_idx < MAX_UNITS &&
1452 ((hw_checksums[card_idx] == -1 && (vp->drv_flags & HAS_HWCKSM)) ||
1453 hw_checksums[card_idx] == 1)) {
1454 dev->features |= NETIF_F_IP_CSUM | NETIF_F_SG;
1455 }
1456 } else
1457 dev->netdev_ops = &vortex_netdev_ops;
1458
1459 if (print_info) {
1460 pr_info("%s: scatter/gather %sabled. h/w checksums %sabled\n",
1461 print_name,
1462 (dev->features & NETIF_F_SG) ? "en":"dis",
1463 (dev->features & NETIF_F_IP_CSUM) ? "en":"dis");
1464 }
1465
1466 dev->ethtool_ops = &vortex_ethtool_ops;
1467 dev->watchdog_timeo = (watchdog * HZ) / 1000;
1468
1469 if (pdev) {
1470 vp->pm_state_valid = 1;
1471 pci_save_state(pdev);
1472 acpi_set_WOL(dev);
1473 }
1474 retval = register_netdev(dev);
1475 if (retval == 0)
1476 return 0;
1477
1478free_ring:
1479 dma_free_coherent(&pdev->dev,
1480 sizeof(struct boom_rx_desc) * RX_RING_SIZE +
1481 sizeof(struct boom_tx_desc) * TX_RING_SIZE,
1482 vp->rx_ring, vp->rx_ring_dma);
1483free_device:
1484 free_netdev(dev);
1485 pr_err(PFX "vortex_probe1 fails. Returns %d\n", retval);
1486out:
1487 return retval;
1488}
1489
1490static void
1491issue_and_wait(struct net_device *dev, int cmd)
1492{
1493 struct vortex_private *vp = netdev_priv(dev);
1494 void __iomem *ioaddr = vp->ioaddr;
1495 int i;
1496
1497 iowrite16(cmd, ioaddr + EL3_CMD);
1498 for (i = 0; i < 2000; i++) {
1499 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
1500 return;
1501 }
1502
1503
1504 for (i = 0; i < 100000; i++) {
1505 if (!(ioread16(ioaddr + EL3_STATUS) & CmdInProgress)) {
1506 if (vortex_debug > 1)
1507 pr_info("%s: command 0x%04x took %d usecs\n",
1508 dev->name, cmd, i * 10);
1509 return;
1510 }
1511 udelay(10);
1512 }
1513 pr_err("%s: command 0x%04x did not complete! Status=0x%x\n",
1514 dev->name, cmd, ioread16(ioaddr + EL3_STATUS));
1515}
1516
1517static void
1518vortex_set_duplex(struct net_device *dev)
1519{
1520 struct vortex_private *vp = netdev_priv(dev);
1521
1522 pr_info("%s: setting %s-duplex.\n",
1523 dev->name, (vp->full_duplex) ? "full" : "half");
1524
1525
1526 window_write16(vp,
1527 ((vp->info1 & 0x8000) || vp->full_duplex ? 0x20 : 0) |
1528 (vp->large_frames ? 0x40 : 0) |
1529 ((vp->full_duplex && vp->flow_ctrl && vp->partner_flow_ctrl) ?
1530 0x100 : 0),
1531 3, Wn3_MAC_Ctrl);
1532}
1533
1534static void vortex_check_media(struct net_device *dev, unsigned int init)
1535{
1536 struct vortex_private *vp = netdev_priv(dev);
1537 unsigned int ok_to_print = 0;
1538
1539 if (vortex_debug > 3)
1540 ok_to_print = 1;
1541
1542 if (mii_check_media(&vp->mii, ok_to_print, init)) {
1543 vp->full_duplex = vp->mii.full_duplex;
1544 vortex_set_duplex(dev);
1545 } else if (init) {
1546 vortex_set_duplex(dev);
1547 }
1548}
1549
1550static int
1551vortex_up(struct net_device *dev)
1552{
1553 struct vortex_private *vp = netdev_priv(dev);
1554 void __iomem *ioaddr = vp->ioaddr;
1555 unsigned int config;
1556 int i, mii_reg1, mii_reg5, err = 0;
1557
1558 if (VORTEX_PCI(vp)) {
1559 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
1560 if (vp->pm_state_valid)
1561 pci_restore_state(VORTEX_PCI(vp));
1562 err = pci_enable_device(VORTEX_PCI(vp));
1563 if (err) {
1564 pr_warn("%s: Could not enable device\n", dev->name);
1565 goto err_out;
1566 }
1567 }
1568
1569
1570 config = window_read32(vp, 3, Wn3_Config);
1571
1572 if (vp->media_override != 7) {
1573 pr_info("%s: Media override to transceiver %d (%s).\n",
1574 dev->name, vp->media_override,
1575 media_tbl[vp->media_override].name);
1576 dev->if_port = vp->media_override;
1577 } else if (vp->autoselect) {
1578 if (vp->has_nway) {
1579 if (vortex_debug > 1)
1580 pr_info("%s: using NWAY device table, not %d\n",
1581 dev->name, dev->if_port);
1582 dev->if_port = XCVR_NWAY;
1583 } else {
1584
1585 dev->if_port = XCVR_100baseTx;
1586 while (! (vp->available_media & media_tbl[dev->if_port].mask))
1587 dev->if_port = media_tbl[dev->if_port].next;
1588 if (vortex_debug > 1)
1589 pr_info("%s: first available media type: %s\n",
1590 dev->name, media_tbl[dev->if_port].name);
1591 }
1592 } else {
1593 dev->if_port = vp->default_media;
1594 if (vortex_debug > 1)
1595 pr_info("%s: using default media %s\n",
1596 dev->name, media_tbl[dev->if_port].name);
1597 }
1598
1599 timer_setup(&vp->timer, vortex_timer, 0);
1600 mod_timer(&vp->timer, RUN_AT(media_tbl[dev->if_port].wait));
1601
1602 if (vortex_debug > 1)
1603 pr_debug("%s: Initial media type %s.\n",
1604 dev->name, media_tbl[dev->if_port].name);
1605
1606 vp->full_duplex = vp->mii.force_media;
1607 config = BFINS(config, dev->if_port, 20, 4);
1608 if (vortex_debug > 6)
1609 pr_debug("vortex_up(): writing 0x%x to InternalConfig\n", config);
1610 window_write32(vp, config, 3, Wn3_Config);
1611
1612 if (dev->if_port == XCVR_MII || dev->if_port == XCVR_NWAY) {
1613 mii_reg1 = mdio_read(dev, vp->phys[0], MII_BMSR);
1614 mii_reg5 = mdio_read(dev, vp->phys[0], MII_LPA);
1615 vp->partner_flow_ctrl = ((mii_reg5 & 0x0400) != 0);
1616 vp->mii.full_duplex = vp->full_duplex;
1617
1618 vortex_check_media(dev, 1);
1619 }
1620 else
1621 vortex_set_duplex(dev);
1622
1623 issue_and_wait(dev, TxReset);
1624
1625
1626
1627 issue_and_wait(dev, RxReset|0x04);
1628
1629
1630 iowrite16(SetStatusEnb | 0x00, ioaddr + EL3_CMD);
1631
1632 if (vortex_debug > 1) {
1633 pr_debug("%s: vortex_up() irq %d media status %4.4x.\n",
1634 dev->name, dev->irq, window_read16(vp, 4, Wn4_Media));
1635 }
1636
1637
1638 for (i = 0; i < 6; i++)
1639 window_write8(vp, dev->dev_addr[i], 2, i);
1640 for (; i < 12; i+=2)
1641 window_write16(vp, 0, 2, i);
1642
1643 if (vp->cb_fn_base) {
1644 unsigned short n = window_read16(vp, 2, Wn2_ResetOptions) & ~0x4010;
1645 if (vp->drv_flags & INVERT_LED_PWR)
1646 n |= 0x10;
1647 if (vp->drv_flags & INVERT_MII_PWR)
1648 n |= 0x4000;
1649 window_write16(vp, n, 2, Wn2_ResetOptions);
1650 }
1651
1652 if (dev->if_port == XCVR_10base2)
1653
1654 iowrite16(StartCoax, ioaddr + EL3_CMD);
1655 if (dev->if_port != XCVR_NWAY) {
1656 window_write16(vp,
1657 (window_read16(vp, 4, Wn4_Media) &
1658 ~(Media_10TP|Media_SQE)) |
1659 media_tbl[dev->if_port].media_bits,
1660 4, Wn4_Media);
1661 }
1662
1663
1664 iowrite16(StatsDisable, ioaddr + EL3_CMD);
1665 for (i = 0; i < 10; i++)
1666 window_read8(vp, 6, i);
1667 window_read16(vp, 6, 10);
1668 window_read16(vp, 6, 12);
1669
1670 window_read8(vp, 4, 12);
1671
1672 window_write16(vp, 0x0040, 4, Wn4_NetDiag);
1673
1674 if (vp->full_bus_master_rx) {
1675 vp->cur_rx = 0;
1676
1677 iowrite16(SetRxThreshold + (1536>>2), ioaddr + EL3_CMD);
1678 iowrite32(0x0020, ioaddr + PktStatus);
1679 iowrite32(vp->rx_ring_dma, ioaddr + UpListPtr);
1680 }
1681 if (vp->full_bus_master_tx) {
1682 vp->cur_tx = vp->dirty_tx = 0;
1683 if (vp->drv_flags & IS_BOOMERANG)
1684 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1685
1686 for (i = 0; i < RX_RING_SIZE; i++)
1687 vp->rx_ring[i].status = 0;
1688 for (i = 0; i < TX_RING_SIZE; i++)
1689 vp->tx_skbuff[i] = NULL;
1690 iowrite32(0, ioaddr + DownListPtr);
1691 }
1692
1693 set_rx_mode(dev);
1694
1695 set_8021q_mode(dev, 1);
1696 iowrite16(StatsEnable, ioaddr + EL3_CMD);
1697
1698 iowrite16(RxEnable, ioaddr + EL3_CMD);
1699 iowrite16(TxEnable, ioaddr + EL3_CMD);
1700
1701 vp->status_enable = SetStatusEnb | HostError|IntReq|StatsFull|TxComplete|
1702 (vp->full_bus_master_tx ? DownComplete : TxAvailable) |
1703 (vp->full_bus_master_rx ? UpComplete : RxComplete) |
1704 (vp->bus_master ? DMADone : 0);
1705 vp->intr_enable = SetIntrEnb | IntLatch | TxAvailable |
1706 (vp->full_bus_master_rx ? 0 : RxComplete) |
1707 StatsFull | HostError | TxComplete | IntReq
1708 | (vp->bus_master ? DMADone : 0) | UpComplete | DownComplete;
1709 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
1710
1711 iowrite16(AckIntr | IntLatch | TxAvailable | RxEarly | IntReq,
1712 ioaddr + EL3_CMD);
1713 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
1714 if (vp->cb_fn_base)
1715 iowrite32(0x8000, vp->cb_fn_base + 4);
1716 netif_start_queue (dev);
1717 netdev_reset_queue(dev);
1718err_out:
1719 return err;
1720}
1721
1722static int
1723vortex_open(struct net_device *dev)
1724{
1725 struct vortex_private *vp = netdev_priv(dev);
1726 int i;
1727 int retval;
1728 dma_addr_t dma;
1729
1730
1731 if ((retval = request_irq(dev->irq, vp->full_bus_master_rx ?
1732 boomerang_interrupt : vortex_interrupt, IRQF_SHARED, dev->name, dev))) {
1733 pr_err("%s: Could not reserve IRQ %d\n", dev->name, dev->irq);
1734 goto err;
1735 }
1736
1737 if (vp->full_bus_master_rx) {
1738 if (vortex_debug > 2)
1739 pr_debug("%s: Filling in the Rx ring.\n", dev->name);
1740 for (i = 0; i < RX_RING_SIZE; i++) {
1741 struct sk_buff *skb;
1742 vp->rx_ring[i].next = cpu_to_le32(vp->rx_ring_dma + sizeof(struct boom_rx_desc) * (i+1));
1743 vp->rx_ring[i].status = 0;
1744 vp->rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LAST_FRAG);
1745
1746 skb = __netdev_alloc_skb(dev, PKT_BUF_SZ + NET_IP_ALIGN,
1747 GFP_KERNEL);
1748 vp->rx_skbuff[i] = skb;
1749 if (skb == NULL)
1750 break;
1751
1752 skb_reserve(skb, NET_IP_ALIGN);
1753 dma = dma_map_single(vp->gendev, skb->data,
1754 PKT_BUF_SZ, DMA_FROM_DEVICE);
1755 if (dma_mapping_error(vp->gendev, dma))
1756 break;
1757 vp->rx_ring[i].addr = cpu_to_le32(dma);
1758 }
1759 if (i != RX_RING_SIZE) {
1760 pr_emerg("%s: no memory for rx ring\n", dev->name);
1761 retval = -ENOMEM;
1762 goto err_free_skb;
1763 }
1764
1765 vp->rx_ring[i-1].next = cpu_to_le32(vp->rx_ring_dma);
1766 }
1767
1768 retval = vortex_up(dev);
1769 if (!retval)
1770 goto out;
1771
1772err_free_skb:
1773 for (i = 0; i < RX_RING_SIZE; i++) {
1774 if (vp->rx_skbuff[i]) {
1775 dev_kfree_skb(vp->rx_skbuff[i]);
1776 vp->rx_skbuff[i] = NULL;
1777 }
1778 }
1779 free_irq(dev->irq, dev);
1780err:
1781 if (vortex_debug > 1)
1782 pr_err("%s: vortex_open() fails: returning %d\n", dev->name, retval);
1783out:
1784 return retval;
1785}
1786
1787static void
1788vortex_timer(struct timer_list *t)
1789{
1790 struct vortex_private *vp = from_timer(vp, t, timer);
1791 struct net_device *dev = vp->mii.dev;
1792 void __iomem *ioaddr = vp->ioaddr;
1793 int next_tick = 60*HZ;
1794 int ok = 0;
1795 int media_status;
1796
1797 if (vortex_debug > 2) {
1798 pr_debug("%s: Media selection timer tick happened, %s.\n",
1799 dev->name, media_tbl[dev->if_port].name);
1800 pr_debug("dev->watchdog_timeo=%d\n", dev->watchdog_timeo);
1801 }
1802
1803 media_status = window_read16(vp, 4, Wn4_Media);
1804 switch (dev->if_port) {
1805 case XCVR_10baseT: case XCVR_100baseTx: case XCVR_100baseFx:
1806 if (media_status & Media_LnkBeat) {
1807 netif_carrier_on(dev);
1808 ok = 1;
1809 if (vortex_debug > 1)
1810 pr_debug("%s: Media %s has link beat, %x.\n",
1811 dev->name, media_tbl[dev->if_port].name, media_status);
1812 } else {
1813 netif_carrier_off(dev);
1814 if (vortex_debug > 1) {
1815 pr_debug("%s: Media %s has no link beat, %x.\n",
1816 dev->name, media_tbl[dev->if_port].name, media_status);
1817 }
1818 }
1819 break;
1820 case XCVR_MII: case XCVR_NWAY:
1821 {
1822 ok = 1;
1823 vortex_check_media(dev, 0);
1824 }
1825 break;
1826 default:
1827 if (vortex_debug > 1)
1828 pr_debug("%s: Media %s has no indication, %x.\n",
1829 dev->name, media_tbl[dev->if_port].name, media_status);
1830 ok = 1;
1831 }
1832
1833 if (dev->flags & IFF_SLAVE || !netif_carrier_ok(dev))
1834 next_tick = 5*HZ;
1835
1836 if (vp->medialock)
1837 goto leave_media_alone;
1838
1839 if (!ok) {
1840 unsigned int config;
1841
1842 spin_lock_irq(&vp->lock);
1843
1844 do {
1845 dev->if_port = media_tbl[dev->if_port].next;
1846 } while ( ! (vp->available_media & media_tbl[dev->if_port].mask));
1847 if (dev->if_port == XCVR_Default) {
1848 dev->if_port = vp->default_media;
1849 if (vortex_debug > 1)
1850 pr_debug("%s: Media selection failing, using default %s port.\n",
1851 dev->name, media_tbl[dev->if_port].name);
1852 } else {
1853 if (vortex_debug > 1)
1854 pr_debug("%s: Media selection failed, now trying %s port.\n",
1855 dev->name, media_tbl[dev->if_port].name);
1856 next_tick = media_tbl[dev->if_port].wait;
1857 }
1858 window_write16(vp,
1859 (media_status & ~(Media_10TP|Media_SQE)) |
1860 media_tbl[dev->if_port].media_bits,
1861 4, Wn4_Media);
1862
1863 config = window_read32(vp, 3, Wn3_Config);
1864 config = BFINS(config, dev->if_port, 20, 4);
1865 window_write32(vp, config, 3, Wn3_Config);
1866
1867 iowrite16(dev->if_port == XCVR_10base2 ? StartCoax : StopCoax,
1868 ioaddr + EL3_CMD);
1869 if (vortex_debug > 1)
1870 pr_debug("wrote 0x%08x to Wn3_Config\n", config);
1871
1872
1873 spin_unlock_irq(&vp->lock);
1874 }
1875
1876leave_media_alone:
1877 if (vortex_debug > 2)
1878 pr_debug("%s: Media selection timer finished, %s.\n",
1879 dev->name, media_tbl[dev->if_port].name);
1880
1881 mod_timer(&vp->timer, RUN_AT(next_tick));
1882 if (vp->deferred)
1883 iowrite16(FakeIntr, ioaddr + EL3_CMD);
1884}
1885
1886static void vortex_tx_timeout(struct net_device *dev)
1887{
1888 struct vortex_private *vp = netdev_priv(dev);
1889 void __iomem *ioaddr = vp->ioaddr;
1890
1891 pr_err("%s: transmit timed out, tx_status %2.2x status %4.4x.\n",
1892 dev->name, ioread8(ioaddr + TxStatus),
1893 ioread16(ioaddr + EL3_STATUS));
1894 pr_err(" diagnostics: net %04x media %04x dma %08x fifo %04x\n",
1895 window_read16(vp, 4, Wn4_NetDiag),
1896 window_read16(vp, 4, Wn4_Media),
1897 ioread32(ioaddr + PktStatus),
1898 window_read16(vp, 4, Wn4_FIFODiag));
1899
1900 if ((ioread8(ioaddr + TxStatus) & 0x88) == 0x88)
1901 pr_err("%s: Transmitter encountered 16 collisions --"
1902 " network cable problem?\n", dev->name);
1903 if (ioread16(ioaddr + EL3_STATUS) & IntLatch) {
1904 pr_err("%s: Interrupt posted but not delivered --"
1905 " IRQ blocked by another device?\n", dev->name);
1906
1907 {
1908
1909
1910
1911 unsigned long flags;
1912 local_irq_save(flags);
1913 if (vp->full_bus_master_tx)
1914 boomerang_interrupt(dev->irq, dev);
1915 else
1916 vortex_interrupt(dev->irq, dev);
1917 local_irq_restore(flags);
1918 }
1919 }
1920
1921 if (vortex_debug > 0)
1922 dump_tx_ring(dev);
1923
1924 issue_and_wait(dev, TxReset);
1925
1926 dev->stats.tx_errors++;
1927 if (vp->full_bus_master_tx) {
1928 pr_debug("%s: Resetting the Tx ring pointer.\n", dev->name);
1929 if (vp->cur_tx - vp->dirty_tx > 0 && ioread32(ioaddr + DownListPtr) == 0)
1930 iowrite32(vp->tx_ring_dma + (vp->dirty_tx % TX_RING_SIZE) * sizeof(struct boom_tx_desc),
1931 ioaddr + DownListPtr);
1932 if (vp->cur_tx - vp->dirty_tx < TX_RING_SIZE) {
1933 netif_wake_queue (dev);
1934 netdev_reset_queue (dev);
1935 }
1936 if (vp->drv_flags & IS_BOOMERANG)
1937 iowrite8(PKT_BUF_SZ>>8, ioaddr + TxFreeThreshold);
1938 iowrite16(DownUnstall, ioaddr + EL3_CMD);
1939 } else {
1940 dev->stats.tx_dropped++;
1941 netif_wake_queue(dev);
1942 netdev_reset_queue(dev);
1943 }
1944
1945 iowrite16(TxEnable, ioaddr + EL3_CMD);
1946 netif_trans_update(dev);
1947}
1948
1949
1950
1951
1952
1953static void
1954vortex_error(struct net_device *dev, int status)
1955{
1956 struct vortex_private *vp = netdev_priv(dev);
1957 void __iomem *ioaddr = vp->ioaddr;
1958 int do_tx_reset = 0, reset_mask = 0;
1959 unsigned char tx_status = 0;
1960
1961 if (vortex_debug > 2) {
1962 pr_err("%s: vortex_error(), status=0x%x\n", dev->name, status);
1963 }
1964
1965 if (status & TxComplete) {
1966 tx_status = ioread8(ioaddr + TxStatus);
1967
1968 if (vortex_debug > 2 ||
1969 (tx_status != 0x88 && vortex_debug > 0)) {
1970 pr_err("%s: Transmit error, Tx status register %2.2x.\n",
1971 dev->name, tx_status);
1972 if (tx_status == 0x82) {
1973 pr_err("Probably a duplex mismatch. See "
1974 "Documentation/networking/vortex.txt\n");
1975 }
1976 dump_tx_ring(dev);
1977 }
1978 if (tx_status & 0x14) dev->stats.tx_fifo_errors++;
1979 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
1980 if (tx_status & 0x08) vp->xstats.tx_max_collisions++;
1981 iowrite8(0, ioaddr + TxStatus);
1982 if (tx_status & 0x30) {
1983 do_tx_reset = 1;
1984 } else if ((tx_status & 0x08) && (vp->drv_flags & MAX_COLLISION_RESET)) {
1985 do_tx_reset = 1;
1986 reset_mask = 0x0108;
1987 } else {
1988 iowrite16(TxEnable, ioaddr + EL3_CMD);
1989 }
1990 }
1991
1992 if (status & RxEarly)
1993 iowrite16(AckIntr | RxEarly, ioaddr + EL3_CMD);
1994
1995 if (status & StatsFull) {
1996 static int DoneDidThat;
1997 if (vortex_debug > 4)
1998 pr_debug("%s: Updating stats.\n", dev->name);
1999 update_stats(ioaddr, dev);
2000
2001
2002 if (DoneDidThat == 0 &&
2003 ioread16(ioaddr + EL3_STATUS) & StatsFull) {
2004 pr_warn("%s: Updating statistics failed, disabling stats as an interrupt source\n",
2005 dev->name);
2006 iowrite16(SetIntrEnb |
2007 (window_read16(vp, 5, 10) & ~StatsFull),
2008 ioaddr + EL3_CMD);
2009 vp->intr_enable &= ~StatsFull;
2010 DoneDidThat++;
2011 }
2012 }
2013 if (status & IntReq) {
2014 iowrite16(vp->status_enable, ioaddr + EL3_CMD);
2015 iowrite16(vp->intr_enable, ioaddr + EL3_CMD);
2016 }
2017 if (status & HostError) {
2018 u16 fifo_diag;
2019 fifo_diag = window_read16(vp, 4, Wn4_FIFODiag);
2020 pr_err("%s: Host error, FIFO diagnostic register %4.4x.\n",
2021 dev->name, fifo_diag);
2022
2023 if (vp->full_bus_master_tx) {
2024 int bus_status = ioread32(ioaddr + PktStatus);
2025
2026
2027 if (vortex_debug)
2028 pr_err("%s: PCI bus error, bus status %8.8x\n", dev->name, bus_status);
2029
2030
2031
2032 vortex_down(dev, 0);
2033 issue_and_wait(dev, TotalReset | 0xff);
2034 vortex_up(dev);
2035 } else if (fifo_diag & 0x0400)
2036 do_tx_reset = 1;
2037 if (fifo_diag & 0x3000) {
2038
2039 issue_and_wait(dev, RxReset|0x07);
2040
2041 set_rx_mode(dev);
2042
2043 set_8021q_mode(dev, 1);
2044 iowrite16(RxEnable, ioaddr + EL3_CMD);
2045 iowrite16(AckIntr | HostError, ioaddr + EL3_CMD);
2046 }
2047 }
2048
2049 if (do_tx_reset) {
2050 issue_and_wait(dev, TxReset|reset_mask);
2051 iowrite16(TxEnable, ioaddr + EL3_CMD);
2052 if (!vp->full_bus_master_tx)
2053 netif_wake_queue(dev);
2054 }
2055}
2056
2057static netdev_tx_t
2058vortex_start_xmit(struct sk_buff *skb, struct net_device *dev)
2059{
2060 struct vortex_private *vp = netdev_priv(dev);
2061 void __iomem *ioaddr = vp->ioaddr;
2062 int skblen = skb->len;
2063
2064
2065 iowrite32(skb->len, ioaddr + TX_FIFO);
2066 if (vp->bus_master) {
2067
2068 int len = (skb->len + 3) & ~3;
2069 vp->tx_skb_dma = dma_map_single(vp->gendev, skb->data, len,
2070 DMA_TO_DEVICE);
2071 if (dma_mapping_error(vp->gendev, vp->tx_skb_dma)) {
2072 dev_kfree_skb_any(skb);
2073 dev->stats.tx_dropped++;
2074 return NETDEV_TX_OK;
2075 }
2076
2077 spin_lock_irq(&vp->window_lock);
2078 window_set(vp, 7);
2079 iowrite32(vp->tx_skb_dma, ioaddr + Wn7_MasterAddr);
2080 iowrite16(len, ioaddr + Wn7_MasterLen);
2081 spin_unlock_irq(&vp->window_lock);
2082 vp->tx_skb = skb;
2083 skb_tx_timestamp(skb);
2084 iowrite16(StartDMADown, ioaddr + EL3_CMD);
2085
2086 } else {
2087
2088 skb_tx_timestamp(skb);
2089 iowrite32_rep(ioaddr + TX_FIFO, skb->data, (skb->len + 3) >> 2);
2090 dev_consume_skb_any (skb);
2091 if (ioread16(ioaddr + TxFree) > 1536) {
2092 netif_start_queue (dev);
2093 } else {
2094
2095 netif_stop_queue(dev);
2096 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2097 }
2098 }
2099
2100 netdev_sent_queue(dev, skblen);
2101
2102
2103 {
2104 int tx_status;
2105 int i = 32;
2106
2107 while (--i > 0 && (tx_status = ioread8(ioaddr + TxStatus)) > 0) {
2108 if (tx_status & 0x3C) {
2109 if (vortex_debug > 2)
2110 pr_debug("%s: Tx error, status %2.2x.\n",
2111 dev->name, tx_status);
2112 if (tx_status & 0x04) dev->stats.tx_fifo_errors++;
2113 if (tx_status & 0x38) dev->stats.tx_aborted_errors++;
2114 if (tx_status & 0x30) {
2115 issue_and_wait(dev, TxReset);
2116 }
2117 iowrite16(TxEnable, ioaddr + EL3_CMD);
2118 }
2119 iowrite8(0x00, ioaddr + TxStatus);
2120 }
2121 }
2122 return NETDEV_TX_OK;
2123}
2124
2125static netdev_tx_t
2126boomerang_start_xmit(struct sk_buff *skb, struct net_device *dev)
2127{
2128 struct vortex_private *vp = netdev_priv(dev);
2129 void __iomem *ioaddr = vp->ioaddr;
2130
2131 int entry = vp->cur_tx % TX_RING_SIZE;
2132 int skblen = skb->len;
2133 struct boom_tx_desc *prev_entry = &vp->tx_ring[(vp->cur_tx-1) % TX_RING_SIZE];
2134 unsigned long flags;
2135 dma_addr_t dma_addr;
2136
2137 if (vortex_debug > 6) {
2138 pr_debug("boomerang_start_xmit()\n");
2139 pr_debug("%s: Trying to send a packet, Tx index %d.\n",
2140 dev->name, vp->cur_tx);
2141 }
2142
2143
2144
2145
2146
2147
2148
2149 if (vp->handling_irq)
2150 return NETDEV_TX_BUSY;
2151
2152 if (vp->cur_tx - vp->dirty_tx >= TX_RING_SIZE) {
2153 if (vortex_debug > 0)
2154 pr_warn("%s: BUG! Tx Ring full, refusing to send buffer\n",
2155 dev->name);
2156 netif_stop_queue(dev);
2157 return NETDEV_TX_BUSY;
2158 }
2159
2160 vp->tx_skbuff[entry] = skb;
2161
2162 vp->tx_ring[entry].next = 0;
2163#if DO_ZEROCOPY
2164 if (skb->ip_summed != CHECKSUM_PARTIAL)
2165 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2166 else
2167 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded | AddTCPChksum | AddUDPChksum);
2168
2169 if (!skb_shinfo(skb)->nr_frags) {
2170 dma_addr = dma_map_single(vp->gendev, skb->data, skb->len,
2171 DMA_TO_DEVICE);
2172 if (dma_mapping_error(vp->gendev, dma_addr))
2173 goto out_dma_err;
2174
2175 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2176 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb->len | LAST_FRAG);
2177 } else {
2178 int i;
2179
2180 dma_addr = dma_map_single(vp->gendev, skb->data,
2181 skb_headlen(skb), DMA_TO_DEVICE);
2182 if (dma_mapping_error(vp->gendev, dma_addr))
2183 goto out_dma_err;
2184
2185 vp->tx_ring[entry].frag[0].addr = cpu_to_le32(dma_addr);
2186 vp->tx_ring[entry].frag[0].length = cpu_to_le32(skb_headlen(skb));
2187
2188 for (i = 0; i < skb_shinfo(skb)->nr_frags; i++) {
2189 skb_frag_t *frag = &skb_shinfo(skb)->frags[i];
2190
2191 dma_addr = skb_frag_dma_map(vp->gendev, frag,
2192 0,
2193 frag->size,
2194 DMA_TO_DEVICE);
2195 if (dma_mapping_error(vp->gendev, dma_addr)) {
2196 for(i = i-1; i >= 0; i--)
2197 dma_unmap_page(vp->gendev,
2198 le32_to_cpu(vp->tx_ring[entry].frag[i+1].addr),
2199 le32_to_cpu(vp->tx_ring[entry].frag[i+1].length),
2200 DMA_TO_DEVICE);
2201
2202 dma_unmap_single(vp->gendev,
2203 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2204 le32_to_cpu(vp->tx_ring[entry].frag[0].length),
2205 DMA_TO_DEVICE);
2206
2207 goto out_dma_err;
2208 }
2209
2210 vp->tx_ring[entry].frag[i+1].addr =
2211 cpu_to_le32(dma_addr);
2212
2213 if (i == skb_shinfo(skb)->nr_frags-1)
2214 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag)|LAST_FRAG);
2215 else
2216 vp->tx_ring[entry].frag[i+1].length = cpu_to_le32(skb_frag_size(frag));
2217 }
2218 }
2219#else
2220 dma_addr = dma_map_single(vp->gendev, skb->data, skb->len, DMA_TO_DEVICE);
2221 if (dma_mapping_error(vp->gendev, dma_addr))
2222 goto out_dma_err;
2223 vp->tx_ring[entry].addr = cpu_to_le32(dma_addr);
2224 vp->tx_ring[entry].length = cpu_to_le32(skb->len | LAST_FRAG);
2225 vp->tx_ring[entry].status = cpu_to_le32(skb->len | TxIntrUploaded);
2226#endif
2227
2228 spin_lock_irqsave(&vp->lock, flags);
2229
2230 issue_and_wait(dev, DownStall);
2231 prev_entry->next = cpu_to_le32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc));
2232 if (ioread32(ioaddr + DownListPtr) == 0) {
2233 iowrite32(vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc), ioaddr + DownListPtr);
2234 vp->queued_packet++;
2235 }
2236
2237 vp->cur_tx++;
2238 netdev_sent_queue(dev, skblen);
2239
2240 if (vp->cur_tx - vp->dirty_tx > TX_RING_SIZE - 1) {
2241 netif_stop_queue (dev);
2242 } else {
2243#if defined(tx_interrupt_mitigation)
2244
2245
2246
2247 prev_entry->status &= cpu_to_le32(~TxIntrUploaded);
2248#endif
2249 }
2250 skb_tx_timestamp(skb);
2251 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2252 spin_unlock_irqrestore(&vp->lock, flags);
2253out:
2254 return NETDEV_TX_OK;
2255out_dma_err:
2256 dev_err(vp->gendev, "Error mapping dma buffer\n");
2257 goto out;
2258}
2259
2260
2261
2262
2263
2264
2265
2266
2267
2268static irqreturn_t
2269vortex_interrupt(int irq, void *dev_id)
2270{
2271 struct net_device *dev = dev_id;
2272 struct vortex_private *vp = netdev_priv(dev);
2273 void __iomem *ioaddr;
2274 int status;
2275 int work_done = max_interrupt_work;
2276 int handled = 0;
2277 unsigned int bytes_compl = 0, pkts_compl = 0;
2278
2279 ioaddr = vp->ioaddr;
2280 spin_lock(&vp->lock);
2281
2282 status = ioread16(ioaddr + EL3_STATUS);
2283
2284 if (vortex_debug > 6)
2285 pr_debug("vortex_interrupt(). status=0x%4x\n", status);
2286
2287 if ((status & IntLatch) == 0)
2288 goto handler_exit;
2289 handled = 1;
2290
2291 if (status & IntReq) {
2292 status |= vp->deferred;
2293 vp->deferred = 0;
2294 }
2295
2296 if (status == 0xffff)
2297 goto handler_exit;
2298
2299 if (vortex_debug > 4)
2300 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2301 dev->name, status, ioread8(ioaddr + Timer));
2302
2303 spin_lock(&vp->window_lock);
2304 window_set(vp, 7);
2305
2306 do {
2307 if (vortex_debug > 5)
2308 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2309 dev->name, status);
2310 if (status & RxComplete)
2311 vortex_rx(dev);
2312
2313 if (status & TxAvailable) {
2314 if (vortex_debug > 5)
2315 pr_debug(" TX room bit was handled.\n");
2316
2317 iowrite16(AckIntr | TxAvailable, ioaddr + EL3_CMD);
2318 netif_wake_queue (dev);
2319 }
2320
2321 if (status & DMADone) {
2322 if (ioread16(ioaddr + Wn7_MasterStatus) & 0x1000) {
2323 iowrite16(0x1000, ioaddr + Wn7_MasterStatus);
2324 dma_unmap_single(vp->gendev, vp->tx_skb_dma, (vp->tx_skb->len + 3) & ~3, DMA_TO_DEVICE);
2325 pkts_compl++;
2326 bytes_compl += vp->tx_skb->len;
2327 dev_kfree_skb_irq(vp->tx_skb);
2328 if (ioread16(ioaddr + TxFree) > 1536) {
2329
2330
2331
2332
2333
2334 netif_wake_queue(dev);
2335 } else {
2336 iowrite16(SetTxThreshold + (1536>>2), ioaddr + EL3_CMD);
2337 netif_stop_queue(dev);
2338 }
2339 }
2340 }
2341
2342 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq)) {
2343 if (status == 0xffff)
2344 break;
2345 if (status & RxEarly)
2346 vortex_rx(dev);
2347 spin_unlock(&vp->window_lock);
2348 vortex_error(dev, status);
2349 spin_lock(&vp->window_lock);
2350 window_set(vp, 7);
2351 }
2352
2353 if (--work_done < 0) {
2354 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2355 dev->name, status);
2356
2357 do {
2358 vp->deferred |= status;
2359 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2360 ioaddr + EL3_CMD);
2361 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2362 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2363
2364 mod_timer(&vp->timer, jiffies + 1*HZ);
2365 break;
2366 }
2367
2368 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2369 } while ((status = ioread16(ioaddr + EL3_STATUS)) & (IntLatch | RxComplete));
2370
2371 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2372 spin_unlock(&vp->window_lock);
2373
2374 if (vortex_debug > 4)
2375 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2376 dev->name, status);
2377handler_exit:
2378 spin_unlock(&vp->lock);
2379 return IRQ_RETVAL(handled);
2380}
2381
2382
2383
2384
2385
2386
2387static irqreturn_t
2388boomerang_interrupt(int irq, void *dev_id)
2389{
2390 struct net_device *dev = dev_id;
2391 struct vortex_private *vp = netdev_priv(dev);
2392 void __iomem *ioaddr;
2393 int status;
2394 int work_done = max_interrupt_work;
2395 int handled = 0;
2396 unsigned int bytes_compl = 0, pkts_compl = 0;
2397
2398 ioaddr = vp->ioaddr;
2399
2400
2401
2402
2403
2404
2405 spin_lock(&vp->lock);
2406 vp->handling_irq = 1;
2407
2408 status = ioread16(ioaddr + EL3_STATUS);
2409
2410 if (vortex_debug > 6)
2411 pr_debug("boomerang_interrupt. status=0x%4x\n", status);
2412
2413 if ((status & IntLatch) == 0)
2414 goto handler_exit;
2415 handled = 1;
2416
2417 if (status == 0xffff) {
2418 if (vortex_debug > 1)
2419 pr_debug("boomerang_interrupt(1): status = 0xffff\n");
2420 goto handler_exit;
2421 }
2422
2423 if (status & IntReq) {
2424 status |= vp->deferred;
2425 vp->deferred = 0;
2426 }
2427
2428 if (vortex_debug > 4)
2429 pr_debug("%s: interrupt, status %4.4x, latency %d ticks.\n",
2430 dev->name, status, ioread8(ioaddr + Timer));
2431 do {
2432 if (vortex_debug > 5)
2433 pr_debug("%s: In interrupt loop, status %4.4x.\n",
2434 dev->name, status);
2435 if (status & UpComplete) {
2436 iowrite16(AckIntr | UpComplete, ioaddr + EL3_CMD);
2437 if (vortex_debug > 5)
2438 pr_debug("boomerang_interrupt->boomerang_rx\n");
2439 boomerang_rx(dev);
2440 }
2441
2442 if (status & DownComplete) {
2443 unsigned int dirty_tx = vp->dirty_tx;
2444
2445 iowrite16(AckIntr | DownComplete, ioaddr + EL3_CMD);
2446 while (vp->cur_tx - dirty_tx > 0) {
2447 int entry = dirty_tx % TX_RING_SIZE;
2448#if 1
2449 if (ioread32(ioaddr + DownListPtr) ==
2450 vp->tx_ring_dma + entry * sizeof(struct boom_tx_desc))
2451 break;
2452#else
2453 if ((vp->tx_ring[entry].status & DN_COMPLETE) == 0)
2454 break;
2455#endif
2456
2457 if (vp->tx_skbuff[entry]) {
2458 struct sk_buff *skb = vp->tx_skbuff[entry];
2459#if DO_ZEROCOPY
2460 int i;
2461 dma_unmap_single(vp->gendev,
2462 le32_to_cpu(vp->tx_ring[entry].frag[0].addr),
2463 le32_to_cpu(vp->tx_ring[entry].frag[0].length)&0xFFF,
2464 DMA_TO_DEVICE);
2465
2466 for (i=1; i<=skb_shinfo(skb)->nr_frags; i++)
2467 dma_unmap_page(vp->gendev,
2468 le32_to_cpu(vp->tx_ring[entry].frag[i].addr),
2469 le32_to_cpu(vp->tx_ring[entry].frag[i].length)&0xFFF,
2470 DMA_TO_DEVICE);
2471#else
2472 dma_unmap_single(vp->gendev,
2473 le32_to_cpu(vp->tx_ring[entry].addr), skb->len, DMA_TO_DEVICE);
2474#endif
2475 pkts_compl++;
2476 bytes_compl += skb->len;
2477 dev_kfree_skb_irq(skb);
2478 vp->tx_skbuff[entry] = NULL;
2479 } else {
2480 pr_debug("boomerang_interrupt: no skb!\n");
2481 }
2482
2483 dirty_tx++;
2484 }
2485 vp->dirty_tx = dirty_tx;
2486 if (vp->cur_tx - dirty_tx <= TX_RING_SIZE - 1) {
2487 if (vortex_debug > 6)
2488 pr_debug("boomerang_interrupt: wake queue\n");
2489 netif_wake_queue (dev);
2490 }
2491 }
2492
2493
2494 if (status & (HostError | RxEarly | StatsFull | TxComplete | IntReq))
2495 vortex_error(dev, status);
2496
2497 if (--work_done < 0) {
2498 pr_warn("%s: Too much work in interrupt, status %4.4x\n",
2499 dev->name, status);
2500
2501 do {
2502 vp->deferred |= status;
2503 iowrite16(SetStatusEnb | (~vp->deferred & vp->status_enable),
2504 ioaddr + EL3_CMD);
2505 iowrite16(AckIntr | (vp->deferred & 0x7ff), ioaddr + EL3_CMD);
2506 } while ((status = ioread16(ioaddr + EL3_CMD)) & IntLatch);
2507
2508 mod_timer(&vp->timer, jiffies + 1*HZ);
2509 break;
2510 }
2511
2512 iowrite16(AckIntr | IntReq | IntLatch, ioaddr + EL3_CMD);
2513 if (vp->cb_fn_base)
2514 iowrite32(0x8000, vp->cb_fn_base + 4);
2515
2516 } while ((status = ioread16(ioaddr + EL3_STATUS)) & IntLatch);
2517 netdev_completed_queue(dev, pkts_compl, bytes_compl);
2518
2519 if (vortex_debug > 4)
2520 pr_debug("%s: exiting interrupt, status %4.4x.\n",
2521 dev->name, status);
2522handler_exit:
2523 vp->handling_irq = 0;
2524 spin_unlock(&vp->lock);
2525 return IRQ_RETVAL(handled);
2526}
2527
2528static int vortex_rx(struct net_device *dev)
2529{
2530 struct vortex_private *vp = netdev_priv(dev);
2531 void __iomem *ioaddr = vp->ioaddr;
2532 int i;
2533 short rx_status;
2534
2535 if (vortex_debug > 5)
2536 pr_debug("vortex_rx(): status %4.4x, rx_status %4.4x.\n",
2537 ioread16(ioaddr+EL3_STATUS), ioread16(ioaddr+RxStatus));
2538 while ((rx_status = ioread16(ioaddr + RxStatus)) > 0) {
2539 if (rx_status & 0x4000) {
2540 unsigned char rx_error = ioread8(ioaddr + RxErrors);
2541 if (vortex_debug > 2)
2542 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2543 dev->stats.rx_errors++;
2544 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2545 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2546 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2547 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2548 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2549 } else {
2550
2551 int pkt_len = rx_status & 0x1fff;
2552 struct sk_buff *skb;
2553
2554 skb = netdev_alloc_skb(dev, pkt_len + 5);
2555 if (vortex_debug > 4)
2556 pr_debug("Receiving packet size %d status %4.4x.\n",
2557 pkt_len, rx_status);
2558 if (skb != NULL) {
2559 skb_reserve(skb, 2);
2560
2561 if (vp->bus_master &&
2562 ! (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)) {
2563 dma_addr_t dma = dma_map_single(vp->gendev, skb_put(skb, pkt_len),
2564 pkt_len, DMA_FROM_DEVICE);
2565 iowrite32(dma, ioaddr + Wn7_MasterAddr);
2566 iowrite16((skb->len + 3) & ~3, ioaddr + Wn7_MasterLen);
2567 iowrite16(StartDMAUp, ioaddr + EL3_CMD);
2568 while (ioread16(ioaddr + Wn7_MasterStatus) & 0x8000)
2569 ;
2570 dma_unmap_single(vp->gendev, dma, pkt_len, DMA_FROM_DEVICE);
2571 } else {
2572 ioread32_rep(ioaddr + RX_FIFO,
2573 skb_put(skb, pkt_len),
2574 (pkt_len + 3) >> 2);
2575 }
2576 iowrite16(RxDiscard, ioaddr + EL3_CMD);
2577 skb->protocol = eth_type_trans(skb, dev);
2578 netif_rx(skb);
2579 dev->stats.rx_packets++;
2580
2581 for (i = 200; i >= 0; i--)
2582 if ( ! (ioread16(ioaddr + EL3_STATUS) & CmdInProgress))
2583 break;
2584 continue;
2585 } else if (vortex_debug > 0)
2586 pr_notice("%s: No memory to allocate a sk_buff of size %d.\n",
2587 dev->name, pkt_len);
2588 dev->stats.rx_dropped++;
2589 }
2590 issue_and_wait(dev, RxDiscard);
2591 }
2592
2593 return 0;
2594}
2595
2596static int
2597boomerang_rx(struct net_device *dev)
2598{
2599 struct vortex_private *vp = netdev_priv(dev);
2600 int entry = vp->cur_rx % RX_RING_SIZE;
2601 void __iomem *ioaddr = vp->ioaddr;
2602 int rx_status;
2603 int rx_work_limit = RX_RING_SIZE;
2604
2605 if (vortex_debug > 5)
2606 pr_debug("boomerang_rx(): status %4.4x\n", ioread16(ioaddr+EL3_STATUS));
2607
2608 while ((rx_status = le32_to_cpu(vp->rx_ring[entry].status)) & RxDComplete){
2609 if (--rx_work_limit < 0)
2610 break;
2611 if (rx_status & RxDError) {
2612 unsigned char rx_error = rx_status >> 16;
2613 if (vortex_debug > 2)
2614 pr_debug(" Rx error: status %2.2x.\n", rx_error);
2615 dev->stats.rx_errors++;
2616 if (rx_error & 0x01) dev->stats.rx_over_errors++;
2617 if (rx_error & 0x02) dev->stats.rx_length_errors++;
2618 if (rx_error & 0x04) dev->stats.rx_frame_errors++;
2619 if (rx_error & 0x08) dev->stats.rx_crc_errors++;
2620 if (rx_error & 0x10) dev->stats.rx_length_errors++;
2621 } else {
2622
2623 int pkt_len = rx_status & 0x1fff;
2624 struct sk_buff *skb, *newskb;
2625 dma_addr_t newdma;
2626 dma_addr_t dma = le32_to_cpu(vp->rx_ring[entry].addr);
2627
2628 if (vortex_debug > 4)
2629 pr_debug("Receiving packet size %d status %4.4x.\n",
2630 pkt_len, rx_status);
2631
2632
2633
2634 if (pkt_len < rx_copybreak &&
2635 (skb = netdev_alloc_skb(dev, pkt_len + 2)) != NULL) {
2636 skb_reserve(skb, 2);
2637 dma_sync_single_for_cpu(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2638
2639 skb_put_data(skb, vp->rx_skbuff[entry]->data,
2640 pkt_len);
2641 dma_sync_single_for_device(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2642 vp->rx_copy++;
2643 } else {
2644
2645
2646
2647
2648 newskb = netdev_alloc_skb_ip_align(dev, PKT_BUF_SZ);
2649 if (!newskb) {
2650 dev->stats.rx_dropped++;
2651 goto clear_complete;
2652 }
2653 newdma = dma_map_single(vp->gendev, newskb->data,
2654 PKT_BUF_SZ, DMA_FROM_DEVICE);
2655 if (dma_mapping_error(vp->gendev, newdma)) {
2656 dev->stats.rx_dropped++;
2657 consume_skb(newskb);
2658 goto clear_complete;
2659 }
2660
2661
2662 skb = vp->rx_skbuff[entry];
2663 vp->rx_skbuff[entry] = newskb;
2664 vp->rx_ring[entry].addr = cpu_to_le32(newdma);
2665 skb_put(skb, pkt_len);
2666 dma_unmap_single(vp->gendev, dma, PKT_BUF_SZ, DMA_FROM_DEVICE);
2667 vp->rx_nocopy++;
2668 }
2669 skb->protocol = eth_type_trans(skb, dev);
2670 {
2671 int csum_bits = rx_status & 0xee000000;
2672 if (csum_bits &&
2673 (csum_bits == (IPChksumValid | TCPChksumValid) ||
2674 csum_bits == (IPChksumValid | UDPChksumValid))) {
2675 skb->ip_summed = CHECKSUM_UNNECESSARY;
2676 vp->rx_csumhits++;
2677 }
2678 }
2679 netif_rx(skb);
2680 dev->stats.rx_packets++;
2681 }
2682
2683clear_complete:
2684 vp->rx_ring[entry].status = 0;
2685 iowrite16(UpUnstall, ioaddr + EL3_CMD);
2686 entry = (++vp->cur_rx) % RX_RING_SIZE;
2687 }
2688 return 0;
2689}
2690
2691static void
2692vortex_down(struct net_device *dev, int final_down)
2693{
2694 struct vortex_private *vp = netdev_priv(dev);
2695 void __iomem *ioaddr = vp->ioaddr;
2696
2697 netdev_reset_queue(dev);
2698 netif_stop_queue(dev);
2699
2700 del_timer_sync(&vp->timer);
2701
2702
2703 iowrite16(StatsDisable, ioaddr + EL3_CMD);
2704
2705
2706 iowrite16(RxDisable, ioaddr + EL3_CMD);
2707 iowrite16(TxDisable, ioaddr + EL3_CMD);
2708
2709
2710 set_8021q_mode(dev, 0);
2711
2712 if (dev->if_port == XCVR_10base2)
2713
2714 iowrite16(StopCoax, ioaddr + EL3_CMD);
2715
2716 iowrite16(SetIntrEnb | 0x0000, ioaddr + EL3_CMD);
2717
2718 update_stats(ioaddr, dev);
2719 if (vp->full_bus_master_rx)
2720 iowrite32(0, ioaddr + UpListPtr);
2721 if (vp->full_bus_master_tx)
2722 iowrite32(0, ioaddr + DownListPtr);
2723
2724 if (final_down && VORTEX_PCI(vp)) {
2725 vp->pm_state_valid = 1;
2726 pci_save_state(VORTEX_PCI(vp));
2727 acpi_set_WOL(dev);
2728 }
2729}
2730
2731static int
2732vortex_close(struct net_device *dev)
2733{
2734 struct vortex_private *vp = netdev_priv(dev);
2735 void __iomem *ioaddr = vp->ioaddr;
2736 int i;
2737
2738 if (netif_device_present(dev))
2739 vortex_down(dev, 1);
2740
2741 if (vortex_debug > 1) {
2742 pr_debug("%s: vortex_close() status %4.4x, Tx status %2.2x.\n",
2743 dev->name, ioread16(ioaddr + EL3_STATUS), ioread8(ioaddr + TxStatus));
2744 pr_debug("%s: vortex close stats: rx_nocopy %d rx_copy %d"
2745 " tx_queued %d Rx pre-checksummed %d.\n",
2746 dev->name, vp->rx_nocopy, vp->rx_copy, vp->queued_packet, vp->rx_csumhits);
2747 }
2748
2749#if DO_ZEROCOPY
2750 if (vp->rx_csumhits &&
2751 (vp->drv_flags & HAS_HWCKSM) == 0 &&
2752 (vp->card_idx >= MAX_UNITS || hw_checksums[vp->card_idx] == -1)) {
2753 pr_warn("%s supports hardware checksums, and we're not using them!\n",
2754 dev->name);
2755 }
2756#endif
2757
2758 free_irq(dev->irq, dev);
2759
2760 if (vp->full_bus_master_rx) {
2761 for (i = 0; i < RX_RING_SIZE; i++)
2762 if (vp->rx_skbuff[i]) {
2763 dma_unmap_single(vp->gendev, le32_to_cpu(vp->rx_ring[i].addr),
2764 PKT_BUF_SZ, DMA_FROM_DEVICE);
2765 dev_kfree_skb(vp->rx_skbuff[i]);
2766 vp->rx_skbuff[i] = NULL;
2767 }
2768 }
2769 if (vp->full_bus_master_tx) {
2770 for (i = 0; i < TX_RING_SIZE; i++) {
2771 if (vp->tx_skbuff[i]) {
2772 struct sk_buff *skb = vp->tx_skbuff[i];
2773#if DO_ZEROCOPY
2774 int k;
2775
2776 for (k=0; k<=skb_shinfo(skb)->nr_frags; k++)
2777 dma_unmap_single(vp->gendev,
2778 le32_to_cpu(vp->tx_ring[i].frag[k].addr),
2779 le32_to_cpu(vp->tx_ring[i].frag[k].length)&0xFFF,
2780 DMA_TO_DEVICE);
2781#else
2782 dma_unmap_single(vp->gendev, le32_to_cpu(vp->tx_ring[i].addr), skb->len, DMA_TO_DEVICE);
2783#endif
2784 dev_kfree_skb(skb);
2785 vp->tx_skbuff[i] = NULL;
2786 }
2787 }
2788 }
2789
2790 return 0;
2791}
2792
2793static void
2794dump_tx_ring(struct net_device *dev)
2795{
2796 if (vortex_debug > 0) {
2797 struct vortex_private *vp = netdev_priv(dev);
2798 void __iomem *ioaddr = vp->ioaddr;
2799
2800 if (vp->full_bus_master_tx) {
2801 int i;
2802 int stalled = ioread32(ioaddr + PktStatus) & 0x04;
2803
2804 pr_err(" Flags; bus-master %d, dirty %d(%d) current %d(%d)\n",
2805 vp->full_bus_master_tx,
2806 vp->dirty_tx, vp->dirty_tx % TX_RING_SIZE,
2807 vp->cur_tx, vp->cur_tx % TX_RING_SIZE);
2808 pr_err(" Transmit list %8.8x vs. %p.\n",
2809 ioread32(ioaddr + DownListPtr),
2810 &vp->tx_ring[vp->dirty_tx % TX_RING_SIZE]);
2811 issue_and_wait(dev, DownStall);
2812 for (i = 0; i < TX_RING_SIZE; i++) {
2813 unsigned int length;
2814
2815#if DO_ZEROCOPY
2816 length = le32_to_cpu(vp->tx_ring[i].frag[0].length);
2817#else
2818 length = le32_to_cpu(vp->tx_ring[i].length);
2819#endif
2820 pr_err(" %d: @%p length %8.8x status %8.8x\n",
2821 i, &vp->tx_ring[i], length,
2822 le32_to_cpu(vp->tx_ring[i].status));
2823 }
2824 if (!stalled)
2825 iowrite16(DownUnstall, ioaddr + EL3_CMD);
2826 }
2827 }
2828}
2829
2830static struct net_device_stats *vortex_get_stats(struct net_device *dev)
2831{
2832 struct vortex_private *vp = netdev_priv(dev);
2833 void __iomem *ioaddr = vp->ioaddr;
2834 unsigned long flags;
2835
2836 if (netif_device_present(dev)) {
2837 spin_lock_irqsave (&vp->lock, flags);
2838 update_stats(ioaddr, dev);
2839 spin_unlock_irqrestore (&vp->lock, flags);
2840 }
2841 return &dev->stats;
2842}
2843
2844
2845
2846
2847
2848
2849
2850
2851static void update_stats(void __iomem *ioaddr, struct net_device *dev)
2852{
2853 struct vortex_private *vp = netdev_priv(dev);
2854
2855
2856
2857 dev->stats.tx_carrier_errors += window_read8(vp, 6, 0);
2858 dev->stats.tx_heartbeat_errors += window_read8(vp, 6, 1);
2859 dev->stats.tx_window_errors += window_read8(vp, 6, 4);
2860 dev->stats.rx_fifo_errors += window_read8(vp, 6, 5);
2861 dev->stats.tx_packets += window_read8(vp, 6, 6);
2862 dev->stats.tx_packets += (window_read8(vp, 6, 9) &
2863 0x30) << 4;
2864 window_read8(vp, 6, 7);
2865
2866
2867
2868 dev->stats.rx_bytes += window_read16(vp, 6, 10);
2869 dev->stats.tx_bytes += window_read16(vp, 6, 12);
2870
2871 vp->xstats.tx_multiple_collisions += window_read8(vp, 6, 2);
2872 vp->xstats.tx_single_collisions += window_read8(vp, 6, 3);
2873 vp->xstats.tx_deferred += window_read8(vp, 6, 8);
2874 vp->xstats.rx_bad_ssd += window_read8(vp, 4, 12);
2875
2876 dev->stats.collisions = vp->xstats.tx_multiple_collisions
2877 + vp->xstats.tx_single_collisions
2878 + vp->xstats.tx_max_collisions;
2879
2880 {
2881 u8 up = window_read8(vp, 4, 13);
2882 dev->stats.rx_bytes += (up & 0x0f) << 16;
2883 dev->stats.tx_bytes += (up & 0xf0) << 12;
2884 }
2885}
2886
2887static int vortex_nway_reset(struct net_device *dev)
2888{
2889 struct vortex_private *vp = netdev_priv(dev);
2890
2891 return mii_nway_restart(&vp->mii);
2892}
2893
2894static int vortex_get_link_ksettings(struct net_device *dev,
2895 struct ethtool_link_ksettings *cmd)
2896{
2897 struct vortex_private *vp = netdev_priv(dev);
2898
2899 mii_ethtool_get_link_ksettings(&vp->mii, cmd);
2900
2901 return 0;
2902}
2903
2904static int vortex_set_link_ksettings(struct net_device *dev,
2905 const struct ethtool_link_ksettings *cmd)
2906{
2907 struct vortex_private *vp = netdev_priv(dev);
2908
2909 return mii_ethtool_set_link_ksettings(&vp->mii, cmd);
2910}
2911
2912static u32 vortex_get_msglevel(struct net_device *dev)
2913{
2914 return vortex_debug;
2915}
2916
2917static void vortex_set_msglevel(struct net_device *dev, u32 dbg)
2918{
2919 vortex_debug = dbg;
2920}
2921
2922static int vortex_get_sset_count(struct net_device *dev, int sset)
2923{
2924 switch (sset) {
2925 case ETH_SS_STATS:
2926 return VORTEX_NUM_STATS;
2927 default:
2928 return -EOPNOTSUPP;
2929 }
2930}
2931
2932static void vortex_get_ethtool_stats(struct net_device *dev,
2933 struct ethtool_stats *stats, u64 *data)
2934{
2935 struct vortex_private *vp = netdev_priv(dev);
2936 void __iomem *ioaddr = vp->ioaddr;
2937 unsigned long flags;
2938
2939 spin_lock_irqsave(&vp->lock, flags);
2940 update_stats(ioaddr, dev);
2941 spin_unlock_irqrestore(&vp->lock, flags);
2942
2943 data[0] = vp->xstats.tx_deferred;
2944 data[1] = vp->xstats.tx_max_collisions;
2945 data[2] = vp->xstats.tx_multiple_collisions;
2946 data[3] = vp->xstats.tx_single_collisions;
2947 data[4] = vp->xstats.rx_bad_ssd;
2948}
2949
2950
2951static void vortex_get_strings(struct net_device *dev, u32 stringset, u8 *data)
2952{
2953 switch (stringset) {
2954 case ETH_SS_STATS:
2955 memcpy(data, ðtool_stats_keys, sizeof(ethtool_stats_keys));
2956 break;
2957 default:
2958 WARN_ON(1);
2959 break;
2960 }
2961}
2962
2963static void vortex_get_drvinfo(struct net_device *dev,
2964 struct ethtool_drvinfo *info)
2965{
2966 struct vortex_private *vp = netdev_priv(dev);
2967
2968 strlcpy(info->driver, DRV_NAME, sizeof(info->driver));
2969 if (VORTEX_PCI(vp)) {
2970 strlcpy(info->bus_info, pci_name(VORTEX_PCI(vp)),
2971 sizeof(info->bus_info));
2972 } else {
2973 if (VORTEX_EISA(vp))
2974 strlcpy(info->bus_info, dev_name(vp->gendev),
2975 sizeof(info->bus_info));
2976 else
2977 snprintf(info->bus_info, sizeof(info->bus_info),
2978 "EISA 0x%lx %d", dev->base_addr, dev->irq);
2979 }
2980}
2981
2982static void vortex_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2983{
2984 struct vortex_private *vp = netdev_priv(dev);
2985
2986 if (!VORTEX_PCI(vp))
2987 return;
2988
2989 wol->supported = WAKE_MAGIC;
2990
2991 wol->wolopts = 0;
2992 if (vp->enable_wol)
2993 wol->wolopts |= WAKE_MAGIC;
2994}
2995
2996static int vortex_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol)
2997{
2998 struct vortex_private *vp = netdev_priv(dev);
2999
3000 if (!VORTEX_PCI(vp))
3001 return -EOPNOTSUPP;
3002
3003 if (wol->wolopts & ~WAKE_MAGIC)
3004 return -EINVAL;
3005
3006 if (wol->wolopts & WAKE_MAGIC)
3007 vp->enable_wol = 1;
3008 else
3009 vp->enable_wol = 0;
3010 acpi_set_WOL(dev);
3011
3012 return 0;
3013}
3014
3015static const struct ethtool_ops vortex_ethtool_ops = {
3016 .get_drvinfo = vortex_get_drvinfo,
3017 .get_strings = vortex_get_strings,
3018 .get_msglevel = vortex_get_msglevel,
3019 .set_msglevel = vortex_set_msglevel,
3020 .get_ethtool_stats = vortex_get_ethtool_stats,
3021 .get_sset_count = vortex_get_sset_count,
3022 .get_link = ethtool_op_get_link,
3023 .nway_reset = vortex_nway_reset,
3024 .get_wol = vortex_get_wol,
3025 .set_wol = vortex_set_wol,
3026 .get_ts_info = ethtool_op_get_ts_info,
3027 .get_link_ksettings = vortex_get_link_ksettings,
3028 .set_link_ksettings = vortex_set_link_ksettings,
3029};
3030
3031#ifdef CONFIG_PCI
3032
3033
3034
3035static int vortex_ioctl(struct net_device *dev, struct ifreq *rq, int cmd)
3036{
3037 int err;
3038 struct vortex_private *vp = netdev_priv(dev);
3039 pci_power_t state = 0;
3040
3041 if(VORTEX_PCI(vp))
3042 state = VORTEX_PCI(vp)->current_state;
3043
3044
3045
3046 if(state != 0)
3047 pci_set_power_state(VORTEX_PCI(vp), PCI_D0);
3048 err = generic_mii_ioctl(&vp->mii, if_mii(rq), cmd, NULL);
3049 if(state != 0)
3050 pci_set_power_state(VORTEX_PCI(vp), state);
3051
3052 return err;
3053}
3054#endif
3055
3056
3057
3058
3059
3060static void set_rx_mode(struct net_device *dev)
3061{
3062 struct vortex_private *vp = netdev_priv(dev);
3063 void __iomem *ioaddr = vp->ioaddr;
3064 int new_mode;
3065
3066 if (dev->flags & IFF_PROMISC) {
3067 if (vortex_debug > 3)
3068 pr_notice("%s: Setting promiscuous mode.\n", dev->name);
3069 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast|RxProm;
3070 } else if (!netdev_mc_empty(dev) || dev->flags & IFF_ALLMULTI) {
3071 new_mode = SetRxFilter|RxStation|RxMulticast|RxBroadcast;
3072 } else
3073 new_mode = SetRxFilter | RxStation | RxBroadcast;
3074
3075 iowrite16(new_mode, ioaddr + EL3_CMD);
3076}
3077
3078#if IS_ENABLED(CONFIG_VLAN_8021Q)
3079
3080
3081
3082
3083
3084#define VLAN_ETHER_TYPE 0x8100
3085
3086static void set_8021q_mode(struct net_device *dev, int enable)
3087{
3088 struct vortex_private *vp = netdev_priv(dev);
3089 int mac_ctrl;
3090
3091 if ((vp->drv_flags&IS_CYCLONE) || (vp->drv_flags&IS_TORNADO)) {
3092
3093
3094
3095 int max_pkt_size = dev->mtu+14;
3096 if (enable)
3097 max_pkt_size += 4;
3098
3099 window_write16(vp, max_pkt_size, 3, Wn3_MaxPktSize);
3100
3101
3102
3103 window_write16(vp, VLAN_ETHER_TYPE, 7, Wn7_VlanEtherType);
3104 } else {
3105
3106
3107 vp->large_frames = dev->mtu > 1500 || enable;
3108
3109 mac_ctrl = window_read16(vp, 3, Wn3_MAC_Ctrl);
3110 if (vp->large_frames)
3111 mac_ctrl |= 0x40;
3112 else
3113 mac_ctrl &= ~0x40;
3114 window_write16(vp, mac_ctrl, 3, Wn3_MAC_Ctrl);
3115 }
3116}
3117#else
3118
3119static void set_8021q_mode(struct net_device *dev, int enable)
3120{
3121}
3122
3123
3124#endif
3125
3126
3127
3128
3129
3130
3131
3132
3133
3134static void mdio_delay(struct vortex_private *vp)
3135{
3136 window_read32(vp, 4, Wn4_PhysicalMgmt);
3137}
3138
3139#define MDIO_SHIFT_CLK 0x01
3140#define MDIO_DIR_WRITE 0x04
3141#define MDIO_DATA_WRITE0 (0x00 | MDIO_DIR_WRITE)
3142#define MDIO_DATA_WRITE1 (0x02 | MDIO_DIR_WRITE)
3143#define MDIO_DATA_READ 0x02
3144#define MDIO_ENB_IN 0x00
3145
3146
3147
3148static void mdio_sync(struct vortex_private *vp, int bits)
3149{
3150
3151 while (-- bits >= 0) {
3152 window_write16(vp, MDIO_DATA_WRITE1, 4, Wn4_PhysicalMgmt);
3153 mdio_delay(vp);
3154 window_write16(vp, MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK,
3155 4, Wn4_PhysicalMgmt);
3156 mdio_delay(vp);
3157 }
3158}
3159
3160static int mdio_read(struct net_device *dev, int phy_id, int location)
3161{
3162 int i;
3163 struct vortex_private *vp = netdev_priv(dev);
3164 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
3165 unsigned int retval = 0;
3166
3167 spin_lock_bh(&vp->mii_lock);
3168
3169 if (mii_preamble_required)
3170 mdio_sync(vp, 32);
3171
3172
3173 for (i = 14; i >= 0; i--) {
3174 int dataval = (read_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3175 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3176 mdio_delay(vp);
3177 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3178 4, Wn4_PhysicalMgmt);
3179 mdio_delay(vp);
3180 }
3181
3182 for (i = 19; i > 0; i--) {
3183 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3184 mdio_delay(vp);
3185 retval = (retval << 1) |
3186 ((window_read16(vp, 4, Wn4_PhysicalMgmt) &
3187 MDIO_DATA_READ) ? 1 : 0);
3188 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3189 4, Wn4_PhysicalMgmt);
3190 mdio_delay(vp);
3191 }
3192
3193 spin_unlock_bh(&vp->mii_lock);
3194
3195 return retval & 0x20000 ? 0xffff : retval>>1 & 0xffff;
3196}
3197
3198static void mdio_write(struct net_device *dev, int phy_id, int location, int value)
3199{
3200 struct vortex_private *vp = netdev_priv(dev);
3201 int write_cmd = 0x50020000 | (phy_id << 23) | (location << 18) | value;
3202 int i;
3203
3204 spin_lock_bh(&vp->mii_lock);
3205
3206 if (mii_preamble_required)
3207 mdio_sync(vp, 32);
3208
3209
3210 for (i = 31; i >= 0; i--) {
3211 int dataval = (write_cmd&(1<<i)) ? MDIO_DATA_WRITE1 : MDIO_DATA_WRITE0;
3212 window_write16(vp, dataval, 4, Wn4_PhysicalMgmt);
3213 mdio_delay(vp);
3214 window_write16(vp, dataval | MDIO_SHIFT_CLK,
3215 4, Wn4_PhysicalMgmt);
3216 mdio_delay(vp);
3217 }
3218
3219 for (i = 1; i >= 0; i--) {
3220 window_write16(vp, MDIO_ENB_IN, 4, Wn4_PhysicalMgmt);
3221 mdio_delay(vp);
3222 window_write16(vp, MDIO_ENB_IN | MDIO_SHIFT_CLK,
3223 4, Wn4_PhysicalMgmt);
3224 mdio_delay(vp);
3225 }
3226
3227 spin_unlock_bh(&vp->mii_lock);
3228}
3229
3230
3231
3232static void acpi_set_WOL(struct net_device *dev)
3233{
3234 struct vortex_private *vp = netdev_priv(dev);
3235 void __iomem *ioaddr = vp->ioaddr;
3236
3237 device_set_wakeup_enable(vp->gendev, vp->enable_wol);
3238
3239 if (vp->enable_wol) {
3240
3241 window_write16(vp, 2, 7, 0x0c);
3242
3243 iowrite16(SetRxFilter|RxStation|RxMulticast|RxBroadcast, ioaddr + EL3_CMD);
3244 iowrite16(RxEnable, ioaddr + EL3_CMD);
3245
3246 if (pci_enable_wake(VORTEX_PCI(vp), PCI_D3hot, 1)) {
3247 pr_info("%s: WOL not supported.\n", pci_name(VORTEX_PCI(vp)));
3248
3249 vp->enable_wol = 0;
3250 return;
3251 }
3252
3253 if (VORTEX_PCI(vp)->current_state < PCI_D3hot)
3254 return;
3255
3256
3257 pci_set_power_state(VORTEX_PCI(vp), PCI_D3hot);
3258 }
3259}
3260
3261
3262static void vortex_remove_one(struct pci_dev *pdev)
3263{
3264 struct net_device *dev = pci_get_drvdata(pdev);
3265 struct vortex_private *vp;
3266
3267 if (!dev) {
3268 pr_err("vortex_remove_one called for Compaq device!\n");
3269 BUG();
3270 }
3271
3272 vp = netdev_priv(dev);
3273
3274 if (vp->cb_fn_base)
3275 pci_iounmap(pdev, vp->cb_fn_base);
3276
3277 unregister_netdev(dev);
3278
3279 pci_set_power_state(pdev, PCI_D0);
3280 if (vp->pm_state_valid)
3281 pci_restore_state(pdev);
3282 pci_disable_device(pdev);
3283
3284
3285 iowrite16(TotalReset | ((vp->drv_flags & EEPROM_RESET) ? 0x04 : 0x14),
3286 vp->ioaddr + EL3_CMD);
3287
3288 pci_iounmap(pdev, vp->ioaddr);
3289
3290 dma_free_coherent(&pdev->dev,
3291 sizeof(struct boom_rx_desc) * RX_RING_SIZE +
3292 sizeof(struct boom_tx_desc) * TX_RING_SIZE,
3293 vp->rx_ring, vp->rx_ring_dma);
3294
3295 pci_release_regions(pdev);
3296
3297 free_netdev(dev);
3298}
3299
3300
3301static struct pci_driver vortex_driver = {
3302 .name = "3c59x",
3303 .probe = vortex_init_one,
3304 .remove = vortex_remove_one,
3305 .id_table = vortex_pci_tbl,
3306 .driver.pm = VORTEX_PM_OPS,
3307};
3308
3309
3310static int vortex_have_pci;
3311static int vortex_have_eisa;
3312
3313
3314static int __init vortex_init(void)
3315{
3316 int pci_rc, eisa_rc;
3317
3318 pci_rc = pci_register_driver(&vortex_driver);
3319 eisa_rc = vortex_eisa_init();
3320
3321 if (pci_rc == 0)
3322 vortex_have_pci = 1;
3323 if (eisa_rc > 0)
3324 vortex_have_eisa = 1;
3325
3326 return (vortex_have_pci + vortex_have_eisa) ? 0 : -ENODEV;
3327}
3328
3329
3330static void __exit vortex_eisa_cleanup(void)
3331{
3332 void __iomem *ioaddr;
3333
3334#ifdef CONFIG_EISA
3335
3336 eisa_driver_unregister(&vortex_eisa_driver);
3337#endif
3338
3339 if (compaq_net_device) {
3340 ioaddr = ioport_map(compaq_net_device->base_addr,
3341 VORTEX_TOTAL_SIZE);
3342
3343 unregister_netdev(compaq_net_device);
3344 iowrite16(TotalReset, ioaddr + EL3_CMD);
3345 release_region(compaq_net_device->base_addr,
3346 VORTEX_TOTAL_SIZE);
3347
3348 free_netdev(compaq_net_device);
3349 }
3350}
3351
3352
3353static void __exit vortex_cleanup(void)
3354{
3355 if (vortex_have_pci)
3356 pci_unregister_driver(&vortex_driver);
3357 if (vortex_have_eisa)
3358 vortex_eisa_cleanup();
3359}
3360
3361
3362module_init(vortex_init);
3363module_exit(vortex_cleanup);
3364