1/* Broadcom NetXtreme-C/E network driver. 2 * 3 * Copyright (c) 2014-2016 Broadcom Corporation 4 * Copyright (c) 2016-2018 Broadcom Limited 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation. 9 * 10 * DO NOT MODIFY!!! This file is automatically generated. 11 */ 12 13#ifndef _BNXT_HSI_H_ 14#define _BNXT_HSI_H_ 15 16/* hwrm_cmd_hdr (size:128b/16B) */ 17struct hwrm_cmd_hdr { 18 __le16 req_type; 19 __le16 cmpl_ring; 20 __le16 seq_id; 21 __le16 target_id; 22 __le64 resp_addr; 23}; 24 25/* hwrm_resp_hdr (size:64b/8B) */ 26struct hwrm_resp_hdr { 27 __le16 error_code; 28 __le16 req_type; 29 __le16 seq_id; 30 __le16 resp_len; 31}; 32 33#define CMD_DISCR_TLV_ENCAP 0x8000UL 34#define CMD_DISCR_LAST CMD_DISCR_TLV_ENCAP 35 36 37#define TLV_TYPE_HWRM_REQUEST 0x1UL 38#define TLV_TYPE_HWRM_RESPONSE 0x2UL 39#define TLV_TYPE_ROCE_SP_COMMAND 0x3UL 40#define TLV_TYPE_ENGINE_CKV_DEVICE_SERIAL_NUMBER 0x8001UL 41#define TLV_TYPE_ENGINE_CKV_NONCE 0x8002UL 42#define TLV_TYPE_ENGINE_CKV_IV 0x8003UL 43#define TLV_TYPE_ENGINE_CKV_AUTH_TAG 0x8004UL 44#define TLV_TYPE_ENGINE_CKV_CIPHERTEXT 0x8005UL 45#define TLV_TYPE_ENGINE_CKV_ALGORITHMS 0x8006UL 46#define TLV_TYPE_ENGINE_CKV_ECC_PUBLIC_KEY 0x8007UL 47#define TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 0x8008UL 48#define TLV_TYPE_LAST TLV_TYPE_ENGINE_CKV_ECDSA_SIGNATURE 49 50 51/* tlv (size:64b/8B) */ 52struct tlv { 53 __le16 cmd_discr; 54 u8 reserved_8b; 55 u8 flags; 56 #define TLV_FLAGS_MORE 0x1UL 57 #define TLV_FLAGS_MORE_LAST 0x0UL 58 #define TLV_FLAGS_MORE_NOT_LAST 0x1UL 59 #define TLV_FLAGS_REQUIRED 0x2UL 60 #define TLV_FLAGS_REQUIRED_NO (0x0UL << 1) 61 #define TLV_FLAGS_REQUIRED_YES (0x1UL << 1) 62 #define TLV_FLAGS_REQUIRED_LAST TLV_FLAGS_REQUIRED_YES 63 __le16 tlv_type; 64 __le16 length; 65}; 66 67/* input (size:128b/16B) */ 68struct input { 69 __le16 req_type; 70 __le16 cmpl_ring; 71 __le16 seq_id; 72 __le16 target_id; 73 __le64 resp_addr; 74}; 75 76/* output (size:64b/8B) */ 77struct output { 78 __le16 error_code; 79 __le16 req_type; 80 __le16 seq_id; 81 __le16 resp_len; 82}; 83 84/* hwrm_short_input (size:128b/16B) */ 85struct hwrm_short_input { 86 __le16 req_type; 87 __le16 signature; 88 #define SHORT_REQ_SIGNATURE_SHORT_CMD 0x4321UL 89 #define SHORT_REQ_SIGNATURE_LAST SHORT_REQ_SIGNATURE_SHORT_CMD 90 __le16 unused_0; 91 __le16 size; 92 __le64 req_addr; 93}; 94 95/* cmd_nums (size:64b/8B) */ 96struct cmd_nums { 97 __le16 req_type; 98 #define HWRM_VER_GET 0x0UL 99 #define HWRM_FUNC_BUF_UNRGTR 0xeUL 100 #define HWRM_FUNC_VF_CFG 0xfUL 101 #define HWRM_RESERVED1 0x10UL 102 #define HWRM_FUNC_RESET 0x11UL 103 #define HWRM_FUNC_GETFID 0x12UL 104 #define HWRM_FUNC_VF_ALLOC 0x13UL 105 #define HWRM_FUNC_VF_FREE 0x14UL 106 #define HWRM_FUNC_QCAPS 0x15UL 107 #define HWRM_FUNC_QCFG 0x16UL 108 #define HWRM_FUNC_CFG 0x17UL 109 #define HWRM_FUNC_QSTATS 0x18UL 110 #define HWRM_FUNC_CLR_STATS 0x19UL 111 #define HWRM_FUNC_DRV_UNRGTR 0x1aUL 112 #define HWRM_FUNC_VF_RESC_FREE 0x1bUL 113 #define HWRM_FUNC_VF_VNIC_IDS_QUERY 0x1cUL 114 #define HWRM_FUNC_DRV_RGTR 0x1dUL 115 #define HWRM_FUNC_DRV_QVER 0x1eUL 116 #define HWRM_FUNC_BUF_RGTR 0x1fUL 117 #define HWRM_PORT_PHY_CFG 0x20UL 118 #define HWRM_PORT_MAC_CFG 0x21UL 119 #define HWRM_PORT_TS_QUERY 0x22UL 120 #define HWRM_PORT_QSTATS 0x23UL 121 #define HWRM_PORT_LPBK_QSTATS 0x24UL 122 #define HWRM_PORT_CLR_STATS 0x25UL 123 #define HWRM_PORT_LPBK_CLR_STATS 0x26UL 124 #define HWRM_PORT_PHY_QCFG 0x27UL 125 #define HWRM_PORT_MAC_QCFG 0x28UL 126 #define HWRM_PORT_MAC_PTP_QCFG 0x29UL 127 #define HWRM_PORT_PHY_QCAPS 0x2aUL 128 #define HWRM_PORT_PHY_I2C_WRITE 0x2bUL 129 #define HWRM_PORT_PHY_I2C_READ 0x2cUL 130 #define HWRM_PORT_LED_CFG 0x2dUL 131 #define HWRM_PORT_LED_QCFG 0x2eUL 132 #define HWRM_PORT_LED_QCAPS 0x2fUL 133 #define HWRM_QUEUE_QPORTCFG 0x30UL 134 #define HWRM_QUEUE_QCFG 0x31UL 135 #define HWRM_QUEUE_CFG 0x32UL 136 #define HWRM_FUNC_VLAN_CFG 0x33UL 137 #define HWRM_FUNC_VLAN_QCFG 0x34UL 138 #define HWRM_QUEUE_PFCENABLE_QCFG 0x35UL 139 #define HWRM_QUEUE_PFCENABLE_CFG 0x36UL 140 #define HWRM_QUEUE_PRI2COS_QCFG 0x37UL 141 #define HWRM_QUEUE_PRI2COS_CFG 0x38UL 142 #define HWRM_QUEUE_COS2BW_QCFG 0x39UL 143 #define HWRM_QUEUE_COS2BW_CFG 0x3aUL 144 #define HWRM_QUEUE_DSCP_QCAPS 0x3bUL 145 #define HWRM_QUEUE_DSCP2PRI_QCFG 0x3cUL 146 #define HWRM_QUEUE_DSCP2PRI_CFG 0x3dUL 147 #define HWRM_VNIC_ALLOC 0x40UL 148 #define HWRM_VNIC_FREE 0x41UL 149 #define HWRM_VNIC_CFG 0x42UL 150 #define HWRM_VNIC_QCFG 0x43UL 151 #define HWRM_VNIC_TPA_CFG 0x44UL 152 #define HWRM_VNIC_TPA_QCFG 0x45UL 153 #define HWRM_VNIC_RSS_CFG 0x46UL 154 #define HWRM_VNIC_RSS_QCFG 0x47UL 155 #define HWRM_VNIC_PLCMODES_CFG 0x48UL 156 #define HWRM_VNIC_PLCMODES_QCFG 0x49UL 157 #define HWRM_VNIC_QCAPS 0x4aUL 158 #define HWRM_RING_ALLOC 0x50UL 159 #define HWRM_RING_FREE 0x51UL 160 #define HWRM_RING_CMPL_RING_QAGGINT_PARAMS 0x52UL 161 #define HWRM_RING_CMPL_RING_CFG_AGGINT_PARAMS 0x53UL 162 #define HWRM_RING_RESET 0x5eUL 163 #define HWRM_RING_GRP_ALLOC 0x60UL 164 #define HWRM_RING_GRP_FREE 0x61UL 165 #define HWRM_RESERVED5 0x64UL 166 #define HWRM_RESERVED6 0x65UL 167 #define HWRM_VNIC_RSS_COS_LB_CTX_ALLOC 0x70UL 168 #define HWRM_VNIC_RSS_COS_LB_CTX_FREE 0x71UL 169 #define HWRM_CFA_L2_FILTER_ALLOC 0x90UL 170 #define HWRM_CFA_L2_FILTER_FREE 0x91UL 171 #define HWRM_CFA_L2_FILTER_CFG 0x92UL 172 #define HWRM_CFA_L2_SET_RX_MASK 0x93UL 173 #define HWRM_CFA_VLAN_ANTISPOOF_CFG 0x94UL 174 #define HWRM_CFA_TUNNEL_FILTER_ALLOC 0x95UL 175 #define HWRM_CFA_TUNNEL_FILTER_FREE 0x96UL 176 #define HWRM_CFA_ENCAP_RECORD_ALLOC 0x97UL 177 #define HWRM_CFA_ENCAP_RECORD_FREE 0x98UL 178 #define HWRM_CFA_NTUPLE_FILTER_ALLOC 0x99UL 179 #define HWRM_CFA_NTUPLE_FILTER_FREE 0x9aUL 180 #define HWRM_CFA_NTUPLE_FILTER_CFG 0x9bUL 181 #define HWRM_CFA_EM_FLOW_ALLOC 0x9cUL 182 #define HWRM_CFA_EM_FLOW_FREE 0x9dUL 183 #define HWRM_CFA_EM_FLOW_CFG 0x9eUL 184 #define HWRM_TUNNEL_DST_PORT_QUERY 0xa0UL 185 #define HWRM_TUNNEL_DST_PORT_ALLOC 0xa1UL 186 #define HWRM_TUNNEL_DST_PORT_FREE 0xa2UL 187 #define HWRM_STAT_CTX_ALLOC 0xb0UL 188 #define HWRM_STAT_CTX_FREE 0xb1UL 189 #define HWRM_STAT_CTX_QUERY 0xb2UL 190 #define HWRM_STAT_CTX_CLR_STATS 0xb3UL 191 #define HWRM_PORT_QSTATS_EXT 0xb4UL 192 #define HWRM_FW_RESET 0xc0UL 193 #define HWRM_FW_QSTATUS 0xc1UL 194 #define HWRM_FW_SET_TIME 0xc8UL 195 #define HWRM_FW_GET_TIME 0xc9UL 196 #define HWRM_FW_SET_STRUCTURED_DATA 0xcaUL 197 #define HWRM_FW_GET_STRUCTURED_DATA 0xcbUL 198 #define HWRM_FW_IPC_MAILBOX 0xccUL 199 #define HWRM_EXEC_FWD_RESP 0xd0UL 200 #define HWRM_REJECT_FWD_RESP 0xd1UL 201 #define HWRM_FWD_RESP 0xd2UL 202 #define HWRM_FWD_ASYNC_EVENT_CMPL 0xd3UL 203 #define HWRM_OEM_CMD 0xd4UL 204 #define HWRM_TEMP_MONITOR_QUERY 0xe0UL 205 #define HWRM_WOL_FILTER_ALLOC 0xf0UL 206 #define HWRM_WOL_FILTER_FREE 0xf1UL 207 #define HWRM_WOL_FILTER_QCFG 0xf2UL 208 #define HWRM_WOL_REASON_QCFG 0xf3UL 209 #define HWRM_CFA_METER_PROFILE_ALLOC 0xf5UL 210 #define HWRM_CFA_METER_PROFILE_FREE 0xf6UL 211 #define HWRM_CFA_METER_PROFILE_CFG 0xf7UL 212 #define HWRM_CFA_METER_INSTANCE_ALLOC 0xf8UL 213 #define HWRM_CFA_METER_INSTANCE_FREE 0xf9UL 214 #define HWRM_CFA_VFR_ALLOC 0xfdUL 215 #define HWRM_CFA_VFR_FREE 0xfeUL 216 #define HWRM_CFA_VF_PAIR_ALLOC 0x100UL 217 #define HWRM_CFA_VF_PAIR_FREE 0x101UL 218 #define HWRM_CFA_VF_PAIR_INFO 0x102UL 219 #define HWRM_CFA_FLOW_ALLOC 0x103UL 220 #define HWRM_CFA_FLOW_FREE 0x104UL 221 #define HWRM_CFA_FLOW_FLUSH 0x105UL 222 #define HWRM_CFA_FLOW_STATS 0x106UL 223 #define HWRM_CFA_FLOW_INFO 0x107UL 224 #define HWRM_CFA_DECAP_FILTER_ALLOC 0x108UL 225 #define HWRM_CFA_DECAP_FILTER_FREE 0x109UL 226 #define HWRM_CFA_VLAN_ANTISPOOF_QCFG 0x10aUL 227 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_ALLOC 0x10bUL 228 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_FREE 0x10cUL 229 #define HWRM_CFA_PAIR_ALLOC 0x10dUL 230 #define HWRM_CFA_PAIR_FREE 0x10eUL 231 #define HWRM_CFA_PAIR_INFO 0x10fUL 232 #define HWRM_FW_IPC_MSG 0x110UL 233 #define HWRM_CFA_REDIRECT_TUNNEL_TYPE_INFO 0x111UL 234 #define HWRM_ENGINE_CKV_HELLO 0x12dUL 235 #define HWRM_ENGINE_CKV_STATUS 0x12eUL 236 #define HWRM_ENGINE_CKV_CKEK_ADD 0x12fUL 237 #define HWRM_ENGINE_CKV_CKEK_DELETE 0x130UL 238 #define HWRM_ENGINE_CKV_KEY_ADD 0x131UL 239 #define HWRM_ENGINE_CKV_KEY_DELETE 0x132UL 240 #define HWRM_ENGINE_CKV_FLUSH 0x133UL 241 #define HWRM_ENGINE_CKV_RNG_GET 0x134UL 242 #define HWRM_ENGINE_CKV_KEY_GEN 0x135UL 243 #define HWRM_ENGINE_QG_CONFIG_QUERY 0x13cUL 244 #define HWRM_ENGINE_QG_QUERY 0x13dUL 245 #define HWRM_ENGINE_QG_METER_PROFILE_CONFIG_QUERY 0x13eUL 246 #define HWRM_ENGINE_QG_METER_PROFILE_QUERY 0x13fUL 247 #define HWRM_ENGINE_QG_METER_PROFILE_ALLOC 0x140UL 248 #define HWRM_ENGINE_QG_METER_PROFILE_FREE 0x141UL 249 #define HWRM_ENGINE_QG_METER_QUERY 0x142UL 250 #define HWRM_ENGINE_QG_METER_BIND 0x143UL 251 #define HWRM_ENGINE_QG_METER_UNBIND 0x144UL 252 #define HWRM_ENGINE_QG_FUNC_BIND 0x145UL 253 #define HWRM_ENGINE_SG_CONFIG_QUERY 0x146UL 254 #define HWRM_ENGINE_SG_QUERY 0x147UL 255 #define HWRM_ENGINE_SG_METER_QUERY 0x148UL 256 #define HWRM_ENGINE_SG_METER_CONFIG 0x149UL 257 #define HWRM_ENGINE_SG_QG_BIND 0x14aUL 258 #define HWRM_ENGINE_QG_SG_UNBIND 0x14bUL 259 #define HWRM_ENGINE_CONFIG_QUERY 0x154UL 260 #define HWRM_ENGINE_STATS_CONFIG 0x155UL 261 #define HWRM_ENGINE_STATS_CLEAR 0x156UL 262 #define HWRM_ENGINE_STATS_QUERY 0x157UL 263 #define HWRM_ENGINE_RQ_ALLOC 0x15eUL 264 #define HWRM_ENGINE_RQ_FREE 0x15fUL 265 #define HWRM_ENGINE_CQ_ALLOC 0x160UL 266 #define HWRM_ENGINE_CQ_FREE 0x161UL 267 #define HWRM_ENGINE_NQ_ALLOC 0x162UL 268 #define HWRM_ENGINE_NQ_FREE 0x163UL 269 #define HWRM_ENGINE_ON_DIE_RQE_CREDITS 0x164UL 270 #define HWRM_FUNC_RESOURCE_QCAPS 0x190UL 271 #define HWRM_FUNC_VF_RESOURCE_CFG 0x191UL 272 #define HWRM_SELFTEST_QLIST 0x200UL 273 #define HWRM_SELFTEST_EXEC 0x201UL 274 #define HWRM_SELFTEST_IRQ 0x202UL 275 #define HWRM_SELFTEST_RETRIEVE_SERDES_DATA 0x203UL 276 #define HWRM_PCIE_QSTATS 0x204UL 277 #define HWRM_DBG_READ_DIRECT 0xff10UL 278 #define HWRM_DBG_READ_INDIRECT 0xff11UL 279 #define HWRM_DBG_WRITE_DIRECT 0xff12UL 280 #define HWRM_DBG_WRITE_INDIRECT 0xff13UL 281 #define HWRM_DBG_DUMP 0xff14UL 282 #define HWRM_DBG_ERASE_NVM 0xff15UL 283 #define HWRM_DBG_CFG 0xff16UL 284 #define HWRM_DBG_COREDUMP_LIST 0xff17UL 285 #define HWRM_DBG_COREDUMP_INITIATE 0xff18UL 286 #define HWRM_DBG_COREDUMP_RETRIEVE 0xff19UL 287 #define HWRM_NVM_FACTORY_DEFAULTS 0xffeeUL 288 #define HWRM_NVM_VALIDATE_OPTION 0xffefUL 289 #define HWRM_NVM_FLUSH 0xfff0UL 290 #define HWRM_NVM_GET_VARIABLE 0xfff1UL 291 #define HWRM_NVM_SET_VARIABLE 0xfff2UL 292 #define HWRM_NVM_INSTALL_UPDATE 0xfff3UL 293 #define HWRM_NVM_MODIFY 0xfff4UL 294 #define HWRM_NVM_VERIFY_UPDATE 0xfff5UL 295 #define HWRM_NVM_GET_DEV_INFO 0xfff6UL 296 #define HWRM_NVM_ERASE_DIR_ENTRY 0xfff7UL 297 #define HWRM_NVM_MOD_DIR_ENTRY 0xfff8UL 298 #define HWRM_NVM_FIND_DIR_ENTRY 0xfff9UL 299 #define HWRM_NVM_GET_DIR_ENTRIES 0xfffaUL 300 #define HWRM_NVM_GET_DIR_INFO 0xfffbUL 301 #define HWRM_NVM_RAW_DUMP 0xfffcUL 302 #define HWRM_NVM_READ 0xfffdUL 303 #define HWRM_NVM_WRITE 0xfffeUL 304 #define HWRM_NVM_RAW_WRITE_BLK 0xffffUL 305 #define HWRM_LAST HWRM_NVM_RAW_WRITE_BLK 306 __le16 unused_0[3]; 307}; 308 309/* ret_codes (size:64b/8B) */ 310struct ret_codes { 311 __le16 error_code; 312 #define HWRM_ERR_CODE_SUCCESS 0x0UL 313 #define HWRM_ERR_CODE_FAIL 0x1UL 314 #define HWRM_ERR_CODE_INVALID_PARAMS 0x2UL 315 #define HWRM_ERR_CODE_RESOURCE_ACCESS_DENIED 0x3UL 316 #define HWRM_ERR_CODE_RESOURCE_ALLOC_ERROR 0x4UL 317 #define HWRM_ERR_CODE_INVALID_FLAGS 0x5UL 318 #define HWRM_ERR_CODE_INVALID_ENABLES 0x6UL 319 #define HWRM_ERR_CODE_UNSUPPORTED_TLV 0x7UL 320 #define HWRM_ERR_CODE_NO_BUFFER 0x8UL 321 #define HWRM_ERR_CODE_HWRM_ERROR 0xfUL 322 #define HWRM_ERR_CODE_UNKNOWN_ERR 0xfffeUL 323 #define HWRM_ERR_CODE_CMD_NOT_SUPPORTED 0xffffUL 324 #define HWRM_ERR_CODE_LAST HWRM_ERR_CODE_CMD_NOT_SUPPORTED 325 __le16 unused_0[3]; 326}; 327 328/* hwrm_err_output (size:128b/16B) */ 329struct hwrm_err_output { 330 __le16 error_code; 331 __le16 req_type; 332 __le16 seq_id; 333 __le16 resp_len; 334 __le32 opaque_0; 335 __le16 opaque_1; 336 u8 cmd_err; 337 u8 valid; 338}; 339#define HWRM_NA_SIGNATURE ((__le32)(-1)) 340#define HWRM_MAX_REQ_LEN 128 341#define HWRM_MAX_RESP_LEN 280 342#define HW_HASH_INDEX_SIZE 0x80 343#define HW_HASH_KEY_SIZE 40 344#define HWRM_RESP_VALID_KEY 1 345#define HWRM_VERSION_MAJOR 1 346#define HWRM_VERSION_MINOR 9 347#define HWRM_VERSION_UPDATE 1 348#define HWRM_VERSION_RSVD 15 349#define HWRM_VERSION_STR "1.9.1.15" 350 351/* hwrm_ver_get_input (size:192b/24B) */ 352struct hwrm_ver_get_input { 353 __le16 req_type; 354 __le16 cmpl_ring; 355 __le16 seq_id; 356 __le16 target_id; 357 __le64 resp_addr; 358 u8 hwrm_intf_maj; 359 u8 hwrm_intf_min; 360 u8 hwrm_intf_upd; 361 u8 unused_0[5]; 362}; 363 364/* hwrm_ver_get_output (size:1408b/176B) */ 365struct hwrm_ver_get_output { 366 __le16 error_code; 367 __le16 req_type; 368 __le16 seq_id; 369 __le16 resp_len; 370 u8 hwrm_intf_maj_8b; 371 u8 hwrm_intf_min_8b; 372 u8 hwrm_intf_upd_8b; 373 u8 hwrm_intf_rsvd_8b; 374 u8 hwrm_fw_maj_8b; 375 u8 hwrm_fw_min_8b; 376 u8 hwrm_fw_bld_8b; 377 u8 hwrm_fw_rsvd_8b; 378 u8 mgmt_fw_maj_8b; 379 u8 mgmt_fw_min_8b; 380 u8 mgmt_fw_bld_8b; 381 u8 mgmt_fw_rsvd_8b; 382 u8 netctrl_fw_maj_8b; 383 u8 netctrl_fw_min_8b; 384 u8 netctrl_fw_bld_8b; 385 u8 netctrl_fw_rsvd_8b; 386 __le32 dev_caps_cfg; 387 #define VER_GET_RESP_DEV_CAPS_CFG_SECURE_FW_UPD_SUPPORTED 0x1UL 388 #define VER_GET_RESP_DEV_CAPS_CFG_FW_DCBX_AGENT_SUPPORTED 0x2UL 389 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_SUPPORTED 0x4UL 390 #define VER_GET_RESP_DEV_CAPS_CFG_SHORT_CMD_REQUIRED 0x8UL 391 u8 roce_fw_maj_8b; 392 u8 roce_fw_min_8b; 393 u8 roce_fw_bld_8b; 394 u8 roce_fw_rsvd_8b; 395 char hwrm_fw_name[16]; 396 char mgmt_fw_name[16]; 397 char netctrl_fw_name[16]; 398 u8 reserved2[16]; 399 char roce_fw_name[16]; 400 __le16 chip_num; 401 u8 chip_rev; 402 u8 chip_metal; 403 u8 chip_bond_id; 404 u8 chip_platform_type; 405 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_ASIC 0x0UL 406 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_FPGA 0x1UL 407 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 0x2UL 408 #define VER_GET_RESP_CHIP_PLATFORM_TYPE_LAST VER_GET_RESP_CHIP_PLATFORM_TYPE_PALLADIUM 409 __le16 max_req_win_len; 410 __le16 max_resp_len; 411 __le16 def_req_timeout; 412 u8 flags; 413 #define VER_GET_RESP_FLAGS_DEV_NOT_RDY 0x1UL 414 #define VER_GET_RESP_FLAGS_EXT_VER_AVAIL 0x2UL 415 u8 unused_0[2]; 416 u8 always_1; 417 __le16 hwrm_intf_major; 418 __le16 hwrm_intf_minor; 419 __le16 hwrm_intf_build; 420 __le16 hwrm_intf_patch; 421 __le16 hwrm_fw_major; 422 __le16 hwrm_fw_minor; 423 __le16 hwrm_fw_build; 424 __le16 hwrm_fw_patch; 425 __le16 mgmt_fw_major; 426 __le16 mgmt_fw_minor; 427 __le16 mgmt_fw_build; 428 __le16 mgmt_fw_patch; 429 __le16 netctrl_fw_major; 430 __le16 netctrl_fw_minor; 431 __le16 netctrl_fw_build; 432 __le16 netctrl_fw_patch; 433 __le16 roce_fw_major; 434 __le16 roce_fw_minor; 435 __le16 roce_fw_build; 436 __le16 roce_fw_patch; 437 __le16 max_ext_req_len; 438 u8 unused_1[5]; 439 u8 valid; 440}; 441 442/* eject_cmpl (size:128b/16B) */ 443struct eject_cmpl { 444 __le16 type; 445 #define EJECT_CMPL_TYPE_MASK 0x3fUL 446 #define EJECT_CMPL_TYPE_SFT 0 447 #define EJECT_CMPL_TYPE_STAT_EJECT 0x1aUL 448 #define EJECT_CMPL_TYPE_LAST EJECT_CMPL_TYPE_STAT_EJECT 449 __le16 len; 450 __le32 opaque; 451 __le32 v; 452 #define EJECT_CMPL_V 0x1UL 453 __le32 unused_2; 454}; 455 456/* hwrm_cmpl (size:128b/16B) */ 457struct hwrm_cmpl { 458 __le16 type; 459 #define CMPL_TYPE_MASK 0x3fUL 460 #define CMPL_TYPE_SFT 0 461 #define CMPL_TYPE_HWRM_DONE 0x20UL 462 #define CMPL_TYPE_LAST CMPL_TYPE_HWRM_DONE 463 __le16 sequence_id; 464 __le32 unused_1; 465 __le32 v; 466 #define CMPL_V 0x1UL 467 __le32 unused_3; 468}; 469 470/* hwrm_fwd_req_cmpl (size:128b/16B) */ 471struct hwrm_fwd_req_cmpl { 472 __le16 req_len_type; 473 #define FWD_REQ_CMPL_TYPE_MASK 0x3fUL 474 #define FWD_REQ_CMPL_TYPE_SFT 0 475 #define FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 0x22UL 476 #define FWD_REQ_CMPL_TYPE_LAST FWD_REQ_CMPL_TYPE_HWRM_FWD_REQ 477 #define FWD_REQ_CMPL_REQ_LEN_MASK 0xffc0UL 478 #define FWD_REQ_CMPL_REQ_LEN_SFT 6 479 __le16 source_id; 480 __le32 unused0; 481 __le32 req_buf_addr_v[2]; 482 #define FWD_REQ_CMPL_V 0x1UL 483 #define FWD_REQ_CMPL_REQ_BUF_ADDR_MASK 0xfffffffeUL 484 #define FWD_REQ_CMPL_REQ_BUF_ADDR_SFT 1 485}; 486 487/* hwrm_fwd_resp_cmpl (size:128b/16B) */ 488struct hwrm_fwd_resp_cmpl { 489 __le16 type; 490 #define FWD_RESP_CMPL_TYPE_MASK 0x3fUL 491 #define FWD_RESP_CMPL_TYPE_SFT 0 492 #define FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 0x24UL 493 #define FWD_RESP_CMPL_TYPE_LAST FWD_RESP_CMPL_TYPE_HWRM_FWD_RESP 494 __le16 source_id; 495 __le16 resp_len; 496 __le16 unused_1; 497 __le32 resp_buf_addr_v[2]; 498 #define FWD_RESP_CMPL_V 0x1UL 499 #define FWD_RESP_CMPL_RESP_BUF_ADDR_MASK 0xfffffffeUL 500 #define FWD_RESP_CMPL_RESP_BUF_ADDR_SFT 1 501}; 502 503/* hwrm_async_event_cmpl (size:128b/16B) */ 504struct hwrm_async_event_cmpl { 505 __le16 type; 506 #define ASYNC_EVENT_CMPL_TYPE_MASK 0x3fUL 507 #define ASYNC_EVENT_CMPL_TYPE_SFT 0 508 #define ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 0x2eUL 509 #define ASYNC_EVENT_CMPL_TYPE_LAST ASYNC_EVENT_CMPL_TYPE_HWRM_ASYNC_EVENT 510 __le16 event_id; 511 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 512 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_MTU_CHANGE 0x1UL 513 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CHANGE 0x2UL 514 #define ASYNC_EVENT_CMPL_EVENT_ID_DCB_CONFIG_CHANGE 0x3UL 515 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 516 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_NOT_ALLOWED 0x5UL 517 #define ASYNC_EVENT_CMPL_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 518 #define ASYNC_EVENT_CMPL_EVENT_ID_PORT_PHY_CFG_CHANGE 0x7UL 519 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_UNLOAD 0x10UL 520 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_DRVR_LOAD 0x11UL 521 #define ASYNC_EVENT_CMPL_EVENT_ID_FUNC_FLR_PROC_CMPLT 0x12UL 522 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_UNLOAD 0x20UL 523 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_DRVR_LOAD 0x21UL 524 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_FLR 0x30UL 525 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_MAC_ADDR_CHANGE 0x31UL 526 #define ASYNC_EVENT_CMPL_EVENT_ID_PF_VF_COMM_STATUS_CHANGE 0x32UL 527 #define ASYNC_EVENT_CMPL_EVENT_ID_VF_CFG_CHANGE 0x33UL 528 #define ASYNC_EVENT_CMPL_EVENT_ID_LLFC_PFC_CHANGE 0x34UL 529 #define ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 0xffUL 530 #define ASYNC_EVENT_CMPL_EVENT_ID_LAST ASYNC_EVENT_CMPL_EVENT_ID_HWRM_ERROR 531 __le32 event_data2; 532 u8 opaque_v; 533 #define ASYNC_EVENT_CMPL_V 0x1UL 534 #define ASYNC_EVENT_CMPL_OPAQUE_MASK 0xfeUL 535 #define ASYNC_EVENT_CMPL_OPAQUE_SFT 1 536 u8 timestamp_lo; 537 __le16 timestamp_hi; 538 __le32 event_data1; 539}; 540 541/* hwrm_async_event_cmpl_link_status_change (size:128b/16B) */ 542struct hwrm_async_event_cmpl_link_status_change { 543 __le16 type; 544 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_MASK 0x3fUL 545 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_SFT 0 546 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 547 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_TYPE_HWRM_ASYNC_EVENT 548 __le16 event_id; 549 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 0x0UL 550 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_ID_LINK_STATUS_CHANGE 551 __le32 event_data2; 552 u8 opaque_v; 553 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_V 0x1UL 554 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_MASK 0xfeUL 555 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_OPAQUE_SFT 1 556 u8 timestamp_lo; 557 __le16 timestamp_hi; 558 __le32 event_data1; 559 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE 0x1UL 560 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_DOWN 0x0UL 561 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 0x1UL 562 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_LAST ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_LINK_CHANGE_UP 563 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_MASK 0xeUL 564 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_SFT 1 565 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffff0UL 566 #define ASYNC_EVENT_CMPL_LINK_STATUS_CHANGE_EVENT_DATA1_PORT_ID_SFT 4 567}; 568 569/* hwrm_async_event_cmpl_port_conn_not_allowed (size:128b/16B) */ 570struct hwrm_async_event_cmpl_port_conn_not_allowed { 571 __le16 type; 572 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_MASK 0x3fUL 573 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_SFT 0 574 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 0x2eUL 575 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_TYPE_HWRM_ASYNC_EVENT 576 __le16 event_id; 577 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 0x4UL 578 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_ID_PORT_CONN_NOT_ALLOWED 579 __le32 event_data2; 580 u8 opaque_v; 581 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_V 0x1UL 582 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_MASK 0xfeUL 583 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_OPAQUE_SFT 1 584 u8 timestamp_lo; 585 __le16 timestamp_hi; 586 __le32 event_data1; 587 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_MASK 0xffffUL 588 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_PORT_ID_SFT 0 589 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_MASK 0xff0000UL 590 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_SFT 16 591 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_NONE (0x0UL << 16) 592 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_DISABLETX (0x1UL << 16) 593 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_WARNINGMSG (0x2UL << 16) 594 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN (0x3UL << 16) 595 #define ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_LAST ASYNC_EVENT_CMPL_PORT_CONN_NOT_ALLOWED_EVENT_DATA1_ENFORCEMENT_POLICY_PWRDOWN 596}; 597 598/* hwrm_async_event_cmpl_link_speed_cfg_change (size:128b/16B) */ 599struct hwrm_async_event_cmpl_link_speed_cfg_change { 600 __le16 type; 601 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_MASK 0x3fUL 602 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_SFT 0 603 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 604 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 605 __le16 event_id; 606 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 0x6UL 607 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_ID_LINK_SPEED_CFG_CHANGE 608 __le32 event_data2; 609 u8 opaque_v; 610 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_V 0x1UL 611 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_MASK 0xfeUL 612 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_OPAQUE_SFT 1 613 u8 timestamp_lo; 614 __le16 timestamp_hi; 615 __le32 event_data1; 616 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_MASK 0xffffUL 617 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_PORT_ID_SFT 0 618 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_SUPPORTED_LINK_SPEEDS_CHANGE 0x10000UL 619 #define ASYNC_EVENT_CMPL_LINK_SPEED_CFG_CHANGE_EVENT_DATA1_ILLEGAL_LINK_SPEED_CFG 0x20000UL 620}; 621 622/* hwrm_async_event_cmpl_vf_cfg_change (size:128b/16B) */ 623struct hwrm_async_event_cmpl_vf_cfg_change { 624 __le16 type; 625 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_MASK 0x3fUL 626 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_SFT 0 627 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 0x2eUL 628 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_TYPE_HWRM_ASYNC_EVENT 629 __le16 event_id; 630 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 0x33UL 631 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_LAST ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_ID_VF_CFG_CHANGE 632 __le32 event_data2; 633 u8 opaque_v; 634 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_V 0x1UL 635 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_MASK 0xfeUL 636 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_OPAQUE_SFT 1 637 u8 timestamp_lo; 638 __le16 timestamp_hi; 639 __le32 event_data1; 640 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MTU_CHANGE 0x1UL 641 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_MRU_CHANGE 0x2UL 642 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_MAC_ADDR_CHANGE 0x4UL 643 #define ASYNC_EVENT_CMPL_VF_CFG_CHANGE_EVENT_DATA1_DFLT_VLAN_CHANGE 0x8UL 644}; 645 646/* hwrm_func_reset_input (size:192b/24B) */ 647struct hwrm_func_reset_input { 648 __le16 req_type; 649 __le16 cmpl_ring; 650 __le16 seq_id; 651 __le16 target_id; 652 __le64 resp_addr; 653 __le32 enables; 654 #define FUNC_RESET_REQ_ENABLES_VF_ID_VALID 0x1UL 655 __le16 vf_id; 656 u8 func_reset_level; 657 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETALL 0x0UL 658 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETME 0x1UL 659 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETCHILDREN 0x2UL 660 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 0x3UL 661 #define FUNC_RESET_REQ_FUNC_RESET_LEVEL_LAST FUNC_RESET_REQ_FUNC_RESET_LEVEL_RESETVF 662 u8 unused_0; 663}; 664 665/* hwrm_func_reset_output (size:128b/16B) */ 666struct hwrm_func_reset_output { 667 __le16 error_code; 668 __le16 req_type; 669 __le16 seq_id; 670 __le16 resp_len; 671 u8 unused_0[7]; 672 u8 valid; 673}; 674 675/* hwrm_func_getfid_input (size:192b/24B) */ 676struct hwrm_func_getfid_input { 677 __le16 req_type; 678 __le16 cmpl_ring; 679 __le16 seq_id; 680 __le16 target_id; 681 __le64 resp_addr; 682 __le32 enables; 683 #define FUNC_GETFID_REQ_ENABLES_PCI_ID 0x1UL 684 __le16 pci_id; 685 u8 unused_0[2]; 686}; 687 688/* hwrm_func_getfid_output (size:128b/16B) */ 689struct hwrm_func_getfid_output { 690 __le16 error_code; 691 __le16 req_type; 692 __le16 seq_id; 693 __le16 resp_len; 694 __le16 fid; 695 u8 unused_0[5]; 696 u8 valid; 697}; 698 699/* hwrm_func_vf_alloc_input (size:192b/24B) */ 700struct hwrm_func_vf_alloc_input { 701 __le16 req_type; 702 __le16 cmpl_ring; 703 __le16 seq_id; 704 __le16 target_id; 705 __le64 resp_addr; 706 __le32 enables; 707 #define FUNC_VF_ALLOC_REQ_ENABLES_FIRST_VF_ID 0x1UL 708 __le16 first_vf_id; 709 __le16 num_vfs; 710}; 711 712/* hwrm_func_vf_alloc_output (size:128b/16B) */ 713struct hwrm_func_vf_alloc_output { 714 __le16 error_code; 715 __le16 req_type; 716 __le16 seq_id; 717 __le16 resp_len; 718 __le16 first_vf_id; 719 u8 unused_0[5]; 720 u8 valid; 721}; 722 723/* hwrm_func_vf_free_input (size:192b/24B) */ 724struct hwrm_func_vf_free_input { 725 __le16 req_type; 726 __le16 cmpl_ring; 727 __le16 seq_id; 728 __le16 target_id; 729 __le64 resp_addr; 730 __le32 enables; 731 #define FUNC_VF_FREE_REQ_ENABLES_FIRST_VF_ID 0x1UL 732 __le16 first_vf_id; 733 __le16 num_vfs; 734}; 735 736/* hwrm_func_vf_free_output (size:128b/16B) */ 737struct hwrm_func_vf_free_output { 738 __le16 error_code; 739 __le16 req_type; 740 __le16 seq_id; 741 __le16 resp_len; 742 u8 unused_0[7]; 743 u8 valid; 744}; 745 746/* hwrm_func_vf_cfg_input (size:448b/56B) */ 747struct hwrm_func_vf_cfg_input { 748 __le16 req_type; 749 __le16 cmpl_ring; 750 __le16 seq_id; 751 __le16 target_id; 752 __le64 resp_addr; 753 __le32 enables; 754 #define FUNC_VF_CFG_REQ_ENABLES_MTU 0x1UL 755 #define FUNC_VF_CFG_REQ_ENABLES_GUEST_VLAN 0x2UL 756 #define FUNC_VF_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4UL 757 #define FUNC_VF_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x8UL 758 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x10UL 759 #define FUNC_VF_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x20UL 760 #define FUNC_VF_CFG_REQ_ENABLES_NUM_TX_RINGS 0x40UL 761 #define FUNC_VF_CFG_REQ_ENABLES_NUM_RX_RINGS 0x80UL 762 #define FUNC_VF_CFG_REQ_ENABLES_NUM_L2_CTXS 0x100UL 763 #define FUNC_VF_CFG_REQ_ENABLES_NUM_VNICS 0x200UL 764 #define FUNC_VF_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x400UL 765 #define FUNC_VF_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x800UL 766 __le16 mtu; 767 __le16 guest_vlan; 768 __le16 async_event_cr; 769 u8 dflt_mac_addr[6]; 770 __le32 flags; 771 #define FUNC_VF_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x1UL 772 #define FUNC_VF_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x2UL 773 #define FUNC_VF_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x4UL 774 #define FUNC_VF_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x8UL 775 #define FUNC_VF_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x10UL 776 #define FUNC_VF_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x20UL 777 #define FUNC_VF_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x40UL 778 #define FUNC_VF_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x80UL 779 __le16 num_rsscos_ctxs; 780 __le16 num_cmpl_rings; 781 __le16 num_tx_rings; 782 __le16 num_rx_rings; 783 __le16 num_l2_ctxs; 784 __le16 num_vnics; 785 __le16 num_stat_ctxs; 786 __le16 num_hw_ring_grps; 787 u8 unused_0[4]; 788}; 789 790/* hwrm_func_vf_cfg_output (size:128b/16B) */ 791struct hwrm_func_vf_cfg_output { 792 __le16 error_code; 793 __le16 req_type; 794 __le16 seq_id; 795 __le16 resp_len; 796 u8 unused_0[7]; 797 u8 valid; 798}; 799 800/* hwrm_func_qcaps_input (size:192b/24B) */ 801struct hwrm_func_qcaps_input { 802 __le16 req_type; 803 __le16 cmpl_ring; 804 __le16 seq_id; 805 __le16 target_id; 806 __le64 resp_addr; 807 __le16 fid; 808 u8 unused_0[6]; 809}; 810 811/* hwrm_func_qcaps_output (size:640b/80B) */ 812struct hwrm_func_qcaps_output { 813 __le16 error_code; 814 __le16 req_type; 815 __le16 seq_id; 816 __le16 resp_len; 817 __le16 fid; 818 __le16 port_id; 819 __le32 flags; 820 #define FUNC_QCAPS_RESP_FLAGS_PUSH_MODE_SUPPORTED 0x1UL 821 #define FUNC_QCAPS_RESP_FLAGS_GLOBAL_MSIX_AUTOMASKING 0x2UL 822 #define FUNC_QCAPS_RESP_FLAGS_PTP_SUPPORTED 0x4UL 823 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V1_SUPPORTED 0x8UL 824 #define FUNC_QCAPS_RESP_FLAGS_ROCE_V2_SUPPORTED 0x10UL 825 #define FUNC_QCAPS_RESP_FLAGS_WOL_MAGICPKT_SUPPORTED 0x20UL 826 #define FUNC_QCAPS_RESP_FLAGS_WOL_BMP_SUPPORTED 0x40UL 827 #define FUNC_QCAPS_RESP_FLAGS_TX_RING_RL_SUPPORTED 0x80UL 828 #define FUNC_QCAPS_RESP_FLAGS_TX_BW_CFG_SUPPORTED 0x100UL 829 #define FUNC_QCAPS_RESP_FLAGS_VF_TX_RING_RL_SUPPORTED 0x200UL 830 #define FUNC_QCAPS_RESP_FLAGS_VF_BW_CFG_SUPPORTED 0x400UL 831 #define FUNC_QCAPS_RESP_FLAGS_STD_TX_RING_MODE_SUPPORTED 0x800UL 832 #define FUNC_QCAPS_RESP_FLAGS_GENEVE_TUN_FLAGS_SUPPORTED 0x1000UL 833 #define FUNC_QCAPS_RESP_FLAGS_NVGRE_TUN_FLAGS_SUPPORTED 0x2000UL 834 #define FUNC_QCAPS_RESP_FLAGS_GRE_TUN_FLAGS_SUPPORTED 0x4000UL 835 #define FUNC_QCAPS_RESP_FLAGS_MPLS_TUN_FLAGS_SUPPORTED 0x8000UL 836 #define FUNC_QCAPS_RESP_FLAGS_PCIE_STATS_SUPPORTED 0x10000UL 837 u8 mac_address[6]; 838 __le16 max_rsscos_ctx; 839 __le16 max_cmpl_rings; 840 __le16 max_tx_rings; 841 __le16 max_rx_rings; 842 __le16 max_l2_ctxs; 843 __le16 max_vnics; 844 __le16 first_vf_id; 845 __le16 max_vfs; 846 __le16 max_stat_ctx; 847 __le32 max_encap_records; 848 __le32 max_decap_records; 849 __le32 max_tx_em_flows; 850 __le32 max_tx_wm_flows; 851 __le32 max_rx_em_flows; 852 __le32 max_rx_wm_flows; 853 __le32 max_mcast_filters; 854 __le32 max_flow_id; 855 __le32 max_hw_ring_grps; 856 __le16 max_sp_tx_rings; 857 u8 unused_0; 858 u8 valid; 859}; 860 861/* hwrm_func_qcfg_input (size:192b/24B) */ 862struct hwrm_func_qcfg_input { 863 __le16 req_type; 864 __le16 cmpl_ring; 865 __le16 seq_id; 866 __le16 target_id; 867 __le64 resp_addr; 868 __le16 fid; 869 u8 unused_0[6]; 870}; 871 872/* hwrm_func_qcfg_output (size:640b/80B) */ 873struct hwrm_func_qcfg_output { 874 __le16 error_code; 875 __le16 req_type; 876 __le16 seq_id; 877 __le16 resp_len; 878 __le16 fid; 879 __le16 port_id; 880 __le16 vlan; 881 __le16 flags; 882 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_MAGICPKT_ENABLED 0x1UL 883 #define FUNC_QCFG_RESP_FLAGS_OOB_WOL_BMP_ENABLED 0x2UL 884 #define FUNC_QCFG_RESP_FLAGS_FW_DCBX_AGENT_ENABLED 0x4UL 885 #define FUNC_QCFG_RESP_FLAGS_STD_TX_RING_MODE_ENABLED 0x8UL 886 #define FUNC_QCFG_RESP_FLAGS_FW_LLDP_AGENT_ENABLED 0x10UL 887 #define FUNC_QCFG_RESP_FLAGS_MULTI_HOST 0x20UL 888 u8 mac_address[6]; 889 __le16 pci_id; 890 __le16 alloc_rsscos_ctx; 891 __le16 alloc_cmpl_rings; 892 __le16 alloc_tx_rings; 893 __le16 alloc_rx_rings; 894 __le16 alloc_l2_ctx; 895 __le16 alloc_vnics; 896 __le16 mtu; 897 __le16 mru; 898 __le16 stat_ctx_id; 899 u8 port_partition_type; 900 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_SPF 0x0UL 901 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_MPFS 0x1UL 902 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_0 0x2UL 903 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR1_5 0x3UL 904 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_NPAR2_0 0x4UL 905 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 0xffUL 906 #define FUNC_QCFG_RESP_PORT_PARTITION_TYPE_LAST FUNC_QCFG_RESP_PORT_PARTITION_TYPE_UNKNOWN 907 u8 port_pf_cnt; 908 #define FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 0x0UL 909 #define FUNC_QCFG_RESP_PORT_PF_CNT_LAST FUNC_QCFG_RESP_PORT_PF_CNT_UNAVAIL 910 __le16 dflt_vnic_id; 911 __le16 max_mtu_configured; 912 __le32 min_bw; 913 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_MASK 0xfffffffUL 914 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_SFT 0 915 #define FUNC_QCFG_RESP_MIN_BW_SCALE 0x10000000UL 916 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BITS (0x0UL << 28) 917 #define FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES (0x1UL << 28) 918 #define FUNC_QCFG_RESP_MIN_BW_SCALE_LAST FUNC_QCFG_RESP_MIN_BW_SCALE_BYTES 919 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 920 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_SFT 29 921 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 922 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 923 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 924 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 925 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 926 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 927 #define FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MIN_BW_BW_VALUE_UNIT_INVALID 928 __le32 max_bw; 929 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_MASK 0xfffffffUL 930 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_SFT 0 931 #define FUNC_QCFG_RESP_MAX_BW_SCALE 0x10000000UL 932 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BITS (0x0UL << 28) 933 #define FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES (0x1UL << 28) 934 #define FUNC_QCFG_RESP_MAX_BW_SCALE_LAST FUNC_QCFG_RESP_MAX_BW_SCALE_BYTES 935 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 936 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_SFT 29 937 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 938 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 939 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 940 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 941 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 942 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 943 #define FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_LAST FUNC_QCFG_RESP_MAX_BW_BW_VALUE_UNIT_INVALID 944 u8 evb_mode; 945 #define FUNC_QCFG_RESP_EVB_MODE_NO_EVB 0x0UL 946 #define FUNC_QCFG_RESP_EVB_MODE_VEB 0x1UL 947 #define FUNC_QCFG_RESP_EVB_MODE_VEPA 0x2UL 948 #define FUNC_QCFG_RESP_EVB_MODE_LAST FUNC_QCFG_RESP_EVB_MODE_VEPA 949 u8 options; 950 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 951 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SFT 0 952 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 953 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 954 #define FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_LAST FUNC_QCFG_RESP_OPTIONS_CACHE_LINESIZE_SIZE_128 955 #define FUNC_QCFG_RESP_OPTIONS_RSVD_MASK 0xfcUL 956 #define FUNC_QCFG_RESP_OPTIONS_RSVD_SFT 2 957 __le16 alloc_vfs; 958 __le32 alloc_mcast_filters; 959 __le32 alloc_hw_ring_grps; 960 __le16 alloc_sp_tx_rings; 961 __le16 alloc_stat_ctx; 962 u8 unused_2[7]; 963 u8 valid; 964}; 965 966/* hwrm_func_vlan_cfg_input (size:384b/48B) */ 967struct hwrm_func_vlan_cfg_input { 968 __le16 req_type; 969 __le16 cmpl_ring; 970 __le16 seq_id; 971 __le16 target_id; 972 __le64 resp_addr; 973 __le16 fid; 974 u8 unused_0[2]; 975 __le32 enables; 976 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_VID 0x1UL 977 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_VID 0x2UL 978 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_PCP 0x4UL 979 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_PCP 0x8UL 980 #define FUNC_VLAN_CFG_REQ_ENABLES_STAG_TPID 0x10UL 981 #define FUNC_VLAN_CFG_REQ_ENABLES_CTAG_TPID 0x20UL 982 __le16 stag_vid; 983 u8 stag_pcp; 984 u8 unused_1; 985 __be16 stag_tpid; 986 __le16 ctag_vid; 987 u8 ctag_pcp; 988 u8 unused_2; 989 __be16 ctag_tpid; 990 __le32 rsvd1; 991 __le32 rsvd2; 992 u8 unused_3[4]; 993}; 994 995/* hwrm_func_vlan_cfg_output (size:128b/16B) */ 996struct hwrm_func_vlan_cfg_output { 997 __le16 error_code; 998 __le16 req_type; 999 __le16 seq_id; 1000 __le16 resp_len;
1001 u8 unused_0[7]; 1002 u8 valid; 1003}; 1004 1005/* hwrm_func_cfg_input (size:704b/88B) */ 1006struct hwrm_func_cfg_input { 1007 __le16 req_type; 1008 __le16 cmpl_ring; 1009 __le16 seq_id; 1010 __le16 target_id; 1011 __le64 resp_addr; 1012 __le16 fid; 1013 u8 unused_0[2]; 1014 __le32 flags; 1015 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_DISABLE 0x1UL 1016 #define FUNC_CFG_REQ_FLAGS_SRC_MAC_ADDR_CHECK_ENABLE 0x2UL 1017 #define FUNC_CFG_REQ_FLAGS_RSVD_MASK 0x1fcUL 1018 #define FUNC_CFG_REQ_FLAGS_RSVD_SFT 2 1019 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_ENABLE 0x200UL 1020 #define FUNC_CFG_REQ_FLAGS_STD_TX_RING_MODE_DISABLE 0x400UL 1021 #define FUNC_CFG_REQ_FLAGS_VIRT_MAC_PERSIST 0x800UL 1022 #define FUNC_CFG_REQ_FLAGS_NO_AUTOCLEAR_STATISTIC 0x1000UL 1023 #define FUNC_CFG_REQ_FLAGS_TX_ASSETS_TEST 0x2000UL 1024 #define FUNC_CFG_REQ_FLAGS_RX_ASSETS_TEST 0x4000UL 1025 #define FUNC_CFG_REQ_FLAGS_CMPL_ASSETS_TEST 0x8000UL 1026 #define FUNC_CFG_REQ_FLAGS_RSSCOS_CTX_ASSETS_TEST 0x10000UL 1027 #define FUNC_CFG_REQ_FLAGS_RING_GRP_ASSETS_TEST 0x20000UL 1028 #define FUNC_CFG_REQ_FLAGS_STAT_CTX_ASSETS_TEST 0x40000UL 1029 #define FUNC_CFG_REQ_FLAGS_VNIC_ASSETS_TEST 0x80000UL 1030 #define FUNC_CFG_REQ_FLAGS_L2_CTX_ASSETS_TEST 0x100000UL 1031 __le32 enables; 1032 #define FUNC_CFG_REQ_ENABLES_MTU 0x1UL 1033 #define FUNC_CFG_REQ_ENABLES_MRU 0x2UL 1034 #define FUNC_CFG_REQ_ENABLES_NUM_RSSCOS_CTXS 0x4UL 1035 #define FUNC_CFG_REQ_ENABLES_NUM_CMPL_RINGS 0x8UL 1036 #define FUNC_CFG_REQ_ENABLES_NUM_TX_RINGS 0x10UL 1037 #define FUNC_CFG_REQ_ENABLES_NUM_RX_RINGS 0x20UL 1038 #define FUNC_CFG_REQ_ENABLES_NUM_L2_CTXS 0x40UL 1039 #define FUNC_CFG_REQ_ENABLES_NUM_VNICS 0x80UL 1040 #define FUNC_CFG_REQ_ENABLES_NUM_STAT_CTXS 0x100UL 1041 #define FUNC_CFG_REQ_ENABLES_DFLT_MAC_ADDR 0x200UL 1042 #define FUNC_CFG_REQ_ENABLES_DFLT_VLAN 0x400UL 1043 #define FUNC_CFG_REQ_ENABLES_DFLT_IP_ADDR 0x800UL 1044 #define FUNC_CFG_REQ_ENABLES_MIN_BW 0x1000UL 1045 #define FUNC_CFG_REQ_ENABLES_MAX_BW 0x2000UL 1046 #define FUNC_CFG_REQ_ENABLES_ASYNC_EVENT_CR 0x4000UL 1047 #define FUNC_CFG_REQ_ENABLES_VLAN_ANTISPOOF_MODE 0x8000UL 1048 #define FUNC_CFG_REQ_ENABLES_ALLOWED_VLAN_PRIS 0x10000UL 1049 #define FUNC_CFG_REQ_ENABLES_EVB_MODE 0x20000UL 1050 #define FUNC_CFG_REQ_ENABLES_NUM_MCAST_FILTERS 0x40000UL 1051 #define FUNC_CFG_REQ_ENABLES_NUM_HW_RING_GRPS 0x80000UL 1052 #define FUNC_CFG_REQ_ENABLES_CACHE_LINESIZE 0x100000UL 1053 __le16 mtu; 1054 __le16 mru; 1055 __le16 num_rsscos_ctxs; 1056 __le16 num_cmpl_rings; 1057 __le16 num_tx_rings; 1058 __le16 num_rx_rings; 1059 __le16 num_l2_ctxs; 1060 __le16 num_vnics; 1061 __le16 num_stat_ctxs; 1062 __le16 num_hw_ring_grps; 1063 u8 dflt_mac_addr[6]; 1064 __le16 dflt_vlan; 1065 __be32 dflt_ip_addr[4]; 1066 __le32 min_bw; 1067 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_MASK 0xfffffffUL 1068 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_SFT 0 1069 #define FUNC_CFG_REQ_MIN_BW_SCALE 0x10000000UL 1070 #define FUNC_CFG_REQ_MIN_BW_SCALE_BITS (0x0UL << 28) 1071 #define FUNC_CFG_REQ_MIN_BW_SCALE_BYTES (0x1UL << 28) 1072 #define FUNC_CFG_REQ_MIN_BW_SCALE_LAST FUNC_CFG_REQ_MIN_BW_SCALE_BYTES 1073 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1074 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_SFT 29 1075 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1076 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1077 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1078 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1079 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1080 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1081 #define FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MIN_BW_BW_VALUE_UNIT_INVALID 1082 __le32 max_bw; 1083 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 1084 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_SFT 0 1085 #define FUNC_CFG_REQ_MAX_BW_SCALE 0x10000000UL 1086 #define FUNC_CFG_REQ_MAX_BW_SCALE_BITS (0x0UL << 28) 1087 #define FUNC_CFG_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 1088 #define FUNC_CFG_REQ_MAX_BW_SCALE_LAST FUNC_CFG_REQ_MAX_BW_SCALE_BYTES 1089 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 1090 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 1091 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 1092 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 1093 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 1094 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 1095 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 1096 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 1097 #define FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_LAST FUNC_CFG_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 1098 __le16 async_event_cr; 1099 u8 vlan_antispoof_mode; 1100 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_NOCHECK 0x0UL 1101 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_VALIDATE_VLAN 0x1UL 1102 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_IF_VLANDNE 0x2UL 1103 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 0x3UL 1104 #define FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_LAST FUNC_CFG_REQ_VLAN_ANTISPOOF_MODE_INSERT_OR_OVERRIDE_VLAN 1105 u8 allowed_vlan_pris; 1106 u8 evb_mode; 1107 #define FUNC_CFG_REQ_EVB_MODE_NO_EVB 0x0UL 1108 #define FUNC_CFG_REQ_EVB_MODE_VEB 0x1UL 1109 #define FUNC_CFG_REQ_EVB_MODE_VEPA 0x2UL 1110 #define FUNC_CFG_REQ_EVB_MODE_LAST FUNC_CFG_REQ_EVB_MODE_VEPA 1111 u8 options; 1112 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_MASK 0x3UL 1113 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SFT 0 1114 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_64 0x0UL 1115 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 0x1UL 1116 #define FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_LAST FUNC_CFG_REQ_OPTIONS_CACHE_LINESIZE_SIZE_128 1117 #define FUNC_CFG_REQ_OPTIONS_RSVD_MASK 0xfcUL 1118 #define FUNC_CFG_REQ_OPTIONS_RSVD_SFT 2 1119 __le16 num_mcast_filters; 1120}; 1121 1122/* hwrm_func_cfg_output (size:128b/16B) */ 1123struct hwrm_func_cfg_output { 1124 __le16 error_code; 1125 __le16 req_type; 1126 __le16 seq_id; 1127 __le16 resp_len; 1128 u8 unused_0[7]; 1129 u8 valid; 1130}; 1131 1132/* hwrm_func_qstats_input (size:192b/24B) */ 1133struct hwrm_func_qstats_input { 1134 __le16 req_type; 1135 __le16 cmpl_ring; 1136 __le16 seq_id; 1137 __le16 target_id; 1138 __le64 resp_addr; 1139 __le16 fid; 1140 u8 unused_0[6]; 1141}; 1142 1143/* hwrm_func_qstats_output (size:1408b/176B) */ 1144struct hwrm_func_qstats_output { 1145 __le16 error_code; 1146 __le16 req_type; 1147 __le16 seq_id; 1148 __le16 resp_len; 1149 __le64 tx_ucast_pkts; 1150 __le64 tx_mcast_pkts; 1151 __le64 tx_bcast_pkts; 1152 __le64 tx_discard_pkts; 1153 __le64 tx_drop_pkts; 1154 __le64 tx_ucast_bytes; 1155 __le64 tx_mcast_bytes; 1156 __le64 tx_bcast_bytes; 1157 __le64 rx_ucast_pkts; 1158 __le64 rx_mcast_pkts; 1159 __le64 rx_bcast_pkts; 1160 __le64 rx_discard_pkts; 1161 __le64 rx_drop_pkts; 1162 __le64 rx_ucast_bytes; 1163 __le64 rx_mcast_bytes; 1164 __le64 rx_bcast_bytes; 1165 __le64 rx_agg_pkts; 1166 __le64 rx_agg_bytes; 1167 __le64 rx_agg_events; 1168 __le64 rx_agg_aborts; 1169 u8 unused_0[7]; 1170 u8 valid; 1171}; 1172 1173/* hwrm_func_clr_stats_input (size:192b/24B) */ 1174struct hwrm_func_clr_stats_input { 1175 __le16 req_type; 1176 __le16 cmpl_ring; 1177 __le16 seq_id; 1178 __le16 target_id; 1179 __le64 resp_addr; 1180 __le16 fid; 1181 u8 unused_0[6]; 1182}; 1183 1184/* hwrm_func_clr_stats_output (size:128b/16B) */ 1185struct hwrm_func_clr_stats_output { 1186 __le16 error_code; 1187 __le16 req_type; 1188 __le16 seq_id; 1189 __le16 resp_len; 1190 u8 unused_0[7]; 1191 u8 valid; 1192}; 1193 1194/* hwrm_func_vf_resc_free_input (size:192b/24B) */ 1195struct hwrm_func_vf_resc_free_input { 1196 __le16 req_type; 1197 __le16 cmpl_ring; 1198 __le16 seq_id; 1199 __le16 target_id; 1200 __le64 resp_addr; 1201 __le16 vf_id; 1202 u8 unused_0[6]; 1203}; 1204 1205/* hwrm_func_vf_resc_free_output (size:128b/16B) */ 1206struct hwrm_func_vf_resc_free_output { 1207 __le16 error_code; 1208 __le16 req_type; 1209 __le16 seq_id; 1210 __le16 resp_len; 1211 u8 unused_0[7]; 1212 u8 valid; 1213}; 1214 1215/* hwrm_func_vf_vnic_ids_query_input (size:256b/32B) */ 1216struct hwrm_func_vf_vnic_ids_query_input { 1217 __le16 req_type; 1218 __le16 cmpl_ring; 1219 __le16 seq_id; 1220 __le16 target_id; 1221 __le64 resp_addr; 1222 __le16 vf_id; 1223 u8 unused_0[2]; 1224 __le32 max_vnic_id_cnt; 1225 __le64 vnic_id_tbl_addr; 1226}; 1227 1228/* hwrm_func_vf_vnic_ids_query_output (size:128b/16B) */ 1229struct hwrm_func_vf_vnic_ids_query_output { 1230 __le16 error_code; 1231 __le16 req_type; 1232 __le16 seq_id; 1233 __le16 resp_len; 1234 __le32 vnic_id_cnt; 1235 u8 unused_0[3]; 1236 u8 valid; 1237}; 1238 1239/* hwrm_func_drv_rgtr_input (size:896b/112B) */ 1240struct hwrm_func_drv_rgtr_input { 1241 __le16 req_type; 1242 __le16 cmpl_ring; 1243 __le16 seq_id; 1244 __le16 target_id; 1245 __le64 resp_addr; 1246 __le32 flags; 1247 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_ALL_MODE 0x1UL 1248 #define FUNC_DRV_RGTR_REQ_FLAGS_FWD_NONE_MODE 0x2UL 1249 #define FUNC_DRV_RGTR_REQ_FLAGS_16BIT_VER_MODE 0x4UL 1250 __le32 enables; 1251 #define FUNC_DRV_RGTR_REQ_ENABLES_OS_TYPE 0x1UL 1252 #define FUNC_DRV_RGTR_REQ_ENABLES_VER 0x2UL 1253 #define FUNC_DRV_RGTR_REQ_ENABLES_TIMESTAMP 0x4UL 1254 #define FUNC_DRV_RGTR_REQ_ENABLES_VF_REQ_FWD 0x8UL 1255 #define FUNC_DRV_RGTR_REQ_ENABLES_ASYNC_EVENT_FWD 0x10UL 1256 __le16 os_type; 1257 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UNKNOWN 0x0UL 1258 #define FUNC_DRV_RGTR_REQ_OS_TYPE_OTHER 0x1UL 1259 #define FUNC_DRV_RGTR_REQ_OS_TYPE_MSDOS 0xeUL 1260 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WINDOWS 0x12UL 1261 #define FUNC_DRV_RGTR_REQ_OS_TYPE_SOLARIS 0x1dUL 1262 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LINUX 0x24UL 1263 #define FUNC_DRV_RGTR_REQ_OS_TYPE_FREEBSD 0x2aUL 1264 #define FUNC_DRV_RGTR_REQ_OS_TYPE_ESXI 0x68UL 1265 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN864 0x73UL 1266 #define FUNC_DRV_RGTR_REQ_OS_TYPE_WIN2012R2 0x74UL 1267 #define FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 0x8000UL 1268 #define FUNC_DRV_RGTR_REQ_OS_TYPE_LAST FUNC_DRV_RGTR_REQ_OS_TYPE_UEFI 1269 u8 ver_maj_8b; 1270 u8 ver_min_8b; 1271 u8 ver_upd_8b; 1272 u8 unused_0[3]; 1273 __le32 timestamp; 1274 u8 unused_1[4]; 1275 __le32 vf_req_fwd[8]; 1276 __le32 async_event_fwd[8]; 1277 __le16 ver_maj; 1278 __le16 ver_min; 1279 __le16 ver_upd; 1280 __le16 ver_patch; 1281}; 1282 1283/* hwrm_func_drv_rgtr_output (size:128b/16B) */ 1284struct hwrm_func_drv_rgtr_output { 1285 __le16 error_code; 1286 __le16 req_type; 1287 __le16 seq_id; 1288 __le16 resp_len; 1289 u8 unused_0[7]; 1290 u8 valid; 1291}; 1292 1293/* hwrm_func_drv_unrgtr_input (size:192b/24B) */ 1294struct hwrm_func_drv_unrgtr_input { 1295 __le16 req_type; 1296 __le16 cmpl_ring; 1297 __le16 seq_id; 1298 __le16 target_id; 1299 __le64 resp_addr; 1300 __le32 flags; 1301 #define FUNC_DRV_UNRGTR_REQ_FLAGS_PREPARE_FOR_SHUTDOWN 0x1UL 1302 u8 unused_0[4]; 1303}; 1304 1305/* hwrm_func_drv_unrgtr_output (size:128b/16B) */ 1306struct hwrm_func_drv_unrgtr_output { 1307 __le16 error_code; 1308 __le16 req_type; 1309 __le16 seq_id; 1310 __le16 resp_len; 1311 u8 unused_0[7]; 1312 u8 valid; 1313}; 1314 1315/* hwrm_func_buf_rgtr_input (size:1024b/128B) */ 1316struct hwrm_func_buf_rgtr_input { 1317 __le16 req_type; 1318 __le16 cmpl_ring; 1319 __le16 seq_id; 1320 __le16 target_id; 1321 __le64 resp_addr; 1322 __le32 enables; 1323 #define FUNC_BUF_RGTR_REQ_ENABLES_VF_ID 0x1UL 1324 #define FUNC_BUF_RGTR_REQ_ENABLES_ERR_BUF_ADDR 0x2UL 1325 __le16 vf_id; 1326 __le16 req_buf_num_pages; 1327 __le16 req_buf_page_size; 1328 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_16B 0x4UL 1329 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4K 0xcUL 1330 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_8K 0xdUL 1331 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_64K 0x10UL 1332 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_2M 0x15UL 1333 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_4M 0x16UL 1334 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 0x1eUL 1335 #define FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_LAST FUNC_BUF_RGTR_REQ_REQ_BUF_PAGE_SIZE_1G 1336 __le16 req_buf_len; 1337 __le16 resp_buf_len; 1338 u8 unused_0[2]; 1339 __le64 req_buf_page_addr0; 1340 __le64 req_buf_page_addr1; 1341 __le64 req_buf_page_addr2; 1342 __le64 req_buf_page_addr3; 1343 __le64 req_buf_page_addr4; 1344 __le64 req_buf_page_addr5; 1345 __le64 req_buf_page_addr6; 1346 __le64 req_buf_page_addr7; 1347 __le64 req_buf_page_addr8; 1348 __le64 req_buf_page_addr9; 1349 __le64 error_buf_addr; 1350 __le64 resp_buf_addr; 1351}; 1352 1353/* hwrm_func_buf_rgtr_output (size:128b/16B) */ 1354struct hwrm_func_buf_rgtr_output { 1355 __le16 error_code; 1356 __le16 req_type; 1357 __le16 seq_id; 1358 __le16 resp_len; 1359 u8 unused_0[7]; 1360 u8 valid; 1361}; 1362 1363/* hwrm_func_drv_qver_input (size:192b/24B) */ 1364struct hwrm_func_drv_qver_input { 1365 __le16 req_type; 1366 __le16 cmpl_ring; 1367 __le16 seq_id; 1368 __le16 target_id; 1369 __le64 resp_addr; 1370 __le32 reserved; 1371 __le16 fid; 1372 u8 unused_0[2]; 1373}; 1374 1375/* hwrm_func_drv_qver_output (size:192b/24B) */ 1376struct hwrm_func_drv_qver_output { 1377 __le16 error_code; 1378 __le16 req_type; 1379 __le16 seq_id; 1380 __le16 resp_len; 1381 __le16 os_type; 1382 #define FUNC_DRV_QVER_RESP_OS_TYPE_UNKNOWN 0x0UL 1383 #define FUNC_DRV_QVER_RESP_OS_TYPE_OTHER 0x1UL 1384 #define FUNC_DRV_QVER_RESP_OS_TYPE_MSDOS 0xeUL 1385 #define FUNC_DRV_QVER_RESP_OS_TYPE_WINDOWS 0x12UL 1386 #define FUNC_DRV_QVER_RESP_OS_TYPE_SOLARIS 0x1dUL 1387 #define FUNC_DRV_QVER_RESP_OS_TYPE_LINUX 0x24UL 1388 #define FUNC_DRV_QVER_RESP_OS_TYPE_FREEBSD 0x2aUL 1389 #define FUNC_DRV_QVER_RESP_OS_TYPE_ESXI 0x68UL 1390 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN864 0x73UL 1391 #define FUNC_DRV_QVER_RESP_OS_TYPE_WIN2012R2 0x74UL 1392 #define FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 0x8000UL 1393 #define FUNC_DRV_QVER_RESP_OS_TYPE_LAST FUNC_DRV_QVER_RESP_OS_TYPE_UEFI 1394 u8 ver_maj_8b; 1395 u8 ver_min_8b; 1396 u8 ver_upd_8b; 1397 u8 unused_0[2]; 1398 u8 valid; 1399 __le16 ver_maj; 1400 __le16 ver_min; 1401 __le16 ver_upd; 1402 __le16 ver_patch; 1403}; 1404 1405/* hwrm_func_resource_qcaps_input (size:192b/24B) */ 1406struct hwrm_func_resource_qcaps_input { 1407 __le16 req_type; 1408 __le16 cmpl_ring; 1409 __le16 seq_id; 1410 __le16 target_id; 1411 __le64 resp_addr; 1412 __le16 fid; 1413 u8 unused_0[6]; 1414}; 1415 1416/* hwrm_func_resource_qcaps_output (size:448b/56B) */ 1417struct hwrm_func_resource_qcaps_output { 1418 __le16 error_code; 1419 __le16 req_type; 1420 __le16 seq_id; 1421 __le16 resp_len; 1422 __le16 max_vfs; 1423 __le16 max_msix; 1424 __le16 vf_reservation_strategy; 1425 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MAXIMAL 0x0UL 1426 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL 0x1UL 1427 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 0x2UL 1428 #define FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_LAST FUNC_RESOURCE_QCAPS_RESP_VF_RESERVATION_STRATEGY_MINIMAL_STATIC 1429 __le16 min_rsscos_ctx; 1430 __le16 max_rsscos_ctx; 1431 __le16 min_cmpl_rings; 1432 __le16 max_cmpl_rings; 1433 __le16 min_tx_rings; 1434 __le16 max_tx_rings; 1435 __le16 min_rx_rings; 1436 __le16 max_rx_rings; 1437 __le16 min_l2_ctxs; 1438 __le16 max_l2_ctxs; 1439 __le16 min_vnics; 1440 __le16 max_vnics; 1441 __le16 min_stat_ctx; 1442 __le16 max_stat_ctx; 1443 __le16 min_hw_ring_grps; 1444 __le16 max_hw_ring_grps; 1445 __le16 max_tx_scheduler_inputs; 1446 u8 unused_0[7]; 1447 u8 valid; 1448}; 1449 1450/* hwrm_func_vf_resource_cfg_input (size:448b/56B) */ 1451struct hwrm_func_vf_resource_cfg_input { 1452 __le16 req_type; 1453 __le16 cmpl_ring; 1454 __le16 seq_id; 1455 __le16 target_id; 1456 __le64 resp_addr; 1457 __le16 vf_id; 1458 __le16 max_msix; 1459 __le16 min_rsscos_ctx; 1460 __le16 max_rsscos_ctx; 1461 __le16 min_cmpl_rings; 1462 __le16 max_cmpl_rings; 1463 __le16 min_tx_rings; 1464 __le16 max_tx_rings; 1465 __le16 min_rx_rings; 1466 __le16 max_rx_rings; 1467 __le16 min_l2_ctxs; 1468 __le16 max_l2_ctxs; 1469 __le16 min_vnics; 1470 __le16 max_vnics; 1471 __le16 min_stat_ctx; 1472 __le16 max_stat_ctx; 1473 __le16 min_hw_ring_grps; 1474 __le16 max_hw_ring_grps; 1475 u8 unused_0[4]; 1476}; 1477 1478/* hwrm_func_vf_resource_cfg_output (size:256b/32B) */ 1479struct hwrm_func_vf_resource_cfg_output { 1480 __le16 error_code; 1481 __le16 req_type; 1482 __le16 seq_id; 1483 __le16 resp_len; 1484 __le16 reserved_rsscos_ctx; 1485 __le16 reserved_cmpl_rings; 1486 __le16 reserved_tx_rings; 1487 __le16 reserved_rx_rings; 1488 __le16 reserved_l2_ctxs; 1489 __le16 reserved_vnics; 1490 __le16 reserved_stat_ctx; 1491 __le16 reserved_hw_ring_grps; 1492 u8 unused_0[7]; 1493 u8 valid; 1494}; 1495 1496/* hwrm_port_phy_cfg_input (size:448b/56B) */ 1497struct hwrm_port_phy_cfg_input { 1498 __le16 req_type; 1499 __le16 cmpl_ring; 1500 __le16 seq_id; 1501 __le16 target_id; 1502 __le64 resp_addr; 1503 __le32 flags; 1504 #define PORT_PHY_CFG_REQ_FLAGS_RESET_PHY 0x1UL 1505 #define PORT_PHY_CFG_REQ_FLAGS_DEPRECATED 0x2UL 1506 #define PORT_PHY_CFG_REQ_FLAGS_FORCE 0x4UL 1507 #define PORT_PHY_CFG_REQ_FLAGS_RESTART_AUTONEG 0x8UL 1508 #define PORT_PHY_CFG_REQ_FLAGS_EEE_ENABLE 0x10UL 1509 #define PORT_PHY_CFG_REQ_FLAGS_EEE_DISABLE 0x20UL 1510 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_ENABLE 0x40UL 1511 #define PORT_PHY_CFG_REQ_FLAGS_EEE_TX_LPI_DISABLE 0x80UL 1512 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_ENABLE 0x100UL 1513 #define PORT_PHY_CFG_REQ_FLAGS_FEC_AUTONEG_DISABLE 0x200UL 1514 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_ENABLE 0x400UL 1515 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE74_DISABLE 0x800UL 1516 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_ENABLE 0x1000UL 1517 #define PORT_PHY_CFG_REQ_FLAGS_FEC_CLAUSE91_DISABLE 0x2000UL 1518 #define PORT_PHY_CFG_REQ_FLAGS_FORCE_LINK_DWN 0x4000UL 1519 __le32 enables; 1520 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_MODE 0x1UL 1521 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_DUPLEX 0x2UL 1522 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_PAUSE 0x4UL 1523 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED 0x8UL 1524 #define PORT_PHY_CFG_REQ_ENABLES_AUTO_LINK_SPEED_MASK 0x10UL 1525 #define PORT_PHY_CFG_REQ_ENABLES_WIRESPEED 0x20UL 1526 #define PORT_PHY_CFG_REQ_ENABLES_LPBK 0x40UL 1527 #define PORT_PHY_CFG_REQ_ENABLES_PREEMPHASIS 0x80UL 1528 #define PORT_PHY_CFG_REQ_ENABLES_FORCE_PAUSE 0x100UL 1529 #define PORT_PHY_CFG_REQ_ENABLES_EEE_LINK_SPEED_MASK 0x200UL 1530 #define PORT_PHY_CFG_REQ_ENABLES_TX_LPI_TIMER 0x400UL 1531 __le16 port_id; 1532 __le16 force_link_speed; 1533 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100MB 0x1UL 1534 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_1GB 0xaUL 1535 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2GB 0x14UL 1536 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_2_5GB 0x19UL 1537 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10GB 0x64UL 1538 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_20GB 0xc8UL 1539 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_25GB 0xfaUL 1540 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_40GB 0x190UL 1541 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_50GB 0x1f4UL 1542 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_100GB 0x3e8UL 1543 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 0xffffUL 1544 #define PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_LAST PORT_PHY_CFG_REQ_FORCE_LINK_SPEED_10MB 1545 u8 auto_mode; 1546 #define PORT_PHY_CFG_REQ_AUTO_MODE_NONE 0x0UL 1547 #define PORT_PHY_CFG_REQ_AUTO_MODE_ALL_SPEEDS 0x1UL 1548 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_SPEED 0x2UL 1549 #define PORT_PHY_CFG_REQ_AUTO_MODE_ONE_OR_BELOW 0x3UL 1550 #define PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 0x4UL 1551 #define PORT_PHY_CFG_REQ_AUTO_MODE_LAST PORT_PHY_CFG_REQ_AUTO_MODE_SPEED_MASK 1552 u8 auto_duplex; 1553 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_HALF 0x0UL 1554 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_FULL 0x1UL 1555 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 0x2UL 1556 #define PORT_PHY_CFG_REQ_AUTO_DUPLEX_LAST PORT_PHY_CFG_REQ_AUTO_DUPLEX_BOTH 1557 u8 auto_pause; 1558 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_TX 0x1UL 1559 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_RX 0x2UL 1560 #define PORT_PHY_CFG_REQ_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1561 u8 unused_0; 1562 __le16 auto_link_speed; 1563 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100MB 0x1UL 1564 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_1GB 0xaUL 1565 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2GB 0x14UL 1566 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_2_5GB 0x19UL 1567 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10GB 0x64UL 1568 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_20GB 0xc8UL 1569 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_25GB 0xfaUL 1570 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_40GB 0x190UL 1571 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_50GB 0x1f4UL 1572 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_100GB 0x3e8UL 1573 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 0xffffUL 1574 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_LAST PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_10MB 1575 __le16 auto_link_speed_mask; 1576 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1577 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1578 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1579 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1580 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1581 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1582 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1583 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1584 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1585 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1586 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1587 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1588 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1589 #define PORT_PHY_CFG_REQ_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1590 u8 wirespeed; 1591 #define PORT_PHY_CFG_REQ_WIRESPEED_OFF 0x0UL 1592 #define PORT_PHY_CFG_REQ_WIRESPEED_ON 0x1UL 1593 #define PORT_PHY_CFG_REQ_WIRESPEED_LAST PORT_PHY_CFG_REQ_WIRESPEED_ON 1594 u8 lpbk; 1595 #define PORT_PHY_CFG_REQ_LPBK_NONE 0x0UL 1596 #define PORT_PHY_CFG_REQ_LPBK_LOCAL 0x1UL 1597 #define PORT_PHY_CFG_REQ_LPBK_REMOTE 0x2UL 1598 #define PORT_PHY_CFG_REQ_LPBK_LAST PORT_PHY_CFG_REQ_LPBK_REMOTE 1599 u8 force_pause; 1600 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_TX 0x1UL 1601 #define PORT_PHY_CFG_REQ_FORCE_PAUSE_RX 0x2UL 1602 u8 unused_1; 1603 __le32 preemphasis; 1604 __le16 eee_link_speed_mask; 1605 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1606 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_100MB 0x2UL 1607 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1608 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_1GB 0x8UL 1609 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1610 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1611 #define PORT_PHY_CFG_REQ_EEE_LINK_SPEED_MASK_10GB 0x40UL 1612 u8 unused_2[2]; 1613 __le32 tx_lpi_timer; 1614 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_MASK 0xffffffUL 1615 #define PORT_PHY_CFG_REQ_TX_LPI_TIMER_SFT 0 1616 __le32 unused_3; 1617}; 1618 1619/* hwrm_port_phy_cfg_output (size:128b/16B) */ 1620struct hwrm_port_phy_cfg_output { 1621 __le16 error_code; 1622 __le16 req_type; 1623 __le16 seq_id; 1624 __le16 resp_len; 1625 u8 unused_0[7]; 1626 u8 valid; 1627}; 1628 1629/* hwrm_port_phy_cfg_cmd_err (size:64b/8B) */ 1630struct hwrm_port_phy_cfg_cmd_err { 1631 u8 code; 1632 #define PORT_PHY_CFG_CMD_ERR_CODE_UNKNOWN 0x0UL 1633 #define PORT_PHY_CFG_CMD_ERR_CODE_ILLEGAL_SPEED 0x1UL 1634 #define PORT_PHY_CFG_CMD_ERR_CODE_RETRY 0x2UL 1635 #define PORT_PHY_CFG_CMD_ERR_CODE_LAST PORT_PHY_CFG_CMD_ERR_CODE_RETRY 1636 u8 unused_0[7]; 1637}; 1638 1639/* hwrm_port_phy_qcfg_input (size:192b/24B) */ 1640struct hwrm_port_phy_qcfg_input { 1641 __le16 req_type; 1642 __le16 cmpl_ring; 1643 __le16 seq_id; 1644 __le16 target_id; 1645 __le64 resp_addr; 1646 __le16 port_id; 1647 u8 unused_0[6]; 1648}; 1649 1650/* hwrm_port_phy_qcfg_output (size:768b/96B) */ 1651struct hwrm_port_phy_qcfg_output { 1652 __le16 error_code; 1653 __le16 req_type; 1654 __le16 seq_id; 1655 __le16 resp_len; 1656 u8 link; 1657 #define PORT_PHY_QCFG_RESP_LINK_NO_LINK 0x0UL 1658 #define PORT_PHY_QCFG_RESP_LINK_SIGNAL 0x1UL 1659 #define PORT_PHY_QCFG_RESP_LINK_LINK 0x2UL 1660 #define PORT_PHY_QCFG_RESP_LINK_LAST PORT_PHY_QCFG_RESP_LINK_LINK 1661 u8 unused_0; 1662 __le16 link_speed; 1663 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100MB 0x1UL 1664 #define PORT_PHY_QCFG_RESP_LINK_SPEED_1GB 0xaUL 1665 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2GB 0x14UL 1666 #define PORT_PHY_QCFG_RESP_LINK_SPEED_2_5GB 0x19UL 1667 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10GB 0x64UL 1668 #define PORT_PHY_QCFG_RESP_LINK_SPEED_20GB 0xc8UL 1669 #define PORT_PHY_QCFG_RESP_LINK_SPEED_25GB 0xfaUL 1670 #define PORT_PHY_QCFG_RESP_LINK_SPEED_40GB 0x190UL 1671 #define PORT_PHY_QCFG_RESP_LINK_SPEED_50GB 0x1f4UL 1672 #define PORT_PHY_QCFG_RESP_LINK_SPEED_100GB 0x3e8UL 1673 #define PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 0xffffUL 1674 #define PORT_PHY_QCFG_RESP_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_LINK_SPEED_10MB 1675 u8 duplex_cfg; 1676 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_HALF 0x0UL 1677 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 0x1UL 1678 #define PORT_PHY_QCFG_RESP_DUPLEX_CFG_LAST PORT_PHY_QCFG_RESP_DUPLEX_CFG_FULL 1679 u8 pause; 1680 #define PORT_PHY_QCFG_RESP_PAUSE_TX 0x1UL 1681 #define PORT_PHY_QCFG_RESP_PAUSE_RX 0x2UL 1682 __le16 support_speeds; 1683 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MBHD 0x1UL 1684 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100MB 0x2UL 1685 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GBHD 0x4UL 1686 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_1GB 0x8UL 1687 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2GB 0x10UL 1688 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_2_5GB 0x20UL 1689 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10GB 0x40UL 1690 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_20GB 0x80UL 1691 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_25GB 0x100UL 1692 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_40GB 0x200UL 1693 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_50GB 0x400UL 1694 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_100GB 0x800UL 1695 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MBHD 0x1000UL 1696 #define PORT_PHY_QCFG_RESP_SUPPORT_SPEEDS_10MB 0x2000UL 1697 __le16 force_link_speed; 1698 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100MB 0x1UL 1699 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_1GB 0xaUL 1700 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2GB 0x14UL 1701 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_2_5GB 0x19UL 1702 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10GB 0x64UL 1703 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_20GB 0xc8UL 1704 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_25GB 0xfaUL 1705 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_40GB 0x190UL 1706 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_50GB 0x1f4UL 1707 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_100GB 0x3e8UL 1708 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 0xffffUL 1709 #define PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_FORCE_LINK_SPEED_10MB 1710 u8 auto_mode; 1711 #define PORT_PHY_QCFG_RESP_AUTO_MODE_NONE 0x0UL 1712 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ALL_SPEEDS 0x1UL 1713 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_SPEED 0x2UL 1714 #define PORT_PHY_QCFG_RESP_AUTO_MODE_ONE_OR_BELOW 0x3UL 1715 #define PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 0x4UL 1716 #define PORT_PHY_QCFG_RESP_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_AUTO_MODE_SPEED_MASK 1717 u8 auto_pause; 1718 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_TX 0x1UL 1719 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_RX 0x2UL 1720 #define PORT_PHY_QCFG_RESP_AUTO_PAUSE_AUTONEG_PAUSE 0x4UL 1721 __le16 auto_link_speed; 1722 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100MB 0x1UL 1723 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_1GB 0xaUL 1724 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2GB 0x14UL 1725 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_2_5GB 0x19UL 1726 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10GB 0x64UL 1727 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_20GB 0xc8UL 1728 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_25GB 0xfaUL 1729 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_40GB 0x190UL 1730 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_50GB 0x1f4UL 1731 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_100GB 0x3e8UL 1732 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 0xffffUL 1733 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_LAST PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_10MB 1734 __le16 auto_link_speed_mask; 1735 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MBHD 0x1UL 1736 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100MB 0x2UL 1737 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GBHD 0x4UL 1738 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_1GB 0x8UL 1739 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2GB 0x10UL 1740 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_2_5GB 0x20UL 1741 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10GB 0x40UL 1742 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_20GB 0x80UL 1743 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_25GB 0x100UL 1744 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_40GB 0x200UL 1745 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_50GB 0x400UL 1746 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_100GB 0x800UL 1747 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MBHD 0x1000UL 1748 #define PORT_PHY_QCFG_RESP_AUTO_LINK_SPEED_MASK_10MB 0x2000UL 1749 u8 wirespeed; 1750 #define PORT_PHY_QCFG_RESP_WIRESPEED_OFF 0x0UL 1751 #define PORT_PHY_QCFG_RESP_WIRESPEED_ON 0x1UL 1752 #define PORT_PHY_QCFG_RESP_WIRESPEED_LAST PORT_PHY_QCFG_RESP_WIRESPEED_ON 1753 u8 lpbk; 1754 #define PORT_PHY_QCFG_RESP_LPBK_NONE 0x0UL 1755 #define PORT_PHY_QCFG_RESP_LPBK_LOCAL 0x1UL 1756 #define PORT_PHY_QCFG_RESP_LPBK_REMOTE 0x2UL 1757 #define PORT_PHY_QCFG_RESP_LPBK_LAST PORT_PHY_QCFG_RESP_LPBK_REMOTE 1758 u8 force_pause; 1759 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_TX 0x1UL 1760 #define PORT_PHY_QCFG_RESP_FORCE_PAUSE_RX 0x2UL 1761 u8 module_status; 1762 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NONE 0x0UL 1763 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_DISABLETX 0x1UL 1764 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_WARNINGMSG 0x2UL 1765 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_PWRDOWN 0x3UL 1766 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTINSERTED 0x4UL 1767 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 0xffUL 1768 #define PORT_PHY_QCFG_RESP_MODULE_STATUS_LAST PORT_PHY_QCFG_RESP_MODULE_STATUS_NOTAPPLICABLE 1769 __le32 preemphasis; 1770 u8 phy_maj; 1771 u8 phy_min; 1772 u8 phy_bld; 1773 u8 phy_type; 1774 #define PORT_PHY_QCFG_RESP_PHY_TYPE_UNKNOWN 0x0UL 1775 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASECR 0x1UL 1776 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR4 0x2UL 1777 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASELR 0x3UL 1778 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASESR 0x4UL 1779 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR2 0x5UL 1780 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKX 0x6UL 1781 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASEKR 0x7UL 1782 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASET 0x8UL 1783 #define PORT_PHY_QCFG_RESP_PHY_TYPE_BASETE 0x9UL 1784 #define PORT_PHY_QCFG_RESP_PHY_TYPE_SGMIIEXTPHY 0xaUL 1785 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_L 0xbUL 1786 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_S 0xcUL 1787 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASECR_CA_N 0xdUL 1788 #define PORT_PHY_QCFG_RESP_PHY_TYPE_25G_BASESR 0xeUL 1789 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASECR4 0xfUL 1790 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR4 0x10UL 1791 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASELR4 0x11UL 1792 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASEER4 0x12UL 1793 #define PORT_PHY_QCFG_RESP_PHY_TYPE_100G_BASESR10 0x13UL 1794 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASECR4 0x14UL 1795 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASESR4 0x15UL 1796 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASELR4 0x16UL 1797 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_BASEER4 0x17UL 1798 #define PORT_PHY_QCFG_RESP_PHY_TYPE_40G_ACTIVE_CABLE 0x18UL 1799 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASET 0x19UL 1800 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASESX 0x1aUL 1801 #define PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 0x1bUL 1802 #define PORT_PHY_QCFG_RESP_PHY_TYPE_LAST PORT_PHY_QCFG_RESP_PHY_TYPE_1G_BASECX 1803 u8 media_type; 1804 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_UNKNOWN 0x0UL 1805 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_TP 0x1UL 1806 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_DAC 0x2UL 1807 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 0x3UL 1808 #define PORT_PHY_QCFG_RESP_MEDIA_TYPE_LAST PORT_PHY_QCFG_RESP_MEDIA_TYPE_FIBRE 1809 u8 xcvr_pkg_type; 1810 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_INTERNAL 0x1UL 1811 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 0x2UL 1812 #define PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_PKG_TYPE_XCVR_EXTERNAL 1813 u8 eee_config_phy_addr; 1814 #define PORT_PHY_QCFG_RESP_PHY_ADDR_MASK 0x1fUL 1815 #define PORT_PHY_QCFG_RESP_PHY_ADDR_SFT 0 1816 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_MASK 0xe0UL 1817 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_SFT 5 1818 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ENABLED 0x20UL 1819 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_ACTIVE 0x40UL 1820 #define PORT_PHY_QCFG_RESP_EEE_CONFIG_EEE_TX_LPI 0x80UL 1821 u8 parallel_detect; 1822 #define PORT_PHY_QCFG_RESP_PARALLEL_DETECT 0x1UL 1823 __le16 link_partner_adv_speeds; 1824 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MBHD 0x1UL 1825 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100MB 0x2UL 1826 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GBHD 0x4UL 1827 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_1GB 0x8UL 1828 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2GB 0x10UL 1829 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_2_5GB 0x20UL 1830 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10GB 0x40UL 1831 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_20GB 0x80UL 1832 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_25GB 0x100UL 1833 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_40GB 0x200UL 1834 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_50GB 0x400UL 1835 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_100GB 0x800UL 1836 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MBHD 0x1000UL 1837 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_SPEEDS_10MB 0x2000UL 1838 u8 link_partner_adv_auto_mode; 1839 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_NONE 0x0UL 1840 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ALL_SPEEDS 0x1UL 1841 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_SPEED 0x2UL 1842 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_ONE_OR_BELOW 0x3UL 1843 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 0x4UL 1844 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_LAST PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_AUTO_MODE_SPEED_MASK 1845 u8 link_partner_adv_pause; 1846 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_TX 0x1UL 1847 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_PAUSE_RX 0x2UL 1848 __le16 adv_eee_link_speed_mask; 1849 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1850 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1851 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1852 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1853 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1854 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1855 #define PORT_PHY_QCFG_RESP_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1856 __le16 link_partner_adv_eee_link_speed_mask; 1857 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD1 0x1UL 1858 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_100MB 0x2UL 1859 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD2 0x4UL 1860 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_1GB 0x8UL 1861 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD3 0x10UL 1862 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_RSVD4 0x20UL 1863 #define PORT_PHY_QCFG_RESP_LINK_PARTNER_ADV_EEE_LINK_SPEED_MASK_10GB 0x40UL 1864 __le32 xcvr_identifier_type_tx_lpi_timer; 1865 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_MASK 0xffffffUL 1866 #define PORT_PHY_QCFG_RESP_TX_LPI_TIMER_SFT 0 1867 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_MASK 0xff000000UL 1868 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFT 24 1869 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_UNKNOWN (0x0UL << 24) 1870 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_SFP (0x3UL << 24) 1871 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP (0xcUL << 24) 1872 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFPPLUS (0xdUL << 24) 1873 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 (0x11UL << 24) 1874 #define PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_LAST PORT_PHY_QCFG_RESP_XCVR_IDENTIFIER_TYPE_QSFP28 1875 __le16 fec_cfg; 1876 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_NONE_SUPPORTED 0x1UL 1877 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_SUPPORTED 0x2UL 1878 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_AUTONEG_ENABLED 0x4UL 1879 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_SUPPORTED 0x8UL 1880 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE74_ENABLED 0x10UL 1881 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_SUPPORTED 0x20UL 1882 #define PORT_PHY_QCFG_RESP_FEC_CFG_FEC_CLAUSE91_ENABLED 0x40UL 1883 u8 duplex_state; 1884 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_HALF 0x0UL 1885 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 0x1UL 1886 #define PORT_PHY_QCFG_RESP_DUPLEX_STATE_LAST PORT_PHY_QCFG_RESP_DUPLEX_STATE_FULL 1887 u8 option_flags; 1888 #define PORT_PHY_QCFG_RESP_OPTION_FLAGS_MEDIA_AUTO_DETECT 0x1UL 1889 char phy_vendor_name[16]; 1890 char phy_vendor_partnumber[16]; 1891 u8 unused_2[7]; 1892 u8 valid; 1893}; 1894 1895/* hwrm_port_mac_cfg_input (size:320b/40B) */ 1896struct hwrm_port_mac_cfg_input { 1897 __le16 req_type; 1898 __le16 cmpl_ring; 1899 __le16 seq_id; 1900 __le16 target_id; 1901 __le64 resp_addr; 1902 __le32 flags; 1903 #define PORT_MAC_CFG_REQ_FLAGS_MATCH_LINK 0x1UL 1904 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_ENABLE 0x2UL 1905 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_ENABLE 0x4UL 1906 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_ENABLE 0x8UL 1907 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_ENABLE 0x10UL 1908 #define PORT_MAC_CFG_REQ_FLAGS_PTP_RX_TS_CAPTURE_DISABLE 0x20UL 1909 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_ENABLE 0x40UL 1910 #define PORT_MAC_CFG_REQ_FLAGS_PTP_TX_TS_CAPTURE_DISABLE 0x80UL 1911 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_ENABLE 0x100UL 1912 #define PORT_MAC_CFG_REQ_FLAGS_OOB_WOL_DISABLE 0x200UL 1913 #define PORT_MAC_CFG_REQ_FLAGS_VLAN_PRI2COS_DISABLE 0x400UL 1914 #define PORT_MAC_CFG_REQ_FLAGS_TUNNEL_PRI2COS_DISABLE 0x800UL 1915 #define PORT_MAC_CFG_REQ_FLAGS_IP_DSCP2COS_DISABLE 0x1000UL 1916 __le32 enables; 1917 #define PORT_MAC_CFG_REQ_ENABLES_IPG 0x1UL 1918 #define PORT_MAC_CFG_REQ_ENABLES_LPBK 0x2UL 1919 #define PORT_MAC_CFG_REQ_ENABLES_VLAN_PRI2COS_MAP_PRI 0x4UL 1920 #define PORT_MAC_CFG_REQ_ENABLES_TUNNEL_PRI2COS_MAP_PRI 0x10UL 1921 #define PORT_MAC_CFG_REQ_ENABLES_DSCP2COS_MAP_PRI 0x20UL 1922 #define PORT_MAC_CFG_REQ_ENABLES_RX_TS_CAPTURE_PTP_MSG_TYPE 0x40UL 1923 #define PORT_MAC_CFG_REQ_ENABLES_TX_TS_CAPTURE_PTP_MSG_TYPE 0x80UL 1924 #define PORT_MAC_CFG_REQ_ENABLES_COS_FIELD_CFG 0x100UL 1925 __le16 port_id; 1926 u8 ipg; 1927 u8 lpbk; 1928 #define PORT_MAC_CFG_REQ_LPBK_NONE 0x0UL 1929 #define PORT_MAC_CFG_REQ_LPBK_LOCAL 0x1UL 1930 #define PORT_MAC_CFG_REQ_LPBK_REMOTE 0x2UL 1931 #define PORT_MAC_CFG_REQ_LPBK_LAST PORT_MAC_CFG_REQ_LPBK_REMOTE 1932 u8 vlan_pri2cos_map_pri; 1933 u8 reserved1; 1934 u8 tunnel_pri2cos_map_pri; 1935 u8 dscp2pri_map_pri; 1936 __le16 rx_ts_capture_ptp_msg_type; 1937 __le16 tx_ts_capture_ptp_msg_type; 1938 u8 cos_field_cfg; 1939 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_RSVD1 0x1UL 1940 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_MASK 0x6UL 1941 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_SFT 1 1942 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_INNERMOST (0x0UL << 1) 1943 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTER (0x1UL << 1) 1944 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_OUTERMOST (0x2UL << 1) 1945 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 1) 1946 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_VLAN_PRI_SEL_UNSPECIFIED 1947 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_MASK 0x18UL 1948 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_SFT 3 1949 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_INNERMOST (0x0UL << 3) 1950 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTER (0x1UL << 3) 1951 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_OUTERMOST (0x2UL << 3) 1952 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED (0x3UL << 3) 1953 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_LAST PORT_MAC_CFG_REQ_COS_FIELD_CFG_T_VLAN_PRI_SEL_UNSPECIFIED 1954 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_MASK 0xe0UL 1955 #define PORT_MAC_CFG_REQ_COS_FIELD_CFG_DEFAULT_COS_SFT 5 1956 u8 unused_0[3]; 1957}; 1958 1959/* hwrm_port_mac_cfg_output (size:128b/16B) */ 1960struct hwrm_port_mac_cfg_output { 1961 __le16 error_code; 1962 __le16 req_type; 1963 __le16 seq_id; 1964 __le16 resp_len; 1965 __le16 mru; 1966 __le16 mtu; 1967 u8 ipg; 1968 u8 lpbk; 1969 #define PORT_MAC_CFG_RESP_LPBK_NONE 0x0UL 1970 #define PORT_MAC_CFG_RESP_LPBK_LOCAL 0x1UL 1971 #define PORT_MAC_CFG_RESP_LPBK_REMOTE 0x2UL 1972 #define PORT_MAC_CFG_RESP_LPBK_LAST PORT_MAC_CFG_RESP_LPBK_REMOTE 1973 u8 unused_0; 1974 u8 valid; 1975}; 1976 1977/* hwrm_port_mac_ptp_qcfg_input (size:192b/24B) */ 1978struct hwrm_port_mac_ptp_qcfg_input { 1979 __le16 req_type; 1980 __le16 cmpl_ring; 1981 __le16 seq_id; 1982 __le16 target_id; 1983 __le64 resp_addr; 1984 __le16 port_id; 1985 u8 unused_0[6]; 1986}; 1987 1988/* hwrm_port_mac_ptp_qcfg_output (size:640b/80B) */ 1989struct hwrm_port_mac_ptp_qcfg_output { 1990 __le16 error_code; 1991 __le16 req_type; 1992 __le16 seq_id; 1993 __le16 resp_len; 1994 u8 flags; 1995 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_DIRECT_ACCESS 0x1UL 1996 #define PORT_MAC_PTP_QCFG_RESP_FLAGS_HWRM_ACCESS 0x2UL 1997 u8 unused_0[3]; 1998 __le32 rx_ts_reg_off_lower; 1999 __le32 rx_ts_reg_off_upper; 2000 __le32 rx_ts_reg_off_seq_id;
2001 __le32 rx_ts_reg_off_src_id_0; 2002 __le32 rx_ts_reg_off_src_id_1; 2003 __le32 rx_ts_reg_off_src_id_2; 2004 __le32 rx_ts_reg_off_domain_id; 2005 __le32 rx_ts_reg_off_fifo; 2006 __le32 rx_ts_reg_off_fifo_adv; 2007 __le32 rx_ts_reg_off_granularity; 2008 __le32 tx_ts_reg_off_lower; 2009 __le32 tx_ts_reg_off_upper; 2010 __le32 tx_ts_reg_off_seq_id; 2011 __le32 tx_ts_reg_off_fifo; 2012 __le32 tx_ts_reg_off_granularity; 2013 u8 unused_1[7]; 2014 u8 valid; 2015}; 2016 2017/* hwrm_port_qstats_input (size:320b/40B) */ 2018struct hwrm_port_qstats_input { 2019 __le16 req_type; 2020 __le16 cmpl_ring; 2021 __le16 seq_id; 2022 __le16 target_id; 2023 __le64 resp_addr; 2024 __le16 port_id; 2025 u8 unused_0[6]; 2026 __le64 tx_stat_host_addr; 2027 __le64 rx_stat_host_addr; 2028}; 2029 2030/* hwrm_port_qstats_output (size:128b/16B) */ 2031struct hwrm_port_qstats_output { 2032 __le16 error_code; 2033 __le16 req_type; 2034 __le16 seq_id; 2035 __le16 resp_len; 2036 __le16 tx_stat_size; 2037 __le16 rx_stat_size; 2038 u8 unused_0[3]; 2039 u8 valid; 2040}; 2041 2042/* hwrm_port_qstats_ext_input (size:320b/40B) */ 2043struct hwrm_port_qstats_ext_input { 2044 __le16 req_type; 2045 __le16 cmpl_ring; 2046 __le16 seq_id; 2047 __le16 target_id; 2048 __le64 resp_addr; 2049 __le16 port_id; 2050 __le16 tx_stat_size; 2051 __le16 rx_stat_size; 2052 u8 unused_0[2]; 2053 __le64 tx_stat_host_addr; 2054 __le64 rx_stat_host_addr; 2055}; 2056 2057/* hwrm_port_qstats_ext_output (size:128b/16B) */ 2058struct hwrm_port_qstats_ext_output { 2059 __le16 error_code; 2060 __le16 req_type; 2061 __le16 seq_id; 2062 __le16 resp_len; 2063 __le16 tx_stat_size; 2064 __le16 rx_stat_size; 2065 u8 unused_0[3]; 2066 u8 valid; 2067}; 2068 2069/* hwrm_port_lpbk_qstats_input (size:128b/16B) */ 2070struct hwrm_port_lpbk_qstats_input { 2071 __le16 req_type; 2072 __le16 cmpl_ring; 2073 __le16 seq_id; 2074 __le16 target_id; 2075 __le64 resp_addr; 2076}; 2077 2078/* hwrm_port_lpbk_qstats_output (size:768b/96B) */ 2079struct hwrm_port_lpbk_qstats_output { 2080 __le16 error_code; 2081 __le16 req_type; 2082 __le16 seq_id; 2083 __le16 resp_len; 2084 __le64 lpbk_ucast_frames; 2085 __le64 lpbk_mcast_frames; 2086 __le64 lpbk_bcast_frames; 2087 __le64 lpbk_ucast_bytes; 2088 __le64 lpbk_mcast_bytes; 2089 __le64 lpbk_bcast_bytes; 2090 __le64 tx_stat_discard; 2091 __le64 tx_stat_error; 2092 __le64 rx_stat_discard; 2093 __le64 rx_stat_error; 2094 u8 unused_0[7]; 2095 u8 valid; 2096}; 2097 2098/* hwrm_port_clr_stats_input (size:192b/24B) */ 2099struct hwrm_port_clr_stats_input { 2100 __le16 req_type; 2101 __le16 cmpl_ring; 2102 __le16 seq_id; 2103 __le16 target_id; 2104 __le64 resp_addr; 2105 __le16 port_id; 2106 u8 unused_0[6]; 2107}; 2108 2109/* hwrm_port_clr_stats_output (size:128b/16B) */ 2110struct hwrm_port_clr_stats_output { 2111 __le16 error_code; 2112 __le16 req_type; 2113 __le16 seq_id; 2114 __le16 resp_len; 2115 u8 unused_0[7]; 2116 u8 valid; 2117}; 2118 2119/* hwrm_port_lpbk_clr_stats_input (size:128b/16B) */ 2120struct hwrm_port_lpbk_clr_stats_input { 2121 __le16 req_type; 2122 __le16 cmpl_ring; 2123 __le16 seq_id; 2124 __le16 target_id; 2125 __le64 resp_addr; 2126}; 2127 2128/* hwrm_port_lpbk_clr_stats_output (size:128b/16B) */ 2129struct hwrm_port_lpbk_clr_stats_output { 2130 __le16 error_code; 2131 __le16 req_type; 2132 __le16 seq_id; 2133 __le16 resp_len; 2134 u8 unused_0[7]; 2135 u8 valid; 2136}; 2137 2138/* hwrm_port_phy_qcaps_input (size:192b/24B) */ 2139struct hwrm_port_phy_qcaps_input { 2140 __le16 req_type; 2141 __le16 cmpl_ring; 2142 __le16 seq_id; 2143 __le16 target_id; 2144 __le64 resp_addr; 2145 __le16 port_id; 2146 u8 unused_0[6]; 2147}; 2148 2149/* hwrm_port_phy_qcaps_output (size:192b/24B) */ 2150struct hwrm_port_phy_qcaps_output { 2151 __le16 error_code; 2152 __le16 req_type; 2153 __le16 seq_id; 2154 __le16 resp_len; 2155 u8 flags; 2156 #define PORT_PHY_QCAPS_RESP_FLAGS_EEE_SUPPORTED 0x1UL 2157 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_MASK 0xfeUL 2158 #define PORT_PHY_QCAPS_RESP_FLAGS_RSVD1_SFT 1 2159 u8 port_cnt; 2160 #define PORT_PHY_QCAPS_RESP_PORT_CNT_UNKNOWN 0x0UL 2161 #define PORT_PHY_QCAPS_RESP_PORT_CNT_1 0x1UL 2162 #define PORT_PHY_QCAPS_RESP_PORT_CNT_2 0x2UL 2163 #define PORT_PHY_QCAPS_RESP_PORT_CNT_3 0x3UL 2164 #define PORT_PHY_QCAPS_RESP_PORT_CNT_4 0x4UL 2165 #define PORT_PHY_QCAPS_RESP_PORT_CNT_LAST PORT_PHY_QCAPS_RESP_PORT_CNT_4 2166 __le16 supported_speeds_force_mode; 2167 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MBHD 0x1UL 2168 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100MB 0x2UL 2169 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GBHD 0x4UL 2170 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_1GB 0x8UL 2171 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2GB 0x10UL 2172 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_2_5GB 0x20UL 2173 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10GB 0x40UL 2174 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_20GB 0x80UL 2175 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_25GB 0x100UL 2176 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_40GB 0x200UL 2177 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_50GB 0x400UL 2178 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_100GB 0x800UL 2179 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MBHD 0x1000UL 2180 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_FORCE_MODE_10MB 0x2000UL 2181 __le16 supported_speeds_auto_mode; 2182 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MBHD 0x1UL 2183 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100MB 0x2UL 2184 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GBHD 0x4UL 2185 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_1GB 0x8UL 2186 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2GB 0x10UL 2187 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_2_5GB 0x20UL 2188 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10GB 0x40UL 2189 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_20GB 0x80UL 2190 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_25GB 0x100UL 2191 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_40GB 0x200UL 2192 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_50GB 0x400UL 2193 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_100GB 0x800UL 2194 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MBHD 0x1000UL 2195 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_AUTO_MODE_10MB 0x2000UL 2196 __le16 supported_speeds_eee_mode; 2197 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD1 0x1UL 2198 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_100MB 0x2UL 2199 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD2 0x4UL 2200 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_1GB 0x8UL 2201 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD3 0x10UL 2202 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_RSVD4 0x20UL 2203 #define PORT_PHY_QCAPS_RESP_SUPPORTED_SPEEDS_EEE_MODE_10GB 0x40UL 2204 __le32 tx_lpi_timer_low; 2205 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_MASK 0xffffffUL 2206 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_LOW_SFT 0 2207 #define PORT_PHY_QCAPS_RESP_RSVD2_MASK 0xff000000UL 2208 #define PORT_PHY_QCAPS_RESP_RSVD2_SFT 24 2209 __le32 valid_tx_lpi_timer_high; 2210 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_MASK 0xffffffUL 2211 #define PORT_PHY_QCAPS_RESP_TX_LPI_TIMER_HIGH_SFT 0 2212 #define PORT_PHY_QCAPS_RESP_VALID_MASK 0xff000000UL 2213 #define PORT_PHY_QCAPS_RESP_VALID_SFT 24 2214}; 2215 2216/* hwrm_port_phy_i2c_read_input (size:320b/40B) */ 2217struct hwrm_port_phy_i2c_read_input { 2218 __le16 req_type; 2219 __le16 cmpl_ring; 2220 __le16 seq_id; 2221 __le16 target_id; 2222 __le64 resp_addr; 2223 __le32 flags; 2224 __le32 enables; 2225 #define PORT_PHY_I2C_READ_REQ_ENABLES_PAGE_OFFSET 0x1UL 2226 __le16 port_id; 2227 u8 i2c_slave_addr; 2228 u8 unused_0; 2229 __le16 page_number; 2230 __le16 page_offset; 2231 u8 data_length; 2232 u8 unused_1[7]; 2233}; 2234 2235/* hwrm_port_phy_i2c_read_output (size:640b/80B) */ 2236struct hwrm_port_phy_i2c_read_output { 2237 __le16 error_code; 2238 __le16 req_type; 2239 __le16 seq_id; 2240 __le16 resp_len; 2241 __le32 data[16]; 2242 u8 unused_0[7]; 2243 u8 valid; 2244}; 2245 2246/* hwrm_port_led_cfg_input (size:512b/64B) */ 2247struct hwrm_port_led_cfg_input { 2248 __le16 req_type; 2249 __le16 cmpl_ring; 2250 __le16 seq_id; 2251 __le16 target_id; 2252 __le64 resp_addr; 2253 __le32 enables; 2254 #define PORT_LED_CFG_REQ_ENABLES_LED0_ID 0x1UL 2255 #define PORT_LED_CFG_REQ_ENABLES_LED0_STATE 0x2UL 2256 #define PORT_LED_CFG_REQ_ENABLES_LED0_COLOR 0x4UL 2257 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_ON 0x8UL 2258 #define PORT_LED_CFG_REQ_ENABLES_LED0_BLINK_OFF 0x10UL 2259 #define PORT_LED_CFG_REQ_ENABLES_LED0_GROUP_ID 0x20UL 2260 #define PORT_LED_CFG_REQ_ENABLES_LED1_ID 0x40UL 2261 #define PORT_LED_CFG_REQ_ENABLES_LED1_STATE 0x80UL 2262 #define PORT_LED_CFG_REQ_ENABLES_LED1_COLOR 0x100UL 2263 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_ON 0x200UL 2264 #define PORT_LED_CFG_REQ_ENABLES_LED1_BLINK_OFF 0x400UL 2265 #define PORT_LED_CFG_REQ_ENABLES_LED1_GROUP_ID 0x800UL 2266 #define PORT_LED_CFG_REQ_ENABLES_LED2_ID 0x1000UL 2267 #define PORT_LED_CFG_REQ_ENABLES_LED2_STATE 0x2000UL 2268 #define PORT_LED_CFG_REQ_ENABLES_LED2_COLOR 0x4000UL 2269 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_ON 0x8000UL 2270 #define PORT_LED_CFG_REQ_ENABLES_LED2_BLINK_OFF 0x10000UL 2271 #define PORT_LED_CFG_REQ_ENABLES_LED2_GROUP_ID 0x20000UL 2272 #define PORT_LED_CFG_REQ_ENABLES_LED3_ID 0x40000UL 2273 #define PORT_LED_CFG_REQ_ENABLES_LED3_STATE 0x80000UL 2274 #define PORT_LED_CFG_REQ_ENABLES_LED3_COLOR 0x100000UL 2275 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_ON 0x200000UL 2276 #define PORT_LED_CFG_REQ_ENABLES_LED3_BLINK_OFF 0x400000UL 2277 #define PORT_LED_CFG_REQ_ENABLES_LED3_GROUP_ID 0x800000UL 2278 __le16 port_id; 2279 u8 num_leds; 2280 u8 rsvd; 2281 u8 led0_id; 2282 u8 led0_state; 2283 #define PORT_LED_CFG_REQ_LED0_STATE_DEFAULT 0x0UL 2284 #define PORT_LED_CFG_REQ_LED0_STATE_OFF 0x1UL 2285 #define PORT_LED_CFG_REQ_LED0_STATE_ON 0x2UL 2286 #define PORT_LED_CFG_REQ_LED0_STATE_BLINK 0x3UL 2287 #define PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 0x4UL 2288 #define PORT_LED_CFG_REQ_LED0_STATE_LAST PORT_LED_CFG_REQ_LED0_STATE_BLINKALT 2289 u8 led0_color; 2290 #define PORT_LED_CFG_REQ_LED0_COLOR_DEFAULT 0x0UL 2291 #define PORT_LED_CFG_REQ_LED0_COLOR_AMBER 0x1UL 2292 #define PORT_LED_CFG_REQ_LED0_COLOR_GREEN 0x2UL 2293 #define PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 0x3UL 2294 #define PORT_LED_CFG_REQ_LED0_COLOR_LAST PORT_LED_CFG_REQ_LED0_COLOR_GREENAMBER 2295 u8 unused_0; 2296 __le16 led0_blink_on; 2297 __le16 led0_blink_off; 2298 u8 led0_group_id; 2299 u8 rsvd0; 2300 u8 led1_id; 2301 u8 led1_state; 2302 #define PORT_LED_CFG_REQ_LED1_STATE_DEFAULT 0x0UL 2303 #define PORT_LED_CFG_REQ_LED1_STATE_OFF 0x1UL 2304 #define PORT_LED_CFG_REQ_LED1_STATE_ON 0x2UL 2305 #define PORT_LED_CFG_REQ_LED1_STATE_BLINK 0x3UL 2306 #define PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 0x4UL 2307 #define PORT_LED_CFG_REQ_LED1_STATE_LAST PORT_LED_CFG_REQ_LED1_STATE_BLINKALT 2308 u8 led1_color; 2309 #define PORT_LED_CFG_REQ_LED1_COLOR_DEFAULT 0x0UL 2310 #define PORT_LED_CFG_REQ_LED1_COLOR_AMBER 0x1UL 2311 #define PORT_LED_CFG_REQ_LED1_COLOR_GREEN 0x2UL 2312 #define PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 0x3UL 2313 #define PORT_LED_CFG_REQ_LED1_COLOR_LAST PORT_LED_CFG_REQ_LED1_COLOR_GREENAMBER 2314 u8 unused_1; 2315 __le16 led1_blink_on; 2316 __le16 led1_blink_off; 2317 u8 led1_group_id; 2318 u8 rsvd1; 2319 u8 led2_id; 2320 u8 led2_state; 2321 #define PORT_LED_CFG_REQ_LED2_STATE_DEFAULT 0x0UL 2322 #define PORT_LED_CFG_REQ_LED2_STATE_OFF 0x1UL 2323 #define PORT_LED_CFG_REQ_LED2_STATE_ON 0x2UL 2324 #define PORT_LED_CFG_REQ_LED2_STATE_BLINK 0x3UL 2325 #define PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 0x4UL 2326 #define PORT_LED_CFG_REQ_LED2_STATE_LAST PORT_LED_CFG_REQ_LED2_STATE_BLINKALT 2327 u8 led2_color; 2328 #define PORT_LED_CFG_REQ_LED2_COLOR_DEFAULT 0x0UL 2329 #define PORT_LED_CFG_REQ_LED2_COLOR_AMBER 0x1UL 2330 #define PORT_LED_CFG_REQ_LED2_COLOR_GREEN 0x2UL 2331 #define PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 0x3UL 2332 #define PORT_LED_CFG_REQ_LED2_COLOR_LAST PORT_LED_CFG_REQ_LED2_COLOR_GREENAMBER 2333 u8 unused_2; 2334 __le16 led2_blink_on; 2335 __le16 led2_blink_off; 2336 u8 led2_group_id; 2337 u8 rsvd2; 2338 u8 led3_id; 2339 u8 led3_state; 2340 #define PORT_LED_CFG_REQ_LED3_STATE_DEFAULT 0x0UL 2341 #define PORT_LED_CFG_REQ_LED3_STATE_OFF 0x1UL 2342 #define PORT_LED_CFG_REQ_LED3_STATE_ON 0x2UL 2343 #define PORT_LED_CFG_REQ_LED3_STATE_BLINK 0x3UL 2344 #define PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 0x4UL 2345 #define PORT_LED_CFG_REQ_LED3_STATE_LAST PORT_LED_CFG_REQ_LED3_STATE_BLINKALT 2346 u8 led3_color; 2347 #define PORT_LED_CFG_REQ_LED3_COLOR_DEFAULT 0x0UL 2348 #define PORT_LED_CFG_REQ_LED3_COLOR_AMBER 0x1UL 2349 #define PORT_LED_CFG_REQ_LED3_COLOR_GREEN 0x2UL 2350 #define PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 0x3UL 2351 #define PORT_LED_CFG_REQ_LED3_COLOR_LAST PORT_LED_CFG_REQ_LED3_COLOR_GREENAMBER 2352 u8 unused_3; 2353 __le16 led3_blink_on; 2354 __le16 led3_blink_off; 2355 u8 led3_group_id; 2356 u8 rsvd3; 2357}; 2358 2359/* hwrm_port_led_cfg_output (size:128b/16B) */ 2360struct hwrm_port_led_cfg_output { 2361 __le16 error_code; 2362 __le16 req_type; 2363 __le16 seq_id; 2364 __le16 resp_len; 2365 u8 unused_0[7]; 2366 u8 valid; 2367}; 2368 2369/* hwrm_port_led_qcfg_input (size:192b/24B) */ 2370struct hwrm_port_led_qcfg_input { 2371 __le16 req_type; 2372 __le16 cmpl_ring; 2373 __le16 seq_id; 2374 __le16 target_id; 2375 __le64 resp_addr; 2376 __le16 port_id; 2377 u8 unused_0[6]; 2378}; 2379 2380/* hwrm_port_led_qcfg_output (size:448b/56B) */ 2381struct hwrm_port_led_qcfg_output { 2382 __le16 error_code; 2383 __le16 req_type; 2384 __le16 seq_id; 2385 __le16 resp_len; 2386 u8 num_leds; 2387 u8 led0_id; 2388 u8 led0_type; 2389 #define PORT_LED_QCFG_RESP_LED0_TYPE_SPEED 0x0UL 2390 #define PORT_LED_QCFG_RESP_LED0_TYPE_ACTIVITY 0x1UL 2391 #define PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 0xffUL 2392 #define PORT_LED_QCFG_RESP_LED0_TYPE_LAST PORT_LED_QCFG_RESP_LED0_TYPE_INVALID 2393 u8 led0_state; 2394 #define PORT_LED_QCFG_RESP_LED0_STATE_DEFAULT 0x0UL 2395 #define PORT_LED_QCFG_RESP_LED0_STATE_OFF 0x1UL 2396 #define PORT_LED_QCFG_RESP_LED0_STATE_ON 0x2UL 2397 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINK 0x3UL 2398 #define PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 0x4UL 2399 #define PORT_LED_QCFG_RESP_LED0_STATE_LAST PORT_LED_QCFG_RESP_LED0_STATE_BLINKALT 2400 u8 led0_color; 2401 #define PORT_LED_QCFG_RESP_LED0_COLOR_DEFAULT 0x0UL 2402 #define PORT_LED_QCFG_RESP_LED0_COLOR_AMBER 0x1UL 2403 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREEN 0x2UL 2404 #define PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 0x3UL 2405 #define PORT_LED_QCFG_RESP_LED0_COLOR_LAST PORT_LED_QCFG_RESP_LED0_COLOR_GREENAMBER 2406 u8 unused_0; 2407 __le16 led0_blink_on; 2408 __le16 led0_blink_off; 2409 u8 led0_group_id; 2410 u8 led1_id; 2411 u8 led1_type; 2412 #define PORT_LED_QCFG_RESP_LED1_TYPE_SPEED 0x0UL 2413 #define PORT_LED_QCFG_RESP_LED1_TYPE_ACTIVITY 0x1UL 2414 #define PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 0xffUL 2415 #define PORT_LED_QCFG_RESP_LED1_TYPE_LAST PORT_LED_QCFG_RESP_LED1_TYPE_INVALID 2416 u8 led1_state; 2417 #define PORT_LED_QCFG_RESP_LED1_STATE_DEFAULT 0x0UL 2418 #define PORT_LED_QCFG_RESP_LED1_STATE_OFF 0x1UL 2419 #define PORT_LED_QCFG_RESP_LED1_STATE_ON 0x2UL 2420 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINK 0x3UL 2421 #define PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 0x4UL 2422 #define PORT_LED_QCFG_RESP_LED1_STATE_LAST PORT_LED_QCFG_RESP_LED1_STATE_BLINKALT 2423 u8 led1_color; 2424 #define PORT_LED_QCFG_RESP_LED1_COLOR_DEFAULT 0x0UL 2425 #define PORT_LED_QCFG_RESP_LED1_COLOR_AMBER 0x1UL 2426 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREEN 0x2UL 2427 #define PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 0x3UL 2428 #define PORT_LED_QCFG_RESP_LED1_COLOR_LAST PORT_LED_QCFG_RESP_LED1_COLOR_GREENAMBER 2429 u8 unused_1; 2430 __le16 led1_blink_on; 2431 __le16 led1_blink_off; 2432 u8 led1_group_id; 2433 u8 led2_id; 2434 u8 led2_type; 2435 #define PORT_LED_QCFG_RESP_LED2_TYPE_SPEED 0x0UL 2436 #define PORT_LED_QCFG_RESP_LED2_TYPE_ACTIVITY 0x1UL 2437 #define PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 0xffUL 2438 #define PORT_LED_QCFG_RESP_LED2_TYPE_LAST PORT_LED_QCFG_RESP_LED2_TYPE_INVALID 2439 u8 led2_state; 2440 #define PORT_LED_QCFG_RESP_LED2_STATE_DEFAULT 0x0UL 2441 #define PORT_LED_QCFG_RESP_LED2_STATE_OFF 0x1UL 2442 #define PORT_LED_QCFG_RESP_LED2_STATE_ON 0x2UL 2443 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINK 0x3UL 2444 #define PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 0x4UL 2445 #define PORT_LED_QCFG_RESP_LED2_STATE_LAST PORT_LED_QCFG_RESP_LED2_STATE_BLINKALT 2446 u8 led2_color; 2447 #define PORT_LED_QCFG_RESP_LED2_COLOR_DEFAULT 0x0UL 2448 #define PORT_LED_QCFG_RESP_LED2_COLOR_AMBER 0x1UL 2449 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREEN 0x2UL 2450 #define PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 0x3UL 2451 #define PORT_LED_QCFG_RESP_LED2_COLOR_LAST PORT_LED_QCFG_RESP_LED2_COLOR_GREENAMBER 2452 u8 unused_2; 2453 __le16 led2_blink_on; 2454 __le16 led2_blink_off; 2455 u8 led2_group_id; 2456 u8 led3_id; 2457 u8 led3_type; 2458 #define PORT_LED_QCFG_RESP_LED3_TYPE_SPEED 0x0UL 2459 #define PORT_LED_QCFG_RESP_LED3_TYPE_ACTIVITY 0x1UL 2460 #define PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 0xffUL 2461 #define PORT_LED_QCFG_RESP_LED3_TYPE_LAST PORT_LED_QCFG_RESP_LED3_TYPE_INVALID 2462 u8 led3_state; 2463 #define PORT_LED_QCFG_RESP_LED3_STATE_DEFAULT 0x0UL 2464 #define PORT_LED_QCFG_RESP_LED3_STATE_OFF 0x1UL 2465 #define PORT_LED_QCFG_RESP_LED3_STATE_ON 0x2UL 2466 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINK 0x3UL 2467 #define PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 0x4UL 2468 #define PORT_LED_QCFG_RESP_LED3_STATE_LAST PORT_LED_QCFG_RESP_LED3_STATE_BLINKALT 2469 u8 led3_color; 2470 #define PORT_LED_QCFG_RESP_LED3_COLOR_DEFAULT 0x0UL 2471 #define PORT_LED_QCFG_RESP_LED3_COLOR_AMBER 0x1UL 2472 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREEN 0x2UL 2473 #define PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 0x3UL 2474 #define PORT_LED_QCFG_RESP_LED3_COLOR_LAST PORT_LED_QCFG_RESP_LED3_COLOR_GREENAMBER 2475 u8 unused_3; 2476 __le16 led3_blink_on; 2477 __le16 led3_blink_off; 2478 u8 led3_group_id; 2479 u8 unused_4[6]; 2480 u8 valid; 2481}; 2482 2483/* hwrm_port_led_qcaps_input (size:192b/24B) */ 2484struct hwrm_port_led_qcaps_input { 2485 __le16 req_type; 2486 __le16 cmpl_ring; 2487 __le16 seq_id; 2488 __le16 target_id; 2489 __le64 resp_addr; 2490 __le16 port_id; 2491 u8 unused_0[6]; 2492}; 2493 2494/* hwrm_port_led_qcaps_output (size:384b/48B) */ 2495struct hwrm_port_led_qcaps_output { 2496 __le16 error_code; 2497 __le16 req_type; 2498 __le16 seq_id; 2499 __le16 resp_len; 2500 u8 num_leds; 2501 u8 unused[3]; 2502 u8 led0_id; 2503 u8 led0_type; 2504 #define PORT_LED_QCAPS_RESP_LED0_TYPE_SPEED 0x0UL 2505 #define PORT_LED_QCAPS_RESP_LED0_TYPE_ACTIVITY 0x1UL 2506 #define PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 0xffUL 2507 #define PORT_LED_QCAPS_RESP_LED0_TYPE_LAST PORT_LED_QCAPS_RESP_LED0_TYPE_INVALID 2508 u8 led0_group_id; 2509 u8 unused_0; 2510 __le16 led0_state_caps; 2511 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ENABLED 0x1UL 2512 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_OFF_SUPPORTED 0x2UL 2513 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_ON_SUPPORTED 0x4UL 2514 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2515 #define PORT_LED_QCAPS_RESP_LED0_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2516 __le16 led0_color_caps; 2517 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_RSVD 0x1UL 2518 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2519 #define PORT_LED_QCAPS_RESP_LED0_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2520 u8 led1_id; 2521 u8 led1_type; 2522 #define PORT_LED_QCAPS_RESP_LED1_TYPE_SPEED 0x0UL 2523 #define PORT_LED_QCAPS_RESP_LED1_TYPE_ACTIVITY 0x1UL 2524 #define PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 0xffUL 2525 #define PORT_LED_QCAPS_RESP_LED1_TYPE_LAST PORT_LED_QCAPS_RESP_LED1_TYPE_INVALID 2526 u8 led1_group_id; 2527 u8 unused_1; 2528 __le16 led1_state_caps; 2529 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ENABLED 0x1UL 2530 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_OFF_SUPPORTED 0x2UL 2531 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_ON_SUPPORTED 0x4UL 2532 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2533 #define PORT_LED_QCAPS_RESP_LED1_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2534 __le16 led1_color_caps; 2535 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_RSVD 0x1UL 2536 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2537 #define PORT_LED_QCAPS_RESP_LED1_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2538 u8 led2_id; 2539 u8 led2_type; 2540 #define PORT_LED_QCAPS_RESP_LED2_TYPE_SPEED 0x0UL 2541 #define PORT_LED_QCAPS_RESP_LED2_TYPE_ACTIVITY 0x1UL 2542 #define PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 0xffUL 2543 #define PORT_LED_QCAPS_RESP_LED2_TYPE_LAST PORT_LED_QCAPS_RESP_LED2_TYPE_INVALID 2544 u8 led2_group_id; 2545 u8 unused_2; 2546 __le16 led2_state_caps; 2547 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ENABLED 0x1UL 2548 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_OFF_SUPPORTED 0x2UL 2549 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_ON_SUPPORTED 0x4UL 2550 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2551 #define PORT_LED_QCAPS_RESP_LED2_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2552 __le16 led2_color_caps; 2553 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_RSVD 0x1UL 2554 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2555 #define PORT_LED_QCAPS_RESP_LED2_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2556 u8 led3_id; 2557 u8 led3_type; 2558 #define PORT_LED_QCAPS_RESP_LED3_TYPE_SPEED 0x0UL 2559 #define PORT_LED_QCAPS_RESP_LED3_TYPE_ACTIVITY 0x1UL 2560 #define PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 0xffUL 2561 #define PORT_LED_QCAPS_RESP_LED3_TYPE_LAST PORT_LED_QCAPS_RESP_LED3_TYPE_INVALID 2562 u8 led3_group_id; 2563 u8 unused_3; 2564 __le16 led3_state_caps; 2565 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ENABLED 0x1UL 2566 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_OFF_SUPPORTED 0x2UL 2567 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_ON_SUPPORTED 0x4UL 2568 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_SUPPORTED 0x8UL 2569 #define PORT_LED_QCAPS_RESP_LED3_STATE_CAPS_BLINK_ALT_SUPPORTED 0x10UL 2570 __le16 led3_color_caps; 2571 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_RSVD 0x1UL 2572 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_AMBER_SUPPORTED 0x2UL 2573 #define PORT_LED_QCAPS_RESP_LED3_COLOR_CAPS_GREEN_SUPPORTED 0x4UL 2574 u8 unused_4[3]; 2575 u8 valid; 2576}; 2577 2578/* hwrm_queue_qportcfg_input (size:192b/24B) */ 2579struct hwrm_queue_qportcfg_input { 2580 __le16 req_type; 2581 __le16 cmpl_ring; 2582 __le16 seq_id; 2583 __le16 target_id; 2584 __le64 resp_addr; 2585 __le32 flags; 2586 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH 0x1UL 2587 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_TX 0x0UL 2588 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 0x1UL 2589 #define QUEUE_QPORTCFG_REQ_FLAGS_PATH_LAST QUEUE_QPORTCFG_REQ_FLAGS_PATH_RX 2590 __le16 port_id; 2591 u8 drv_qmap_cap; 2592 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_DISABLED 0x0UL 2593 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 0x1UL 2594 #define QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_LAST QUEUE_QPORTCFG_REQ_DRV_QMAP_CAP_ENABLED 2595 u8 unused_0; 2596}; 2597 2598/* hwrm_queue_qportcfg_output (size:256b/32B) */ 2599struct hwrm_queue_qportcfg_output { 2600 __le16 error_code; 2601 __le16 req_type; 2602 __le16 seq_id; 2603 __le16 resp_len; 2604 u8 max_configurable_queues; 2605 u8 max_configurable_lossless_queues; 2606 u8 queue_cfg_allowed; 2607 u8 queue_cfg_info; 2608 #define QUEUE_QPORTCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2609 u8 queue_pfcenable_cfg_allowed; 2610 u8 queue_pri2cos_cfg_allowed; 2611 u8 queue_cos2bw_cfg_allowed; 2612 u8 queue_id0; 2613 u8 queue_id0_service_profile; 2614 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY 0x0UL 2615 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2616 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2617 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2618 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 0xffUL 2619 #define QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID0_SERVICE_PROFILE_UNKNOWN 2620 u8 queue_id1; 2621 u8 queue_id1_service_profile; 2622 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY 0x0UL 2623 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2624 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2625 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2626 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 0xffUL 2627 #define QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID1_SERVICE_PROFILE_UNKNOWN 2628 u8 queue_id2; 2629 u8 queue_id2_service_profile; 2630 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY 0x0UL 2631 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2632 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2633 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2634 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 0xffUL 2635 #define QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID2_SERVICE_PROFILE_UNKNOWN 2636 u8 queue_id3; 2637 u8 queue_id3_service_profile; 2638 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY 0x0UL 2639 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2640 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2641 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2642 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 0xffUL 2643 #define QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID3_SERVICE_PROFILE_UNKNOWN 2644 u8 queue_id4; 2645 u8 queue_id4_service_profile; 2646 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY 0x0UL 2647 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2648 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2649 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2650 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 0xffUL 2651 #define QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID4_SERVICE_PROFILE_UNKNOWN 2652 u8 queue_id5; 2653 u8 queue_id5_service_profile; 2654 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY 0x0UL 2655 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2656 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2657 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2658 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 0xffUL 2659 #define QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID5_SERVICE_PROFILE_UNKNOWN 2660 u8 queue_id6; 2661 u8 queue_id6_service_profile; 2662 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY 0x0UL 2663 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2664 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2665 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2666 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 0xffUL 2667 #define QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID6_SERVICE_PROFILE_UNKNOWN 2668 u8 queue_id7; 2669 u8 queue_id7_service_profile; 2670 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY 0x0UL 2671 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_ROCE 0x1UL 2672 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSY_ROCE_CNP 0x2UL 2673 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LOSSLESS_NIC 0x3UL 2674 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 0xffUL 2675 #define QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_LAST QUEUE_QPORTCFG_RESP_QUEUE_ID7_SERVICE_PROFILE_UNKNOWN 2676 u8 valid; 2677}; 2678 2679/* hwrm_queue_cfg_input (size:320b/40B) */ 2680struct hwrm_queue_cfg_input { 2681 __le16 req_type; 2682 __le16 cmpl_ring; 2683 __le16 seq_id; 2684 __le16 target_id; 2685 __le64 resp_addr; 2686 __le32 flags; 2687 #define QUEUE_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2688 #define QUEUE_CFG_REQ_FLAGS_PATH_SFT 0 2689 #define QUEUE_CFG_REQ_FLAGS_PATH_TX 0x0UL 2690 #define QUEUE_CFG_REQ_FLAGS_PATH_RX 0x1UL 2691 #define QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2692 #define QUEUE_CFG_REQ_FLAGS_PATH_LAST QUEUE_CFG_REQ_FLAGS_PATH_BIDIR 2693 __le32 enables; 2694 #define QUEUE_CFG_REQ_ENABLES_DFLT_LEN 0x1UL 2695 #define QUEUE_CFG_REQ_ENABLES_SERVICE_PROFILE 0x2UL 2696 __le32 queue_id; 2697 __le32 dflt_len; 2698 u8 service_profile; 2699 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSY 0x0UL 2700 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LOSSLESS 0x1UL 2701 #define QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 0xffUL 2702 #define QUEUE_CFG_REQ_SERVICE_PROFILE_LAST QUEUE_CFG_REQ_SERVICE_PROFILE_UNKNOWN 2703 u8 unused_0[7]; 2704}; 2705 2706/* hwrm_queue_cfg_output (size:128b/16B) */ 2707struct hwrm_queue_cfg_output { 2708 __le16 error_code; 2709 __le16 req_type; 2710 __le16 seq_id; 2711 __le16 resp_len; 2712 u8 unused_0[7]; 2713 u8 valid; 2714}; 2715 2716/* hwrm_queue_pfcenable_qcfg_input (size:192b/24B) */ 2717struct hwrm_queue_pfcenable_qcfg_input { 2718 __le16 req_type; 2719 __le16 cmpl_ring; 2720 __le16 seq_id; 2721 __le16 target_id; 2722 __le64 resp_addr; 2723 __le16 port_id; 2724 u8 unused_0[6]; 2725}; 2726 2727/* hwrm_queue_pfcenable_qcfg_output (size:128b/16B) */ 2728struct hwrm_queue_pfcenable_qcfg_output { 2729 __le16 error_code; 2730 __le16 req_type; 2731 __le16 seq_id; 2732 __le16 resp_len; 2733 __le32 flags; 2734 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI0_PFC_ENABLED 0x1UL 2735 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI1_PFC_ENABLED 0x2UL 2736 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI2_PFC_ENABLED 0x4UL 2737 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI3_PFC_ENABLED 0x8UL 2738 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI4_PFC_ENABLED 0x10UL 2739 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI5_PFC_ENABLED 0x20UL 2740 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI6_PFC_ENABLED 0x40UL 2741 #define QUEUE_PFCENABLE_QCFG_RESP_FLAGS_PRI7_PFC_ENABLED 0x80UL 2742 u8 unused_0[3]; 2743 u8 valid; 2744}; 2745 2746/* hwrm_queue_pfcenable_cfg_input (size:192b/24B) */ 2747struct hwrm_queue_pfcenable_cfg_input { 2748 __le16 req_type; 2749 __le16 cmpl_ring; 2750 __le16 seq_id; 2751 __le16 target_id; 2752 __le64 resp_addr; 2753 __le32 flags; 2754 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI0_PFC_ENABLED 0x1UL 2755 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI1_PFC_ENABLED 0x2UL 2756 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI2_PFC_ENABLED 0x4UL 2757 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI3_PFC_ENABLED 0x8UL 2758 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI4_PFC_ENABLED 0x10UL 2759 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI5_PFC_ENABLED 0x20UL 2760 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI6_PFC_ENABLED 0x40UL 2761 #define QUEUE_PFCENABLE_CFG_REQ_FLAGS_PRI7_PFC_ENABLED 0x80UL 2762 __le16 port_id; 2763 u8 unused_0[2]; 2764}; 2765 2766/* hwrm_queue_pfcenable_cfg_output (size:128b/16B) */ 2767struct hwrm_queue_pfcenable_cfg_output { 2768 __le16 error_code; 2769 __le16 req_type; 2770 __le16 seq_id; 2771 __le16 resp_len; 2772 u8 unused_0[7]; 2773 u8 valid; 2774}; 2775 2776/* hwrm_queue_pri2cos_qcfg_input (size:192b/24B) */ 2777struct hwrm_queue_pri2cos_qcfg_input { 2778 __le16 req_type; 2779 __le16 cmpl_ring; 2780 __le16 seq_id; 2781 __le16 target_id; 2782 __le64 resp_addr; 2783 __le32 flags; 2784 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH 0x1UL 2785 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_TX 0x0UL 2786 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 0x1UL 2787 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_QCFG_REQ_FLAGS_PATH_RX 2788 #define QUEUE_PRI2COS_QCFG_REQ_FLAGS_IVLAN 0x2UL 2789 u8 port_id; 2790 u8 unused_0[3]; 2791}; 2792 2793/* hwrm_queue_pri2cos_qcfg_output (size:192b/24B) */ 2794struct hwrm_queue_pri2cos_qcfg_output { 2795 __le16 error_code; 2796 __le16 req_type; 2797 __le16 seq_id; 2798 __le16 resp_len; 2799 u8 pri0_cos_queue_id; 2800 u8 pri1_cos_queue_id; 2801 u8 pri2_cos_queue_id; 2802 u8 pri3_cos_queue_id; 2803 u8 pri4_cos_queue_id; 2804 u8 pri5_cos_queue_id; 2805 u8 pri6_cos_queue_id; 2806 u8 pri7_cos_queue_id; 2807 u8 queue_cfg_info; 2808 #define QUEUE_PRI2COS_QCFG_RESP_QUEUE_CFG_INFO_ASYM_CFG 0x1UL 2809 u8 unused_0[6]; 2810 u8 valid; 2811}; 2812 2813/* hwrm_queue_pri2cos_cfg_input (size:320b/40B) */ 2814struct hwrm_queue_pri2cos_cfg_input { 2815 __le16 req_type; 2816 __le16 cmpl_ring; 2817 __le16 seq_id; 2818 __le16 target_id; 2819 __le64 resp_addr; 2820 __le32 flags; 2821 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_MASK 0x3UL 2822 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_SFT 0 2823 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_TX 0x0UL 2824 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_RX 0x1UL 2825 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 0x2UL 2826 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_LAST QUEUE_PRI2COS_CFG_REQ_FLAGS_PATH_BIDIR 2827 #define QUEUE_PRI2COS_CFG_REQ_FLAGS_IVLAN 0x4UL 2828 __le32 enables; 2829 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI0_COS_QUEUE_ID 0x1UL 2830 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI1_COS_QUEUE_ID 0x2UL 2831 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI2_COS_QUEUE_ID 0x4UL 2832 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI3_COS_QUEUE_ID 0x8UL 2833 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI4_COS_QUEUE_ID 0x10UL 2834 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI5_COS_QUEUE_ID 0x20UL 2835 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI6_COS_QUEUE_ID 0x40UL 2836 #define QUEUE_PRI2COS_CFG_REQ_ENABLES_PRI7_COS_QUEUE_ID 0x80UL 2837 u8 port_id; 2838 u8 pri0_cos_queue_id; 2839 u8 pri1_cos_queue_id; 2840 u8 pri2_cos_queue_id; 2841 u8 pri3_cos_queue_id; 2842 u8 pri4_cos_queue_id; 2843 u8 pri5_cos_queue_id; 2844 u8 pri6_cos_queue_id; 2845 u8 pri7_cos_queue_id; 2846 u8 unused_0[7]; 2847}; 2848 2849/* hwrm_queue_pri2cos_cfg_output (size:128b/16B) */ 2850struct hwrm_queue_pri2cos_cfg_output { 2851 __le16 error_code; 2852 __le16 req_type; 2853 __le16 seq_id; 2854 __le16 resp_len; 2855 u8 unused_0[7]; 2856 u8 valid; 2857}; 2858 2859/* hwrm_queue_cos2bw_qcfg_input (size:192b/24B) */ 2860struct hwrm_queue_cos2bw_qcfg_input { 2861 __le16 req_type; 2862 __le16 cmpl_ring; 2863 __le16 seq_id; 2864 __le16 target_id; 2865 __le64 resp_addr; 2866 __le16 port_id; 2867 u8 unused_0[6]; 2868}; 2869 2870/* hwrm_queue_cos2bw_qcfg_output (size:896b/112B) */ 2871struct hwrm_queue_cos2bw_qcfg_output { 2872 __le16 error_code; 2873 __le16 req_type; 2874 __le16 seq_id; 2875 __le16 resp_len; 2876 u8 queue_id0; 2877 u8 unused_0; 2878 __le16 unused_1; 2879 __le32 queue_id0_min_bw; 2880 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2881 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 2882 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 2883 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 2884 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 2885 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_SCALE_BYTES 2886 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2887 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 2888 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2889 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2890 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2891 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2892 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2893 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2894 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 2895 __le32 queue_id0_max_bw; 2896 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2897 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 2898 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 2899 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 2900 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 2901 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_SCALE_BYTES 2902 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2903 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 2904 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2905 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2906 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2907 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2908 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2909 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2910 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 2911 u8 queue_id0_tsa_assign; 2912 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 2913 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 2914 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2915 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 2916 u8 queue_id0_pri_lvl; 2917 u8 queue_id0_bw_weight; 2918 u8 queue_id1; 2919 __le32 queue_id1_min_bw; 2920 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2921 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 2922 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 2923 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 2924 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 2925 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_SCALE_BYTES 2926 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2927 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 2928 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2929 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2930 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2931 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2932 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2933 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2934 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 2935 __le32 queue_id1_max_bw; 2936 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2937 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 2938 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 2939 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 2940 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 2941 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_SCALE_BYTES 2942 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2943 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 2944 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2945 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2946 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2947 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2948 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2949 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2950 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 2951 u8 queue_id1_tsa_assign; 2952 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 2953 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 2954 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2955 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 2956 u8 queue_id1_pri_lvl; 2957 u8 queue_id1_bw_weight; 2958 u8 queue_id2; 2959 __le32 queue_id2_min_bw; 2960 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 2961 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 2962 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 2963 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 2964 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 2965 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_SCALE_BYTES 2966 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2967 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 2968 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2969 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2970 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2971 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2972 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2973 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2974 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 2975 __le32 queue_id2_max_bw; 2976 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 2977 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 2978 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 2979 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 2980 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 2981 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_SCALE_BYTES 2982 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 2983 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 2984 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 2985 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 2986 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 2987 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 2988 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 2989 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 2990 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 2991 u8 queue_id2_tsa_assign; 2992 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 2993 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 2994 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 2995 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 2996 u8 queue_id2_pri_lvl; 2997 u8 queue_id2_bw_weight; 2998 u8 queue_id3; 2999 __le32 queue_id3_min_bw; 3000 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL
3001 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3002 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3003 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3004 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3005 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_SCALE_BYTES 3006 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3007 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3008 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3009 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3010 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3011 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3012 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3013 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3014 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3015 __le32 queue_id3_max_bw; 3016 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3017 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3018 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3019 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3020 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3021 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_SCALE_BYTES 3022 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3023 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3024 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3025 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3026 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3027 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3028 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3029 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3030 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3031 u8 queue_id3_tsa_assign; 3032 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3033 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3034 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3035 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3036 u8 queue_id3_pri_lvl; 3037 u8 queue_id3_bw_weight; 3038 u8 queue_id4; 3039 __le32 queue_id4_min_bw; 3040 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3041 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3042 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3043 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3044 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3045 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_SCALE_BYTES 3046 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3047 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3048 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3049 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3050 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3051 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3052 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3053 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3054 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3055 __le32 queue_id4_max_bw; 3056 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3057 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3058 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3059 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3060 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3061 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_SCALE_BYTES 3062 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3063 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3064 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3065 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3066 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3067 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3068 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3069 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3070 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3071 u8 queue_id4_tsa_assign; 3072 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3073 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3074 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3075 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3076 u8 queue_id4_pri_lvl; 3077 u8 queue_id4_bw_weight; 3078 u8 queue_id5; 3079 __le32 queue_id5_min_bw; 3080 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3081 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3082 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3083 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3084 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3085 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_SCALE_BYTES 3086 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3087 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3088 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3089 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3090 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3091 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3092 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3093 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3094 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3095 __le32 queue_id5_max_bw; 3096 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3097 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3098 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3099 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3100 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3101 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_SCALE_BYTES 3102 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3103 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3104 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3105 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3106 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3107 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3108 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3109 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3110 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3111 u8 queue_id5_tsa_assign; 3112 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3113 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3114 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3115 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3116 u8 queue_id5_pri_lvl; 3117 u8 queue_id5_bw_weight; 3118 u8 queue_id6; 3119 __le32 queue_id6_min_bw; 3120 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3121 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3122 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3123 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3124 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3125 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_SCALE_BYTES 3126 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3127 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3128 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3129 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3130 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3131 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3132 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3133 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3134 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3135 __le32 queue_id6_max_bw; 3136 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3137 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3138 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3139 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3140 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3141 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_SCALE_BYTES 3142 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3143 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3144 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3145 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3146 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3147 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3148 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3149 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3150 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3151 u8 queue_id6_tsa_assign; 3152 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3153 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3154 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3155 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3156 u8 queue_id6_pri_lvl; 3157 u8 queue_id6_bw_weight; 3158 u8 queue_id7; 3159 __le32 queue_id7_min_bw; 3160 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3161 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3162 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3163 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3164 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3165 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_SCALE_BYTES 3166 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3167 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3168 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3169 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3170 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3171 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3172 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3173 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3174 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3175 __le32 queue_id7_max_bw; 3176 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3177 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3178 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3179 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3180 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3181 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_SCALE_BYTES 3182 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3183 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3184 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3185 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3186 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3187 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3188 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3189 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3190 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3191 u8 queue_id7_tsa_assign; 3192 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3193 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3194 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3195 #define QUEUE_COS2BW_QCFG_RESP_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3196 u8 queue_id7_pri_lvl; 3197 u8 queue_id7_bw_weight; 3198 u8 unused_2[4]; 3199 u8 valid; 3200}; 3201 3202/* hwrm_queue_cos2bw_cfg_input (size:1024b/128B) */ 3203struct hwrm_queue_cos2bw_cfg_input { 3204 __le16 req_type; 3205 __le16 cmpl_ring; 3206 __le16 seq_id; 3207 __le16 target_id; 3208 __le64 resp_addr; 3209 __le32 flags; 3210 __le32 enables; 3211 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID0_VALID 0x1UL 3212 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID1_VALID 0x2UL 3213 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID2_VALID 0x4UL 3214 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID3_VALID 0x8UL 3215 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID4_VALID 0x10UL 3216 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID5_VALID 0x20UL 3217 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID6_VALID 0x40UL 3218 #define QUEUE_COS2BW_CFG_REQ_ENABLES_COS_QUEUE_ID7_VALID 0x80UL 3219 __le16 port_id; 3220 u8 queue_id0; 3221 u8 unused_0; 3222 __le32 queue_id0_min_bw; 3223 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3224 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_SFT 0 3225 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE 0x10000000UL 3226 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BITS (0x0UL << 28) 3227 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES (0x1UL << 28) 3228 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_SCALE_BYTES 3229 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3230 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_SFT 29 3231 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3232 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3233 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3234 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3235 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3236 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3237 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MIN_BW_BW_VALUE_UNIT_INVALID 3238 __le32 queue_id0_max_bw; 3239 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3240 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_SFT 0 3241 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE 0x10000000UL 3242 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BITS (0x0UL << 28) 3243 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES (0x1UL << 28) 3244 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_SCALE_BYTES 3245 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3246 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_SFT 29 3247 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3248 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3249 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3250 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3251 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3252 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3253 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_MAX_BW_BW_VALUE_UNIT_INVALID 3254 u8 queue_id0_tsa_assign; 3255 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_SP 0x0UL 3256 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_ETS 0x1UL 3257 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3258 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID0_TSA_ASSIGN_RESERVED_LAST 0xffUL 3259 u8 queue_id0_pri_lvl; 3260 u8 queue_id0_bw_weight; 3261 u8 queue_id1; 3262 __le32 queue_id1_min_bw; 3263 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3264 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_SFT 0 3265 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE 0x10000000UL 3266 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BITS (0x0UL << 28) 3267 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES (0x1UL << 28) 3268 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_SCALE_BYTES 3269 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3270 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_SFT 29 3271 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3272 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3273 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3274 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3275 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3276 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3277 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MIN_BW_BW_VALUE_UNIT_INVALID 3278 __le32 queue_id1_max_bw; 3279 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3280 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_SFT 0 3281 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE 0x10000000UL 3282 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BITS (0x0UL << 28) 3283 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES (0x1UL << 28) 3284 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_SCALE_BYTES 3285 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3286 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_SFT 29 3287 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3288 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3289 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3290 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3291 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3292 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3293 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_MAX_BW_BW_VALUE_UNIT_INVALID 3294 u8 queue_id1_tsa_assign; 3295 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_SP 0x0UL 3296 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_ETS 0x1UL 3297 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3298 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID1_TSA_ASSIGN_RESERVED_LAST 0xffUL 3299 u8 queue_id1_pri_lvl; 3300 u8 queue_id1_bw_weight; 3301 u8 queue_id2; 3302 __le32 queue_id2_min_bw; 3303 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3304 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_SFT 0 3305 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE 0x10000000UL 3306 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BITS (0x0UL << 28) 3307 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES (0x1UL << 28) 3308 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_SCALE_BYTES 3309 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3310 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_SFT 29 3311 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3312 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3313 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3314 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3315 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3316 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3317 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MIN_BW_BW_VALUE_UNIT_INVALID 3318 __le32 queue_id2_max_bw; 3319 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3320 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_SFT 0 3321 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE 0x10000000UL 3322 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BITS (0x0UL << 28) 3323 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES (0x1UL << 28) 3324 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_SCALE_BYTES 3325 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3326 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_SFT 29 3327 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3328 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3329 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3330 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3331 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3332 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3333 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_MAX_BW_BW_VALUE_UNIT_INVALID 3334 u8 queue_id2_tsa_assign; 3335 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_SP 0x0UL 3336 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_ETS 0x1UL 3337 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3338 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID2_TSA_ASSIGN_RESERVED_LAST 0xffUL 3339 u8 queue_id2_pri_lvl; 3340 u8 queue_id2_bw_weight; 3341 u8 queue_id3; 3342 __le32 queue_id3_min_bw; 3343 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3344 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_SFT 0 3345 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE 0x10000000UL 3346 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BITS (0x0UL << 28) 3347 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES (0x1UL << 28) 3348 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_SCALE_BYTES 3349 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3350 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_SFT 29 3351 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3352 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3353 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3354 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3355 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3356 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3357 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MIN_BW_BW_VALUE_UNIT_INVALID 3358 __le32 queue_id3_max_bw; 3359 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3360 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_SFT 0 3361 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE 0x10000000UL 3362 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BITS (0x0UL << 28) 3363 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES (0x1UL << 28) 3364 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_SCALE_BYTES 3365 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3366 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_SFT 29 3367 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3368 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3369 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3370 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3371 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3372 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3373 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_MAX_BW_BW_VALUE_UNIT_INVALID 3374 u8 queue_id3_tsa_assign; 3375 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_SP 0x0UL 3376 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_ETS 0x1UL 3377 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3378 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID3_TSA_ASSIGN_RESERVED_LAST 0xffUL 3379 u8 queue_id3_pri_lvl; 3380 u8 queue_id3_bw_weight; 3381 u8 queue_id4; 3382 __le32 queue_id4_min_bw; 3383 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3384 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_SFT 0 3385 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE 0x10000000UL 3386 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BITS (0x0UL << 28) 3387 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES (0x1UL << 28) 3388 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_SCALE_BYTES 3389 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3390 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_SFT 29 3391 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3392 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3393 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3394 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3395 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3396 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3397 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MIN_BW_BW_VALUE_UNIT_INVALID 3398 __le32 queue_id4_max_bw; 3399 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3400 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_SFT 0 3401 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE 0x10000000UL 3402 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BITS (0x0UL << 28) 3403 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES (0x1UL << 28) 3404 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_SCALE_BYTES 3405 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3406 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_SFT 29 3407 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3408 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3409 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3410 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3411 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3412 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3413 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_MAX_BW_BW_VALUE_UNIT_INVALID 3414 u8 queue_id4_tsa_assign; 3415 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_SP 0x0UL 3416 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_ETS 0x1UL 3417 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3418 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID4_TSA_ASSIGN_RESERVED_LAST 0xffUL 3419 u8 queue_id4_pri_lvl; 3420 u8 queue_id4_bw_weight; 3421 u8 queue_id5; 3422 __le32 queue_id5_min_bw; 3423 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3424 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_SFT 0 3425 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE 0x10000000UL 3426 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BITS (0x0UL << 28) 3427 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES (0x1UL << 28) 3428 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_SCALE_BYTES 3429 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3430 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_SFT 29 3431 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3432 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3433 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3434 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3435 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3436 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3437 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MIN_BW_BW_VALUE_UNIT_INVALID 3438 __le32 queue_id5_max_bw; 3439 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3440 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_SFT 0 3441 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE 0x10000000UL 3442 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BITS (0x0UL << 28) 3443 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES (0x1UL << 28) 3444 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_SCALE_BYTES 3445 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3446 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_SFT 29 3447 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3448 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3449 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3450 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3451 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3452 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3453 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_MAX_BW_BW_VALUE_UNIT_INVALID 3454 u8 queue_id5_tsa_assign; 3455 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_SP 0x0UL 3456 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_ETS 0x1UL 3457 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3458 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID5_TSA_ASSIGN_RESERVED_LAST 0xffUL 3459 u8 queue_id5_pri_lvl; 3460 u8 queue_id5_bw_weight; 3461 u8 queue_id6; 3462 __le32 queue_id6_min_bw; 3463 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3464 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_SFT 0 3465 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE 0x10000000UL 3466 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BITS (0x0UL << 28) 3467 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES (0x1UL << 28) 3468 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_SCALE_BYTES 3469 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3470 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_SFT 29 3471 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3472 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3473 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3474 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3475 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3476 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3477 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MIN_BW_BW_VALUE_UNIT_INVALID 3478 __le32 queue_id6_max_bw; 3479 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3480 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_SFT 0 3481 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE 0x10000000UL 3482 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BITS (0x0UL << 28) 3483 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES (0x1UL << 28) 3484 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_SCALE_BYTES 3485 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3486 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_SFT 29 3487 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3488 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3489 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3490 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3491 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3492 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3493 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_MAX_BW_BW_VALUE_UNIT_INVALID 3494 u8 queue_id6_tsa_assign; 3495 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_SP 0x0UL 3496 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_ETS 0x1UL 3497 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3498 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID6_TSA_ASSIGN_RESERVED_LAST 0xffUL 3499 u8 queue_id6_pri_lvl; 3500 u8 queue_id6_bw_weight; 3501 u8 queue_id7; 3502 __le32 queue_id7_min_bw; 3503 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_MASK 0xfffffffUL 3504 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_SFT 0 3505 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE 0x10000000UL 3506 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BITS (0x0UL << 28) 3507 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES (0x1UL << 28) 3508 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_SCALE_BYTES 3509 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3510 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_SFT 29 3511 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3512 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3513 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3514 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3515 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3516 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3517 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MIN_BW_BW_VALUE_UNIT_INVALID 3518 __le32 queue_id7_max_bw; 3519 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3520 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_SFT 0 3521 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE 0x10000000UL 3522 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BITS (0x0UL << 28) 3523 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES (0x1UL << 28) 3524 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_SCALE_BYTES 3525 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 3526 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_SFT 29 3527 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 3528 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 3529 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 3530 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 3531 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 3532 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 3533 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_LAST QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_MAX_BW_BW_VALUE_UNIT_INVALID 3534 u8 queue_id7_tsa_assign; 3535 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_SP 0x0UL 3536 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_ETS 0x1UL 3537 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_FIRST 0x2UL 3538 #define QUEUE_COS2BW_CFG_REQ_QUEUE_ID7_TSA_ASSIGN_RESERVED_LAST 0xffUL 3539 u8 queue_id7_pri_lvl; 3540 u8 queue_id7_bw_weight; 3541 u8 unused_1[5]; 3542}; 3543 3544/* hwrm_queue_cos2bw_cfg_output (size:128b/16B) */ 3545struct hwrm_queue_cos2bw_cfg_output { 3546 __le16 error_code; 3547 __le16 req_type; 3548 __le16 seq_id; 3549 __le16 resp_len; 3550 u8 unused_0[7]; 3551 u8 valid; 3552}; 3553 3554/* hwrm_queue_dscp_qcaps_input (size:192b/24B) */ 3555struct hwrm_queue_dscp_qcaps_input { 3556 __le16 req_type; 3557 __le16 cmpl_ring; 3558 __le16 seq_id; 3559 __le16 target_id; 3560 __le64 resp_addr; 3561 u8 port_id; 3562 u8 unused_0[7]; 3563}; 3564 3565/* hwrm_queue_dscp_qcaps_output (size:128b/16B) */ 3566struct hwrm_queue_dscp_qcaps_output { 3567 __le16 error_code; 3568 __le16 req_type; 3569 __le16 seq_id; 3570 __le16 resp_len; 3571 u8 num_dscp_bits; 3572 u8 unused_0; 3573 __le16 max_entries; 3574 u8 unused_1[3]; 3575 u8 valid; 3576}; 3577 3578/* hwrm_queue_dscp2pri_qcfg_input (size:256b/32B) */ 3579struct hwrm_queue_dscp2pri_qcfg_input { 3580 __le16 req_type; 3581 __le16 cmpl_ring; 3582 __le16 seq_id; 3583 __le16 target_id; 3584 __le64 resp_addr; 3585 __le64 dest_data_addr; 3586 u8 port_id; 3587 u8 unused_0; 3588 __le16 dest_data_buffer_size; 3589 u8 unused_1[4]; 3590}; 3591 3592/* hwrm_queue_dscp2pri_qcfg_output (size:128b/16B) */ 3593struct hwrm_queue_dscp2pri_qcfg_output { 3594 __le16 error_code; 3595 __le16 req_type; 3596 __le16 seq_id; 3597 __le16 resp_len; 3598 __le16 entry_cnt; 3599 u8 default_pri; 3600 u8 unused_0[4]; 3601 u8 valid; 3602}; 3603 3604/* hwrm_queue_dscp2pri_cfg_input (size:320b/40B) */ 3605struct hwrm_queue_dscp2pri_cfg_input { 3606 __le16 req_type; 3607 __le16 cmpl_ring; 3608 __le16 seq_id; 3609 __le16 target_id; 3610 __le64 resp_addr; 3611 __le64 src_data_addr; 3612 __le32 flags; 3613 #define QUEUE_DSCP2PRI_CFG_REQ_FLAGS_USE_HW_DEFAULT_PRI 0x1UL 3614 __le32 enables; 3615 #define QUEUE_DSCP2PRI_CFG_REQ_ENABLES_DEFAULT_PRI 0x1UL 3616 u8 port_id; 3617 u8 default_pri; 3618 __le16 entry_cnt; 3619 u8 unused_0[4]; 3620}; 3621 3622/* hwrm_queue_dscp2pri_cfg_output (size:128b/16B) */ 3623struct hwrm_queue_dscp2pri_cfg_output { 3624 __le16 error_code; 3625 __le16 req_type; 3626 __le16 seq_id; 3627 __le16 resp_len; 3628 u8 unused_0[7]; 3629 u8 valid; 3630}; 3631 3632/* hwrm_vnic_alloc_input (size:192b/24B) */ 3633struct hwrm_vnic_alloc_input { 3634 __le16 req_type; 3635 __le16 cmpl_ring; 3636 __le16 seq_id; 3637 __le16 target_id; 3638 __le64 resp_addr; 3639 __le32 flags; 3640 #define VNIC_ALLOC_REQ_FLAGS_DEFAULT 0x1UL 3641 u8 unused_0[4]; 3642}; 3643 3644/* hwrm_vnic_alloc_output (size:128b/16B) */ 3645struct hwrm_vnic_alloc_output { 3646 __le16 error_code; 3647 __le16 req_type; 3648 __le16 seq_id; 3649 __le16 resp_len; 3650 __le32 vnic_id; 3651 u8 unused_0[3]; 3652 u8 valid; 3653}; 3654 3655/* hwrm_vnic_free_input (size:192b/24B) */ 3656struct hwrm_vnic_free_input { 3657 __le16 req_type; 3658 __le16 cmpl_ring; 3659 __le16 seq_id; 3660 __le16 target_id; 3661 __le64 resp_addr; 3662 __le32 vnic_id; 3663 u8 unused_0[4]; 3664}; 3665 3666/* hwrm_vnic_free_output (size:128b/16B) */ 3667struct hwrm_vnic_free_output { 3668 __le16 error_code; 3669 __le16 req_type; 3670 __le16 seq_id; 3671 __le16 resp_len; 3672 u8 unused_0[7]; 3673 u8 valid; 3674}; 3675 3676/* hwrm_vnic_cfg_input (size:320b/40B) */ 3677struct hwrm_vnic_cfg_input { 3678 __le16 req_type; 3679 __le16 cmpl_ring; 3680 __le16 seq_id; 3681 __le16 target_id; 3682 __le64 resp_addr; 3683 __le32 flags; 3684 #define VNIC_CFG_REQ_FLAGS_DEFAULT 0x1UL 3685 #define VNIC_CFG_REQ_FLAGS_VLAN_STRIP_MODE 0x2UL 3686 #define VNIC_CFG_REQ_FLAGS_BD_STALL_MODE 0x4UL 3687 #define VNIC_CFG_REQ_FLAGS_ROCE_DUAL_VNIC_MODE 0x8UL 3688 #define VNIC_CFG_REQ_FLAGS_ROCE_ONLY_VNIC_MODE 0x10UL 3689 #define VNIC_CFG_REQ_FLAGS_RSS_DFLT_CR_MODE 0x20UL 3690 #define VNIC_CFG_REQ_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_MODE 0x40UL 3691 __le32 enables; 3692 #define VNIC_CFG_REQ_ENABLES_DFLT_RING_GRP 0x1UL 3693 #define VNIC_CFG_REQ_ENABLES_RSS_RULE 0x2UL 3694 #define VNIC_CFG_REQ_ENABLES_COS_RULE 0x4UL 3695 #define VNIC_CFG_REQ_ENABLES_LB_RULE 0x8UL 3696 #define VNIC_CFG_REQ_ENABLES_MRU 0x10UL 3697 __le16 vnic_id; 3698 __le16 dflt_ring_grp; 3699 __le16 rss_rule; 3700 __le16 cos_rule; 3701 __le16 lb_rule; 3702 __le16 mru; 3703 u8 unused_0[4]; 3704}; 3705 3706/* hwrm_vnic_cfg_output (size:128b/16B) */ 3707struct hwrm_vnic_cfg_output { 3708 __le16 error_code; 3709 __le16 req_type; 3710 __le16 seq_id; 3711 __le16 resp_len; 3712 u8 unused_0[7]; 3713 u8 valid; 3714}; 3715 3716/* hwrm_vnic_qcaps_input (size:192b/24B) */ 3717struct hwrm_vnic_qcaps_input { 3718 __le16 req_type; 3719 __le16 cmpl_ring; 3720 __le16 seq_id; 3721 __le16 target_id; 3722 __le64 resp_addr; 3723 __le32 enables; 3724 u8 unused_0[4]; 3725}; 3726 3727/* hwrm_vnic_qcaps_output (size:192b/24B) */ 3728struct hwrm_vnic_qcaps_output { 3729 __le16 error_code; 3730 __le16 req_type; 3731 __le16 seq_id; 3732 __le16 resp_len; 3733 __le16 mru; 3734 u8 unused_0[2]; 3735 __le32 flags; 3736 #define VNIC_QCAPS_RESP_FLAGS_UNUSED 0x1UL 3737 #define VNIC_QCAPS_RESP_FLAGS_VLAN_STRIP_CAP 0x2UL 3738 #define VNIC_QCAPS_RESP_FLAGS_BD_STALL_CAP 0x4UL 3739 #define VNIC_QCAPS_RESP_FLAGS_ROCE_DUAL_VNIC_CAP 0x8UL 3740 #define VNIC_QCAPS_RESP_FLAGS_ROCE_ONLY_VNIC_CAP 0x10UL 3741 #define VNIC_QCAPS_RESP_FLAGS_RSS_DFLT_CR_CAP 0x20UL 3742 #define VNIC_QCAPS_RESP_FLAGS_ROCE_MIRRORING_CAPABLE_VNIC_CAP 0x40UL 3743 u8 unused_1[7]; 3744 u8 valid; 3745}; 3746 3747/* hwrm_vnic_tpa_cfg_input (size:320b/40B) */ 3748struct hwrm_vnic_tpa_cfg_input { 3749 __le16 req_type; 3750 __le16 cmpl_ring; 3751 __le16 seq_id; 3752 __le16 target_id; 3753 __le64 resp_addr; 3754 __le32 flags; 3755 #define VNIC_TPA_CFG_REQ_FLAGS_TPA 0x1UL 3756 #define VNIC_TPA_CFG_REQ_FLAGS_ENCAP_TPA 0x2UL 3757 #define VNIC_TPA_CFG_REQ_FLAGS_RSC_WND_UPDATE 0x4UL 3758 #define VNIC_TPA_CFG_REQ_FLAGS_GRO 0x8UL 3759 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_ECN 0x10UL 3760 #define VNIC_TPA_CFG_REQ_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3761 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_IPID_CHECK 0x40UL 3762 #define VNIC_TPA_CFG_REQ_FLAGS_GRO_TTL_CHECK 0x80UL 3763 __le32 enables; 3764 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_SEGS 0x1UL 3765 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGGS 0x2UL 3766 #define VNIC_TPA_CFG_REQ_ENABLES_MAX_AGG_TIMER 0x4UL 3767 #define VNIC_TPA_CFG_REQ_ENABLES_MIN_AGG_LEN 0x8UL 3768 __le16 vnic_id; 3769 __le16 max_agg_segs; 3770 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_1 0x0UL 3771 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_2 0x1UL 3772 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_4 0x2UL 3773 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_8 0x3UL 3774 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 0x1fUL 3775 #define VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_LAST VNIC_TPA_CFG_REQ_MAX_AGG_SEGS_MAX 3776 __le16 max_aggs; 3777 #define VNIC_TPA_CFG_REQ_MAX_AGGS_1 0x0UL 3778 #define VNIC_TPA_CFG_REQ_MAX_AGGS_2 0x1UL 3779 #define VNIC_TPA_CFG_REQ_MAX_AGGS_4 0x2UL 3780 #define VNIC_TPA_CFG_REQ_MAX_AGGS_8 0x3UL 3781 #define VNIC_TPA_CFG_REQ_MAX_AGGS_16 0x4UL 3782 #define VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 0x7UL 3783 #define VNIC_TPA_CFG_REQ_MAX_AGGS_LAST VNIC_TPA_CFG_REQ_MAX_AGGS_MAX 3784 u8 unused_0[2]; 3785 __le32 max_agg_timer; 3786 __le32 min_agg_len; 3787}; 3788 3789/* hwrm_vnic_tpa_cfg_output (size:128b/16B) */ 3790struct hwrm_vnic_tpa_cfg_output { 3791 __le16 error_code; 3792 __le16 req_type; 3793 __le16 seq_id; 3794 __le16 resp_len; 3795 u8 unused_0[7]; 3796 u8 valid; 3797}; 3798 3799/* hwrm_vnic_tpa_qcfg_input (size:192b/24B) */ 3800struct hwrm_vnic_tpa_qcfg_input { 3801 __le16 req_type; 3802 __le16 cmpl_ring; 3803 __le16 seq_id; 3804 __le16 target_id; 3805 __le64 resp_addr; 3806 __le16 vnic_id; 3807 u8 unused_0[6]; 3808}; 3809 3810/* hwrm_vnic_tpa_qcfg_output (size:256b/32B) */ 3811struct hwrm_vnic_tpa_qcfg_output { 3812 __le16 error_code; 3813 __le16 req_type; 3814 __le16 seq_id; 3815 __le16 resp_len; 3816 __le32 flags; 3817 #define VNIC_TPA_QCFG_RESP_FLAGS_TPA 0x1UL 3818 #define VNIC_TPA_QCFG_RESP_FLAGS_ENCAP_TPA 0x2UL 3819 #define VNIC_TPA_QCFG_RESP_FLAGS_RSC_WND_UPDATE 0x4UL 3820 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO 0x8UL 3821 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_ECN 0x10UL 3822 #define VNIC_TPA_QCFG_RESP_FLAGS_AGG_WITH_SAME_GRE_SEQ 0x20UL 3823 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_IPID_CHECK 0x40UL 3824 #define VNIC_TPA_QCFG_RESP_FLAGS_GRO_TTL_CHECK 0x80UL 3825 __le16 max_agg_segs; 3826 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_1 0x0UL 3827 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_2 0x1UL 3828 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_4 0x2UL 3829 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_8 0x3UL 3830 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 0x1fUL 3831 #define VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGG_SEGS_MAX 3832 __le16 max_aggs; 3833 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_1 0x0UL 3834 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_2 0x1UL 3835 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_4 0x2UL 3836 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_8 0x3UL 3837 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_16 0x4UL 3838 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 0x7UL 3839 #define VNIC_TPA_QCFG_RESP_MAX_AGGS_LAST VNIC_TPA_QCFG_RESP_MAX_AGGS_MAX 3840 __le32 max_agg_timer; 3841 __le32 min_agg_len; 3842 u8 unused_0[7]; 3843 u8 valid; 3844}; 3845 3846/* hwrm_vnic_rss_cfg_input (size:384b/48B) */ 3847struct hwrm_vnic_rss_cfg_input { 3848 __le16 req_type; 3849 __le16 cmpl_ring; 3850 __le16 seq_id; 3851 __le16 target_id; 3852 __le64 resp_addr; 3853 __le32 hash_type; 3854 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV4 0x1UL 3855 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV4 0x2UL 3856 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV4 0x4UL 3857 #define VNIC_RSS_CFG_REQ_HASH_TYPE_IPV6 0x8UL 3858 #define VNIC_RSS_CFG_REQ_HASH_TYPE_TCP_IPV6 0x10UL 3859 #define VNIC_RSS_CFG_REQ_HASH_TYPE_UDP_IPV6 0x20UL 3860 u8 unused_0[4]; 3861 __le64 ring_grp_tbl_addr; 3862 __le64 hash_key_tbl_addr; 3863 __le16 rss_ctx_idx; 3864 u8 unused_1[6]; 3865}; 3866 3867/* hwrm_vnic_rss_cfg_output (size:128b/16B) */ 3868struct hwrm_vnic_rss_cfg_output { 3869 __le16 error_code; 3870 __le16 req_type; 3871 __le16 seq_id; 3872 __le16 resp_len; 3873 u8 unused_0[7]; 3874 u8 valid; 3875}; 3876 3877/* hwrm_vnic_plcmodes_cfg_input (size:320b/40B) */ 3878struct hwrm_vnic_plcmodes_cfg_input { 3879 __le16 req_type; 3880 __le16 cmpl_ring; 3881 __le16 seq_id; 3882 __le16 target_id; 3883 __le64 resp_addr; 3884 __le32 flags; 3885 #define VNIC_PLCMODES_CFG_REQ_FLAGS_REGULAR_PLACEMENT 0x1UL 3886 #define VNIC_PLCMODES_CFG_REQ_FLAGS_JUMBO_PLACEMENT 0x2UL 3887 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV4 0x4UL 3888 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_IPV6 0x8UL 3889 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_FCOE 0x10UL 3890 #define VNIC_PLCMODES_CFG_REQ_FLAGS_HDS_ROCE 0x20UL 3891 __le32 enables; 3892 #define VNIC_PLCMODES_CFG_REQ_ENABLES_JUMBO_THRESH_VALID 0x1UL 3893 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_OFFSET_VALID 0x2UL 3894 #define VNIC_PLCMODES_CFG_REQ_ENABLES_HDS_THRESHOLD_VALID 0x4UL 3895 __le32 vnic_id; 3896 __le16 jumbo_thresh; 3897 __le16 hds_offset; 3898 __le16 hds_threshold; 3899 u8 unused_0[6]; 3900}; 3901 3902/* hwrm_vnic_plcmodes_cfg_output (size:128b/16B) */ 3903struct hwrm_vnic_plcmodes_cfg_output { 3904 __le16 error_code; 3905 __le16 req_type; 3906 __le16 seq_id; 3907 __le16 resp_len; 3908 u8 unused_0[7]; 3909 u8 valid; 3910}; 3911 3912/* hwrm_vnic_rss_cos_lb_ctx_alloc_input (size:128b/16B) */ 3913struct hwrm_vnic_rss_cos_lb_ctx_alloc_input { 3914 __le16 req_type; 3915 __le16 cmpl_ring; 3916 __le16 seq_id; 3917 __le16 target_id; 3918 __le64 resp_addr; 3919}; 3920 3921/* hwrm_vnic_rss_cos_lb_ctx_alloc_output (size:128b/16B) */ 3922struct hwrm_vnic_rss_cos_lb_ctx_alloc_output { 3923 __le16 error_code; 3924 __le16 req_type; 3925 __le16 seq_id; 3926 __le16 resp_len; 3927 __le16 rss_cos_lb_ctx_id; 3928 u8 unused_0[5]; 3929 u8 valid; 3930}; 3931 3932/* hwrm_vnic_rss_cos_lb_ctx_free_input (size:192b/24B) */ 3933struct hwrm_vnic_rss_cos_lb_ctx_free_input { 3934 __le16 req_type; 3935 __le16 cmpl_ring; 3936 __le16 seq_id; 3937 __le16 target_id; 3938 __le64 resp_addr; 3939 __le16 rss_cos_lb_ctx_id; 3940 u8 unused_0[6]; 3941}; 3942 3943/* hwrm_vnic_rss_cos_lb_ctx_free_output (size:128b/16B) */ 3944struct hwrm_vnic_rss_cos_lb_ctx_free_output { 3945 __le16 error_code; 3946 __le16 req_type; 3947 __le16 seq_id; 3948 __le16 resp_len; 3949 u8 unused_0[7]; 3950 u8 valid; 3951}; 3952 3953/* hwrm_ring_alloc_input (size:640b/80B) */ 3954struct hwrm_ring_alloc_input { 3955 __le16 req_type; 3956 __le16 cmpl_ring; 3957 __le16 seq_id; 3958 __le16 target_id; 3959 __le64 resp_addr; 3960 __le32 enables; 3961 #define RING_ALLOC_REQ_ENABLES_RING_ARB_CFG 0x2UL 3962 #define RING_ALLOC_REQ_ENABLES_STAT_CTX_ID_VALID 0x8UL 3963 #define RING_ALLOC_REQ_ENABLES_MAX_BW_VALID 0x20UL 3964 u8 ring_type; 3965 #define RING_ALLOC_REQ_RING_TYPE_L2_CMPL 0x0UL 3966 #define RING_ALLOC_REQ_RING_TYPE_TX 0x1UL 3967 #define RING_ALLOC_REQ_RING_TYPE_RX 0x2UL 3968 #define RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 0x3UL 3969 #define RING_ALLOC_REQ_RING_TYPE_LAST RING_ALLOC_REQ_RING_TYPE_ROCE_CMPL 3970 u8 unused_0[3]; 3971 __le64 page_tbl_addr; 3972 __le32 fbo; 3973 u8 page_size; 3974 u8 page_tbl_depth; 3975 u8 unused_1[2]; 3976 __le32 length; 3977 __le16 logical_id; 3978 __le16 cmpl_ring_id; 3979 __le16 queue_id; 3980 u8 unused_2[2]; 3981 __le32 reserved1; 3982 __le16 ring_arb_cfg; 3983 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_MASK 0xfUL 3984 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SFT 0 3985 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_SP 0x1UL 3986 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 0x2UL 3987 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_LAST RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_WFQ 3988 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_MASK 0xf0UL 3989 #define RING_ALLOC_REQ_RING_ARB_CFG_RSVD_SFT 4 3990 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_MASK 0xff00UL 3991 #define RING_ALLOC_REQ_RING_ARB_CFG_ARB_POLICY_PARAM_SFT 8 3992 __le16 unused_3; 3993 __le32 reserved3; 3994 __le32 stat_ctx_id; 3995 __le32 reserved4; 3996 __le32 max_bw; 3997 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_MASK 0xfffffffUL 3998 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_SFT 0 3999 #define RING_ALLOC_REQ_MAX_BW_SCALE 0x10000000UL 4000 #define RING_ALLOC_REQ_MAX_BW_SCALE_BITS (0x0UL << 28)
4001 #define RING_ALLOC_REQ_MAX_BW_SCALE_BYTES (0x1UL << 28) 4002 #define RING_ALLOC_REQ_MAX_BW_SCALE_LAST RING_ALLOC_REQ_MAX_BW_SCALE_BYTES 4003 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MASK 0xe0000000UL 4004 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_SFT 29 4005 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_MEGA (0x0UL << 29) 4006 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_KILO (0x2UL << 29) 4007 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_BASE (0x4UL << 29) 4008 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_GIGA (0x6UL << 29) 4009 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_PERCENT1_100 (0x1UL << 29) 4010 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID (0x7UL << 29) 4011 #define RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_LAST RING_ALLOC_REQ_MAX_BW_BW_VALUE_UNIT_INVALID 4012 u8 int_mode; 4013 #define RING_ALLOC_REQ_INT_MODE_LEGACY 0x0UL 4014 #define RING_ALLOC_REQ_INT_MODE_RSVD 0x1UL 4015 #define RING_ALLOC_REQ_INT_MODE_MSIX 0x2UL 4016 #define RING_ALLOC_REQ_INT_MODE_POLL 0x3UL 4017 #define RING_ALLOC_REQ_INT_MODE_LAST RING_ALLOC_REQ_INT_MODE_POLL 4018 u8 unused_4[3]; 4019}; 4020 4021/* hwrm_ring_alloc_output (size:128b/16B) */ 4022struct hwrm_ring_alloc_output { 4023 __le16 error_code; 4024 __le16 req_type; 4025 __le16 seq_id; 4026 __le16 resp_len; 4027 __le16 ring_id; 4028 __le16 logical_ring_id; 4029 u8 unused_0[3]; 4030 u8 valid; 4031}; 4032 4033/* hwrm_ring_free_input (size:192b/24B) */ 4034struct hwrm_ring_free_input { 4035 __le16 req_type; 4036 __le16 cmpl_ring; 4037 __le16 seq_id; 4038 __le16 target_id; 4039 __le64 resp_addr; 4040 u8 ring_type; 4041 #define RING_FREE_REQ_RING_TYPE_L2_CMPL 0x0UL 4042 #define RING_FREE_REQ_RING_TYPE_TX 0x1UL 4043 #define RING_FREE_REQ_RING_TYPE_RX 0x2UL 4044 #define RING_FREE_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4045 #define RING_FREE_REQ_RING_TYPE_LAST RING_FREE_REQ_RING_TYPE_ROCE_CMPL 4046 u8 unused_0; 4047 __le16 ring_id; 4048 u8 unused_1[4]; 4049}; 4050 4051/* hwrm_ring_free_output (size:128b/16B) */ 4052struct hwrm_ring_free_output { 4053 __le16 error_code; 4054 __le16 req_type; 4055 __le16 seq_id; 4056 __le16 resp_len; 4057 u8 unused_0[7]; 4058 u8 valid; 4059}; 4060 4061/* hwrm_ring_cmpl_ring_qaggint_params_input (size:192b/24B) */ 4062struct hwrm_ring_cmpl_ring_qaggint_params_input { 4063 __le16 req_type; 4064 __le16 cmpl_ring; 4065 __le16 seq_id; 4066 __le16 target_id; 4067 __le64 resp_addr; 4068 __le16 ring_id; 4069 u8 unused_0[6]; 4070}; 4071 4072/* hwrm_ring_cmpl_ring_qaggint_params_output (size:256b/32B) */ 4073struct hwrm_ring_cmpl_ring_qaggint_params_output { 4074 __le16 error_code; 4075 __le16 req_type; 4076 __le16 seq_id; 4077 __le16 resp_len; 4078 __le16 flags; 4079 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_TIMER_RESET 0x1UL 4080 #define RING_CMPL_RING_QAGGINT_PARAMS_RESP_FLAGS_RING_IDLE 0x2UL 4081 __le16 num_cmpl_dma_aggr; 4082 __le16 num_cmpl_dma_aggr_during_int; 4083 __le16 cmpl_aggr_dma_tmr; 4084 __le16 cmpl_aggr_dma_tmr_during_int; 4085 __le16 int_lat_tmr_min; 4086 __le16 int_lat_tmr_max; 4087 __le16 num_cmpl_aggr_int; 4088 u8 unused_0[7]; 4089 u8 valid; 4090}; 4091 4092/* hwrm_ring_cmpl_ring_cfg_aggint_params_input (size:320b/40B) */ 4093struct hwrm_ring_cmpl_ring_cfg_aggint_params_input { 4094 __le16 req_type; 4095 __le16 cmpl_ring; 4096 __le16 seq_id; 4097 __le16 target_id; 4098 __le64 resp_addr; 4099 __le16 ring_id; 4100 __le16 flags; 4101 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_TIMER_RESET 0x1UL 4102 #define RING_CMPL_RING_CFG_AGGINT_PARAMS_REQ_FLAGS_RING_IDLE 0x2UL 4103 __le16 num_cmpl_dma_aggr; 4104 __le16 num_cmpl_dma_aggr_during_int; 4105 __le16 cmpl_aggr_dma_tmr; 4106 __le16 cmpl_aggr_dma_tmr_during_int; 4107 __le16 int_lat_tmr_min; 4108 __le16 int_lat_tmr_max; 4109 __le16 num_cmpl_aggr_int; 4110 u8 unused_0[6]; 4111}; 4112 4113/* hwrm_ring_cmpl_ring_cfg_aggint_params_output (size:128b/16B) */ 4114struct hwrm_ring_cmpl_ring_cfg_aggint_params_output { 4115 __le16 error_code; 4116 __le16 req_type; 4117 __le16 seq_id; 4118 __le16 resp_len; 4119 u8 unused_0[7]; 4120 u8 valid; 4121}; 4122 4123/* hwrm_ring_reset_input (size:192b/24B) */ 4124struct hwrm_ring_reset_input { 4125 __le16 req_type; 4126 __le16 cmpl_ring; 4127 __le16 seq_id; 4128 __le16 target_id; 4129 __le64 resp_addr; 4130 u8 ring_type; 4131 #define RING_RESET_REQ_RING_TYPE_L2_CMPL 0x0UL 4132 #define RING_RESET_REQ_RING_TYPE_TX 0x1UL 4133 #define RING_RESET_REQ_RING_TYPE_RX 0x2UL 4134 #define RING_RESET_REQ_RING_TYPE_ROCE_CMPL 0x3UL 4135 #define RING_RESET_REQ_RING_TYPE_LAST RING_RESET_REQ_RING_TYPE_ROCE_CMPL 4136 u8 unused_0; 4137 __le16 ring_id; 4138 u8 unused_1[4]; 4139}; 4140 4141/* hwrm_ring_reset_output (size:128b/16B) */ 4142struct hwrm_ring_reset_output { 4143 __le16 error_code; 4144 __le16 req_type; 4145 __le16 seq_id; 4146 __le16 resp_len; 4147 u8 unused_0[7]; 4148 u8 valid; 4149}; 4150 4151/* hwrm_ring_grp_alloc_input (size:192b/24B) */ 4152struct hwrm_ring_grp_alloc_input { 4153 __le16 req_type; 4154 __le16 cmpl_ring; 4155 __le16 seq_id; 4156 __le16 target_id; 4157 __le64 resp_addr; 4158 __le16 cr; 4159 __le16 rr; 4160 __le16 ar; 4161 __le16 sc; 4162}; 4163 4164/* hwrm_ring_grp_alloc_output (size:128b/16B) */ 4165struct hwrm_ring_grp_alloc_output { 4166 __le16 error_code; 4167 __le16 req_type; 4168 __le16 seq_id; 4169 __le16 resp_len; 4170 __le32 ring_group_id; 4171 u8 unused_0[3]; 4172 u8 valid; 4173}; 4174 4175/* hwrm_ring_grp_free_input (size:192b/24B) */ 4176struct hwrm_ring_grp_free_input { 4177 __le16 req_type; 4178 __le16 cmpl_ring; 4179 __le16 seq_id; 4180 __le16 target_id; 4181 __le64 resp_addr; 4182 __le32 ring_group_id; 4183 u8 unused_0[4]; 4184}; 4185 4186/* hwrm_ring_grp_free_output (size:128b/16B) */ 4187struct hwrm_ring_grp_free_output { 4188 __le16 error_code; 4189 __le16 req_type; 4190 __le16 seq_id; 4191 __le16 resp_len; 4192 u8 unused_0[7]; 4193 u8 valid; 4194}; 4195 4196/* hwrm_cfa_l2_filter_alloc_input (size:768b/96B) */ 4197struct hwrm_cfa_l2_filter_alloc_input { 4198 __le16 req_type; 4199 __le16 cmpl_ring; 4200 __le16 seq_id; 4201 __le16 target_id; 4202 __le64 resp_addr; 4203 __le32 flags; 4204 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH 0x1UL 4205 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_TX 0x0UL 4206 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 0x1UL 4207 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_ALLOC_REQ_FLAGS_PATH_RX 4208 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x2UL 4209 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_DROP 0x4UL 4210 #define CFA_L2_FILTER_ALLOC_REQ_FLAGS_OUTERMOST 0x8UL 4211 __le32 enables; 4212 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x1UL 4213 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_ADDR_MASK 0x2UL 4214 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN 0x4UL 4215 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_OVLAN_MASK 0x8UL 4216 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x10UL 4217 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN_MASK 0x20UL 4218 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR 0x40UL 4219 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_ADDR_MASK 0x80UL 4220 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN 0x100UL 4221 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_OVLAN_MASK 0x200UL 4222 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN 0x400UL 4223 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_T_L2_IVLAN_MASK 0x800UL 4224 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_TYPE 0x1000UL 4225 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_SRC_ID 0x2000UL 4226 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4000UL 4227 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4228 #define CFA_L2_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4229 u8 l2_addr[6]; 4230 u8 unused_0[2]; 4231 u8 l2_addr_mask[6]; 4232 __le16 l2_ovlan; 4233 __le16 l2_ovlan_mask; 4234 __le16 l2_ivlan; 4235 __le16 l2_ivlan_mask; 4236 u8 unused_1[2]; 4237 u8 t_l2_addr[6]; 4238 u8 unused_2[2]; 4239 u8 t_l2_addr_mask[6]; 4240 __le16 t_l2_ovlan; 4241 __le16 t_l2_ovlan_mask; 4242 __le16 t_l2_ivlan; 4243 __le16 t_l2_ivlan_mask; 4244 u8 src_type; 4245 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_NPORT 0x0UL 4246 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_PF 0x1UL 4247 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VF 0x2UL 4248 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_VNIC 0x3UL 4249 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_KONG 0x4UL 4250 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_APE 0x5UL 4251 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_BONO 0x6UL 4252 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 0x7UL 4253 #define CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_SRC_TYPE_TANG 4254 u8 unused_3; 4255 __le32 src_id; 4256 u8 tunnel_type; 4257 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4258 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4259 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4260 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4261 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4262 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4263 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4264 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4265 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4266 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4267 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4268 #define CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_L2_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4269 u8 unused_4; 4270 __le16 dst_id; 4271 __le16 mirror_vnic_id; 4272 u8 pri_hint; 4273 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4274 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_ABOVE_FILTER 0x1UL 4275 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_BELOW_FILTER 0x2UL 4276 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MAX 0x3UL 4277 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 0x4UL 4278 #define CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_L2_FILTER_ALLOC_REQ_PRI_HINT_MIN 4279 u8 unused_5; 4280 __le32 unused_6; 4281 __le64 l2_filter_id_hint; 4282}; 4283 4284/* hwrm_cfa_l2_filter_alloc_output (size:192b/24B) */ 4285struct hwrm_cfa_l2_filter_alloc_output { 4286 __le16 error_code; 4287 __le16 req_type; 4288 __le16 seq_id; 4289 __le16 resp_len; 4290 __le64 l2_filter_id; 4291 __le32 flow_id; 4292 u8 unused_0[3]; 4293 u8 valid; 4294}; 4295 4296/* hwrm_cfa_l2_filter_free_input (size:192b/24B) */ 4297struct hwrm_cfa_l2_filter_free_input { 4298 __le16 req_type; 4299 __le16 cmpl_ring; 4300 __le16 seq_id; 4301 __le16 target_id; 4302 __le64 resp_addr; 4303 __le64 l2_filter_id; 4304}; 4305 4306/* hwrm_cfa_l2_filter_free_output (size:128b/16B) */ 4307struct hwrm_cfa_l2_filter_free_output { 4308 __le16 error_code; 4309 __le16 req_type; 4310 __le16 seq_id; 4311 __le16 resp_len; 4312 u8 unused_0[7]; 4313 u8 valid; 4314}; 4315 4316/* hwrm_cfa_l2_filter_cfg_input (size:320b/40B) */ 4317struct hwrm_cfa_l2_filter_cfg_input { 4318 __le16 req_type; 4319 __le16 cmpl_ring; 4320 __le16 seq_id; 4321 __le16 target_id; 4322 __le64 resp_addr; 4323 __le32 flags; 4324 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH 0x1UL 4325 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_TX 0x0UL 4326 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 0x1UL 4327 #define CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_LAST CFA_L2_FILTER_CFG_REQ_FLAGS_PATH_RX 4328 #define CFA_L2_FILTER_CFG_REQ_FLAGS_DROP 0x2UL 4329 __le32 enables; 4330 #define CFA_L2_FILTER_CFG_REQ_ENABLES_DST_ID 0x1UL 4331 #define CFA_L2_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4332 __le64 l2_filter_id; 4333 __le32 dst_id; 4334 __le32 new_mirror_vnic_id; 4335}; 4336 4337/* hwrm_cfa_l2_filter_cfg_output (size:128b/16B) */ 4338struct hwrm_cfa_l2_filter_cfg_output { 4339 __le16 error_code; 4340 __le16 req_type; 4341 __le16 seq_id; 4342 __le16 resp_len; 4343 u8 unused_0[7]; 4344 u8 valid; 4345}; 4346 4347/* hwrm_cfa_l2_set_rx_mask_input (size:448b/56B) */ 4348struct hwrm_cfa_l2_set_rx_mask_input { 4349 __le16 req_type; 4350 __le16 cmpl_ring; 4351 __le16 seq_id; 4352 __le16 target_id; 4353 __le64 resp_addr; 4354 __le32 vnic_id; 4355 __le32 mask; 4356 #define CFA_L2_SET_RX_MASK_REQ_MASK_MCAST 0x2UL 4357 #define CFA_L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x4UL 4358 #define CFA_L2_SET_RX_MASK_REQ_MASK_BCAST 0x8UL 4359 #define CFA_L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x10UL 4360 #define CFA_L2_SET_RX_MASK_REQ_MASK_OUTERMOST 0x20UL 4361 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLANONLY 0x40UL 4362 #define CFA_L2_SET_RX_MASK_REQ_MASK_VLAN_NONVLAN 0x80UL 4363 #define CFA_L2_SET_RX_MASK_REQ_MASK_ANYVLAN_NONVLAN 0x100UL 4364 __le64 mc_tbl_addr; 4365 __le32 num_mc_entries; 4366 u8 unused_0[4]; 4367 __le64 vlan_tag_tbl_addr; 4368 __le32 num_vlan_tags; 4369 u8 unused_1[4]; 4370}; 4371 4372/* hwrm_cfa_l2_set_rx_mask_output (size:128b/16B) */ 4373struct hwrm_cfa_l2_set_rx_mask_output { 4374 __le16 error_code; 4375 __le16 req_type; 4376 __le16 seq_id; 4377 __le16 resp_len; 4378 u8 unused_0[7]; 4379 u8 valid; 4380}; 4381 4382/* hwrm_cfa_l2_set_rx_mask_cmd_err (size:64b/8B) */ 4383struct hwrm_cfa_l2_set_rx_mask_cmd_err { 4384 u8 code; 4385 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_UNKNOWN 0x0UL 4386 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 0x1UL 4387 #define CFA_L2_SET_RX_MASK_CMD_ERR_CODE_LAST CFA_L2_SET_RX_MASK_CMD_ERR_CODE_NTUPLE_FILTER_CONFLICT_ERR 4388 u8 unused_0[7]; 4389}; 4390 4391/* hwrm_cfa_tunnel_filter_alloc_input (size:704b/88B) */ 4392struct hwrm_cfa_tunnel_filter_alloc_input { 4393 __le16 req_type; 4394 __le16 cmpl_ring; 4395 __le16 seq_id; 4396 __le16 target_id; 4397 __le64 resp_addr; 4398 __le32 flags; 4399 #define CFA_TUNNEL_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4400 __le32 enables; 4401 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4402 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_ADDR 0x2UL 4403 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L2_IVLAN 0x4UL 4404 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR 0x8UL 4405 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_L3_ADDR_TYPE 0x10UL 4406 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR_TYPE 0x20UL 4407 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_T_L3_ADDR 0x40UL 4408 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x80UL 4409 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_VNI 0x100UL 4410 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_DST_VNIC_ID 0x200UL 4411 #define CFA_TUNNEL_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x400UL 4412 __le64 l2_filter_id; 4413 u8 l2_addr[6]; 4414 __le16 l2_ivlan; 4415 __le32 l3_addr[4]; 4416 __le32 t_l3_addr[4]; 4417 u8 l3_addr_type; 4418 u8 t_l3_addr_type; 4419 u8 tunnel_type; 4420 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4421 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4422 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4423 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4424 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4425 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4426 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4427 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4428 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4429 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4430 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4431 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4432 u8 tunnel_flags; 4433 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_OAM_CHECKSUM_EXPLHDR 0x1UL 4434 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_CRITICAL_OPT_S1 0x2UL 4435 #define CFA_TUNNEL_FILTER_ALLOC_REQ_TUNNEL_FLAGS_TUN_FLAGS_EXTHDR_SEQNUM_S0 0x4UL 4436 __le32 vni; 4437 __le32 dst_vnic_id; 4438 __le32 mirror_vnic_id; 4439}; 4440 4441/* hwrm_cfa_tunnel_filter_alloc_output (size:192b/24B) */ 4442struct hwrm_cfa_tunnel_filter_alloc_output { 4443 __le16 error_code; 4444 __le16 req_type; 4445 __le16 seq_id; 4446 __le16 resp_len; 4447 __le64 tunnel_filter_id; 4448 __le32 flow_id; 4449 u8 unused_0[3]; 4450 u8 valid; 4451}; 4452 4453/* hwrm_cfa_tunnel_filter_free_input (size:192b/24B) */ 4454struct hwrm_cfa_tunnel_filter_free_input { 4455 __le16 req_type; 4456 __le16 cmpl_ring; 4457 __le16 seq_id; 4458 __le16 target_id; 4459 __le64 resp_addr; 4460 __le64 tunnel_filter_id; 4461}; 4462 4463/* hwrm_cfa_tunnel_filter_free_output (size:128b/16B) */ 4464struct hwrm_cfa_tunnel_filter_free_output { 4465 __le16 error_code; 4466 __le16 req_type; 4467 __le16 seq_id; 4468 __le16 resp_len; 4469 u8 unused_0[7]; 4470 u8 valid; 4471}; 4472 4473/* hwrm_vxlan_ipv4_hdr (size:128b/16B) */ 4474struct hwrm_vxlan_ipv4_hdr { 4475 u8 ver_hlen; 4476 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_MASK 0xfUL 4477 #define VXLAN_IPV4_HDR_VER_HLEN_HEADER_LENGTH_SFT 0 4478 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_MASK 0xf0UL 4479 #define VXLAN_IPV4_HDR_VER_HLEN_VERSION_SFT 4 4480 u8 tos; 4481 __be16 ip_id; 4482 __be16 flags_frag_offset; 4483 u8 ttl; 4484 u8 protocol; 4485 __be32 src_ip_addr; 4486 __be32 dest_ip_addr; 4487}; 4488 4489/* hwrm_vxlan_ipv6_hdr (size:320b/40B) */ 4490struct hwrm_vxlan_ipv6_hdr { 4491 __be32 ver_tc_flow_label; 4492 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_SFT 0x1cUL 4493 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_VER_MASK 0xf0000000UL 4494 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_SFT 0x14UL 4495 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_TC_MASK 0xff00000UL 4496 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_SFT 0x0UL 4497 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 0xfffffUL 4498 #define VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_LAST VXLAN_IPV6_HDR_VER_TC_FLOW_LABEL_FLOW_LABEL_MASK 4499 __be16 payload_len; 4500 u8 next_hdr; 4501 u8 ttl; 4502 __be32 src_ip_addr[4]; 4503 __be32 dest_ip_addr[4]; 4504}; 4505 4506/* hwrm_cfa_encap_data_vxlan (size:576b/72B) */ 4507struct hwrm_cfa_encap_data_vxlan { 4508 u8 src_mac_addr[6]; 4509 __le16 unused_0; 4510 u8 dst_mac_addr[6]; 4511 u8 num_vlan_tags; 4512 u8 unused_1; 4513 __be16 ovlan_tpid; 4514 __be16 ovlan_tci; 4515 __be16 ivlan_tpid; 4516 __be16 ivlan_tci; 4517 __le32 l3[10]; 4518 #define CFA_ENCAP_DATA_VXLAN_L3_VER_MASK 0xfUL 4519 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV4 0x4UL 4520 #define CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 0x6UL 4521 #define CFA_ENCAP_DATA_VXLAN_L3_LAST CFA_ENCAP_DATA_VXLAN_L3_VER_IPV6 4522 __be16 src_port; 4523 __be16 dst_port; 4524 __be32 vni; 4525}; 4526 4527/* hwrm_cfa_encap_record_alloc_input (size:832b/104B) */ 4528struct hwrm_cfa_encap_record_alloc_input { 4529 __le16 req_type; 4530 __le16 cmpl_ring; 4531 __le16 seq_id; 4532 __le16 target_id; 4533 __le64 resp_addr; 4534 __le32 flags; 4535 #define CFA_ENCAP_RECORD_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4536 u8 encap_type; 4537 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VXLAN 0x1UL 4538 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_NVGRE 0x2UL 4539 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_L2GRE 0x3UL 4540 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPIP 0x4UL 4541 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_GENEVE 0x5UL 4542 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_MPLS 0x6UL 4543 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_VLAN 0x7UL 4544 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 0x8UL 4545 #define CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_LAST CFA_ENCAP_RECORD_ALLOC_REQ_ENCAP_TYPE_IPGRE 4546 u8 unused_0[3]; 4547 __le32 encap_data[20]; 4548}; 4549 4550/* hwrm_cfa_encap_record_alloc_output (size:128b/16B) */ 4551struct hwrm_cfa_encap_record_alloc_output { 4552 __le16 error_code; 4553 __le16 req_type; 4554 __le16 seq_id; 4555 __le16 resp_len; 4556 __le32 encap_record_id; 4557 u8 unused_0[3]; 4558 u8 valid; 4559}; 4560 4561/* hwrm_cfa_encap_record_free_input (size:192b/24B) */ 4562struct hwrm_cfa_encap_record_free_input { 4563 __le16 req_type; 4564 __le16 cmpl_ring; 4565 __le16 seq_id; 4566 __le16 target_id; 4567 __le64 resp_addr; 4568 __le32 encap_record_id; 4569 u8 unused_0[4]; 4570}; 4571 4572/* hwrm_cfa_encap_record_free_output (size:128b/16B) */ 4573struct hwrm_cfa_encap_record_free_output { 4574 __le16 error_code; 4575 __le16 req_type; 4576 __le16 seq_id; 4577 __le16 resp_len; 4578 u8 unused_0[7]; 4579 u8 valid; 4580}; 4581 4582/* hwrm_cfa_ntuple_filter_alloc_input (size:1024b/128B) */ 4583struct hwrm_cfa_ntuple_filter_alloc_input { 4584 __le16 req_type; 4585 __le16 cmpl_ring; 4586 __le16 seq_id; 4587 __le16 target_id; 4588 __le64 resp_addr; 4589 __le32 flags; 4590 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_LOOPBACK 0x1UL 4591 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_DROP 0x2UL 4592 #define CFA_NTUPLE_FILTER_ALLOC_REQ_FLAGS_METER 0x4UL 4593 __le32 enables; 4594 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_L2_FILTER_ID 0x1UL 4595 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x2UL 4596 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x4UL 4597 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x8UL 4598 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x10UL 4599 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x20UL 4600 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR_MASK 0x40UL 4601 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x80UL 4602 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR_MASK 0x100UL 4603 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x200UL 4604 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x400UL 4605 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_SRC_PORT_MASK 0x800UL 4606 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x1000UL 4607 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_PORT_MASK 0x2000UL 4608 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_PRI_HINT 0x4000UL 4609 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_NTUPLE_FILTER_ID 0x8000UL 4610 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x10000UL 4611 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x20000UL 4612 #define CFA_NTUPLE_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x40000UL 4613 __le64 l2_filter_id; 4614 u8 src_macaddr[6]; 4615 __be16 ethertype; 4616 u8 ip_addr_type; 4617 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4618 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4619 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4620 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 4621 u8 ip_protocol; 4622 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4623 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4624 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4625 #define CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 4626 __le16 dst_id; 4627 __le16 mirror_vnic_id; 4628 u8 tunnel_type; 4629 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4630 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4631 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4632 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4633 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4634 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4635 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4636 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4637 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4638 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4639 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4640 #define CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4641 u8 pri_hint; 4642 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_NO_PREFER 0x0UL 4643 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_ABOVE 0x1UL 4644 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_BELOW 0x2UL 4645 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_HIGHEST 0x3UL 4646 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 0x4UL 4647 #define CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LAST CFA_NTUPLE_FILTER_ALLOC_REQ_PRI_HINT_LOWEST 4648 __be32 src_ipaddr[4]; 4649 __be32 src_ipaddr_mask[4]; 4650 __be32 dst_ipaddr[4]; 4651 __be32 dst_ipaddr_mask[4]; 4652 __be16 src_port; 4653 __be16 src_port_mask; 4654 __be16 dst_port; 4655 __be16 dst_port_mask; 4656 __le64 ntuple_filter_id_hint; 4657}; 4658 4659/* hwrm_cfa_ntuple_filter_alloc_output (size:192b/24B) */ 4660struct hwrm_cfa_ntuple_filter_alloc_output { 4661 __le16 error_code; 4662 __le16 req_type; 4663 __le16 seq_id; 4664 __le16 resp_len; 4665 __le64 ntuple_filter_id; 4666 __le32 flow_id; 4667 u8 unused_0[3]; 4668 u8 valid; 4669}; 4670 4671/* hwrm_cfa_ntuple_filter_alloc_cmd_err (size:64b/8B) */ 4672struct hwrm_cfa_ntuple_filter_alloc_cmd_err { 4673 u8 code; 4674 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_UNKNOWN 0x0UL 4675 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 0x1UL 4676 #define CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_LAST CFA_NTUPLE_FILTER_ALLOC_CMD_ERR_CODE_RX_MASK_VLAN_CONFLICT_ERR 4677 u8 unused_0[7]; 4678}; 4679 4680/* hwrm_cfa_ntuple_filter_free_input (size:192b/24B) */ 4681struct hwrm_cfa_ntuple_filter_free_input { 4682 __le16 req_type; 4683 __le16 cmpl_ring; 4684 __le16 seq_id; 4685 __le16 target_id; 4686 __le64 resp_addr; 4687 __le64 ntuple_filter_id; 4688}; 4689 4690/* hwrm_cfa_ntuple_filter_free_output (size:128b/16B) */ 4691struct hwrm_cfa_ntuple_filter_free_output { 4692 __le16 error_code; 4693 __le16 req_type; 4694 __le16 seq_id; 4695 __le16 resp_len; 4696 u8 unused_0[7]; 4697 u8 valid; 4698}; 4699 4700/* hwrm_cfa_ntuple_filter_cfg_input (size:384b/48B) */ 4701struct hwrm_cfa_ntuple_filter_cfg_input { 4702 __le16 req_type; 4703 __le16 cmpl_ring; 4704 __le16 seq_id; 4705 __le16 target_id; 4706 __le64 resp_addr; 4707 __le32 enables; 4708 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_DST_ID 0x1UL 4709 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_MIRROR_VNIC_ID 0x2UL 4710 #define CFA_NTUPLE_FILTER_CFG_REQ_ENABLES_NEW_METER_INSTANCE_ID 0x4UL 4711 u8 unused_0[4]; 4712 __le64 ntuple_filter_id; 4713 __le32 new_dst_id; 4714 __le32 new_mirror_vnic_id; 4715 __le16 new_meter_instance_id; 4716 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 0xffffUL 4717 #define CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_LAST CFA_NTUPLE_FILTER_CFG_REQ_NEW_METER_INSTANCE_ID_INVALID 4718 u8 unused_1[6]; 4719}; 4720 4721/* hwrm_cfa_ntuple_filter_cfg_output (size:128b/16B) */ 4722struct hwrm_cfa_ntuple_filter_cfg_output { 4723 __le16 error_code; 4724 __le16 req_type; 4725 __le16 seq_id; 4726 __le16 resp_len; 4727 u8 unused_0[7]; 4728 u8 valid; 4729}; 4730 4731/* hwrm_cfa_decap_filter_alloc_input (size:832b/104B) */ 4732struct hwrm_cfa_decap_filter_alloc_input { 4733 __le16 req_type; 4734 __le16 cmpl_ring; 4735 __le16 seq_id; 4736 __le16 target_id; 4737 __le64 resp_addr; 4738 __le32 flags; 4739 #define CFA_DECAP_FILTER_ALLOC_REQ_FLAGS_OVS_TUNNEL 0x1UL 4740 __le32 enables; 4741 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_TYPE 0x1UL 4742 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_TUNNEL_ID 0x2UL 4743 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_MACADDR 0x4UL 4744 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_MACADDR 0x8UL 4745 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_OVLAN_VID 0x10UL 4746 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IVLAN_VID 0x20UL 4747 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_OVLAN_VID 0x40UL 4748 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_T_IVLAN_VID 0x80UL 4749 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_ETHERTYPE 0x100UL 4750 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_IPADDR 0x200UL 4751 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_IPADDR 0x400UL 4752 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IPADDR_TYPE 0x800UL 4753 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_IP_PROTOCOL 0x1000UL 4754 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_SRC_PORT 0x2000UL 4755 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_PORT 0x4000UL 4756 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_DST_ID 0x8000UL 4757 #define CFA_DECAP_FILTER_ALLOC_REQ_ENABLES_MIRROR_VNIC_ID 0x10000UL 4758 __be32 tunnel_id; 4759 u8 tunnel_type; 4760 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NONTUNNEL 0x0UL 4761 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 4762 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_NVGRE 0x2UL 4763 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_L2GRE 0x3UL 4764 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPIP 0x4UL 4765 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 4766 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_MPLS 0x6UL 4767 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_STT 0x7UL 4768 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_IPGRE 0x8UL 4769 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 4770 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 0xffUL 4771 #define CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_TUNNEL_TYPE_ANYTUNNEL 4772 u8 unused_0; 4773 __le16 unused_1; 4774 u8 src_macaddr[6]; 4775 u8 unused_2[2]; 4776 u8 dst_macaddr[6]; 4777 __be16 ovlan_vid; 4778 __be16 ivlan_vid; 4779 __be16 t_ovlan_vid; 4780 __be16 t_ivlan_vid; 4781 __be16 ethertype; 4782 u8 ip_addr_type; 4783 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_UNKNOWN 0x0UL 4784 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV4 0x4UL 4785 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 0x6UL 4786 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_ADDR_TYPE_IPV6 4787 u8 ip_protocol; 4788 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UNKNOWN 0x0UL 4789 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_TCP 0x6UL 4790 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 0x11UL 4791 #define CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_LAST CFA_DECAP_FILTER_ALLOC_REQ_IP_PROTOCOL_UDP 4792 __le16 unused_3; 4793 __le32 unused_4; 4794 __be32 src_ipaddr[4]; 4795 __be32 dst_ipaddr[4]; 4796 __be16 src_port; 4797 __be16 dst_port; 4798 __le16 dst_id; 4799 __le16 l2_ctxt_ref_id; 4800}; 4801 4802/* hwrm_cfa_decap_filter_alloc_output (size:128b/16B) */ 4803struct hwrm_cfa_decap_filter_alloc_output { 4804 __le16 error_code; 4805 __le16 req_type; 4806 __le16 seq_id; 4807 __le16 resp_len; 4808 __le32 decap_filter_id; 4809 u8 unused_0[3]; 4810 u8 valid; 4811}; 4812 4813/* hwrm_cfa_decap_filter_free_input (size:192b/24B) */ 4814struct hwrm_cfa_decap_filter_free_input { 4815 __le16 req_type; 4816 __le16 cmpl_ring; 4817 __le16 seq_id; 4818 __le16 target_id; 4819 __le64 resp_addr; 4820 __le32 decap_filter_id; 4821 u8 unused_0[4]; 4822}; 4823 4824/* hwrm_cfa_decap_filter_free_output (size:128b/16B) */ 4825struct hwrm_cfa_decap_filter_free_output { 4826 __le16 error_code; 4827 __le16 req_type; 4828 __le16 seq_id; 4829 __le16 resp_len; 4830 u8 unused_0[7]; 4831 u8 valid; 4832}; 4833 4834/* hwrm_cfa_flow_alloc_input (size:1024b/128B) */ 4835struct hwrm_cfa_flow_alloc_input { 4836 __le16 req_type; 4837 __le16 cmpl_ring; 4838 __le16 seq_id; 4839 __le16 target_id; 4840 __le64 resp_addr; 4841 __le16 flags; 4842 #define CFA_FLOW_ALLOC_REQ_FLAGS_TUNNEL 0x1UL 4843 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_MASK 0x6UL 4844 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_SFT 1 4845 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_NONE (0x0UL << 1) 4846 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_ONE (0x1UL << 1) 4847 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO (0x2UL << 1) 4848 #define CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_LAST CFA_FLOW_ALLOC_REQ_FLAGS_NUM_VLAN_TWO 4849 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_MASK 0x38UL 4850 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_SFT 3 4851 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_L2 (0x0UL << 3) 4852 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV4 (0x1UL << 3) 4853 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 (0x2UL << 3) 4854 #define CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_LAST CFA_FLOW_ALLOC_REQ_FLAGS_FLOWTYPE_IPV6 4855 __le16 src_fid; 4856 __le32 tunnel_handle; 4857 __le16 action_flags; 4858 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_FWD 0x1UL 4859 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_RECYCLE 0x2UL 4860 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_DROP 0x4UL 4861 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_METER 0x8UL 4862 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TUNNEL 0x10UL 4863 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_SRC 0x20UL 4864 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_DEST 0x40UL 4865 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_NAT_IPV4_ADDRESS 0x80UL 4866 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_L2_HEADER_REWRITE 0x100UL 4867 #define CFA_FLOW_ALLOC_REQ_ACTION_FLAGS_TTL_DECREMENT 0x200UL 4868 __le16 dst_fid; 4869 __be16 l2_rewrite_vlan_tpid; 4870 __be16 l2_rewrite_vlan_tci; 4871 __le16 act_meter_id; 4872 __le16 ref_flow_handle; 4873 __be16 ethertype; 4874 __be16 outer_vlan_tci; 4875 __be16 dmac[3]; 4876 __be16 inner_vlan_tci; 4877 __be16 smac[3]; 4878 u8 ip_dst_mask_len; 4879 u8 ip_src_mask_len; 4880 __be32 ip_dst[4]; 4881 __be32 ip_src[4]; 4882 __be16 l4_src_port; 4883 __be16 l4_src_port_mask; 4884 __be16 l4_dst_port; 4885 __be16 l4_dst_port_mask; 4886 __be32 nat_ip_address[4]; 4887 __be16 l2_rewrite_dmac[3]; 4888 __be16 nat_port; 4889 __be16 l2_rewrite_smac[3]; 4890 u8 ip_proto; 4891 u8 unused_0; 4892}; 4893 4894/* hwrm_cfa_flow_alloc_output (size:128b/16B) */ 4895struct hwrm_cfa_flow_alloc_output { 4896 __le16 error_code; 4897 __le16 req_type; 4898 __le16 seq_id; 4899 __le16 resp_len; 4900 __le16 flow_handle; 4901 u8 unused_0[5]; 4902 u8 valid; 4903}; 4904 4905/* hwrm_cfa_flow_free_input (size:192b/24B) */ 4906struct hwrm_cfa_flow_free_input { 4907 __le16 req_type; 4908 __le16 cmpl_ring; 4909 __le16 seq_id; 4910 __le16 target_id; 4911 __le64 resp_addr; 4912 __le16 flow_handle; 4913 u8 unused_0[6]; 4914}; 4915 4916/* hwrm_cfa_flow_free_output (size:256b/32B) */ 4917struct hwrm_cfa_flow_free_output { 4918 __le16 error_code; 4919 __le16 req_type; 4920 __le16 seq_id; 4921 __le16 resp_len; 4922 __le64 packet; 4923 __le64 byte; 4924 u8 unused_0[7]; 4925 u8 valid; 4926}; 4927 4928/* hwrm_cfa_flow_stats_input (size:320b/40B) */ 4929struct hwrm_cfa_flow_stats_input { 4930 __le16 req_type; 4931 __le16 cmpl_ring; 4932 __le16 seq_id; 4933 __le16 target_id; 4934 __le64 resp_addr; 4935 __le16 num_flows; 4936 __le16 flow_handle_0; 4937 __le16 flow_handle_1; 4938 __le16 flow_handle_2; 4939 __le16 flow_handle_3; 4940 __le16 flow_handle_4; 4941 __le16 flow_handle_5; 4942 __le16 flow_handle_6; 4943 __le16 flow_handle_7; 4944 __le16 flow_handle_8; 4945 __le16 flow_handle_9; 4946 u8 unused_0[2]; 4947}; 4948 4949/* hwrm_cfa_flow_stats_output (size:1408b/176B) */ 4950struct hwrm_cfa_flow_stats_output { 4951 __le16 error_code; 4952 __le16 req_type; 4953 __le16 seq_id; 4954 __le16 resp_len; 4955 __le64 packet_0; 4956 __le64 packet_1; 4957 __le64 packet_2; 4958 __le64 packet_3; 4959 __le64 packet_4; 4960 __le64 packet_5; 4961 __le64 packet_6; 4962 __le64 packet_7; 4963 __le64 packet_8; 4964 __le64 packet_9; 4965 __le64 byte_0; 4966 __le64 byte_1; 4967 __le64 byte_2; 4968 __le64 byte_3; 4969 __le64 byte_4; 4970 __le64 byte_5; 4971 __le64 byte_6; 4972 __le64 byte_7; 4973 __le64 byte_8; 4974 __le64 byte_9; 4975 u8 unused_0[7]; 4976 u8 valid; 4977}; 4978 4979/* hwrm_cfa_vfr_alloc_input (size:448b/56B) */ 4980struct hwrm_cfa_vfr_alloc_input { 4981 __le16 req_type; 4982 __le16 cmpl_ring; 4983 __le16 seq_id; 4984 __le16 target_id; 4985 __le64 resp_addr; 4986 __le16 vf_id; 4987 __le16 reserved; 4988 u8 unused_0[4]; 4989 char vfr_name[32]; 4990}; 4991 4992/* hwrm_cfa_vfr_alloc_output (size:128b/16B) */ 4993struct hwrm_cfa_vfr_alloc_output { 4994 __le16 error_code; 4995 __le16 req_type; 4996 __le16 seq_id; 4997 __le16 resp_len; 4998 __le16 rx_cfa_code; 4999 __le16 tx_cfa_action; 5000 u8 unused_0[3];
5001 u8 valid; 5002}; 5003 5004/* hwrm_cfa_vfr_free_input (size:384b/48B) */ 5005struct hwrm_cfa_vfr_free_input { 5006 __le16 req_type; 5007 __le16 cmpl_ring; 5008 __le16 seq_id; 5009 __le16 target_id; 5010 __le64 resp_addr; 5011 char vfr_name[32]; 5012}; 5013 5014/* hwrm_cfa_vfr_free_output (size:128b/16B) */ 5015struct hwrm_cfa_vfr_free_output { 5016 __le16 error_code; 5017 __le16 req_type; 5018 __le16 seq_id; 5019 __le16 resp_len; 5020 u8 unused_0[7]; 5021 u8 valid; 5022}; 5023 5024/* hwrm_tunnel_dst_port_query_input (size:192b/24B) */ 5025struct hwrm_tunnel_dst_port_query_input { 5026 __le16 req_type; 5027 __le16 cmpl_ring; 5028 __le16 seq_id; 5029 __le16 target_id; 5030 __le64 resp_addr; 5031 u8 tunnel_type; 5032 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5033 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5034 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5035 #define TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_QUERY_REQ_TUNNEL_TYPE_VXLAN_V4 5036 u8 unused_0[7]; 5037}; 5038 5039/* hwrm_tunnel_dst_port_query_output (size:128b/16B) */ 5040struct hwrm_tunnel_dst_port_query_output { 5041 __le16 error_code; 5042 __le16 req_type; 5043 __le16 seq_id; 5044 __le16 resp_len; 5045 __le16 tunnel_dst_port_id; 5046 __be16 tunnel_dst_port_val; 5047 u8 unused_0[3]; 5048 u8 valid; 5049}; 5050 5051/* hwrm_tunnel_dst_port_alloc_input (size:192b/24B) */ 5052struct hwrm_tunnel_dst_port_alloc_input { 5053 __le16 req_type; 5054 __le16 cmpl_ring; 5055 __le16 seq_id; 5056 __le16 target_id; 5057 __le64 resp_addr; 5058 u8 tunnel_type; 5059 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5060 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5061 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5062 #define TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_ALLOC_REQ_TUNNEL_TYPE_VXLAN_V4 5063 u8 unused_0; 5064 __be16 tunnel_dst_port_val; 5065 u8 unused_1[4]; 5066}; 5067 5068/* hwrm_tunnel_dst_port_alloc_output (size:128b/16B) */ 5069struct hwrm_tunnel_dst_port_alloc_output { 5070 __le16 error_code; 5071 __le16 req_type; 5072 __le16 seq_id; 5073 __le16 resp_len; 5074 __le16 tunnel_dst_port_id; 5075 u8 unused_0[5]; 5076 u8 valid; 5077}; 5078 5079/* hwrm_tunnel_dst_port_free_input (size:192b/24B) */ 5080struct hwrm_tunnel_dst_port_free_input { 5081 __le16 req_type; 5082 __le16 cmpl_ring; 5083 __le16 seq_id; 5084 __le16 target_id; 5085 __le64 resp_addr; 5086 u8 tunnel_type; 5087 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN 0x1UL 5088 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_GENEVE 0x5UL 5089 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 0x9UL 5090 #define TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_LAST TUNNEL_DST_PORT_FREE_REQ_TUNNEL_TYPE_VXLAN_V4 5091 u8 unused_0; 5092 __le16 tunnel_dst_port_id; 5093 u8 unused_1[4]; 5094}; 5095 5096/* hwrm_tunnel_dst_port_free_output (size:128b/16B) */ 5097struct hwrm_tunnel_dst_port_free_output { 5098 __le16 error_code; 5099 __le16 req_type; 5100 __le16 seq_id; 5101 __le16 resp_len; 5102 u8 unused_1[7]; 5103 u8 valid; 5104}; 5105 5106/* ctx_hw_stats (size:1280b/160B) */ 5107struct ctx_hw_stats { 5108 __le64 rx_ucast_pkts; 5109 __le64 rx_mcast_pkts; 5110 __le64 rx_bcast_pkts; 5111 __le64 rx_discard_pkts; 5112 __le64 rx_drop_pkts; 5113 __le64 rx_ucast_bytes; 5114 __le64 rx_mcast_bytes; 5115 __le64 rx_bcast_bytes; 5116 __le64 tx_ucast_pkts; 5117 __le64 tx_mcast_pkts; 5118 __le64 tx_bcast_pkts; 5119 __le64 tx_discard_pkts; 5120 __le64 tx_drop_pkts; 5121 __le64 tx_ucast_bytes; 5122 __le64 tx_mcast_bytes; 5123 __le64 tx_bcast_bytes; 5124 __le64 tpa_pkts; 5125 __le64 tpa_bytes; 5126 __le64 tpa_events; 5127 __le64 tpa_aborts; 5128}; 5129 5130/* hwrm_stat_ctx_alloc_input (size:256b/32B) */ 5131struct hwrm_stat_ctx_alloc_input { 5132 __le16 req_type; 5133 __le16 cmpl_ring; 5134 __le16 seq_id; 5135 __le16 target_id; 5136 __le64 resp_addr; 5137 __le64 stats_dma_addr; 5138 __le32 update_period_ms; 5139 u8 stat_ctx_flags; 5140 #define STAT_CTX_ALLOC_REQ_STAT_CTX_FLAGS_ROCE 0x1UL 5141 u8 unused_0[3]; 5142}; 5143 5144/* hwrm_stat_ctx_alloc_output (size:128b/16B) */ 5145struct hwrm_stat_ctx_alloc_output { 5146 __le16 error_code; 5147 __le16 req_type; 5148 __le16 seq_id; 5149 __le16 resp_len; 5150 __le32 stat_ctx_id; 5151 u8 unused_0[3]; 5152 u8 valid; 5153}; 5154 5155/* hwrm_stat_ctx_free_input (size:192b/24B) */ 5156struct hwrm_stat_ctx_free_input { 5157 __le16 req_type; 5158 __le16 cmpl_ring; 5159 __le16 seq_id; 5160 __le16 target_id; 5161 __le64 resp_addr; 5162 __le32 stat_ctx_id; 5163 u8 unused_0[4]; 5164}; 5165 5166/* hwrm_stat_ctx_free_output (size:128b/16B) */ 5167struct hwrm_stat_ctx_free_output { 5168 __le16 error_code; 5169 __le16 req_type; 5170 __le16 seq_id; 5171 __le16 resp_len; 5172 __le32 stat_ctx_id; 5173 u8 unused_0[3]; 5174 u8 valid; 5175}; 5176 5177/* hwrm_stat_ctx_query_input (size:192b/24B) */ 5178struct hwrm_stat_ctx_query_input { 5179 __le16 req_type; 5180 __le16 cmpl_ring; 5181 __le16 seq_id; 5182 __le16 target_id; 5183 __le64 resp_addr; 5184 __le32 stat_ctx_id; 5185 u8 unused_0[4]; 5186}; 5187 5188/* hwrm_stat_ctx_query_output (size:1408b/176B) */ 5189struct hwrm_stat_ctx_query_output { 5190 __le16 error_code; 5191 __le16 req_type; 5192 __le16 seq_id; 5193 __le16 resp_len; 5194 __le64 tx_ucast_pkts; 5195 __le64 tx_mcast_pkts; 5196 __le64 tx_bcast_pkts; 5197 __le64 tx_err_pkts; 5198 __le64 tx_drop_pkts; 5199 __le64 tx_ucast_bytes; 5200 __le64 tx_mcast_bytes; 5201 __le64 tx_bcast_bytes; 5202 __le64 rx_ucast_pkts; 5203 __le64 rx_mcast_pkts; 5204 __le64 rx_bcast_pkts; 5205 __le64 rx_err_pkts; 5206 __le64 rx_drop_pkts; 5207 __le64 rx_ucast_bytes; 5208 __le64 rx_mcast_bytes; 5209 __le64 rx_bcast_bytes; 5210 __le64 rx_agg_pkts; 5211 __le64 rx_agg_bytes; 5212 __le64 rx_agg_events; 5213 __le64 rx_agg_aborts; 5214 u8 unused_0[7]; 5215 u8 valid; 5216}; 5217 5218/* hwrm_stat_ctx_clr_stats_input (size:192b/24B) */ 5219struct hwrm_stat_ctx_clr_stats_input { 5220 __le16 req_type; 5221 __le16 cmpl_ring; 5222 __le16 seq_id; 5223 __le16 target_id; 5224 __le64 resp_addr; 5225 __le32 stat_ctx_id; 5226 u8 unused_0[4]; 5227}; 5228 5229/* hwrm_stat_ctx_clr_stats_output (size:128b/16B) */ 5230struct hwrm_stat_ctx_clr_stats_output { 5231 __le16 error_code; 5232 __le16 req_type; 5233 __le16 seq_id; 5234 __le16 resp_len; 5235 u8 unused_0[7]; 5236 u8 valid; 5237}; 5238 5239/* hwrm_pcie_qstats_input (size:256b/32B) */ 5240struct hwrm_pcie_qstats_input { 5241 __le16 req_type; 5242 __le16 cmpl_ring; 5243 __le16 seq_id; 5244 __le16 target_id; 5245 __le64 resp_addr; 5246 __le16 pcie_stat_size; 5247 u8 unused_0[6]; 5248 __le64 pcie_stat_host_addr; 5249}; 5250 5251/* hwrm_pcie_qstats_output (size:128b/16B) */ 5252struct hwrm_pcie_qstats_output { 5253 __le16 error_code; 5254 __le16 req_type; 5255 __le16 seq_id; 5256 __le16 resp_len; 5257 __le16 pcie_stat_size; 5258 u8 unused_0[5]; 5259 u8 valid; 5260}; 5261 5262/* tx_port_stats (size:3264b/408B) */ 5263struct tx_port_stats { 5264 __le64 tx_64b_frames; 5265 __le64 tx_65b_127b_frames; 5266 __le64 tx_128b_255b_frames; 5267 __le64 tx_256b_511b_frames; 5268 __le64 tx_512b_1023b_frames; 5269 __le64 tx_1024b_1518_frames; 5270 __le64 tx_good_vlan_frames; 5271 __le64 tx_1519b_2047_frames; 5272 __le64 tx_2048b_4095b_frames; 5273 __le64 tx_4096b_9216b_frames; 5274 __le64 tx_9217b_16383b_frames; 5275 __le64 tx_good_frames; 5276 __le64 tx_total_frames; 5277 __le64 tx_ucast_frames; 5278 __le64 tx_mcast_frames; 5279 __le64 tx_bcast_frames; 5280 __le64 tx_pause_frames; 5281 __le64 tx_pfc_frames; 5282 __le64 tx_jabber_frames; 5283 __le64 tx_fcs_err_frames; 5284 __le64 tx_control_frames; 5285 __le64 tx_oversz_frames; 5286 __le64 tx_single_dfrl_frames; 5287 __le64 tx_multi_dfrl_frames; 5288 __le64 tx_single_coll_frames; 5289 __le64 tx_multi_coll_frames; 5290 __le64 tx_late_coll_frames; 5291 __le64 tx_excessive_coll_frames; 5292 __le64 tx_frag_frames; 5293 __le64 tx_err; 5294 __le64 tx_tagged_frames; 5295 __le64 tx_dbl_tagged_frames; 5296 __le64 tx_runt_frames; 5297 __le64 tx_fifo_underruns; 5298 __le64 tx_pfc_ena_frames_pri0; 5299 __le64 tx_pfc_ena_frames_pri1; 5300 __le64 tx_pfc_ena_frames_pri2; 5301 __le64 tx_pfc_ena_frames_pri3; 5302 __le64 tx_pfc_ena_frames_pri4; 5303 __le64 tx_pfc_ena_frames_pri5; 5304 __le64 tx_pfc_ena_frames_pri6; 5305 __le64 tx_pfc_ena_frames_pri7; 5306 __le64 tx_eee_lpi_events; 5307 __le64 tx_eee_lpi_duration; 5308 __le64 tx_llfc_logical_msgs; 5309 __le64 tx_hcfc_msgs; 5310 __le64 tx_total_collisions; 5311 __le64 tx_bytes; 5312 __le64 tx_xthol_frames; 5313 __le64 tx_stat_discard; 5314 __le64 tx_stat_error; 5315}; 5316 5317/* rx_port_stats (size:4224b/528B) */ 5318struct rx_port_stats { 5319 __le64 rx_64b_frames; 5320 __le64 rx_65b_127b_frames; 5321 __le64 rx_128b_255b_frames; 5322 __le64 rx_256b_511b_frames; 5323 __le64 rx_512b_1023b_frames; 5324 __le64 rx_1024b_1518_frames; 5325 __le64 rx_good_vlan_frames; 5326 __le64 rx_1519b_2047b_frames; 5327 __le64 rx_2048b_4095b_frames; 5328 __le64 rx_4096b_9216b_frames; 5329 __le64 rx_9217b_16383b_frames; 5330 __le64 rx_total_frames; 5331 __le64 rx_ucast_frames; 5332 __le64 rx_mcast_frames; 5333 __le64 rx_bcast_frames; 5334 __le64 rx_fcs_err_frames; 5335 __le64 rx_ctrl_frames; 5336 __le64 rx_pause_frames; 5337 __le64 rx_pfc_frames; 5338 __le64 rx_unsupported_opcode_frames; 5339 __le64 rx_unsupported_da_pausepfc_frames; 5340 __le64 rx_wrong_sa_frames; 5341 __le64 rx_align_err_frames; 5342 __le64 rx_oor_len_frames; 5343 __le64 rx_code_err_frames; 5344 __le64 rx_false_carrier_frames; 5345 __le64 rx_ovrsz_frames; 5346 __le64 rx_jbr_frames; 5347 __le64 rx_mtu_err_frames; 5348 __le64 rx_match_crc_frames; 5349 __le64 rx_promiscuous_frames; 5350 __le64 rx_tagged_frames; 5351 __le64 rx_double_tagged_frames; 5352 __le64 rx_trunc_frames; 5353 __le64 rx_good_frames; 5354 __le64 rx_pfc_xon2xoff_frames_pri0; 5355 __le64 rx_pfc_xon2xoff_frames_pri1; 5356 __le64 rx_pfc_xon2xoff_frames_pri2; 5357 __le64 rx_pfc_xon2xoff_frames_pri3; 5358 __le64 rx_pfc_xon2xoff_frames_pri4; 5359 __le64 rx_pfc_xon2xoff_frames_pri5; 5360 __le64 rx_pfc_xon2xoff_frames_pri6; 5361 __le64 rx_pfc_xon2xoff_frames_pri7; 5362 __le64 rx_pfc_ena_frames_pri0; 5363 __le64 rx_pfc_ena_frames_pri1; 5364 __le64 rx_pfc_ena_frames_pri2; 5365 __le64 rx_pfc_ena_frames_pri3; 5366 __le64 rx_pfc_ena_frames_pri4; 5367 __le64 rx_pfc_ena_frames_pri5; 5368 __le64 rx_pfc_ena_frames_pri6; 5369 __le64 rx_pfc_ena_frames_pri7; 5370 __le64 rx_sch_crc_err_frames; 5371 __le64 rx_undrsz_frames; 5372 __le64 rx_frag_frames; 5373 __le64 rx_eee_lpi_events; 5374 __le64 rx_eee_lpi_duration; 5375 __le64 rx_llfc_physical_msgs; 5376 __le64 rx_llfc_logical_msgs; 5377 __le64 rx_llfc_msgs_with_crc_err; 5378 __le64 rx_hcfc_msgs; 5379 __le64 rx_hcfc_msgs_with_crc_err; 5380 __le64 rx_bytes; 5381 __le64 rx_runt_bytes; 5382 __le64 rx_runt_frames; 5383 __le64 rx_stat_discard; 5384 __le64 rx_stat_err; 5385}; 5386 5387/* rx_port_stats_ext (size:320b/40B) */ 5388struct rx_port_stats_ext { 5389 __le64 link_down_events; 5390 __le64 continuous_pause_events; 5391 __le64 resume_pause_events; 5392 __le64 continuous_roce_pause_events; 5393 __le64 resume_roce_pause_events; 5394}; 5395 5396/* pcie_ctx_hw_stats (size:768b/96B) */ 5397struct pcie_ctx_hw_stats { 5398 __le64 pcie_pl_signal_integrity; 5399 __le64 pcie_dl_signal_integrity; 5400 __le64 pcie_tl_signal_integrity; 5401 __le64 pcie_link_integrity; 5402 __le64 pcie_tx_traffic_rate; 5403 __le64 pcie_rx_traffic_rate; 5404 __le64 pcie_tx_dllp_statistics; 5405 __le64 pcie_rx_dllp_statistics; 5406 __le64 pcie_equalization_time; 5407 __le32 pcie_ltssm_histogram[4]; 5408 __le64 pcie_recovery_histogram; 5409}; 5410 5411/* hwrm_fw_reset_input (size:192b/24B) */ 5412struct hwrm_fw_reset_input { 5413 __le16 req_type; 5414 __le16 cmpl_ring; 5415 __le16 seq_id; 5416 __le16 target_id; 5417 __le64 resp_addr; 5418 u8 embedded_proc_type; 5419 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5420 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5421 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5422 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5423 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5424 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5425 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5426 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 0x7UL 5427 #define FW_RESET_REQ_EMBEDDED_PROC_TYPE_LAST FW_RESET_REQ_EMBEDDED_PROC_TYPE_HOST_RESOURCE_REINIT 5428 u8 selfrst_status; 5429 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTNONE 0x0UL 5430 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTASAP 0x1UL 5431 #define FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5432 #define FW_RESET_REQ_SELFRST_STATUS_LAST FW_RESET_REQ_SELFRST_STATUS_SELFRSTPCIERST 5433 u8 host_idx; 5434 u8 unused_0[5]; 5435}; 5436 5437/* hwrm_fw_reset_output (size:128b/16B) */ 5438struct hwrm_fw_reset_output { 5439 __le16 error_code; 5440 __le16 req_type; 5441 __le16 seq_id; 5442 __le16 resp_len; 5443 u8 selfrst_status; 5444 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5445 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5446 #define FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5447 #define FW_RESET_RESP_SELFRST_STATUS_LAST FW_RESET_RESP_SELFRST_STATUS_SELFRSTPCIERST 5448 u8 unused_0[6]; 5449 u8 valid; 5450}; 5451 5452/* hwrm_fw_qstatus_input (size:192b/24B) */ 5453struct hwrm_fw_qstatus_input { 5454 __le16 req_type; 5455 __le16 cmpl_ring; 5456 __le16 seq_id; 5457 __le16 target_id; 5458 __le64 resp_addr; 5459 u8 embedded_proc_type; 5460 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_BOOT 0x0UL 5461 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_MGMT 0x1UL 5462 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_NETCTRL 0x2UL 5463 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_ROCE 0x3UL 5464 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_HOST 0x4UL 5465 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_AP 0x5UL 5466 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 0x6UL 5467 #define FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_LAST FW_QSTATUS_REQ_EMBEDDED_PROC_TYPE_CHIP 5468 u8 unused_0[7]; 5469}; 5470 5471/* hwrm_fw_qstatus_output (size:128b/16B) */ 5472struct hwrm_fw_qstatus_output { 5473 __le16 error_code; 5474 __le16 req_type; 5475 __le16 seq_id; 5476 __le16 resp_len; 5477 u8 selfrst_status; 5478 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTNONE 0x0UL 5479 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTASAP 0x1UL 5480 #define FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 0x2UL 5481 #define FW_QSTATUS_RESP_SELFRST_STATUS_LAST FW_QSTATUS_RESP_SELFRST_STATUS_SELFRSTPCIERST 5482 u8 unused_0[6]; 5483 u8 valid; 5484}; 5485 5486/* hwrm_fw_set_time_input (size:256b/32B) */ 5487struct hwrm_fw_set_time_input { 5488 __le16 req_type; 5489 __le16 cmpl_ring; 5490 __le16 seq_id; 5491 __le16 target_id; 5492 __le64 resp_addr; 5493 __le16 year; 5494 #define FW_SET_TIME_REQ_YEAR_UNKNOWN 0x0UL 5495 #define FW_SET_TIME_REQ_YEAR_LAST FW_SET_TIME_REQ_YEAR_UNKNOWN 5496 u8 month; 5497 u8 day; 5498 u8 hour; 5499 u8 minute; 5500 u8 second; 5501 u8 unused_0; 5502 __le16 millisecond; 5503 __le16 zone; 5504 #define FW_SET_TIME_REQ_ZONE_UTC 0x0UL 5505 #define FW_SET_TIME_REQ_ZONE_UNKNOWN 0xffffUL 5506 #define FW_SET_TIME_REQ_ZONE_LAST FW_SET_TIME_REQ_ZONE_UNKNOWN 5507 u8 unused_1[4]; 5508}; 5509 5510/* hwrm_fw_set_time_output (size:128b/16B) */ 5511struct hwrm_fw_set_time_output { 5512 __le16 error_code; 5513 __le16 req_type; 5514 __le16 seq_id; 5515 __le16 resp_len; 5516 u8 unused_0[7]; 5517 u8 valid; 5518}; 5519 5520/* hwrm_struct_hdr (size:128b/16B) */ 5521struct hwrm_struct_hdr { 5522 __le16 struct_id; 5523 #define STRUCT_HDR_STRUCT_ID_LLDP_CFG 0x41bUL 5524 #define STRUCT_HDR_STRUCT_ID_DCBX_ETS 0x41dUL 5525 #define STRUCT_HDR_STRUCT_ID_DCBX_PFC 0x41fUL 5526 #define STRUCT_HDR_STRUCT_ID_DCBX_APP 0x421UL 5527 #define STRUCT_HDR_STRUCT_ID_DCBX_FEATURE_STATE 0x422UL 5528 #define STRUCT_HDR_STRUCT_ID_LLDP_GENERIC 0x424UL 5529 #define STRUCT_HDR_STRUCT_ID_LLDP_DEVICE 0x426UL 5530 #define STRUCT_HDR_STRUCT_ID_AFM_OPAQUE 0x1UL 5531 #define STRUCT_HDR_STRUCT_ID_PORT_DESCRIPTION 0xaUL 5532 #define STRUCT_HDR_STRUCT_ID_RSS_V2 0x64UL 5533 #define STRUCT_HDR_STRUCT_ID_LAST STRUCT_HDR_STRUCT_ID_RSS_V2 5534 __le16 len; 5535 u8 version; 5536 u8 count; 5537 __le16 subtype; 5538 __le16 next_offset; 5539 #define STRUCT_HDR_NEXT_OFFSET_LAST 0x0UL 5540 u8 unused_0[6]; 5541}; 5542 5543/* hwrm_struct_data_dcbx_app (size:64b/8B) */ 5544struct hwrm_struct_data_dcbx_app { 5545 __be16 protocol_id; 5546 u8 protocol_selector; 5547 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_ETHER_TYPE 0x1UL 5548 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_PORT 0x2UL 5549 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_UDP_PORT 0x3UL 5550 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 0x4UL 5551 #define STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_LAST STRUCT_DATA_DCBX_APP_PROTOCOL_SELECTOR_TCP_UDP_PORT 5552 u8 priority; 5553 u8 valid; 5554 u8 unused_0[3]; 5555}; 5556 5557/* hwrm_fw_set_structured_data_input (size:256b/32B) */ 5558struct hwrm_fw_set_structured_data_input { 5559 __le16 req_type; 5560 __le16 cmpl_ring; 5561 __le16 seq_id; 5562 __le16 target_id; 5563 __le64 resp_addr; 5564 __le64 src_data_addr; 5565 __le16 data_len; 5566 u8 hdr_cnt; 5567 u8 unused_0[5]; 5568}; 5569 5570/* hwrm_fw_set_structured_data_output (size:128b/16B) */ 5571struct hwrm_fw_set_structured_data_output { 5572 __le16 error_code; 5573 __le16 req_type; 5574 __le16 seq_id; 5575 __le16 resp_len; 5576 u8 unused_0[7]; 5577 u8 valid; 5578}; 5579 5580/* hwrm_fw_set_structured_data_cmd_err (size:64b/8B) */ 5581struct hwrm_fw_set_structured_data_cmd_err { 5582 u8 code; 5583 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5584 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_HDR_CNT 0x1UL 5585 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_FMT 0x2UL 5586 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5587 #define FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_SET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 5588 u8 unused_0[7]; 5589}; 5590 5591/* hwrm_fw_get_structured_data_input (size:256b/32B) */ 5592struct hwrm_fw_get_structured_data_input { 5593 __le16 req_type; 5594 __le16 cmpl_ring; 5595 __le16 seq_id; 5596 __le16 target_id; 5597 __le64 resp_addr; 5598 __le64 dest_data_addr; 5599 __le16 data_len; 5600 __le16 structure_id; 5601 __le16 subtype; 5602 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_UNUSED 0x0UL 5603 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_ALL 0xffffUL 5604 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_ADMIN 0x100UL 5605 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_PEER 0x101UL 5606 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NEAR_BRIDGE_OPERATIONAL 0x102UL 5607 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_ADMIN 0x200UL 5608 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_PEER 0x201UL 5609 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_NON_TPMR_OPERATIONAL 0x202UL 5610 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 0x300UL 5611 #define FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_LAST FW_GET_STRUCTURED_DATA_REQ_SUBTYPE_HOST_OPERATIONAL 5612 u8 count; 5613 u8 unused_0; 5614}; 5615 5616/* hwrm_fw_get_structured_data_output (size:128b/16B) */ 5617struct hwrm_fw_get_structured_data_output { 5618 __le16 error_code; 5619 __le16 req_type; 5620 __le16 seq_id; 5621 __le16 resp_len; 5622 u8 hdr_cnt; 5623 u8 unused_0[6]; 5624 u8 valid; 5625}; 5626 5627/* hwrm_fw_get_structured_data_cmd_err (size:64b/8B) */ 5628struct hwrm_fw_get_structured_data_cmd_err { 5629 u8 code; 5630 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_UNKNOWN 0x0UL 5631 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 0x3UL 5632 #define FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_LAST FW_GET_STRUCTURED_DATA_CMD_ERR_CODE_BAD_ID 5633 u8 unused_0[7]; 5634}; 5635 5636/* hwrm_exec_fwd_resp_input (size:1024b/128B) */ 5637struct hwrm_exec_fwd_resp_input { 5638 __le16 req_type; 5639 __le16 cmpl_ring; 5640 __le16 seq_id; 5641 __le16 target_id; 5642 __le64 resp_addr; 5643 __le32 encap_request[26]; 5644 __le16 encap_resp_target_id; 5645 u8 unused_0[6]; 5646}; 5647 5648/* hwrm_exec_fwd_resp_output (size:128b/16B) */ 5649struct hwrm_exec_fwd_resp_output { 5650 __le16 error_code; 5651 __le16 req_type; 5652 __le16 seq_id; 5653 __le16 resp_len; 5654 u8 unused_0[7]; 5655 u8 valid; 5656}; 5657 5658/* hwrm_reject_fwd_resp_input (size:1024b/128B) */ 5659struct hwrm_reject_fwd_resp_input { 5660 __le16 req_type; 5661 __le16 cmpl_ring; 5662 __le16 seq_id; 5663 __le16 target_id; 5664 __le64 resp_addr; 5665 __le32 encap_request[26]; 5666 __le16 encap_resp_target_id; 5667 u8 unused_0[6]; 5668}; 5669 5670/* hwrm_reject_fwd_resp_output (size:128b/16B) */ 5671struct hwrm_reject_fwd_resp_output { 5672 __le16 error_code; 5673 __le16 req_type; 5674 __le16 seq_id; 5675 __le16 resp_len; 5676 u8 unused_0[7]; 5677 u8 valid; 5678}; 5679 5680/* hwrm_fwd_resp_input (size:1024b/128B) */ 5681struct hwrm_fwd_resp_input { 5682 __le16 req_type; 5683 __le16 cmpl_ring; 5684 __le16 seq_id; 5685 __le16 target_id; 5686 __le64 resp_addr; 5687 __le16 encap_resp_target_id; 5688 __le16 encap_resp_cmpl_ring; 5689 __le16 encap_resp_len; 5690 u8 unused_0; 5691 u8 unused_1; 5692 __le64 encap_resp_addr; 5693 __le32 encap_resp[24]; 5694}; 5695 5696/* hwrm_fwd_resp_output (size:128b/16B) */ 5697struct hwrm_fwd_resp_output { 5698 __le16 error_code; 5699 __le16 req_type; 5700 __le16 seq_id; 5701 __le16 resp_len; 5702 u8 unused_0[7]; 5703 u8 valid; 5704}; 5705 5706/* hwrm_fwd_async_event_cmpl_input (size:320b/40B) */ 5707struct hwrm_fwd_async_event_cmpl_input { 5708 __le16 req_type; 5709 __le16 cmpl_ring; 5710 __le16 seq_id; 5711 __le16 target_id; 5712 __le64 resp_addr; 5713 __le16 encap_async_event_target_id; 5714 u8 unused_0[6]; 5715 __le32 encap_async_event_cmpl[4]; 5716}; 5717 5718/* hwrm_fwd_async_event_cmpl_output (size:128b/16B) */ 5719struct hwrm_fwd_async_event_cmpl_output { 5720 __le16 error_code; 5721 __le16 req_type; 5722 __le16 seq_id; 5723 __le16 resp_len; 5724 u8 unused_0[7]; 5725 u8 valid; 5726}; 5727 5728/* hwrm_temp_monitor_query_input (size:128b/16B) */ 5729struct hwrm_temp_monitor_query_input { 5730 __le16 req_type; 5731 __le16 cmpl_ring; 5732 __le16 seq_id; 5733 __le16 target_id; 5734 __le64 resp_addr; 5735}; 5736 5737/* hwrm_temp_monitor_query_output (size:128b/16B) */ 5738struct hwrm_temp_monitor_query_output { 5739 __le16 error_code; 5740 __le16 req_type; 5741 __le16 seq_id; 5742 __le16 resp_len; 5743 u8 temp; 5744 u8 unused_0[6]; 5745 u8 valid; 5746}; 5747 5748/* hwrm_wol_filter_alloc_input (size:512b/64B) */ 5749struct hwrm_wol_filter_alloc_input { 5750 __le16 req_type; 5751 __le16 cmpl_ring; 5752 __le16 seq_id; 5753 __le16 target_id; 5754 __le64 resp_addr; 5755 __le32 flags; 5756 __le32 enables; 5757 #define WOL_FILTER_ALLOC_REQ_ENABLES_MAC_ADDRESS 0x1UL 5758 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_OFFSET 0x2UL 5759 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_SIZE 0x4UL 5760 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_BUF_ADDR 0x8UL 5761 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_ADDR 0x10UL 5762 #define WOL_FILTER_ALLOC_REQ_ENABLES_PATTERN_MASK_SIZE 0x20UL 5763 __le16 port_id; 5764 u8 wol_type; 5765 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_MAGICPKT 0x0UL 5766 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_BMP 0x1UL 5767 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 0xffUL 5768 #define WOL_FILTER_ALLOC_REQ_WOL_TYPE_LAST WOL_FILTER_ALLOC_REQ_WOL_TYPE_INVALID 5769 u8 unused_0[5]; 5770 u8 mac_address[6]; 5771 __le16 pattern_offset; 5772 __le16 pattern_buf_size; 5773 __le16 pattern_mask_size; 5774 u8 unused_1[4]; 5775 __le64 pattern_buf_addr; 5776 __le64 pattern_mask_addr; 5777}; 5778 5779/* hwrm_wol_filter_alloc_output (size:128b/16B) */ 5780struct hwrm_wol_filter_alloc_output { 5781 __le16 error_code; 5782 __le16 req_type; 5783 __le16 seq_id; 5784 __le16 resp_len; 5785 u8 wol_filter_id; 5786 u8 unused_0[6]; 5787 u8 valid; 5788}; 5789 5790/* hwrm_wol_filter_free_input (size:256b/32B) */ 5791struct hwrm_wol_filter_free_input { 5792 __le16 req_type; 5793 __le16 cmpl_ring; 5794 __le16 seq_id; 5795 __le16 target_id; 5796 __le64 resp_addr; 5797 __le32 flags; 5798 #define WOL_FILTER_FREE_REQ_FLAGS_FREE_ALL_WOL_FILTERS 0x1UL 5799 __le32 enables; 5800 #define WOL_FILTER_FREE_REQ_ENABLES_WOL_FILTER_ID 0x1UL 5801 __le16 port_id; 5802 u8 wol_filter_id; 5803 u8 unused_0[5]; 5804}; 5805 5806/* hwrm_wol_filter_free_output (size:128b/16B) */ 5807struct hwrm_wol_filter_free_output { 5808 __le16 error_code; 5809 __le16 req_type; 5810 __le16 seq_id; 5811 __le16 resp_len; 5812 u8 unused_0[7]; 5813 u8 valid; 5814}; 5815 5816/* hwrm_wol_filter_qcfg_input (size:448b/56B) */ 5817struct hwrm_wol_filter_qcfg_input { 5818 __le16 req_type; 5819 __le16 cmpl_ring; 5820 __le16 seq_id; 5821 __le16 target_id; 5822 __le64 resp_addr; 5823 __le16 port_id; 5824 __le16 handle; 5825 u8 unused_0[4]; 5826 __le64 pattern_buf_addr; 5827 __le16 pattern_buf_size; 5828 u8 unused_1[6]; 5829 __le64 pattern_mask_addr; 5830 __le16 pattern_mask_size; 5831 u8 unused_2[6]; 5832}; 5833 5834/* hwrm_wol_filter_qcfg_output (size:256b/32B) */ 5835struct hwrm_wol_filter_qcfg_output { 5836 __le16 error_code; 5837 __le16 req_type; 5838 __le16 seq_id; 5839 __le16 resp_len; 5840 __le16 next_handle; 5841 u8 wol_filter_id; 5842 u8 wol_type; 5843 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_MAGICPKT 0x0UL 5844 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_BMP 0x1UL 5845 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 0xffUL 5846 #define WOL_FILTER_QCFG_RESP_WOL_TYPE_LAST WOL_FILTER_QCFG_RESP_WOL_TYPE_INVALID 5847 __le32 unused_0; 5848 u8 mac_address[6]; 5849 __le16 pattern_offset; 5850 __le16 pattern_size; 5851 __le16 pattern_mask_size; 5852 u8 unused_1[3]; 5853 u8 valid; 5854}; 5855 5856/* hwrm_wol_reason_qcfg_input (size:320b/40B) */ 5857struct hwrm_wol_reason_qcfg_input { 5858 __le16 req_type; 5859 __le16 cmpl_ring; 5860 __le16 seq_id; 5861 __le16 target_id; 5862 __le64 resp_addr; 5863 __le16 port_id; 5864 u8 unused_0[6]; 5865 __le64 wol_pkt_buf_addr; 5866 __le16 wol_pkt_buf_size; 5867 u8 unused_1[6]; 5868}; 5869 5870/* hwrm_wol_reason_qcfg_output (size:128b/16B) */ 5871struct hwrm_wol_reason_qcfg_output { 5872 __le16 error_code; 5873 __le16 req_type; 5874 __le16 seq_id; 5875 __le16 resp_len; 5876 u8 wol_filter_id; 5877 u8 wol_reason; 5878 #define WOL_REASON_QCFG_RESP_WOL_REASON_MAGICPKT 0x0UL 5879 #define WOL_REASON_QCFG_RESP_WOL_REASON_BMP 0x1UL 5880 #define WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 0xffUL 5881 #define WOL_REASON_QCFG_RESP_WOL_REASON_LAST WOL_REASON_QCFG_RESP_WOL_REASON_INVALID 5882 u8 wol_pkt_len; 5883 u8 unused_0[4]; 5884 u8 valid; 5885}; 5886 5887/* hwrm_nvm_read_input (size:320b/40B) */ 5888struct hwrm_nvm_read_input { 5889 __le16 req_type; 5890 __le16 cmpl_ring; 5891 __le16 seq_id; 5892 __le16 target_id; 5893 __le64 resp_addr; 5894 __le64 host_dest_addr; 5895 __le16 dir_idx; 5896 u8 unused_0[2]; 5897 __le32 offset; 5898 __le32 len; 5899 u8 unused_1[4]; 5900}; 5901 5902/* hwrm_nvm_read_output (size:128b/16B) */ 5903struct hwrm_nvm_read_output { 5904 __le16 error_code; 5905 __le16 req_type; 5906 __le16 seq_id; 5907 __le16 resp_len; 5908 u8 unused_0[7]; 5909 u8 valid; 5910}; 5911 5912/* hwrm_nvm_get_dir_entries_input (size:192b/24B) */ 5913struct hwrm_nvm_get_dir_entries_input { 5914 __le16 req_type; 5915 __le16 cmpl_ring; 5916 __le16 seq_id; 5917 __le16 target_id; 5918 __le64 resp_addr; 5919 __le64 host_dest_addr; 5920}; 5921 5922/* hwrm_nvm_get_dir_entries_output (size:128b/16B) */ 5923struct hwrm_nvm_get_dir_entries_output { 5924 __le16 error_code; 5925 __le16 req_type; 5926 __le16 seq_id; 5927 __le16 resp_len; 5928 u8 unused_0[7]; 5929 u8 valid; 5930}; 5931 5932/* hwrm_nvm_get_dir_info_input (size:128b/16B) */ 5933struct hwrm_nvm_get_dir_info_input { 5934 __le16 req_type; 5935 __le16 cmpl_ring; 5936 __le16 seq_id; 5937 __le16 target_id; 5938 __le64 resp_addr; 5939}; 5940 5941/* hwrm_nvm_get_dir_info_output (size:192b/24B) */ 5942struct hwrm_nvm_get_dir_info_output { 5943 __le16 error_code; 5944 __le16 req_type; 5945 __le16 seq_id; 5946 __le16 resp_len; 5947 __le32 entries; 5948 __le32 entry_length; 5949 u8 unused_0[7]; 5950 u8 valid; 5951}; 5952 5953/* hwrm_nvm_write_input (size:384b/48B) */ 5954struct hwrm_nvm_write_input { 5955 __le16 req_type; 5956 __le16 cmpl_ring; 5957 __le16 seq_id; 5958 __le16 target_id; 5959 __le64 resp_addr; 5960 __le64 host_src_addr; 5961 __le16 dir_type; 5962 __le16 dir_ordinal; 5963 __le16 dir_ext; 5964 __le16 dir_attr; 5965 __le32 dir_data_length; 5966 __le16 option; 5967 __le16 flags; 5968 #define NVM_WRITE_REQ_FLAGS_KEEP_ORIG_ACTIVE_IMG 0x1UL 5969 __le32 dir_item_length; 5970 __le32 unused_0; 5971}; 5972 5973/* hwrm_nvm_write_output (size:128b/16B) */ 5974struct hwrm_nvm_write_output { 5975 __le16 error_code; 5976 __le16 req_type; 5977 __le16 seq_id; 5978 __le16 resp_len; 5979 __le32 dir_item_length; 5980 __le16 dir_idx; 5981 u8 unused_0; 5982 u8 valid; 5983}; 5984 5985/* hwrm_nvm_write_cmd_err (size:64b/8B) */ 5986struct hwrm_nvm_write_cmd_err { 5987 u8 code; 5988 #define NVM_WRITE_CMD_ERR_CODE_UNKNOWN 0x0UL 5989 #define NVM_WRITE_CMD_ERR_CODE_FRAG_ERR 0x1UL 5990 #define NVM_WRITE_CMD_ERR_CODE_NO_SPACE 0x2UL 5991 #define NVM_WRITE_CMD_ERR_CODE_LAST NVM_WRITE_CMD_ERR_CODE_NO_SPACE 5992 u8 unused_0[7]; 5993}; 5994 5995/* hwrm_nvm_modify_input (size:320b/40B) */ 5996struct hwrm_nvm_modify_input { 5997 __le16 req_type; 5998 __le16 cmpl_ring; 5999 __le16 seq_id; 6000 __le16 target_id;
6001 __le64 resp_addr; 6002 __le64 host_src_addr; 6003 __le16 dir_idx; 6004 u8 unused_0[2]; 6005 __le32 offset; 6006 __le32 len; 6007 u8 unused_1[4]; 6008}; 6009 6010/* hwrm_nvm_modify_output (size:128b/16B) */ 6011struct hwrm_nvm_modify_output { 6012 __le16 error_code; 6013 __le16 req_type; 6014 __le16 seq_id; 6015 __le16 resp_len; 6016 u8 unused_0[7]; 6017 u8 valid; 6018}; 6019 6020/* hwrm_nvm_find_dir_entry_input (size:256b/32B) */ 6021struct hwrm_nvm_find_dir_entry_input { 6022 __le16 req_type; 6023 __le16 cmpl_ring; 6024 __le16 seq_id; 6025 __le16 target_id; 6026 __le64 resp_addr; 6027 __le32 enables; 6028 #define NVM_FIND_DIR_ENTRY_REQ_ENABLES_DIR_IDX_VALID 0x1UL 6029 __le16 dir_idx; 6030 __le16 dir_type; 6031 __le16 dir_ordinal; 6032 __le16 dir_ext; 6033 u8 opt_ordinal; 6034 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_MASK 0x3UL 6035 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_SFT 0 6036 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_EQ 0x0UL 6037 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GE 0x1UL 6038 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 0x2UL 6039 #define NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_LAST NVM_FIND_DIR_ENTRY_REQ_OPT_ORDINAL_GT 6040 u8 unused_0[3]; 6041}; 6042 6043/* hwrm_nvm_find_dir_entry_output (size:256b/32B) */ 6044struct hwrm_nvm_find_dir_entry_output { 6045 __le16 error_code; 6046 __le16 req_type; 6047 __le16 seq_id; 6048 __le16 resp_len; 6049 __le32 dir_item_length; 6050 __le32 dir_data_length; 6051 __le32 fw_ver; 6052 __le16 dir_ordinal; 6053 __le16 dir_idx; 6054 u8 unused_0[7]; 6055 u8 valid; 6056}; 6057 6058/* hwrm_nvm_erase_dir_entry_input (size:192b/24B) */ 6059struct hwrm_nvm_erase_dir_entry_input { 6060 __le16 req_type; 6061 __le16 cmpl_ring; 6062 __le16 seq_id; 6063 __le16 target_id; 6064 __le64 resp_addr; 6065 __le16 dir_idx; 6066 u8 unused_0[6]; 6067}; 6068 6069/* hwrm_nvm_erase_dir_entry_output (size:128b/16B) */ 6070struct hwrm_nvm_erase_dir_entry_output { 6071 __le16 error_code; 6072 __le16 req_type; 6073 __le16 seq_id; 6074 __le16 resp_len; 6075 u8 unused_0[7]; 6076 u8 valid; 6077}; 6078 6079/* hwrm_nvm_get_dev_info_input (size:128b/16B) */ 6080struct hwrm_nvm_get_dev_info_input { 6081 __le16 req_type; 6082 __le16 cmpl_ring; 6083 __le16 seq_id; 6084 __le16 target_id; 6085 __le64 resp_addr; 6086}; 6087 6088/* hwrm_nvm_get_dev_info_output (size:256b/32B) */ 6089struct hwrm_nvm_get_dev_info_output { 6090 __le16 error_code; 6091 __le16 req_type; 6092 __le16 seq_id; 6093 __le16 resp_len; 6094 __le16 manufacturer_id; 6095 __le16 device_id; 6096 __le32 sector_size; 6097 __le32 nvram_size; 6098 __le32 reserved_size; 6099 __le32 available_size; 6100 u8 unused_0[3]; 6101 u8 valid; 6102}; 6103 6104/* hwrm_nvm_mod_dir_entry_input (size:256b/32B) */ 6105struct hwrm_nvm_mod_dir_entry_input { 6106 __le16 req_type; 6107 __le16 cmpl_ring; 6108 __le16 seq_id; 6109 __le16 target_id; 6110 __le64 resp_addr; 6111 __le32 enables; 6112 #define NVM_MOD_DIR_ENTRY_REQ_ENABLES_CHECKSUM 0x1UL 6113 __le16 dir_idx; 6114 __le16 dir_ordinal; 6115 __le16 dir_ext; 6116 __le16 dir_attr; 6117 __le32 checksum; 6118}; 6119 6120/* hwrm_nvm_mod_dir_entry_output (size:128b/16B) */ 6121struct hwrm_nvm_mod_dir_entry_output { 6122 __le16 error_code; 6123 __le16 req_type; 6124 __le16 seq_id; 6125 __le16 resp_len; 6126 u8 unused_0[7]; 6127 u8 valid; 6128}; 6129 6130/* hwrm_nvm_verify_update_input (size:192b/24B) */ 6131struct hwrm_nvm_verify_update_input { 6132 __le16 req_type; 6133 __le16 cmpl_ring; 6134 __le16 seq_id; 6135 __le16 target_id; 6136 __le64 resp_addr; 6137 __le16 dir_type; 6138 __le16 dir_ordinal; 6139 __le16 dir_ext; 6140 u8 unused_0[2]; 6141}; 6142 6143/* hwrm_nvm_verify_update_output (size:128b/16B) */ 6144struct hwrm_nvm_verify_update_output { 6145 __le16 error_code; 6146 __le16 req_type; 6147 __le16 seq_id; 6148 __le16 resp_len; 6149 u8 unused_0[7]; 6150 u8 valid; 6151}; 6152 6153/* hwrm_nvm_install_update_input (size:192b/24B) */ 6154struct hwrm_nvm_install_update_input { 6155 __le16 req_type; 6156 __le16 cmpl_ring; 6157 __le16 seq_id; 6158 __le16 target_id; 6159 __le64 resp_addr; 6160 __le32 install_type; 6161 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_NORMAL 0x0UL 6162 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 0xffffffffUL 6163 #define NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_LAST NVM_INSTALL_UPDATE_REQ_INSTALL_TYPE_ALL 6164 __le16 flags; 6165 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ERASE_UNUSED_SPACE 0x1UL 6166 #define NVM_INSTALL_UPDATE_REQ_FLAGS_REMOVE_UNUSED_PKG 0x2UL 6167 #define NVM_INSTALL_UPDATE_REQ_FLAGS_ALLOWED_TO_DEFRAG 0x4UL 6168 u8 unused_0[2]; 6169}; 6170 6171/* hwrm_nvm_install_update_output (size:192b/24B) */ 6172struct hwrm_nvm_install_update_output { 6173 __le16 error_code; 6174 __le16 req_type; 6175 __le16 seq_id; 6176 __le16 resp_len; 6177 __le64 installed_items; 6178 u8 result; 6179 #define NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 0x0UL 6180 #define NVM_INSTALL_UPDATE_RESP_RESULT_LAST NVM_INSTALL_UPDATE_RESP_RESULT_SUCCESS 6181 u8 problem_item; 6182 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_NONE 0x0UL 6183 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 0xffUL 6184 #define NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_LAST NVM_INSTALL_UPDATE_RESP_PROBLEM_ITEM_PACKAGE 6185 u8 reset_required; 6186 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_NONE 0x0UL 6187 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_PCI 0x1UL 6188 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 0x2UL 6189 #define NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_LAST NVM_INSTALL_UPDATE_RESP_RESET_REQUIRED_POWER 6190 u8 unused_0[4]; 6191 u8 valid; 6192}; 6193 6194/* hwrm_nvm_install_update_cmd_err (size:64b/8B) */ 6195struct hwrm_nvm_install_update_cmd_err { 6196 u8 code; 6197 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_UNKNOWN 0x0UL 6198 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_FRAG_ERR 0x1UL 6199 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 0x2UL 6200 #define NVM_INSTALL_UPDATE_CMD_ERR_CODE_LAST NVM_INSTALL_UPDATE_CMD_ERR_CODE_NO_SPACE 6201 u8 unused_0[7]; 6202}; 6203 6204/* hwrm_nvm_get_variable_input (size:320b/40B) */ 6205struct hwrm_nvm_get_variable_input { 6206 __le16 req_type; 6207 __le16 cmpl_ring; 6208 __le16 seq_id; 6209 __le16 target_id; 6210 __le64 resp_addr; 6211 __le64 dest_data_addr; 6212 __le16 data_len; 6213 __le16 option_num; 6214 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6215 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6216 #define NVM_GET_VARIABLE_REQ_OPTION_NUM_LAST NVM_GET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 6217 __le16 dimensions; 6218 __le16 index_0; 6219 __le16 index_1; 6220 __le16 index_2; 6221 __le16 index_3; 6222 u8 flags; 6223 #define NVM_GET_VARIABLE_REQ_FLAGS_FACTORY_DFLT 0x1UL 6224 u8 unused_0; 6225}; 6226 6227/* hwrm_nvm_get_variable_output (size:128b/16B) */ 6228struct hwrm_nvm_get_variable_output { 6229 __le16 error_code; 6230 __le16 req_type; 6231 __le16 seq_id; 6232 __le16 resp_len; 6233 __le16 data_len; 6234 __le16 option_num; 6235 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_0 0x0UL 6236 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 0xffffUL 6237 #define NVM_GET_VARIABLE_RESP_OPTION_NUM_LAST NVM_GET_VARIABLE_RESP_OPTION_NUM_RSVD_FFFF 6238 u8 unused_0[3]; 6239 u8 valid; 6240}; 6241 6242/* hwrm_nvm_get_variable_cmd_err (size:64b/8B) */ 6243struct hwrm_nvm_get_variable_cmd_err { 6244 u8 code; 6245 #define NVM_GET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6246 #define NVM_GET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6247 #define NVM_GET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6248 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 0x3UL 6249 #define NVM_GET_VARIABLE_CMD_ERR_CODE_LAST NVM_GET_VARIABLE_CMD_ERR_CODE_LEN_TOO_SHORT 6250 u8 unused_0[7]; 6251}; 6252 6253/* hwrm_nvm_set_variable_input (size:320b/40B) */ 6254struct hwrm_nvm_set_variable_input { 6255 __le16 req_type; 6256 __le16 cmpl_ring; 6257 __le16 seq_id; 6258 __le16 target_id; 6259 __le64 resp_addr; 6260 __le64 src_data_addr; 6261 __le16 data_len; 6262 __le16 option_num; 6263 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_0 0x0UL 6264 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 0xffffUL 6265 #define NVM_SET_VARIABLE_REQ_OPTION_NUM_LAST NVM_SET_VARIABLE_REQ_OPTION_NUM_RSVD_FFFF 6266 __le16 dimensions; 6267 __le16 index_0; 6268 __le16 index_1; 6269 __le16 index_2; 6270 __le16 index_3; 6271 u8 flags; 6272 #define NVM_SET_VARIABLE_REQ_FLAGS_FORCE_FLUSH 0x1UL 6273 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_MASK 0xeUL 6274 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_SFT 1 6275 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_NONE (0x0UL << 1) 6276 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 (0x1UL << 1) 6277 #define NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_LAST NVM_SET_VARIABLE_REQ_FLAGS_ENCRYPT_MODE_HMAC_SHA1 6278 u8 unused_0; 6279}; 6280 6281/* hwrm_nvm_set_variable_output (size:128b/16B) */ 6282struct hwrm_nvm_set_variable_output { 6283 __le16 error_code; 6284 __le16 req_type; 6285 __le16 seq_id; 6286 __le16 resp_len; 6287 u8 unused_0[7]; 6288 u8 valid; 6289}; 6290 6291/* hwrm_nvm_set_variable_cmd_err (size:64b/8B) */ 6292struct hwrm_nvm_set_variable_cmd_err { 6293 u8 code; 6294 #define NVM_SET_VARIABLE_CMD_ERR_CODE_UNKNOWN 0x0UL 6295 #define NVM_SET_VARIABLE_CMD_ERR_CODE_VAR_NOT_EXIST 0x1UL 6296 #define NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 0x2UL 6297 #define NVM_SET_VARIABLE_CMD_ERR_CODE_LAST NVM_SET_VARIABLE_CMD_ERR_CODE_CORRUPT_VAR 6298 u8 unused_0[7]; 6299}; 6300 6301/* hwrm_selftest_qlist_input (size:128b/16B) */ 6302struct hwrm_selftest_qlist_input { 6303 __le16 req_type; 6304 __le16 cmpl_ring; 6305 __le16 seq_id; 6306 __le16 target_id; 6307 __le64 resp_addr; 6308}; 6309 6310/* hwrm_selftest_qlist_output (size:2240b/280B) */ 6311struct hwrm_selftest_qlist_output { 6312 __le16 error_code; 6313 __le16 req_type; 6314 __le16 seq_id; 6315 __le16 resp_len; 6316 u8 num_tests; 6317 u8 available_tests; 6318 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_NVM_TEST 0x1UL 6319 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_LINK_TEST 0x2UL 6320 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_REGISTER_TEST 0x4UL 6321 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_MEMORY_TEST 0x8UL 6322 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_PCIE_SERDES_TEST 0x10UL 6323 #define SELFTEST_QLIST_RESP_AVAILABLE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6324 u8 offline_tests; 6325 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_NVM_TEST 0x1UL 6326 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_LINK_TEST 0x2UL 6327 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_REGISTER_TEST 0x4UL 6328 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_MEMORY_TEST 0x8UL 6329 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_PCIE_SERDES_TEST 0x10UL 6330 #define SELFTEST_QLIST_RESP_OFFLINE_TESTS_ETHERNET_SERDES_TEST 0x20UL 6331 u8 unused_0; 6332 __le16 test_timeout; 6333 u8 unused_1[2]; 6334 char test0_name[32]; 6335 char test1_name[32]; 6336 char test2_name[32]; 6337 char test3_name[32]; 6338 char test4_name[32]; 6339 char test5_name[32]; 6340 char test6_name[32]; 6341 char test7_name[32]; 6342 u8 unused_2[7]; 6343 u8 valid; 6344}; 6345 6346/* hwrm_selftest_exec_input (size:192b/24B) */ 6347struct hwrm_selftest_exec_input { 6348 __le16 req_type; 6349 __le16 cmpl_ring; 6350 __le16 seq_id; 6351 __le16 target_id; 6352 __le64 resp_addr; 6353 u8 flags; 6354 #define SELFTEST_EXEC_REQ_FLAGS_NVM_TEST 0x1UL 6355 #define SELFTEST_EXEC_REQ_FLAGS_LINK_TEST 0x2UL 6356 #define SELFTEST_EXEC_REQ_FLAGS_REGISTER_TEST 0x4UL 6357 #define SELFTEST_EXEC_REQ_FLAGS_MEMORY_TEST 0x8UL 6358 #define SELFTEST_EXEC_REQ_FLAGS_PCIE_SERDES_TEST 0x10UL 6359 #define SELFTEST_EXEC_REQ_FLAGS_ETHERNET_SERDES_TEST 0x20UL 6360 u8 unused_0[7]; 6361}; 6362 6363/* hwrm_selftest_exec_output (size:128b/16B) */ 6364struct hwrm_selftest_exec_output { 6365 __le16 error_code; 6366 __le16 req_type; 6367 __le16 seq_id; 6368 __le16 resp_len; 6369 u8 requested_tests; 6370 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_NVM_TEST 0x1UL 6371 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_LINK_TEST 0x2UL 6372 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_REGISTER_TEST 0x4UL 6373 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_MEMORY_TEST 0x8UL 6374 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_PCIE_SERDES_TEST 0x10UL 6375 #define SELFTEST_EXEC_RESP_REQUESTED_TESTS_ETHERNET_SERDES_TEST 0x20UL 6376 u8 test_success; 6377 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_NVM_TEST 0x1UL 6378 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_LINK_TEST 0x2UL 6379 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_REGISTER_TEST 0x4UL 6380 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_MEMORY_TEST 0x8UL 6381 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_PCIE_SERDES_TEST 0x10UL 6382 #define SELFTEST_EXEC_RESP_TEST_SUCCESS_ETHERNET_SERDES_TEST 0x20UL 6383 u8 unused_0[5]; 6384 u8 valid; 6385}; 6386 6387/* hwrm_selftest_irq_input (size:128b/16B) */ 6388struct hwrm_selftest_irq_input { 6389 __le16 req_type; 6390 __le16 cmpl_ring; 6391 __le16 seq_id; 6392 __le16 target_id; 6393 __le64 resp_addr; 6394}; 6395 6396/* hwrm_selftest_irq_output (size:128b/16B) */ 6397struct hwrm_selftest_irq_output { 6398 __le16 error_code; 6399 __le16 req_type; 6400 __le16 seq_id; 6401 __le16 resp_len; 6402 u8 unused_0[7]; 6403 u8 valid; 6404}; 6405 6406#endif /* _BNXT_HSI_H_ */ 6407