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35#ifndef __T4_MSG_H
36#define __T4_MSG_H
37
38#include <linux/types.h>
39
40enum {
41 CPL_PASS_OPEN_REQ = 0x1,
42 CPL_PASS_ACCEPT_RPL = 0x2,
43 CPL_ACT_OPEN_REQ = 0x3,
44 CPL_SET_TCB_FIELD = 0x5,
45 CPL_GET_TCB = 0x6,
46 CPL_CLOSE_CON_REQ = 0x8,
47 CPL_CLOSE_LISTSRV_REQ = 0x9,
48 CPL_ABORT_REQ = 0xA,
49 CPL_ABORT_RPL = 0xB,
50 CPL_RX_DATA_ACK = 0xD,
51 CPL_TX_PKT = 0xE,
52 CPL_L2T_WRITE_REQ = 0x12,
53 CPL_SMT_WRITE_REQ = 0x14,
54 CPL_TID_RELEASE = 0x1A,
55 CPL_SRQ_TABLE_REQ = 0x1C,
56 CPL_TX_DATA_ISO = 0x1F,
57
58 CPL_CLOSE_LISTSRV_RPL = 0x20,
59 CPL_L2T_WRITE_RPL = 0x23,
60 CPL_PASS_OPEN_RPL = 0x24,
61 CPL_ACT_OPEN_RPL = 0x25,
62 CPL_PEER_CLOSE = 0x26,
63 CPL_ABORT_REQ_RSS = 0x2B,
64 CPL_ABORT_RPL_RSS = 0x2D,
65 CPL_SMT_WRITE_RPL = 0x2E,
66
67 CPL_RX_PHYS_ADDR = 0x30,
68 CPL_CLOSE_CON_RPL = 0x32,
69 CPL_ISCSI_HDR = 0x33,
70 CPL_RDMA_CQE = 0x35,
71 CPL_RDMA_CQE_READ_RSP = 0x36,
72 CPL_RDMA_CQE_ERR = 0x37,
73 CPL_RX_DATA = 0x39,
74 CPL_SET_TCB_RPL = 0x3A,
75 CPL_RX_PKT = 0x3B,
76 CPL_RX_DDP_COMPLETE = 0x3F,
77
78 CPL_ACT_ESTABLISH = 0x40,
79 CPL_PASS_ESTABLISH = 0x41,
80 CPL_RX_DATA_DDP = 0x42,
81 CPL_PASS_ACCEPT_REQ = 0x44,
82 CPL_RX_ISCSI_CMP = 0x45,
83 CPL_TRACE_PKT_T5 = 0x48,
84 CPL_RX_ISCSI_DDP = 0x49,
85 CPL_RX_TLS_CMP = 0x4E,
86
87 CPL_RDMA_READ_REQ = 0x60,
88
89 CPL_PASS_OPEN_REQ6 = 0x81,
90 CPL_ACT_OPEN_REQ6 = 0x83,
91
92 CPL_TX_TLS_PDU = 0x88,
93 CPL_TX_TLS_SFO = 0x89,
94 CPL_TX_SEC_PDU = 0x8A,
95 CPL_TX_TLS_ACK = 0x8B,
96
97 CPL_RDMA_TERMINATE = 0xA2,
98 CPL_RDMA_WRITE = 0xA4,
99 CPL_SGE_EGR_UPDATE = 0xA5,
100 CPL_RX_MPS_PKT = 0xAF,
101
102 CPL_TRACE_PKT = 0xB0,
103 CPL_TLS_DATA = 0xB1,
104 CPL_ISCSI_DATA = 0xB2,
105
106 CPL_FW4_MSG = 0xC0,
107 CPL_FW4_PLD = 0xC1,
108 CPL_FW4_ACK = 0xC3,
109 CPL_SRQ_TABLE_RPL = 0xCC,
110
111 CPL_RX_PHYS_DSGL = 0xD0,
112
113 CPL_FW6_MSG = 0xE0,
114 CPL_FW6_PLD = 0xE1,
115 CPL_TX_TNL_LSO = 0xEC,
116 CPL_TX_PKT_LSO = 0xED,
117 CPL_TX_PKT_XT = 0xEE,
118
119 NUM_CPL_CMDS
120};
121
122enum CPL_error {
123 CPL_ERR_NONE = 0,
124 CPL_ERR_TCAM_PARITY = 1,
125 CPL_ERR_TCAM_MISS = 2,
126 CPL_ERR_TCAM_FULL = 3,
127 CPL_ERR_BAD_LENGTH = 15,
128 CPL_ERR_BAD_ROUTE = 18,
129 CPL_ERR_CONN_RESET = 20,
130 CPL_ERR_CONN_EXIST_SYNRECV = 21,
131 CPL_ERR_CONN_EXIST = 22,
132 CPL_ERR_ARP_MISS = 23,
133 CPL_ERR_BAD_SYN = 24,
134 CPL_ERR_CONN_TIMEDOUT = 30,
135 CPL_ERR_XMIT_TIMEDOUT = 31,
136 CPL_ERR_PERSIST_TIMEDOUT = 32,
137 CPL_ERR_FINWAIT2_TIMEDOUT = 33,
138 CPL_ERR_KEEPALIVE_TIMEDOUT = 34,
139 CPL_ERR_RTX_NEG_ADVICE = 35,
140 CPL_ERR_PERSIST_NEG_ADVICE = 36,
141 CPL_ERR_KEEPALV_NEG_ADVICE = 37,
142 CPL_ERR_ABORT_FAILED = 42,
143 CPL_ERR_IWARP_FLM = 50,
144 CPL_CONTAINS_READ_RPL = 60,
145 CPL_CONTAINS_WRITE_RPL = 61,
146};
147
148enum {
149 CPL_CONN_POLICY_AUTO = 0,
150 CPL_CONN_POLICY_ASK = 1,
151 CPL_CONN_POLICY_FILTER = 2,
152 CPL_CONN_POLICY_DENY = 3
153};
154
155enum {
156 ULP_MODE_NONE = 0,
157 ULP_MODE_ISCSI = 2,
158 ULP_MODE_RDMA = 4,
159 ULP_MODE_TCPDDP = 5,
160 ULP_MODE_FCOE = 6,
161 ULP_MODE_TLS = 8,
162};
163
164enum {
165 ULP_CRC_HEADER = 1 << 0,
166 ULP_CRC_DATA = 1 << 1
167};
168
169enum {
170 CPL_ABORT_SEND_RST = 0,
171 CPL_ABORT_NO_RST,
172};
173
174enum {
175 TX_CSUM_TCP = 0,
176 TX_CSUM_UDP = 1,
177 TX_CSUM_CRC16 = 4,
178 TX_CSUM_CRC32 = 5,
179 TX_CSUM_CRC32C = 6,
180 TX_CSUM_FCOE = 7,
181 TX_CSUM_TCPIP = 8,
182 TX_CSUM_UDPIP = 9,
183 TX_CSUM_TCPIP6 = 10,
184 TX_CSUM_UDPIP6 = 11,
185 TX_CSUM_IP = 12,
186};
187
188union opcode_tid {
189 __be32 opcode_tid;
190 u8 opcode;
191};
192
193#define CPL_OPCODE_S 24
194#define CPL_OPCODE_V(x) ((x) << CPL_OPCODE_S)
195#define CPL_OPCODE_G(x) (((x) >> CPL_OPCODE_S) & 0xFF)
196#define TID_G(x) ((x) & 0xFFFFFF)
197
198
199#define MK_OPCODE_TID(opcode, tid) (CPL_OPCODE_V(opcode) | (tid))
200
201#define OPCODE_TID(cmd) ((cmd)->ot.opcode_tid)
202
203
204#define GET_TID(cmd) (TID_G(be32_to_cpu(OPCODE_TID(cmd))))
205
206
207#define TID_TID_S 0
208#define TID_TID_M 0x3fff
209#define TID_TID_V(x) ((x) << TID_TID_S)
210#define TID_TID_G(x) (((x) >> TID_TID_S) & TID_TID_M)
211
212#define TID_QID_S 14
213#define TID_QID_M 0x3ff
214#define TID_QID_V(x) ((x) << TID_QID_S)
215#define TID_QID_G(x) (((x) >> TID_QID_S) & TID_QID_M)
216
217struct rss_header {
218 u8 opcode;
219#if defined(__LITTLE_ENDIAN_BITFIELD)
220 u8 channel:2;
221 u8 filter_hit:1;
222 u8 filter_tid:1;
223 u8 hash_type:2;
224 u8 ipv6:1;
225 u8 send2fw:1;
226#else
227 u8 send2fw:1;
228 u8 ipv6:1;
229 u8 hash_type:2;
230 u8 filter_tid:1;
231 u8 filter_hit:1;
232 u8 channel:2;
233#endif
234 __be16 qid;
235 __be32 hash_val;
236};
237
238struct work_request_hdr {
239 __be32 wr_hi;
240 __be32 wr_mid;
241 __be64 wr_lo;
242};
243
244
245#define WR_OP_S 24
246#define WR_OP_V(x) ((__u64)(x) << WR_OP_S)
247
248#define WR_HDR struct work_request_hdr wr
249
250
251#define TX_CHAN_S 2
252#define TX_CHAN_V(x) ((x) << TX_CHAN_S)
253
254#define ULP_MODE_S 8
255#define ULP_MODE_V(x) ((x) << ULP_MODE_S)
256
257#define RCV_BUFSIZ_S 12
258#define RCV_BUFSIZ_M 0x3FFU
259#define RCV_BUFSIZ_V(x) ((x) << RCV_BUFSIZ_S)
260
261#define SMAC_SEL_S 28
262#define SMAC_SEL_V(x) ((__u64)(x) << SMAC_SEL_S)
263
264#define L2T_IDX_S 36
265#define L2T_IDX_V(x) ((__u64)(x) << L2T_IDX_S)
266
267#define WND_SCALE_S 50
268#define WND_SCALE_V(x) ((__u64)(x) << WND_SCALE_S)
269
270#define KEEP_ALIVE_S 54
271#define KEEP_ALIVE_V(x) ((__u64)(x) << KEEP_ALIVE_S)
272#define KEEP_ALIVE_F KEEP_ALIVE_V(1ULL)
273
274#define MSS_IDX_S 60
275#define MSS_IDX_M 0xF
276#define MSS_IDX_V(x) ((__u64)(x) << MSS_IDX_S)
277#define MSS_IDX_G(x) (((x) >> MSS_IDX_S) & MSS_IDX_M)
278
279
280#define RSS_QUEUE_S 0
281#define RSS_QUEUE_M 0x3FF
282#define RSS_QUEUE_V(x) ((x) << RSS_QUEUE_S)
283#define RSS_QUEUE_G(x) (((x) >> RSS_QUEUE_S) & RSS_QUEUE_M)
284
285#define RSS_QUEUE_VALID_S 10
286#define RSS_QUEUE_VALID_V(x) ((x) << RSS_QUEUE_VALID_S)
287#define RSS_QUEUE_VALID_F RSS_QUEUE_VALID_V(1U)
288
289#define RX_FC_DISABLE_S 20
290#define RX_FC_DISABLE_V(x) ((x) << RX_FC_DISABLE_S)
291#define RX_FC_DISABLE_F RX_FC_DISABLE_V(1U)
292
293#define RX_FC_VALID_S 22
294#define RX_FC_VALID_V(x) ((x) << RX_FC_VALID_S)
295#define RX_FC_VALID_F RX_FC_VALID_V(1U)
296
297#define RX_CHANNEL_S 26
298#define RX_CHANNEL_V(x) ((x) << RX_CHANNEL_S)
299#define RX_CHANNEL_F RX_CHANNEL_V(1U)
300
301#define WND_SCALE_EN_S 28
302#define WND_SCALE_EN_V(x) ((x) << WND_SCALE_EN_S)
303#define WND_SCALE_EN_F WND_SCALE_EN_V(1U)
304
305#define T5_OPT_2_VALID_S 31
306#define T5_OPT_2_VALID_V(x) ((x) << T5_OPT_2_VALID_S)
307#define T5_OPT_2_VALID_F T5_OPT_2_VALID_V(1U)
308
309struct cpl_pass_open_req {
310 WR_HDR;
311 union opcode_tid ot;
312 __be16 local_port;
313 __be16 peer_port;
314 __be32 local_ip;
315 __be32 peer_ip;
316 __be64 opt0;
317 __be64 opt1;
318};
319
320
321#define NO_CONG_S 4
322#define NO_CONG_V(x) ((x) << NO_CONG_S)
323#define NO_CONG_F NO_CONG_V(1U)
324
325#define DELACK_S 5
326#define DELACK_V(x) ((x) << DELACK_S)
327#define DELACK_F DELACK_V(1U)
328
329#define NON_OFFLOAD_S 7
330#define NON_OFFLOAD_V(x) ((x) << NON_OFFLOAD_S)
331#define NON_OFFLOAD_F NON_OFFLOAD_V(1U)
332
333#define DSCP_S 22
334#define DSCP_M 0x3F
335#define DSCP_V(x) ((x) << DSCP_S)
336#define DSCP_G(x) (((x) >> DSCP_S) & DSCP_M)
337
338#define TCAM_BYPASS_S 48
339#define TCAM_BYPASS_V(x) ((__u64)(x) << TCAM_BYPASS_S)
340#define TCAM_BYPASS_F TCAM_BYPASS_V(1ULL)
341
342#define NAGLE_S 49
343#define NAGLE_V(x) ((__u64)(x) << NAGLE_S)
344#define NAGLE_F NAGLE_V(1ULL)
345
346
347#define SYN_RSS_ENABLE_S 0
348#define SYN_RSS_ENABLE_V(x) ((x) << SYN_RSS_ENABLE_S)
349#define SYN_RSS_ENABLE_F SYN_RSS_ENABLE_V(1U)
350
351#define SYN_RSS_QUEUE_S 2
352#define SYN_RSS_QUEUE_V(x) ((x) << SYN_RSS_QUEUE_S)
353
354#define CONN_POLICY_S 22
355#define CONN_POLICY_V(x) ((x) << CONN_POLICY_S)
356
357struct cpl_pass_open_req6 {
358 WR_HDR;
359 union opcode_tid ot;
360 __be16 local_port;
361 __be16 peer_port;
362 __be64 local_ip_hi;
363 __be64 local_ip_lo;
364 __be64 peer_ip_hi;
365 __be64 peer_ip_lo;
366 __be64 opt0;
367 __be64 opt1;
368};
369
370struct cpl_pass_open_rpl {
371 union opcode_tid ot;
372 u8 rsvd[3];
373 u8 status;
374};
375
376struct tcp_options {
377 __be16 mss;
378 __u8 wsf;
379#if defined(__LITTLE_ENDIAN_BITFIELD)
380 __u8:4;
381 __u8 unknown:1;
382 __u8:1;
383 __u8 sack:1;
384 __u8 tstamp:1;
385#else
386 __u8 tstamp:1;
387 __u8 sack:1;
388 __u8:1;
389 __u8 unknown:1;
390 __u8:4;
391#endif
392};
393
394struct cpl_pass_accept_req {
395 union opcode_tid ot;
396 __be16 rsvd;
397 __be16 len;
398 __be32 hdr_len;
399 __be16 vlan;
400 __be16 l2info;
401 __be32 tos_stid;
402 struct tcp_options tcpopt;
403};
404
405
406#define SYN_RX_CHAN_S 0
407#define SYN_RX_CHAN_M 0xF
408#define SYN_RX_CHAN_V(x) ((x) << SYN_RX_CHAN_S)
409#define SYN_RX_CHAN_G(x) (((x) >> SYN_RX_CHAN_S) & SYN_RX_CHAN_M)
410
411#define TCP_HDR_LEN_S 10
412#define TCP_HDR_LEN_M 0x3F
413#define TCP_HDR_LEN_V(x) ((x) << TCP_HDR_LEN_S)
414#define TCP_HDR_LEN_G(x) (((x) >> TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
415
416#define IP_HDR_LEN_S 16
417#define IP_HDR_LEN_M 0x3FF
418#define IP_HDR_LEN_V(x) ((x) << IP_HDR_LEN_S)
419#define IP_HDR_LEN_G(x) (((x) >> IP_HDR_LEN_S) & IP_HDR_LEN_M)
420
421#define ETH_HDR_LEN_S 26
422#define ETH_HDR_LEN_M 0x1F
423#define ETH_HDR_LEN_V(x) ((x) << ETH_HDR_LEN_S)
424#define ETH_HDR_LEN_G(x) (((x) >> ETH_HDR_LEN_S) & ETH_HDR_LEN_M)
425
426
427#define SYN_MAC_IDX_S 0
428#define SYN_MAC_IDX_M 0x1FF
429#define SYN_MAC_IDX_V(x) ((x) << SYN_MAC_IDX_S)
430#define SYN_MAC_IDX_G(x) (((x) >> SYN_MAC_IDX_S) & SYN_MAC_IDX_M)
431
432#define SYN_XACT_MATCH_S 9
433#define SYN_XACT_MATCH_V(x) ((x) << SYN_XACT_MATCH_S)
434#define SYN_XACT_MATCH_F SYN_XACT_MATCH_V(1U)
435
436#define SYN_INTF_S 12
437#define SYN_INTF_M 0xF
438#define SYN_INTF_V(x) ((x) << SYN_INTF_S)
439#define SYN_INTF_G(x) (((x) >> SYN_INTF_S) & SYN_INTF_M)
440
441enum {
442 CONG_ALG_RENO,
443 CONG_ALG_TAHOE,
444 CONG_ALG_NEWRENO,
445 CONG_ALG_HIGHSPEED
446};
447
448#define CONG_CNTRL_S 14
449#define CONG_CNTRL_M 0x3
450#define CONG_CNTRL_V(x) ((x) << CONG_CNTRL_S)
451#define CONG_CNTRL_G(x) (((x) >> CONG_CNTRL_S) & CONG_CNTRL_M)
452
453#define T5_ISS_S 18
454#define T5_ISS_V(x) ((x) << T5_ISS_S)
455#define T5_ISS_F T5_ISS_V(1U)
456
457struct cpl_pass_accept_rpl {
458 WR_HDR;
459 union opcode_tid ot;
460 __be32 opt2;
461 __be64 opt0;
462};
463
464
465#define RX_COALESCE_VALID_S 11
466#define RX_COALESCE_VALID_V(x) ((x) << RX_COALESCE_VALID_S)
467#define RX_COALESCE_VALID_F RX_COALESCE_VALID_V(1U)
468
469#define RX_COALESCE_S 12
470#define RX_COALESCE_V(x) ((x) << RX_COALESCE_S)
471
472#define PACE_S 16
473#define PACE_V(x) ((x) << PACE_S)
474
475#define TX_QUEUE_S 23
476#define TX_QUEUE_M 0x7
477#define TX_QUEUE_V(x) ((x) << TX_QUEUE_S)
478#define TX_QUEUE_G(x) (((x) >> TX_QUEUE_S) & TX_QUEUE_M)
479
480#define CCTRL_ECN_S 27
481#define CCTRL_ECN_V(x) ((x) << CCTRL_ECN_S)
482#define CCTRL_ECN_F CCTRL_ECN_V(1U)
483
484#define TSTAMPS_EN_S 29
485#define TSTAMPS_EN_V(x) ((x) << TSTAMPS_EN_S)
486#define TSTAMPS_EN_F TSTAMPS_EN_V(1U)
487
488#define SACK_EN_S 30
489#define SACK_EN_V(x) ((x) << SACK_EN_S)
490#define SACK_EN_F SACK_EN_V(1U)
491
492struct cpl_t5_pass_accept_rpl {
493 WR_HDR;
494 union opcode_tid ot;
495 __be32 opt2;
496 __be64 opt0;
497 __be32 iss;
498 __be32 rsvd;
499};
500
501struct cpl_act_open_req {
502 WR_HDR;
503 union opcode_tid ot;
504 __be16 local_port;
505 __be16 peer_port;
506 __be32 local_ip;
507 __be32 peer_ip;
508 __be64 opt0;
509 __be32 params;
510 __be32 opt2;
511};
512
513#define FILTER_TUPLE_S 24
514#define FILTER_TUPLE_M 0xFFFFFFFFFF
515#define FILTER_TUPLE_V(x) ((x) << FILTER_TUPLE_S)
516#define FILTER_TUPLE_G(x) (((x) >> FILTER_TUPLE_S) & FILTER_TUPLE_M)
517struct cpl_t5_act_open_req {
518 WR_HDR;
519 union opcode_tid ot;
520 __be16 local_port;
521 __be16 peer_port;
522 __be32 local_ip;
523 __be32 peer_ip;
524 __be64 opt0;
525 __be32 rsvd;
526 __be32 opt2;
527 __be64 params;
528};
529
530struct cpl_t6_act_open_req {
531 WR_HDR;
532 union opcode_tid ot;
533 __be16 local_port;
534 __be16 peer_port;
535 __be32 local_ip;
536 __be32 peer_ip;
537 __be64 opt0;
538 __be32 rsvd;
539 __be32 opt2;
540 __be64 params;
541 __be32 rsvd2;
542 __be32 opt3;
543};
544
545struct cpl_act_open_req6 {
546 WR_HDR;
547 union opcode_tid ot;
548 __be16 local_port;
549 __be16 peer_port;
550 __be64 local_ip_hi;
551 __be64 local_ip_lo;
552 __be64 peer_ip_hi;
553 __be64 peer_ip_lo;
554 __be64 opt0;
555 __be32 params;
556 __be32 opt2;
557};
558
559struct cpl_t5_act_open_req6 {
560 WR_HDR;
561 union opcode_tid ot;
562 __be16 local_port;
563 __be16 peer_port;
564 __be64 local_ip_hi;
565 __be64 local_ip_lo;
566 __be64 peer_ip_hi;
567 __be64 peer_ip_lo;
568 __be64 opt0;
569 __be32 rsvd;
570 __be32 opt2;
571 __be64 params;
572};
573
574struct cpl_t6_act_open_req6 {
575 WR_HDR;
576 union opcode_tid ot;
577 __be16 local_port;
578 __be16 peer_port;
579 __be64 local_ip_hi;
580 __be64 local_ip_lo;
581 __be64 peer_ip_hi;
582 __be64 peer_ip_lo;
583 __be64 opt0;
584 __be32 rsvd;
585 __be32 opt2;
586 __be64 params;
587 __be32 rsvd2;
588 __be32 opt3;
589};
590
591struct cpl_act_open_rpl {
592 union opcode_tid ot;
593 __be32 atid_status;
594};
595
596
597#define AOPEN_STATUS_S 0
598#define AOPEN_STATUS_M 0xFF
599#define AOPEN_STATUS_G(x) (((x) >> AOPEN_STATUS_S) & AOPEN_STATUS_M)
600
601#define AOPEN_ATID_S 8
602#define AOPEN_ATID_M 0xFFFFFF
603#define AOPEN_ATID_G(x) (((x) >> AOPEN_ATID_S) & AOPEN_ATID_M)
604
605struct cpl_pass_establish {
606 union opcode_tid ot;
607 __be32 rsvd;
608 __be32 tos_stid;
609 __be16 mac_idx;
610 __be16 tcp_opt;
611 __be32 snd_isn;
612 __be32 rcv_isn;
613};
614
615
616#define PASS_OPEN_TID_S 0
617#define PASS_OPEN_TID_M 0xFFFFFF
618#define PASS_OPEN_TID_V(x) ((x) << PASS_OPEN_TID_S)
619#define PASS_OPEN_TID_G(x) (((x) >> PASS_OPEN_TID_S) & PASS_OPEN_TID_M)
620
621#define PASS_OPEN_TOS_S 24
622#define PASS_OPEN_TOS_M 0xFF
623#define PASS_OPEN_TOS_V(x) ((x) << PASS_OPEN_TOS_S)
624#define PASS_OPEN_TOS_G(x) (((x) >> PASS_OPEN_TOS_S) & PASS_OPEN_TOS_M)
625
626
627#define TCPOPT_WSCALE_OK_S 5
628#define TCPOPT_WSCALE_OK_M 0x1
629#define TCPOPT_WSCALE_OK_G(x) \
630 (((x) >> TCPOPT_WSCALE_OK_S) & TCPOPT_WSCALE_OK_M)
631
632#define TCPOPT_SACK_S 6
633#define TCPOPT_SACK_M 0x1
634#define TCPOPT_SACK_G(x) (((x) >> TCPOPT_SACK_S) & TCPOPT_SACK_M)
635
636#define TCPOPT_TSTAMP_S 7
637#define TCPOPT_TSTAMP_M 0x1
638#define TCPOPT_TSTAMP_G(x) (((x) >> TCPOPT_TSTAMP_S) & TCPOPT_TSTAMP_M)
639
640#define TCPOPT_SND_WSCALE_S 8
641#define TCPOPT_SND_WSCALE_M 0xF
642#define TCPOPT_SND_WSCALE_G(x) \
643 (((x) >> TCPOPT_SND_WSCALE_S) & TCPOPT_SND_WSCALE_M)
644
645#define TCPOPT_MSS_S 12
646#define TCPOPT_MSS_M 0xF
647#define TCPOPT_MSS_G(x) (((x) >> TCPOPT_MSS_S) & TCPOPT_MSS_M)
648
649#define T6_TCP_HDR_LEN_S 8
650#define T6_TCP_HDR_LEN_V(x) ((x) << T6_TCP_HDR_LEN_S)
651#define T6_TCP_HDR_LEN_G(x) (((x) >> T6_TCP_HDR_LEN_S) & TCP_HDR_LEN_M)
652
653#define T6_IP_HDR_LEN_S 14
654#define T6_IP_HDR_LEN_V(x) ((x) << T6_IP_HDR_LEN_S)
655#define T6_IP_HDR_LEN_G(x) (((x) >> T6_IP_HDR_LEN_S) & IP_HDR_LEN_M)
656
657#define T6_ETH_HDR_LEN_S 24
658#define T6_ETH_HDR_LEN_M 0xFF
659#define T6_ETH_HDR_LEN_V(x) ((x) << T6_ETH_HDR_LEN_S)
660#define T6_ETH_HDR_LEN_G(x) (((x) >> T6_ETH_HDR_LEN_S) & T6_ETH_HDR_LEN_M)
661
662struct cpl_act_establish {
663 union opcode_tid ot;
664 __be32 rsvd;
665 __be32 tos_atid;
666 __be16 mac_idx;
667 __be16 tcp_opt;
668 __be32 snd_isn;
669 __be32 rcv_isn;
670};
671
672struct cpl_get_tcb {
673 WR_HDR;
674 union opcode_tid ot;
675 __be16 reply_ctrl;
676 __be16 cookie;
677};
678
679
680#define QUEUENO_S 0
681#define QUEUENO_V(x) ((x) << QUEUENO_S)
682
683#define REPLY_CHAN_S 14
684#define REPLY_CHAN_V(x) ((x) << REPLY_CHAN_S)
685#define REPLY_CHAN_F REPLY_CHAN_V(1U)
686
687#define NO_REPLY_S 15
688#define NO_REPLY_V(x) ((x) << NO_REPLY_S)
689#define NO_REPLY_F NO_REPLY_V(1U)
690
691struct cpl_set_tcb_field {
692 WR_HDR;
693 union opcode_tid ot;
694 __be16 reply_ctrl;
695 __be16 word_cookie;
696 __be64 mask;
697 __be64 val;
698};
699
700
701#define TCB_WORD_S 0
702#define TCB_WORD_V(x) ((x) << TCB_WORD_S)
703
704#define TCB_COOKIE_S 5
705#define TCB_COOKIE_M 0x7
706#define TCB_COOKIE_V(x) ((x) << TCB_COOKIE_S)
707#define TCB_COOKIE_G(x) (((x) >> TCB_COOKIE_S) & TCB_COOKIE_M)
708
709struct cpl_set_tcb_rpl {
710 union opcode_tid ot;
711 __be16 rsvd;
712 u8 cookie;
713 u8 status;
714 __be64 oldval;
715};
716
717struct cpl_close_con_req {
718 WR_HDR;
719 union opcode_tid ot;
720 __be32 rsvd;
721};
722
723struct cpl_close_con_rpl {
724 union opcode_tid ot;
725 u8 rsvd[3];
726 u8 status;
727 __be32 snd_nxt;
728 __be32 rcv_nxt;
729};
730
731struct cpl_close_listsvr_req {
732 WR_HDR;
733 union opcode_tid ot;
734 __be16 reply_ctrl;
735 __be16 rsvd;
736};
737
738
739#define LISTSVR_IPV6_S 14
740#define LISTSVR_IPV6_V(x) ((x) << LISTSVR_IPV6_S)
741#define LISTSVR_IPV6_F LISTSVR_IPV6_V(1U)
742
743struct cpl_close_listsvr_rpl {
744 union opcode_tid ot;
745 u8 rsvd[3];
746 u8 status;
747};
748
749struct cpl_abort_req_rss {
750 union opcode_tid ot;
751 u8 rsvd[3];
752 u8 status;
753};
754
755struct cpl_abort_req_rss6 {
756 WR_HDR;
757 union opcode_tid ot;
758 __u32 srqidx_status;
759};
760
761#define ABORT_RSS_STATUS_S 0
762#define ABORT_RSS_STATUS_M 0xff
763#define ABORT_RSS_STATUS_V(x) ((x) << ABORT_RSS_STATUS_S)
764#define ABORT_RSS_STATUS_G(x) (((x) >> ABORT_RSS_STATUS_S) & ABORT_RSS_STATUS_M)
765
766#define ABORT_RSS_SRQIDX_S 8
767#define ABORT_RSS_SRQIDX_M 0xffffff
768#define ABORT_RSS_SRQIDX_V(x) ((x) << ABORT_RSS_SRQIDX_S)
769#define ABORT_RSS_SRQIDX_G(x) (((x) >> ABORT_RSS_SRQIDX_S) & ABORT_RSS_SRQIDX_M)
770
771struct cpl_abort_req {
772 WR_HDR;
773 union opcode_tid ot;
774 __be32 rsvd0;
775 u8 rsvd1;
776 u8 cmd;
777 u8 rsvd2[6];
778};
779
780struct cpl_abort_rpl_rss {
781 union opcode_tid ot;
782 u8 rsvd[3];
783 u8 status;
784};
785
786struct cpl_abort_rpl_rss6 {
787 union opcode_tid ot;
788 __u32 srqidx_status;
789};
790
791struct cpl_abort_rpl {
792 WR_HDR;
793 union opcode_tid ot;
794 __be32 rsvd0;
795 u8 rsvd1;
796 u8 cmd;
797 u8 rsvd2[6];
798};
799
800struct cpl_peer_close {
801 union opcode_tid ot;
802 __be32 rcv_nxt;
803};
804
805struct cpl_tid_release {
806 WR_HDR;
807 union opcode_tid ot;
808 __be32 rsvd;
809};
810
811struct cpl_tx_pkt_core {
812 __be32 ctrl0;
813 __be16 pack;
814 __be16 len;
815 __be64 ctrl1;
816};
817
818struct cpl_tx_pkt {
819 WR_HDR;
820 struct cpl_tx_pkt_core c;
821};
822
823#define cpl_tx_pkt_xt cpl_tx_pkt
824
825
826#define TXPKT_VF_S 0
827#define TXPKT_VF_V(x) ((x) << TXPKT_VF_S)
828
829#define TXPKT_PF_S 8
830#define TXPKT_PF_V(x) ((x) << TXPKT_PF_S)
831
832#define TXPKT_VF_VLD_S 11
833#define TXPKT_VF_VLD_V(x) ((x) << TXPKT_VF_VLD_S)
834#define TXPKT_VF_VLD_F TXPKT_VF_VLD_V(1U)
835
836#define TXPKT_OVLAN_IDX_S 12
837#define TXPKT_OVLAN_IDX_V(x) ((x) << TXPKT_OVLAN_IDX_S)
838
839#define TXPKT_T5_OVLAN_IDX_S 12
840#define TXPKT_T5_OVLAN_IDX_V(x) ((x) << TXPKT_T5_OVLAN_IDX_S)
841
842#define TXPKT_INTF_S 16
843#define TXPKT_INTF_V(x) ((x) << TXPKT_INTF_S)
844
845#define TXPKT_INS_OVLAN_S 21
846#define TXPKT_INS_OVLAN_V(x) ((x) << TXPKT_INS_OVLAN_S)
847#define TXPKT_INS_OVLAN_F TXPKT_INS_OVLAN_V(1U)
848
849#define TXPKT_TSTAMP_S 23
850#define TXPKT_TSTAMP_V(x) ((x) << TXPKT_TSTAMP_S)
851#define TXPKT_TSTAMP_F TXPKT_TSTAMP_V(1ULL)
852
853#define TXPKT_OPCODE_S 24
854#define TXPKT_OPCODE_V(x) ((x) << TXPKT_OPCODE_S)
855
856
857#define TXPKT_CSUM_END_S 12
858#define TXPKT_CSUM_END_V(x) ((x) << TXPKT_CSUM_END_S)
859
860#define TXPKT_CSUM_START_S 20
861#define TXPKT_CSUM_START_V(x) ((x) << TXPKT_CSUM_START_S)
862
863#define TXPKT_IPHDR_LEN_S 20
864#define TXPKT_IPHDR_LEN_V(x) ((__u64)(x) << TXPKT_IPHDR_LEN_S)
865
866#define TXPKT_CSUM_LOC_S 30
867#define TXPKT_CSUM_LOC_V(x) ((__u64)(x) << TXPKT_CSUM_LOC_S)
868
869#define TXPKT_ETHHDR_LEN_S 34
870#define TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << TXPKT_ETHHDR_LEN_S)
871
872#define T6_TXPKT_ETHHDR_LEN_S 32
873#define T6_TXPKT_ETHHDR_LEN_V(x) ((__u64)(x) << T6_TXPKT_ETHHDR_LEN_S)
874
875#define TXPKT_CSUM_TYPE_S 40
876#define TXPKT_CSUM_TYPE_V(x) ((__u64)(x) << TXPKT_CSUM_TYPE_S)
877
878#define TXPKT_VLAN_S 44
879#define TXPKT_VLAN_V(x) ((__u64)(x) << TXPKT_VLAN_S)
880
881#define TXPKT_VLAN_VLD_S 60
882#define TXPKT_VLAN_VLD_V(x) ((__u64)(x) << TXPKT_VLAN_VLD_S)
883#define TXPKT_VLAN_VLD_F TXPKT_VLAN_VLD_V(1ULL)
884
885#define TXPKT_IPCSUM_DIS_S 62
886#define TXPKT_IPCSUM_DIS_V(x) ((__u64)(x) << TXPKT_IPCSUM_DIS_S)
887#define TXPKT_IPCSUM_DIS_F TXPKT_IPCSUM_DIS_V(1ULL)
888
889#define TXPKT_L4CSUM_DIS_S 63
890#define TXPKT_L4CSUM_DIS_V(x) ((__u64)(x) << TXPKT_L4CSUM_DIS_S)
891#define TXPKT_L4CSUM_DIS_F TXPKT_L4CSUM_DIS_V(1ULL)
892
893struct cpl_tx_pkt_lso_core {
894 __be32 lso_ctrl;
895 __be16 ipid_ofst;
896 __be16 mss;
897 __be32 seqno_offset;
898 __be32 len;
899
900};
901
902
903#define LSO_TCPHDR_LEN_S 0
904#define LSO_TCPHDR_LEN_V(x) ((x) << LSO_TCPHDR_LEN_S)
905
906#define LSO_IPHDR_LEN_S 4
907#define LSO_IPHDR_LEN_V(x) ((x) << LSO_IPHDR_LEN_S)
908
909#define LSO_ETHHDR_LEN_S 16
910#define LSO_ETHHDR_LEN_V(x) ((x) << LSO_ETHHDR_LEN_S)
911
912#define LSO_IPV6_S 20
913#define LSO_IPV6_V(x) ((x) << LSO_IPV6_S)
914#define LSO_IPV6_F LSO_IPV6_V(1U)
915
916#define LSO_LAST_SLICE_S 22
917#define LSO_LAST_SLICE_V(x) ((x) << LSO_LAST_SLICE_S)
918#define LSO_LAST_SLICE_F LSO_LAST_SLICE_V(1U)
919
920#define LSO_FIRST_SLICE_S 23
921#define LSO_FIRST_SLICE_V(x) ((x) << LSO_FIRST_SLICE_S)
922#define LSO_FIRST_SLICE_F LSO_FIRST_SLICE_V(1U)
923
924#define LSO_OPCODE_S 24
925#define LSO_OPCODE_V(x) ((x) << LSO_OPCODE_S)
926
927#define LSO_T5_XFER_SIZE_S 0
928#define LSO_T5_XFER_SIZE_V(x) ((x) << LSO_T5_XFER_SIZE_S)
929
930struct cpl_tx_pkt_lso {
931 WR_HDR;
932 struct cpl_tx_pkt_lso_core c;
933
934};
935
936struct cpl_iscsi_hdr {
937 union opcode_tid ot;
938 __be16 pdu_len_ddp;
939 __be16 len;
940 __be32 seq;
941 __be16 urg;
942 u8 rsvd;
943 u8 status;
944};
945
946
947#define ISCSI_PDU_LEN_S 0
948#define ISCSI_PDU_LEN_M 0x7FFF
949#define ISCSI_PDU_LEN_V(x) ((x) << ISCSI_PDU_LEN_S)
950#define ISCSI_PDU_LEN_G(x) (((x) >> ISCSI_PDU_LEN_S) & ISCSI_PDU_LEN_M)
951
952#define ISCSI_DDP_S 15
953#define ISCSI_DDP_V(x) ((x) << ISCSI_DDP_S)
954#define ISCSI_DDP_F ISCSI_DDP_V(1U)
955
956struct cpl_rx_data_ddp {
957 union opcode_tid ot;
958 __be16 urg;
959 __be16 len;
960 __be32 seq;
961 union {
962 __be32 nxt_seq;
963 __be32 ddp_report;
964 };
965 __be32 ulp_crc;
966 __be32 ddpvld;
967};
968
969#define cpl_rx_iscsi_ddp cpl_rx_data_ddp
970
971struct cpl_iscsi_data {
972 union opcode_tid ot;
973 __u8 rsvd0[2];
974 __be16 len;
975 __be32 seq;
976 __be16 urg;
977 __u8 rsvd1;
978 __u8 status;
979};
980
981struct cpl_rx_iscsi_cmp {
982 union opcode_tid ot;
983 __be16 pdu_len_ddp;
984 __be16 len;
985 __be32 seq;
986 __be16 urg;
987 __u8 rsvd;
988 __u8 status;
989 __be32 ulp_crc;
990 __be32 ddpvld;
991};
992
993struct cpl_tx_data_iso {
994 __be32 op_to_scsi;
995 __u8 reserved1;
996 __u8 ahs_len;
997 __be16 mpdu;
998 __be32 burst_size;
999 __be32 len;
1000 __be32 reserved2_seglen_offset;
1001 __be32 datasn_offset;
1002 __be32 buffer_offset;
1003 __be32 reserved3;
1004
1005
1006};
1007
1008
1009#define CPL_TX_DATA_ISO_OP_S 24
1010#define CPL_TX_DATA_ISO_OP_M 0xff
1011#define CPL_TX_DATA_ISO_OP_V(x) ((x) << CPL_TX_DATA_ISO_OP_S)
1012#define CPL_TX_DATA_ISO_OP_G(x) \
1013 (((x) >> CPL_TX_DATA_ISO_OP_S) & CPL_TX_DATA_ISO_OP_M)
1014
1015#define CPL_TX_DATA_ISO_FIRST_S 23
1016#define CPL_TX_DATA_ISO_FIRST_M 0x1
1017#define CPL_TX_DATA_ISO_FIRST_V(x) ((x) << CPL_TX_DATA_ISO_FIRST_S)
1018#define CPL_TX_DATA_ISO_FIRST_G(x) \
1019 (((x) >> CPL_TX_DATA_ISO_FIRST_S) & CPL_TX_DATA_ISO_FIRST_M)
1020#define CPL_TX_DATA_ISO_FIRST_F CPL_TX_DATA_ISO_FIRST_V(1U)
1021
1022#define CPL_TX_DATA_ISO_LAST_S 22
1023#define CPL_TX_DATA_ISO_LAST_M 0x1
1024#define CPL_TX_DATA_ISO_LAST_V(x) ((x) << CPL_TX_DATA_ISO_LAST_S)
1025#define CPL_TX_DATA_ISO_LAST_G(x) \
1026 (((x) >> CPL_TX_DATA_ISO_LAST_S) & CPL_TX_DATA_ISO_LAST_M)
1027#define CPL_TX_DATA_ISO_LAST_F CPL_TX_DATA_ISO_LAST_V(1U)
1028
1029#define CPL_TX_DATA_ISO_CPLHDRLEN_S 21
1030#define CPL_TX_DATA_ISO_CPLHDRLEN_M 0x1
1031#define CPL_TX_DATA_ISO_CPLHDRLEN_V(x) ((x) << CPL_TX_DATA_ISO_CPLHDRLEN_S)
1032#define CPL_TX_DATA_ISO_CPLHDRLEN_G(x) \
1033 (((x) >> CPL_TX_DATA_ISO_CPLHDRLEN_S) & CPL_TX_DATA_ISO_CPLHDRLEN_M)
1034#define CPL_TX_DATA_ISO_CPLHDRLEN_F CPL_TX_DATA_ISO_CPLHDRLEN_V(1U)
1035
1036#define CPL_TX_DATA_ISO_HDRCRC_S 20
1037#define CPL_TX_DATA_ISO_HDRCRC_M 0x1
1038#define CPL_TX_DATA_ISO_HDRCRC_V(x) ((x) << CPL_TX_DATA_ISO_HDRCRC_S)
1039#define CPL_TX_DATA_ISO_HDRCRC_G(x) \
1040 (((x) >> CPL_TX_DATA_ISO_HDRCRC_S) & CPL_TX_DATA_ISO_HDRCRC_M)
1041#define CPL_TX_DATA_ISO_HDRCRC_F CPL_TX_DATA_ISO_HDRCRC_V(1U)
1042
1043#define CPL_TX_DATA_ISO_PLDCRC_S 19
1044#define CPL_TX_DATA_ISO_PLDCRC_M 0x1
1045#define CPL_TX_DATA_ISO_PLDCRC_V(x) ((x) << CPL_TX_DATA_ISO_PLDCRC_S)
1046#define CPL_TX_DATA_ISO_PLDCRC_G(x) \
1047 (((x) >> CPL_TX_DATA_ISO_PLDCRC_S) & CPL_TX_DATA_ISO_PLDCRC_M)
1048#define CPL_TX_DATA_ISO_PLDCRC_F CPL_TX_DATA_ISO_PLDCRC_V(1U)
1049
1050#define CPL_TX_DATA_ISO_IMMEDIATE_S 18
1051#define CPL_TX_DATA_ISO_IMMEDIATE_M 0x1
1052#define CPL_TX_DATA_ISO_IMMEDIATE_V(x) ((x) << CPL_TX_DATA_ISO_IMMEDIATE_S)
1053#define CPL_TX_DATA_ISO_IMMEDIATE_G(x) \
1054 (((x) >> CPL_TX_DATA_ISO_IMMEDIATE_S) & CPL_TX_DATA_ISO_IMMEDIATE_M)
1055#define CPL_TX_DATA_ISO_IMMEDIATE_F CPL_TX_DATA_ISO_IMMEDIATE_V(1U)
1056
1057#define CPL_TX_DATA_ISO_SCSI_S 16
1058#define CPL_TX_DATA_ISO_SCSI_M 0x3
1059#define CPL_TX_DATA_ISO_SCSI_V(x) ((x) << CPL_TX_DATA_ISO_SCSI_S)
1060#define CPL_TX_DATA_ISO_SCSI_G(x) \
1061 (((x) >> CPL_TX_DATA_ISO_SCSI_S) & CPL_TX_DATA_ISO_SCSI_M)
1062
1063
1064#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_S 0
1065#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_M 0xffffff
1066#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_V(x) \
1067 ((x) << CPL_TX_DATA_ISO_SEGLEN_OFFSET_S)
1068#define CPL_TX_DATA_ISO_SEGLEN_OFFSET_G(x) \
1069 (((x) >> CPL_TX_DATA_ISO_SEGLEN_OFFSET_S) & \
1070 CPL_TX_DATA_ISO_SEGLEN_OFFSET_M)
1071
1072struct cpl_rx_data {
1073 union opcode_tid ot;
1074 __be16 rsvd;
1075 __be16 len;
1076 __be32 seq;
1077 __be16 urg;
1078#if defined(__LITTLE_ENDIAN_BITFIELD)
1079 u8 dack_mode:2;
1080 u8 psh:1;
1081 u8 heartbeat:1;
1082 u8 ddp_off:1;
1083 u8 :3;
1084#else
1085 u8 :3;
1086 u8 ddp_off:1;
1087 u8 heartbeat:1;
1088 u8 psh:1;
1089 u8 dack_mode:2;
1090#endif
1091 u8 status;
1092};
1093
1094struct cpl_rx_data_ack {
1095 WR_HDR;
1096 union opcode_tid ot;
1097 __be32 credit_dack;
1098};
1099
1100
1101#define RX_CREDITS_S 0
1102#define RX_CREDITS_V(x) ((x) << RX_CREDITS_S)
1103
1104#define RX_FORCE_ACK_S 28
1105#define RX_FORCE_ACK_V(x) ((x) << RX_FORCE_ACK_S)
1106#define RX_FORCE_ACK_F RX_FORCE_ACK_V(1U)
1107
1108#define RX_DACK_MODE_S 29
1109#define RX_DACK_MODE_M 0x3
1110#define RX_DACK_MODE_V(x) ((x) << RX_DACK_MODE_S)
1111#define RX_DACK_MODE_G(x) (((x) >> RX_DACK_MODE_S) & RX_DACK_MODE_M)
1112
1113#define RX_DACK_CHANGE_S 31
1114#define RX_DACK_CHANGE_V(x) ((x) << RX_DACK_CHANGE_S)
1115#define RX_DACK_CHANGE_F RX_DACK_CHANGE_V(1U)
1116
1117struct cpl_rx_pkt {
1118 struct rss_header rsshdr;
1119 u8 opcode;
1120#if defined(__LITTLE_ENDIAN_BITFIELD)
1121 u8 iff:4;
1122 u8 csum_calc:1;
1123 u8 ipmi_pkt:1;
1124 u8 vlan_ex:1;
1125 u8 ip_frag:1;
1126#else
1127 u8 ip_frag:1;
1128 u8 vlan_ex:1;
1129 u8 ipmi_pkt:1;
1130 u8 csum_calc:1;
1131 u8 iff:4;
1132#endif
1133 __be16 csum;
1134 __be16 vlan;
1135 __be16 len;
1136 __be32 l2info;
1137 __be16 hdr_len;
1138 __be16 err_vec;
1139};
1140
1141#define RX_T6_ETHHDR_LEN_M 0xFF
1142#define RX_T6_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_T6_ETHHDR_LEN_M)
1143
1144#define RXF_PSH_S 20
1145#define RXF_PSH_V(x) ((x) << RXF_PSH_S)
1146#define RXF_PSH_F RXF_PSH_V(1U)
1147
1148#define RXF_SYN_S 21
1149#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1150#define RXF_SYN_F RXF_SYN_V(1U)
1151
1152#define RXF_UDP_S 22
1153#define RXF_UDP_V(x) ((x) << RXF_UDP_S)
1154#define RXF_UDP_F RXF_UDP_V(1U)
1155
1156#define RXF_TCP_S 23
1157#define RXF_TCP_V(x) ((x) << RXF_TCP_S)
1158#define RXF_TCP_F RXF_TCP_V(1U)
1159
1160#define RXF_IP_S 24
1161#define RXF_IP_V(x) ((x) << RXF_IP_S)
1162#define RXF_IP_F RXF_IP_V(1U)
1163
1164#define RXF_IP6_S 25
1165#define RXF_IP6_V(x) ((x) << RXF_IP6_S)
1166#define RXF_IP6_F RXF_IP6_V(1U)
1167
1168#define RXF_SYN_COOKIE_S 26
1169#define RXF_SYN_COOKIE_V(x) ((x) << RXF_SYN_COOKIE_S)
1170#define RXF_SYN_COOKIE_F RXF_SYN_COOKIE_V(1U)
1171
1172#define RXF_FCOE_S 26
1173#define RXF_FCOE_V(x) ((x) << RXF_FCOE_S)
1174#define RXF_FCOE_F RXF_FCOE_V(1U)
1175
1176#define RXF_LRO_S 27
1177#define RXF_LRO_V(x) ((x) << RXF_LRO_S)
1178#define RXF_LRO_F RXF_LRO_V(1U)
1179
1180
1181#define RX_ETHHDR_LEN_S 0
1182#define RX_ETHHDR_LEN_M 0x1F
1183#define RX_ETHHDR_LEN_V(x) ((x) << RX_ETHHDR_LEN_S)
1184#define RX_ETHHDR_LEN_G(x) (((x) >> RX_ETHHDR_LEN_S) & RX_ETHHDR_LEN_M)
1185
1186#define RX_T5_ETHHDR_LEN_S 0
1187#define RX_T5_ETHHDR_LEN_M 0x3F
1188#define RX_T5_ETHHDR_LEN_V(x) ((x) << RX_T5_ETHHDR_LEN_S)
1189#define RX_T5_ETHHDR_LEN_G(x) (((x) >> RX_T5_ETHHDR_LEN_S) & RX_T5_ETHHDR_LEN_M)
1190
1191#define RX_MACIDX_S 8
1192#define RX_MACIDX_M 0x1FF
1193#define RX_MACIDX_V(x) ((x) << RX_MACIDX_S)
1194#define RX_MACIDX_G(x) (((x) >> RX_MACIDX_S) & RX_MACIDX_M)
1195
1196#define RXF_SYN_S 21
1197#define RXF_SYN_V(x) ((x) << RXF_SYN_S)
1198#define RXF_SYN_F RXF_SYN_V(1U)
1199
1200#define RX_CHAN_S 28
1201#define RX_CHAN_M 0xF
1202#define RX_CHAN_V(x) ((x) << RX_CHAN_S)
1203#define RX_CHAN_G(x) (((x) >> RX_CHAN_S) & RX_CHAN_M)
1204
1205
1206#define RX_TCPHDR_LEN_S 0
1207#define RX_TCPHDR_LEN_M 0x3F
1208#define RX_TCPHDR_LEN_V(x) ((x) << RX_TCPHDR_LEN_S)
1209#define RX_TCPHDR_LEN_G(x) (((x) >> RX_TCPHDR_LEN_S) & RX_TCPHDR_LEN_M)
1210
1211#define RX_IPHDR_LEN_S 6
1212#define RX_IPHDR_LEN_M 0x3FF
1213#define RX_IPHDR_LEN_V(x) ((x) << RX_IPHDR_LEN_S)
1214#define RX_IPHDR_LEN_G(x) (((x) >> RX_IPHDR_LEN_S) & RX_IPHDR_LEN_M)
1215
1216
1217#define RXERR_CSUM_S 13
1218#define RXERR_CSUM_V(x) ((x) << RXERR_CSUM_S)
1219#define RXERR_CSUM_F RXERR_CSUM_V(1U)
1220
1221#define T6_COMPR_RXERR_LEN_S 1
1222#define T6_COMPR_RXERR_LEN_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1223#define T6_COMPR_RXERR_LEN_F T6_COMPR_RXERR_LEN_V(1U)
1224
1225#define T6_COMPR_RXERR_VEC_S 0
1226#define T6_COMPR_RXERR_VEC_M 0x3F
1227#define T6_COMPR_RXERR_VEC_V(x) ((x) << T6_COMPR_RXERR_LEN_S)
1228#define T6_COMPR_RXERR_VEC_G(x) \
1229 (((x) >> T6_COMPR_RXERR_VEC_S) & T6_COMPR_RXERR_VEC_M)
1230
1231
1232#define T6_COMPR_RXERR_SUM_S 4
1233#define T6_COMPR_RXERR_SUM_V(x) ((x) << T6_COMPR_RXERR_SUM_S)
1234#define T6_COMPR_RXERR_SUM_F T6_COMPR_RXERR_SUM_V(1U)
1235
1236struct cpl_trace_pkt {
1237 u8 opcode;
1238 u8 intf;
1239#if defined(__LITTLE_ENDIAN_BITFIELD)
1240 u8 runt:4;
1241 u8 filter_hit:4;
1242 u8 :6;
1243 u8 err:1;
1244 u8 trunc:1;
1245#else
1246 u8 filter_hit:4;
1247 u8 runt:4;
1248 u8 trunc:1;
1249 u8 err:1;
1250 u8 :6;
1251#endif
1252 __be16 rsvd;
1253 __be16 len;
1254 __be64 tstamp;
1255};
1256
1257struct cpl_t5_trace_pkt {
1258 __u8 opcode;
1259 __u8 intf;
1260#if defined(__LITTLE_ENDIAN_BITFIELD)
1261 __u8 runt:4;
1262 __u8 filter_hit:4;
1263 __u8:6;
1264 __u8 err:1;
1265 __u8 trunc:1;
1266#else
1267 __u8 filter_hit:4;
1268 __u8 runt:4;
1269 __u8 trunc:1;
1270 __u8 err:1;
1271 __u8:6;
1272#endif
1273 __be16 rsvd;
1274 __be16 len;
1275 __be64 tstamp;
1276 __be64 rsvd1;
1277};
1278
1279struct cpl_l2t_write_req {
1280 WR_HDR;
1281 union opcode_tid ot;
1282 __be16 params;
1283 __be16 l2t_idx;
1284 __be16 vlan;
1285 u8 dst_mac[6];
1286};
1287
1288
1289#define L2T_W_INFO_S 2
1290#define L2T_W_INFO_V(x) ((x) << L2T_W_INFO_S)
1291
1292#define L2T_W_PORT_S 8
1293#define L2T_W_PORT_V(x) ((x) << L2T_W_PORT_S)
1294
1295#define L2T_W_NOREPLY_S 15
1296#define L2T_W_NOREPLY_V(x) ((x) << L2T_W_NOREPLY_S)
1297#define L2T_W_NOREPLY_F L2T_W_NOREPLY_V(1U)
1298
1299#define CPL_L2T_VLAN_NONE 0xfff
1300
1301struct cpl_l2t_write_rpl {
1302 union opcode_tid ot;
1303 u8 status;
1304 u8 rsvd[3];
1305};
1306
1307struct cpl_smt_write_req {
1308 WR_HDR;
1309 union opcode_tid ot;
1310 __be32 params;
1311 __be16 pfvf1;
1312 u8 src_mac1[6];
1313 __be16 pfvf0;
1314 u8 src_mac0[6];
1315};
1316
1317struct cpl_t6_smt_write_req {
1318 WR_HDR;
1319 union opcode_tid ot;
1320 __be32 params;
1321 __be64 tag;
1322 __be16 pfvf0;
1323 u8 src_mac0[6];
1324 __be32 local_ip;
1325 __be32 rsvd;
1326};
1327
1328struct cpl_smt_write_rpl {
1329 union opcode_tid ot;
1330 u8 status;
1331 u8 rsvd[3];
1332};
1333
1334
1335#define SMTW_OVLAN_IDX_S 16
1336#define SMTW_OVLAN_IDX_V(x) ((x) << SMTW_OVLAN_IDX_S)
1337
1338#define SMTW_IDX_S 20
1339#define SMTW_IDX_V(x) ((x) << SMTW_IDX_S)
1340
1341#define SMTW_NORPL_S 31
1342#define SMTW_NORPL_V(x) ((x) << SMTW_NORPL_S)
1343#define SMTW_NORPL_F SMTW_NORPL_V(1U)
1344
1345struct cpl_rdma_terminate {
1346 union opcode_tid ot;
1347 __be16 rsvd;
1348 __be16 len;
1349};
1350
1351struct cpl_sge_egr_update {
1352 __be32 opcode_qid;
1353 __be16 cidx;
1354 __be16 pidx;
1355};
1356
1357
1358#define EGR_QID_S 0
1359#define EGR_QID_M 0x1FFFF
1360#define EGR_QID_G(x) (((x) >> EGR_QID_S) & EGR_QID_M)
1361
1362
1363enum {
1364 FW_TYPE_CMD_RPL = 0,
1365 FW_TYPE_WR_RPL = 1,
1366 FW_TYPE_CQE = 2,
1367 FW_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1368 FW_TYPE_RSSCPL = 4,
1369};
1370
1371struct cpl_fw4_pld {
1372 u8 opcode;
1373 u8 rsvd0[3];
1374 u8 type;
1375 u8 rsvd1;
1376 __be16 len;
1377 __be64 data;
1378 __be64 rsvd2;
1379};
1380
1381struct cpl_fw6_pld {
1382 u8 opcode;
1383 u8 rsvd[5];
1384 __be16 len;
1385 __be64 data[4];
1386};
1387
1388struct cpl_fw4_msg {
1389 u8 opcode;
1390 u8 type;
1391 __be16 rsvd0;
1392 __be32 rsvd1;
1393 __be64 data[2];
1394};
1395
1396struct cpl_fw4_ack {
1397 union opcode_tid ot;
1398 u8 credits;
1399 u8 rsvd0[2];
1400 u8 seq_vld;
1401 __be32 snd_nxt;
1402 __be32 snd_una;
1403 __be64 rsvd1;
1404};
1405
1406enum {
1407 CPL_FW4_ACK_FLAGS_SEQVAL = 0x1,
1408 CPL_FW4_ACK_FLAGS_CH = 0x2,
1409 CPL_FW4_ACK_FLAGS_FLOWC = 0x4,
1410};
1411
1412struct cpl_fw6_msg {
1413 u8 opcode;
1414 u8 type;
1415 __be16 rsvd0;
1416 __be32 rsvd1;
1417 __be64 data[4];
1418};
1419
1420
1421enum {
1422 FW6_TYPE_CMD_RPL = 0,
1423 FW6_TYPE_WR_RPL = 1,
1424 FW6_TYPE_CQE = 2,
1425 FW6_TYPE_OFLD_CONNECTION_WR_RPL = 3,
1426 FW6_TYPE_RSSCPL = FW_TYPE_RSSCPL,
1427};
1428
1429struct cpl_fw6_msg_ofld_connection_wr_rpl {
1430 __u64 cookie;
1431 __be32 tid;
1432 __u8 t_state;
1433 __u8 retval;
1434 __u8 rsvd[2];
1435};
1436
1437struct cpl_tx_data {
1438 union opcode_tid ot;
1439 __be32 len;
1440 __be32 rsvd;
1441 __be32 flags;
1442};
1443
1444
1445#define TX_FORCE_S 13
1446#define TX_FORCE_V(x) ((x) << TX_FORCE_S)
1447
1448#define T6_TX_FORCE_S 20
1449#define T6_TX_FORCE_V(x) ((x) << T6_TX_FORCE_S)
1450#define T6_TX_FORCE_F T6_TX_FORCE_V(1U)
1451
1452#define TX_SHOVE_S 14
1453#define TX_SHOVE_V(x) ((x) << TX_SHOVE_S)
1454
1455#define TX_ULP_MODE_S 10
1456#define TX_ULP_MODE_M 0x7
1457#define TX_ULP_MODE_V(x) ((x) << TX_ULP_MODE_S)
1458#define TX_ULP_MODE_G(x) (((x) >> TX_ULP_MODE_S) & TX_ULP_MODE_M)
1459
1460enum {
1461 ULP_TX_MEM_READ = 2,
1462 ULP_TX_MEM_WRITE = 3,
1463 ULP_TX_PKT = 4
1464};
1465
1466enum {
1467 ULP_TX_SC_NOOP = 0x80,
1468 ULP_TX_SC_IMM = 0x81,
1469 ULP_TX_SC_DSGL = 0x82,
1470 ULP_TX_SC_ISGL = 0x83,
1471 ULP_TX_SC_MEMRD = 0x86
1472};
1473
1474#define ULPTX_CMD_S 24
1475#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1476
1477#define ULPTX_LEN16_S 0
1478#define ULPTX_LEN16_M 0xFF
1479#define ULPTX_LEN16_V(x) ((x) << ULPTX_LEN16_S)
1480
1481#define ULP_TX_SC_MORE_S 23
1482#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1483#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1484
1485struct ulptx_sge_pair {
1486 __be32 len[2];
1487 __be64 addr[2];
1488};
1489
1490struct ulptx_sgl {
1491 __be32 cmd_nsge;
1492 __be32 len0;
1493 __be64 addr0;
1494 struct ulptx_sge_pair sge[0];
1495};
1496
1497struct ulptx_idata {
1498 __be32 cmd_more;
1499 __be32 len;
1500};
1501
1502struct ulp_txpkt {
1503 __be32 cmd_dest;
1504 __be32 len;
1505};
1506
1507#define ULPTX_CMD_S 24
1508#define ULPTX_CMD_M 0xFF
1509#define ULPTX_CMD_V(x) ((x) << ULPTX_CMD_S)
1510
1511#define ULPTX_NSGE_S 0
1512#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1513
1514#define ULPTX_MORE_S 23
1515#define ULPTX_MORE_V(x) ((x) << ULPTX_MORE_S)
1516#define ULPTX_MORE_F ULPTX_MORE_V(1U)
1517
1518#define ULP_TXPKT_DEST_S 16
1519#define ULP_TXPKT_DEST_M 0x3
1520#define ULP_TXPKT_DEST_V(x) ((x) << ULP_TXPKT_DEST_S)
1521
1522#define ULP_TXPKT_FID_S 4
1523#define ULP_TXPKT_FID_M 0x7ff
1524#define ULP_TXPKT_FID_V(x) ((x) << ULP_TXPKT_FID_S)
1525
1526#define ULP_TXPKT_RO_S 3
1527#define ULP_TXPKT_RO_V(x) ((x) << ULP_TXPKT_RO_S)
1528#define ULP_TXPKT_RO_F ULP_TXPKT_RO_V(1U)
1529
1530enum cpl_tx_tnl_lso_type {
1531 TX_TNL_TYPE_OPAQUE,
1532 TX_TNL_TYPE_NVGRE,
1533 TX_TNL_TYPE_VXLAN,
1534 TX_TNL_TYPE_GENEVE,
1535};
1536
1537struct cpl_tx_tnl_lso {
1538 __be32 op_to_IpIdSplitOut;
1539 __be16 IpIdOffsetOut;
1540 __be16 UdpLenSetOut_to_TnlHdrLen;
1541 __be64 r1;
1542 __be32 Flow_to_TcpHdrLen;
1543 __be16 IpIdOffset;
1544 __be16 IpIdSplit_to_Mss;
1545 __be32 TCPSeqOffset;
1546 __be32 EthLenOffset_Size;
1547
1548};
1549
1550#define CPL_TX_TNL_LSO_OPCODE_S 24
1551#define CPL_TX_TNL_LSO_OPCODE_M 0xff
1552#define CPL_TX_TNL_LSO_OPCODE_V(x) ((x) << CPL_TX_TNL_LSO_OPCODE_S)
1553#define CPL_TX_TNL_LSO_OPCODE_G(x) \
1554 (((x) >> CPL_TX_TNL_LSO_OPCODE_S) & CPL_TX_TNL_LSO_OPCODE_M)
1555
1556#define CPL_TX_TNL_LSO_FIRST_S 23
1557#define CPL_TX_TNL_LSO_FIRST_M 0x1
1558#define CPL_TX_TNL_LSO_FIRST_V(x) ((x) << CPL_TX_TNL_LSO_FIRST_S)
1559#define CPL_TX_TNL_LSO_FIRST_G(x) \
1560 (((x) >> CPL_TX_TNL_LSO_FIRST_S) & CPL_TX_TNL_LSO_FIRST_M)
1561#define CPL_TX_TNL_LSO_FIRST_F CPL_TX_TNL_LSO_FIRST_V(1U)
1562
1563#define CPL_TX_TNL_LSO_LAST_S 22
1564#define CPL_TX_TNL_LSO_LAST_M 0x1
1565#define CPL_TX_TNL_LSO_LAST_V(x) ((x) << CPL_TX_TNL_LSO_LAST_S)
1566#define CPL_TX_TNL_LSO_LAST_G(x) \
1567 (((x) >> CPL_TX_TNL_LSO_LAST_S) & CPL_TX_TNL_LSO_LAST_M)
1568#define CPL_TX_TNL_LSO_LAST_F CPL_TX_TNL_LSO_LAST_V(1U)
1569
1570#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_S 21
1571#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_M 0x1
1572#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(x) \
1573 ((x) << CPL_TX_TNL_LSO_ETHHDRLENXOUT_S)
1574#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_G(x) \
1575 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENXOUT_S) & \
1576 CPL_TX_TNL_LSO_ETHHDRLENXOUT_M)
1577#define CPL_TX_TNL_LSO_ETHHDRLENXOUT_F CPL_TX_TNL_LSO_ETHHDRLENXOUT_V(1U)
1578
1579#define CPL_TX_TNL_LSO_IPV6OUT_S 20
1580#define CPL_TX_TNL_LSO_IPV6OUT_M 0x1
1581#define CPL_TX_TNL_LSO_IPV6OUT_V(x) ((x) << CPL_TX_TNL_LSO_IPV6OUT_S)
1582#define CPL_TX_TNL_LSO_IPV6OUT_G(x) \
1583 (((x) >> CPL_TX_TNL_LSO_IPV6OUT_S) & CPL_TX_TNL_LSO_IPV6OUT_M)
1584#define CPL_TX_TNL_LSO_IPV6OUT_F CPL_TX_TNL_LSO_IPV6OUT_V(1U)
1585
1586#define CPL_TX_TNL_LSO_ETHHDRLEN_S 16
1587#define CPL_TX_TNL_LSO_ETHHDRLEN_M 0xf
1588#define CPL_TX_TNL_LSO_ETHHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_ETHHDRLEN_S)
1589#define CPL_TX_TNL_LSO_ETHHDRLEN_G(x) \
1590 (((x) >> CPL_TX_TNL_LSO_ETHHDRLEN_S) & CPL_TX_TNL_LSO_ETHHDRLEN_M)
1591
1592#define CPL_TX_TNL_LSO_IPHDRLEN_S 4
1593#define CPL_TX_TNL_LSO_IPHDRLEN_M 0xfff
1594#define CPL_TX_TNL_LSO_IPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLEN_S)
1595#define CPL_TX_TNL_LSO_IPHDRLEN_G(x) \
1596 (((x) >> CPL_TX_TNL_LSO_IPHDRLEN_S) & CPL_TX_TNL_LSO_IPHDRLEN_M)
1597
1598#define CPL_TX_TNL_LSO_TCPHDRLEN_S 0
1599#define CPL_TX_TNL_LSO_TCPHDRLEN_M 0xf
1600#define CPL_TX_TNL_LSO_TCPHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TCPHDRLEN_S)
1601#define CPL_TX_TNL_LSO_TCPHDRLEN_G(x) \
1602 (((x) >> CPL_TX_TNL_LSO_TCPHDRLEN_S) & CPL_TX_TNL_LSO_TCPHDRLEN_M)
1603
1604#define CPL_TX_TNL_LSO_MSS_S 0
1605#define CPL_TX_TNL_LSO_MSS_M 0x3fff
1606#define CPL_TX_TNL_LSO_MSS_V(x) ((x) << CPL_TX_TNL_LSO_MSS_S)
1607#define CPL_TX_TNL_LSO_MSS_G(x) \
1608 (((x) >> CPL_TX_TNL_LSO_MSS_S) & CPL_TX_TNL_LSO_MSS_M)
1609
1610#define CPL_TX_TNL_LSO_SIZE_S 0
1611#define CPL_TX_TNL_LSO_SIZE_M 0xfffffff
1612#define CPL_TX_TNL_LSO_SIZE_V(x) ((x) << CPL_TX_TNL_LSO_SIZE_S)
1613#define CPL_TX_TNL_LSO_SIZE_G(x) \
1614 (((x) >> CPL_TX_TNL_LSO_SIZE_S) & CPL_TX_TNL_LSO_SIZE_M)
1615
1616#define CPL_TX_TNL_LSO_ETHHDRLENOUT_S 16
1617#define CPL_TX_TNL_LSO_ETHHDRLENOUT_M 0xf
1618#define CPL_TX_TNL_LSO_ETHHDRLENOUT_V(x) \
1619 ((x) << CPL_TX_TNL_LSO_ETHHDRLENOUT_S)
1620#define CPL_TX_TNL_LSO_ETHHDRLENOUT_G(x) \
1621 (((x) >> CPL_TX_TNL_LSO_ETHHDRLENOUT_S) & CPL_TX_TNL_LSO_ETHHDRLENOUT_M)
1622
1623#define CPL_TX_TNL_LSO_IPHDRLENOUT_S 4
1624#define CPL_TX_TNL_LSO_IPHDRLENOUT_M 0xfff
1625#define CPL_TX_TNL_LSO_IPHDRLENOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRLENOUT_S)
1626#define CPL_TX_TNL_LSO_IPHDRLENOUT_G(x) \
1627 (((x) >> CPL_TX_TNL_LSO_IPHDRLENOUT_S) & CPL_TX_TNL_LSO_IPHDRLENOUT_M)
1628
1629#define CPL_TX_TNL_LSO_IPHDRCHKOUT_S 3
1630#define CPL_TX_TNL_LSO_IPHDRCHKOUT_M 0x1
1631#define CPL_TX_TNL_LSO_IPHDRCHKOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPHDRCHKOUT_S)
1632#define CPL_TX_TNL_LSO_IPHDRCHKOUT_G(x) \
1633 (((x) >> CPL_TX_TNL_LSO_IPHDRCHKOUT_S) & CPL_TX_TNL_LSO_IPHDRCHKOUT_M)
1634#define CPL_TX_TNL_LSO_IPHDRCHKOUT_F CPL_TX_TNL_LSO_IPHDRCHKOUT_V(1U)
1635
1636#define CPL_TX_TNL_LSO_IPLENSETOUT_S 2
1637#define CPL_TX_TNL_LSO_IPLENSETOUT_M 0x1
1638#define CPL_TX_TNL_LSO_IPLENSETOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPLENSETOUT_S)
1639#define CPL_TX_TNL_LSO_IPLENSETOUT_G(x) \
1640 (((x) >> CPL_TX_TNL_LSO_IPLENSETOUT_S) & CPL_TX_TNL_LSO_IPLENSETOUT_M)
1641#define CPL_TX_TNL_LSO_IPLENSETOUT_F CPL_TX_TNL_LSO_IPLENSETOUT_V(1U)
1642
1643#define CPL_TX_TNL_LSO_IPIDINCOUT_S 1
1644#define CPL_TX_TNL_LSO_IPIDINCOUT_M 0x1
1645#define CPL_TX_TNL_LSO_IPIDINCOUT_V(x) ((x) << CPL_TX_TNL_LSO_IPIDINCOUT_S)
1646#define CPL_TX_TNL_LSO_IPIDINCOUT_G(x) \
1647 (((x) >> CPL_TX_TNL_LSO_IPIDINCOUT_S) & CPL_TX_TNL_LSO_IPIDINCOUT_M)
1648#define CPL_TX_TNL_LSO_IPIDINCOUT_F CPL_TX_TNL_LSO_IPIDINCOUT_V(1U)
1649
1650#define CPL_TX_TNL_LSO_UDPCHKCLROUT_S 14
1651#define CPL_TX_TNL_LSO_UDPCHKCLROUT_M 0x1
1652#define CPL_TX_TNL_LSO_UDPCHKCLROUT_V(x) \
1653 ((x) << CPL_TX_TNL_LSO_UDPCHKCLROUT_S)
1654#define CPL_TX_TNL_LSO_UDPCHKCLROUT_G(x) \
1655 (((x) >> CPL_TX_TNL_LSO_UDPCHKCLROUT_S) & \
1656 CPL_TX_TNL_LSO_UDPCHKCLROUT_M)
1657#define CPL_TX_TNL_LSO_UDPCHKCLROUT_F CPL_TX_TNL_LSO_UDPCHKCLROUT_V(1U)
1658
1659#define CPL_TX_TNL_LSO_UDPLENSETOUT_S 15
1660#define CPL_TX_TNL_LSO_UDPLENSETOUT_M 0x1
1661#define CPL_TX_TNL_LSO_UDPLENSETOUT_V(x) \
1662 ((x) << CPL_TX_TNL_LSO_UDPLENSETOUT_S)
1663#define CPL_TX_TNL_LSO_UDPLENSETOUT_G(x) \
1664 (((x) >> CPL_TX_TNL_LSO_UDPLENSETOUT_S) & \
1665 CPL_TX_TNL_LSO_UDPLENSETOUT_M)
1666#define CPL_TX_TNL_LSO_UDPLENSETOUT_F CPL_TX_TNL_LSO_UDPLENSETOUT_V(1U)
1667
1668#define CPL_TX_TNL_LSO_TNLTYPE_S 12
1669#define CPL_TX_TNL_LSO_TNLTYPE_M 0x3
1670#define CPL_TX_TNL_LSO_TNLTYPE_V(x) ((x) << CPL_TX_TNL_LSO_TNLTYPE_S)
1671#define CPL_TX_TNL_LSO_TNLTYPE_G(x) \
1672 (((x) >> CPL_TX_TNL_LSO_TNLTYPE_S) & CPL_TX_TNL_LSO_TNLTYPE_M)
1673
1674#define S_CPL_TX_TNL_LSO_ETHHDRLEN 16
1675#define M_CPL_TX_TNL_LSO_ETHHDRLEN 0xf
1676#define V_CPL_TX_TNL_LSO_ETHHDRLEN(x) ((x) << S_CPL_TX_TNL_LSO_ETHHDRLEN)
1677#define G_CPL_TX_TNL_LSO_ETHHDRLEN(x) \
1678 (((x) >> S_CPL_TX_TNL_LSO_ETHHDRLEN) & M_CPL_TX_TNL_LSO_ETHHDRLEN)
1679
1680#define CPL_TX_TNL_LSO_TNLHDRLEN_S 0
1681#define CPL_TX_TNL_LSO_TNLHDRLEN_M 0xfff
1682#define CPL_TX_TNL_LSO_TNLHDRLEN_V(x) ((x) << CPL_TX_TNL_LSO_TNLHDRLEN_S)
1683#define CPL_TX_TNL_LSO_TNLHDRLEN_G(x) \
1684 (((x) >> CPL_TX_TNL_LSO_TNLHDRLEN_S) & CPL_TX_TNL_LSO_TNLHDRLEN_M)
1685
1686#define CPL_TX_TNL_LSO_IPV6_S 20
1687#define CPL_TX_TNL_LSO_IPV6_M 0x1
1688#define CPL_TX_TNL_LSO_IPV6_V(x) ((x) << CPL_TX_TNL_LSO_IPV6_S)
1689#define CPL_TX_TNL_LSO_IPV6_G(x) \
1690 (((x) >> CPL_TX_TNL_LSO_IPV6_S) & CPL_TX_TNL_LSO_IPV6_M)
1691#define CPL_TX_TNL_LSO_IPV6_F CPL_TX_TNL_LSO_IPV6_V(1U)
1692
1693#define ULP_TX_SC_MORE_S 23
1694#define ULP_TX_SC_MORE_V(x) ((x) << ULP_TX_SC_MORE_S)
1695#define ULP_TX_SC_MORE_F ULP_TX_SC_MORE_V(1U)
1696
1697struct ulp_mem_io {
1698 WR_HDR;
1699 __be32 cmd;
1700 __be32 len16;
1701 __be32 dlen;
1702 __be32 lock_addr;
1703};
1704
1705#define ULP_MEMIO_LOCK_S 31
1706#define ULP_MEMIO_LOCK_V(x) ((x) << ULP_MEMIO_LOCK_S)
1707#define ULP_MEMIO_LOCK_F ULP_MEMIO_LOCK_V(1U)
1708
1709
1710#define ULP_MEMIO_ORDER_S 23
1711#define ULP_MEMIO_ORDER_V(x) ((x) << ULP_MEMIO_ORDER_S)
1712#define ULP_MEMIO_ORDER_F ULP_MEMIO_ORDER_V(1U)
1713
1714#define T5_ULP_MEMIO_IMM_S 23
1715#define T5_ULP_MEMIO_IMM_V(x) ((x) << T5_ULP_MEMIO_IMM_S)
1716#define T5_ULP_MEMIO_IMM_F T5_ULP_MEMIO_IMM_V(1U)
1717
1718#define T5_ULP_MEMIO_ORDER_S 22
1719#define T5_ULP_MEMIO_ORDER_V(x) ((x) << T5_ULP_MEMIO_ORDER_S)
1720#define T5_ULP_MEMIO_ORDER_F T5_ULP_MEMIO_ORDER_V(1U)
1721
1722#define T5_ULP_MEMIO_FID_S 4
1723#define T5_ULP_MEMIO_FID_M 0x7ff
1724#define T5_ULP_MEMIO_FID_V(x) ((x) << T5_ULP_MEMIO_FID_S)
1725
1726
1727#define ULP_MEMIO_ADDR_S 0
1728#define ULP_MEMIO_ADDR_V(x) ((x) << ULP_MEMIO_ADDR_S)
1729
1730
1731#define ULP_MEMIO_DATA_LEN_S 0
1732#define ULP_MEMIO_DATA_LEN_V(x) ((x) << ULP_MEMIO_DATA_LEN_S)
1733
1734#define ULPTX_NSGE_S 0
1735#define ULPTX_NSGE_M 0xFFFF
1736#define ULPTX_NSGE_V(x) ((x) << ULPTX_NSGE_S)
1737#define ULPTX_NSGE_G(x) (((x) >> ULPTX_NSGE_S) & ULPTX_NSGE_M)
1738
1739struct ulptx_sc_memrd {
1740 __be32 cmd_to_len;
1741 __be32 addr;
1742};
1743
1744#define ULP_TXPKT_DATAMODIFY_S 23
1745#define ULP_TXPKT_DATAMODIFY_M 0x1
1746#define ULP_TXPKT_DATAMODIFY_V(x) ((x) << ULP_TXPKT_DATAMODIFY_S)
1747#define ULP_TXPKT_DATAMODIFY_G(x) \
1748 (((x) >> ULP_TXPKT_DATAMODIFY_S) & ULP_TXPKT_DATAMODIFY__M)
1749#define ULP_TXPKT_DATAMODIFY_F ULP_TXPKT_DATAMODIFY_V(1U)
1750
1751#define ULP_TXPKT_CHANNELID_S 22
1752#define ULP_TXPKT_CHANNELID_M 0x1
1753#define ULP_TXPKT_CHANNELID_V(x) ((x) << ULP_TXPKT_CHANNELID_S)
1754#define ULP_TXPKT_CHANNELID_G(x) \
1755 (((x) >> ULP_TXPKT_CHANNELID_S) & ULP_TXPKT_CHANNELID_M)
1756#define ULP_TXPKT_CHANNELID_F ULP_TXPKT_CHANNELID_V(1U)
1757
1758#define SCMD_SEQ_NO_CTRL_S 29
1759#define SCMD_SEQ_NO_CTRL_M 0x3
1760#define SCMD_SEQ_NO_CTRL_V(x) ((x) << SCMD_SEQ_NO_CTRL_S)
1761#define SCMD_SEQ_NO_CTRL_G(x) \
1762 (((x) >> SCMD_SEQ_NO_CTRL_S) & SCMD_SEQ_NO_CTRL_M)
1763
1764
1765#define SCMD_STATUS_PRESENT_S 28
1766#define SCMD_STATUS_PRESENT_M 0x1
1767#define SCMD_STATUS_PRESENT_V(x) ((x) << SCMD_STATUS_PRESENT_S)
1768#define SCMD_STATUS_PRESENT_G(x) \
1769 (((x) >> SCMD_STATUS_PRESENT_S) & SCMD_STATUS_PRESENT_M)
1770#define SCMD_STATUS_PRESENT_F SCMD_STATUS_PRESENT_V(1U)
1771
1772
1773
1774
1775#define SCMD_PROTO_VERSION_S 24
1776#define SCMD_PROTO_VERSION_M 0xf
1777#define SCMD_PROTO_VERSION_V(x) ((x) << SCMD_PROTO_VERSION_S)
1778#define SCMD_PROTO_VERSION_G(x) \
1779 (((x) >> SCMD_PROTO_VERSION_S) & SCMD_PROTO_VERSION_M)
1780
1781
1782#define SCMD_ENC_DEC_CTRL_S 23
1783#define SCMD_ENC_DEC_CTRL_M 0x1
1784#define SCMD_ENC_DEC_CTRL_V(x) ((x) << SCMD_ENC_DEC_CTRL_S)
1785#define SCMD_ENC_DEC_CTRL_G(x) \
1786 (((x) >> SCMD_ENC_DEC_CTRL_S) & SCMD_ENC_DEC_CTRL_M)
1787#define SCMD_ENC_DEC_CTRL_F SCMD_ENC_DEC_CTRL_V(1U)
1788
1789
1790#define SCMD_CIPH_AUTH_SEQ_CTRL_S 22
1791#define SCMD_CIPH_AUTH_SEQ_CTRL_M 0x1
1792#define SCMD_CIPH_AUTH_SEQ_CTRL_V(x) \
1793 ((x) << SCMD_CIPH_AUTH_SEQ_CTRL_S)
1794#define SCMD_CIPH_AUTH_SEQ_CTRL_G(x) \
1795 (((x) >> SCMD_CIPH_AUTH_SEQ_CTRL_S) & SCMD_CIPH_AUTH_SEQ_CTRL_M)
1796#define SCMD_CIPH_AUTH_SEQ_CTRL_F SCMD_CIPH_AUTH_SEQ_CTRL_V(1U)
1797
1798
1799
1800
1801#define SCMD_CIPH_MODE_S 18
1802#define SCMD_CIPH_MODE_M 0xf
1803#define SCMD_CIPH_MODE_V(x) ((x) << SCMD_CIPH_MODE_S)
1804#define SCMD_CIPH_MODE_G(x) \
1805 (((x) >> SCMD_CIPH_MODE_S) & SCMD_CIPH_MODE_M)
1806
1807
1808
1809
1810#define SCMD_AUTH_MODE_S 14
1811#define SCMD_AUTH_MODE_M 0xf
1812#define SCMD_AUTH_MODE_V(x) ((x) << SCMD_AUTH_MODE_S)
1813#define SCMD_AUTH_MODE_G(x) \
1814 (((x) >> SCMD_AUTH_MODE_S) & SCMD_AUTH_MODE_M)
1815
1816
1817
1818
1819#define SCMD_HMAC_CTRL_S 11
1820#define SCMD_HMAC_CTRL_M 0x7
1821#define SCMD_HMAC_CTRL_V(x) ((x) << SCMD_HMAC_CTRL_S)
1822#define SCMD_HMAC_CTRL_G(x) \
1823 (((x) >> SCMD_HMAC_CTRL_S) & SCMD_HMAC_CTRL_M)
1824
1825
1826#define SCMD_IV_SIZE_S 7
1827#define SCMD_IV_SIZE_M 0xf
1828#define SCMD_IV_SIZE_V(x) ((x) << SCMD_IV_SIZE_S)
1829#define SCMD_IV_SIZE_G(x) \
1830 (((x) >> SCMD_IV_SIZE_S) & SCMD_IV_SIZE_M)
1831
1832
1833#define SCMD_NUM_IVS_S 0
1834#define SCMD_NUM_IVS_M 0x7f
1835#define SCMD_NUM_IVS_V(x) ((x) << SCMD_NUM_IVS_S)
1836#define SCMD_NUM_IVS_G(x) \
1837 (((x) >> SCMD_NUM_IVS_S) & SCMD_NUM_IVS_M)
1838
1839
1840
1841
1842
1843
1844#define SCMD_ENB_DBGID_S 31
1845#define SCMD_ENB_DBGID_M 0x1
1846#define SCMD_ENB_DBGID_V(x) ((x) << SCMD_ENB_DBGID_S)
1847#define SCMD_ENB_DBGID_G(x) \
1848 (((x) >> SCMD_ENB_DBGID_S) & SCMD_ENB_DBGID_M)
1849
1850
1851#define SCMD_IV_GEN_CTRL_S 30
1852#define SCMD_IV_GEN_CTRL_M 0x1
1853#define SCMD_IV_GEN_CTRL_V(x) ((x) << SCMD_IV_GEN_CTRL_S)
1854#define SCMD_IV_GEN_CTRL_G(x) \
1855 (((x) >> SCMD_IV_GEN_CTRL_S) & SCMD_IV_GEN_CTRL_M)
1856#define SCMD_IV_GEN_CTRL_F SCMD_IV_GEN_CTRL_V(1U)
1857
1858
1859#define SCMD_MORE_FRAGS_S 20
1860#define SCMD_MORE_FRAGS_M 0x1
1861#define SCMD_MORE_FRAGS_V(x) ((x) << SCMD_MORE_FRAGS_S)
1862#define SCMD_MORE_FRAGS_G(x) (((x) >> SCMD_MORE_FRAGS_S) & SCMD_MORE_FRAGS_M)
1863
1864
1865#define SCMD_LAST_FRAG_S 19
1866#define SCMD_LAST_FRAG_M 0x1
1867#define SCMD_LAST_FRAG_V(x) ((x) << SCMD_LAST_FRAG_S)
1868#define SCMD_LAST_FRAG_G(x) (((x) >> SCMD_LAST_FRAG_S) & SCMD_LAST_FRAG_M)
1869
1870
1871#define SCMD_TLS_COMPPDU_S 18
1872#define SCMD_TLS_COMPPDU_M 0x1
1873#define SCMD_TLS_COMPPDU_V(x) ((x) << SCMD_TLS_COMPPDU_S)
1874#define SCMD_TLS_COMPPDU_G(x) (((x) >> SCMD_TLS_COMPPDU_S) & SCMD_TLS_COMPPDU_M)
1875
1876
1877#define SCMD_KEY_CTX_INLINE_S 17
1878#define SCMD_KEY_CTX_INLINE_M 0x1
1879#define SCMD_KEY_CTX_INLINE_V(x) ((x) << SCMD_KEY_CTX_INLINE_S)
1880#define SCMD_KEY_CTX_INLINE_G(x) \
1881 (((x) >> SCMD_KEY_CTX_INLINE_S) & SCMD_KEY_CTX_INLINE_M)
1882#define SCMD_KEY_CTX_INLINE_F SCMD_KEY_CTX_INLINE_V(1U)
1883
1884
1885#define SCMD_TLS_FRAG_ENABLE_S 16
1886#define SCMD_TLS_FRAG_ENABLE_M 0x1
1887#define SCMD_TLS_FRAG_ENABLE_V(x) ((x) << SCMD_TLS_FRAG_ENABLE_S)
1888#define SCMD_TLS_FRAG_ENABLE_G(x) \
1889 (((x) >> SCMD_TLS_FRAG_ENABLE_S) & SCMD_TLS_FRAG_ENABLE_M)
1890#define SCMD_TLS_FRAG_ENABLE_F SCMD_TLS_FRAG_ENABLE_V(1U)
1891
1892
1893
1894
1895
1896#define SCMD_MAC_ONLY_S 15
1897#define SCMD_MAC_ONLY_M 0x1
1898#define SCMD_MAC_ONLY_V(x) ((x) << SCMD_MAC_ONLY_S)
1899#define SCMD_MAC_ONLY_G(x) \
1900 (((x) >> SCMD_MAC_ONLY_S) & SCMD_MAC_ONLY_M)
1901#define SCMD_MAC_ONLY_F SCMD_MAC_ONLY_V(1U)
1902
1903
1904
1905
1906#define SCMD_AADIVDROP_S 14
1907#define SCMD_AADIVDROP_M 0x1
1908#define SCMD_AADIVDROP_V(x) ((x) << SCMD_AADIVDROP_S)
1909#define SCMD_AADIVDROP_G(x) \
1910 (((x) >> SCMD_AADIVDROP_S) & SCMD_AADIVDROP_M)
1911#define SCMD_AADIVDROP_F SCMD_AADIVDROP_V(1U)
1912
1913
1914
1915
1916#define SCMD_HDR_LEN_S 0
1917#define SCMD_HDR_LEN_M 0x3fff
1918#define SCMD_HDR_LEN_V(x) ((x) << SCMD_HDR_LEN_S)
1919#define SCMD_HDR_LEN_G(x) \
1920 (((x) >> SCMD_HDR_LEN_S) & SCMD_HDR_LEN_M)
1921
1922struct cpl_tx_sec_pdu {
1923 __be32 op_ivinsrtofst;
1924 __be32 pldlen;
1925 __be32 aadstart_cipherstop_hi;
1926 __be32 cipherstop_lo_authinsert;
1927 __be32 seqno_numivs;
1928 __be32 ivgen_hdrlen;
1929 __be64 scmd1;
1930};
1931
1932#define CPL_TX_SEC_PDU_OPCODE_S 24
1933#define CPL_TX_SEC_PDU_OPCODE_M 0xff
1934#define CPL_TX_SEC_PDU_OPCODE_V(x) ((x) << CPL_TX_SEC_PDU_OPCODE_S)
1935#define CPL_TX_SEC_PDU_OPCODE_G(x) \
1936 (((x) >> CPL_TX_SEC_PDU_OPCODE_S) & CPL_TX_SEC_PDU_OPCODE_M)
1937
1938
1939#define CPL_TX_SEC_PDU_RXCHID_S 22
1940#define CPL_TX_SEC_PDU_RXCHID_M 0x1
1941#define CPL_TX_SEC_PDU_RXCHID_V(x) ((x) << CPL_TX_SEC_PDU_RXCHID_S)
1942#define CPL_TX_SEC_PDU_RXCHID_G(x) \
1943 (((x) >> CPL_TX_SEC_PDU_RXCHID_S) & CPL_TX_SEC_PDU_RXCHID_M)
1944#define CPL_TX_SEC_PDU_RXCHID_F CPL_TX_SEC_PDU_RXCHID_V(1U)
1945
1946
1947#define CPL_TX_SEC_PDU_ACKFOLLOWS_S 21
1948#define CPL_TX_SEC_PDU_ACKFOLLOWS_M 0x1
1949#define CPL_TX_SEC_PDU_ACKFOLLOWS_V(x) ((x) << CPL_TX_SEC_PDU_ACKFOLLOWS_S)
1950#define CPL_TX_SEC_PDU_ACKFOLLOWS_G(x) \
1951 (((x) >> CPL_TX_SEC_PDU_ACKFOLLOWS_S) & CPL_TX_SEC_PDU_ACKFOLLOWS_M)
1952#define CPL_TX_SEC_PDU_ACKFOLLOWS_F CPL_TX_SEC_PDU_ACKFOLLOWS_V(1U)
1953
1954
1955#define CPL_TX_SEC_PDU_ULPTXLPBK_S 20
1956#define CPL_TX_SEC_PDU_ULPTXLPBK_M 0x1
1957#define CPL_TX_SEC_PDU_ULPTXLPBK_V(x) ((x) << CPL_TX_SEC_PDU_ULPTXLPBK_S)
1958#define CPL_TX_SEC_PDU_ULPTXLPBK_G(x) \
1959 (((x) >> CPL_TX_SEC_PDU_ULPTXLPBK_S) & CPL_TX_SEC_PDU_ULPTXLPBK_M)
1960#define CPL_TX_SEC_PDU_ULPTXLPBK_F CPL_TX_SEC_PDU_ULPTXLPBK_V(1U)
1961
1962
1963#define CPL_TX_SEC_PDU_CPLLEN_S 16
1964#define CPL_TX_SEC_PDU_CPLLEN_M 0xf
1965#define CPL_TX_SEC_PDU_CPLLEN_V(x) ((x) << CPL_TX_SEC_PDU_CPLLEN_S)
1966#define CPL_TX_SEC_PDU_CPLLEN_G(x) \
1967 (((x) >> CPL_TX_SEC_PDU_CPLLEN_S) & CPL_TX_SEC_PDU_CPLLEN_M)
1968
1969
1970#define CPL_TX_SEC_PDU_PLACEHOLDER_S 10
1971#define CPL_TX_SEC_PDU_PLACEHOLDER_M 0x1
1972#define CPL_TX_SEC_PDU_PLACEHOLDER_V(x) ((x) << CPL_TX_SEC_PDU_PLACEHOLDER_S)
1973#define CPL_TX_SEC_PDU_PLACEHOLDER_G(x) \
1974 (((x) >> CPL_TX_SEC_PDU_PLACEHOLDER_S) & \
1975 CPL_TX_SEC_PDU_PLACEHOLDER_M)
1976
1977
1978#define CPL_TX_SEC_PDU_IVINSRTOFST_S 0
1979#define CPL_TX_SEC_PDU_IVINSRTOFST_M 0x3ff
1980#define CPL_TX_SEC_PDU_IVINSRTOFST_V(x) ((x) << CPL_TX_SEC_PDU_IVINSRTOFST_S)
1981#define CPL_TX_SEC_PDU_IVINSRTOFST_G(x) \
1982 (((x) >> CPL_TX_SEC_PDU_IVINSRTOFST_S) & \
1983 CPL_TX_SEC_PDU_IVINSRTOFST_M)
1984
1985
1986
1987
1988#define CPL_TX_SEC_PDU_AADSTART_S 24
1989#define CPL_TX_SEC_PDU_AADSTART_M 0xff
1990#define CPL_TX_SEC_PDU_AADSTART_V(x) ((x) << CPL_TX_SEC_PDU_AADSTART_S)
1991#define CPL_TX_SEC_PDU_AADSTART_G(x) \
1992 (((x) >> CPL_TX_SEC_PDU_AADSTART_S) & \
1993 CPL_TX_SEC_PDU_AADSTART_M)
1994
1995
1996
1997
1998#define CPL_TX_SEC_PDU_AADSTOP_S 15
1999#define CPL_TX_SEC_PDU_AADSTOP_M 0x1ff
2000#define CPL_TX_SEC_PDU_AADSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AADSTOP_S)
2001#define CPL_TX_SEC_PDU_AADSTOP_G(x) \
2002 (((x) >> CPL_TX_SEC_PDU_AADSTOP_S) & CPL_TX_SEC_PDU_AADSTOP_M)
2003
2004
2005
2006
2007#define CPL_TX_SEC_PDU_CIPHERSTART_S 5
2008#define CPL_TX_SEC_PDU_CIPHERSTART_M 0x3ff
2009#define CPL_TX_SEC_PDU_CIPHERSTART_V(x) ((x) << CPL_TX_SEC_PDU_CIPHERSTART_S)
2010#define CPL_TX_SEC_PDU_CIPHERSTART_G(x) \
2011 (((x) >> CPL_TX_SEC_PDU_CIPHERSTART_S) & \
2012 CPL_TX_SEC_PDU_CIPHERSTART_M)
2013
2014
2015
2016
2017#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_S 0
2018#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_M 0x1f
2019#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_V(x) \
2020 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_HI_S)
2021#define CPL_TX_SEC_PDU_CIPHERSTOP_HI_G(x) \
2022 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_HI_S) & \
2023 CPL_TX_SEC_PDU_CIPHERSTOP_HI_M)
2024
2025#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_S 28
2026#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_M 0xf
2027#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_V(x) \
2028 ((x) << CPL_TX_SEC_PDU_CIPHERSTOP_LO_S)
2029#define CPL_TX_SEC_PDU_CIPHERSTOP_LO_G(x) \
2030 (((x) >> CPL_TX_SEC_PDU_CIPHERSTOP_LO_S) & \
2031 CPL_TX_SEC_PDU_CIPHERSTOP_LO_M)
2032
2033
2034
2035
2036#define CPL_TX_SEC_PDU_AUTHSTART_S 18
2037#define CPL_TX_SEC_PDU_AUTHSTART_M 0x3ff
2038#define CPL_TX_SEC_PDU_AUTHSTART_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTART_S)
2039#define CPL_TX_SEC_PDU_AUTHSTART_G(x) \
2040 (((x) >> CPL_TX_SEC_PDU_AUTHSTART_S) & \
2041 CPL_TX_SEC_PDU_AUTHSTART_M)
2042
2043
2044
2045
2046#define CPL_TX_SEC_PDU_AUTHSTOP_S 9
2047#define CPL_TX_SEC_PDU_AUTHSTOP_M 0x1ff
2048#define CPL_TX_SEC_PDU_AUTHSTOP_V(x) ((x) << CPL_TX_SEC_PDU_AUTHSTOP_S)
2049#define CPL_TX_SEC_PDU_AUTHSTOP_G(x) \
2050 (((x) >> CPL_TX_SEC_PDU_AUTHSTOP_S) & \
2051 CPL_TX_SEC_PDU_AUTHSTOP_M)
2052
2053
2054
2055
2056#define CPL_TX_SEC_PDU_AUTHINSERT_S 0
2057#define CPL_TX_SEC_PDU_AUTHINSERT_M 0x1ff
2058#define CPL_TX_SEC_PDU_AUTHINSERT_V(x) ((x) << CPL_TX_SEC_PDU_AUTHINSERT_S)
2059#define CPL_TX_SEC_PDU_AUTHINSERT_G(x) \
2060 (((x) >> CPL_TX_SEC_PDU_AUTHINSERT_S) & \
2061 CPL_TX_SEC_PDU_AUTHINSERT_M)
2062
2063struct cpl_rx_phys_dsgl {
2064 __be32 op_to_tid;
2065 __be32 pcirlxorder_to_noofsgentr;
2066 struct rss_header rss_hdr_int;
2067};
2068
2069#define CPL_RX_PHYS_DSGL_OPCODE_S 24
2070#define CPL_RX_PHYS_DSGL_OPCODE_M 0xff
2071#define CPL_RX_PHYS_DSGL_OPCODE_V(x) ((x) << CPL_RX_PHYS_DSGL_OPCODE_S)
2072#define CPL_RX_PHYS_DSGL_OPCODE_G(x) \
2073 (((x) >> CPL_RX_PHYS_DSGL_OPCODE_S) & CPL_RX_PHYS_DSGL_OPCODE_M)
2074
2075#define CPL_RX_PHYS_DSGL_ISRDMA_S 23
2076#define CPL_RX_PHYS_DSGL_ISRDMA_M 0x1
2077#define CPL_RX_PHYS_DSGL_ISRDMA_V(x) ((x) << CPL_RX_PHYS_DSGL_ISRDMA_S)
2078#define CPL_RX_PHYS_DSGL_ISRDMA_G(x) \
2079 (((x) >> CPL_RX_PHYS_DSGL_ISRDMA_S) & CPL_RX_PHYS_DSGL_ISRDMA_M)
2080#define CPL_RX_PHYS_DSGL_ISRDMA_F CPL_RX_PHYS_DSGL_ISRDMA_V(1U)
2081
2082#define CPL_RX_PHYS_DSGL_RSVD1_S 20
2083#define CPL_RX_PHYS_DSGL_RSVD1_M 0x7
2084#define CPL_RX_PHYS_DSGL_RSVD1_V(x) ((x) << CPL_RX_PHYS_DSGL_RSVD1_S)
2085#define CPL_RX_PHYS_DSGL_RSVD1_G(x) \
2086 (((x) >> CPL_RX_PHYS_DSGL_RSVD1_S) & \
2087 CPL_RX_PHYS_DSGL_RSVD1_M)
2088
2089#define CPL_RX_PHYS_DSGL_PCIRLXORDER_S 31
2090#define CPL_RX_PHYS_DSGL_PCIRLXORDER_M 0x1
2091#define CPL_RX_PHYS_DSGL_PCIRLXORDER_V(x) \
2092 ((x) << CPL_RX_PHYS_DSGL_PCIRLXORDER_S)
2093#define CPL_RX_PHYS_DSGL_PCIRLXORDER_G(x) \
2094 (((x) >> CPL_RX_PHYS_DSGL_PCIRLXORDER_S) & \
2095 CPL_RX_PHYS_DSGL_PCIRLXORDER_M)
2096#define CPL_RX_PHYS_DSGL_PCIRLXORDER_F CPL_RX_PHYS_DSGL_PCIRLXORDER_V(1U)
2097
2098#define CPL_RX_PHYS_DSGL_PCINOSNOOP_S 30
2099#define CPL_RX_PHYS_DSGL_PCINOSNOOP_M 0x1
2100#define CPL_RX_PHYS_DSGL_PCINOSNOOP_V(x) \
2101 ((x) << CPL_RX_PHYS_DSGL_PCINOSNOOP_S)
2102#define CPL_RX_PHYS_DSGL_PCINOSNOOP_G(x) \
2103 (((x) >> CPL_RX_PHYS_DSGL_PCINOSNOOP_S) & \
2104 CPL_RX_PHYS_DSGL_PCINOSNOOP_M)
2105
2106#define CPL_RX_PHYS_DSGL_PCINOSNOOP_F CPL_RX_PHYS_DSGL_PCINOSNOOP_V(1U)
2107
2108#define CPL_RX_PHYS_DSGL_PCITPHNTENB_S 29
2109#define CPL_RX_PHYS_DSGL_PCITPHNTENB_M 0x1
2110#define CPL_RX_PHYS_DSGL_PCITPHNTENB_V(x) \
2111 ((x) << CPL_RX_PHYS_DSGL_PCITPHNTENB_S)
2112#define CPL_RX_PHYS_DSGL_PCITPHNTENB_G(x) \
2113 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNTENB_S) & \
2114 CPL_RX_PHYS_DSGL_PCITPHNTENB_M)
2115#define CPL_RX_PHYS_DSGL_PCITPHNTENB_F CPL_RX_PHYS_DSGL_PCITPHNTENB_V(1U)
2116
2117#define CPL_RX_PHYS_DSGL_PCITPHNT_S 27
2118#define CPL_RX_PHYS_DSGL_PCITPHNT_M 0x3
2119#define CPL_RX_PHYS_DSGL_PCITPHNT_V(x) ((x) << CPL_RX_PHYS_DSGL_PCITPHNT_S)
2120#define CPL_RX_PHYS_DSGL_PCITPHNT_G(x) \
2121 (((x) >> CPL_RX_PHYS_DSGL_PCITPHNT_S) & \
2122 CPL_RX_PHYS_DSGL_PCITPHNT_M)
2123
2124#define CPL_RX_PHYS_DSGL_DCAID_S 16
2125#define CPL_RX_PHYS_DSGL_DCAID_M 0x7ff
2126#define CPL_RX_PHYS_DSGL_DCAID_V(x) ((x) << CPL_RX_PHYS_DSGL_DCAID_S)
2127#define CPL_RX_PHYS_DSGL_DCAID_G(x) \
2128 (((x) >> CPL_RX_PHYS_DSGL_DCAID_S) & \
2129 CPL_RX_PHYS_DSGL_DCAID_M)
2130
2131#define CPL_RX_PHYS_DSGL_NOOFSGENTR_S 0
2132#define CPL_RX_PHYS_DSGL_NOOFSGENTR_M 0xffff
2133#define CPL_RX_PHYS_DSGL_NOOFSGENTR_V(x) \
2134 ((x) << CPL_RX_PHYS_DSGL_NOOFSGENTR_S)
2135#define CPL_RX_PHYS_DSGL_NOOFSGENTR_G(x) \
2136 (((x) >> CPL_RX_PHYS_DSGL_NOOFSGENTR_S) & \
2137 CPL_RX_PHYS_DSGL_NOOFSGENTR_M)
2138
2139struct cpl_rx_mps_pkt {
2140 __be32 op_to_r1_hi;
2141 __be32 r1_lo_length;
2142};
2143
2144#define CPL_RX_MPS_PKT_OP_S 24
2145#define CPL_RX_MPS_PKT_OP_M 0xff
2146#define CPL_RX_MPS_PKT_OP_V(x) ((x) << CPL_RX_MPS_PKT_OP_S)
2147#define CPL_RX_MPS_PKT_OP_G(x) \
2148 (((x) >> CPL_RX_MPS_PKT_OP_S) & CPL_RX_MPS_PKT_OP_M)
2149
2150#define CPL_RX_MPS_PKT_TYPE_S 20
2151#define CPL_RX_MPS_PKT_TYPE_M 0xf
2152#define CPL_RX_MPS_PKT_TYPE_V(x) ((x) << CPL_RX_MPS_PKT_TYPE_S)
2153#define CPL_RX_MPS_PKT_TYPE_G(x) \
2154 (((x) >> CPL_RX_MPS_PKT_TYPE_S) & CPL_RX_MPS_PKT_TYPE_M)
2155
2156enum {
2157 X_CPL_RX_MPS_PKT_TYPE_PAUSE = 1 << 0,
2158 X_CPL_RX_MPS_PKT_TYPE_PPP = 1 << 1,
2159 X_CPL_RX_MPS_PKT_TYPE_QFC = 1 << 2,
2160 X_CPL_RX_MPS_PKT_TYPE_PTP = 1 << 3
2161};
2162
2163struct cpl_srq_table_req {
2164 WR_HDR;
2165 union opcode_tid ot;
2166 __u8 status;
2167 __u8 rsvd[2];
2168 __u8 idx;
2169 __be64 rsvd_pdid;
2170 __be32 qlen_qbase;
2171 __be16 cur_msn;
2172 __be16 max_msn;
2173};
2174
2175struct cpl_srq_table_rpl {
2176 union opcode_tid ot;
2177 __u8 status;
2178 __u8 rsvd[2];
2179 __u8 idx;
2180 __be64 rsvd_pdid;
2181 __be32 qlen_qbase;
2182 __be16 cur_msn;
2183 __be16 max_msn;
2184};
2185
2186
2187#define SRQT_QLEN_S 28
2188#define SRQT_QLEN_M 0xF
2189#define SRQT_QLEN_V(x) ((x) << SRQT_QLEN_S)
2190#define SRQT_QLEN_G(x) (((x) >> SRQT_QLEN_S) & SRQT_QLEN_M)
2191
2192#define SRQT_QBASE_S 0
2193#define SRQT_QBASE_M 0x3FFFFFF
2194#define SRQT_QBASE_V(x) ((x) << SRQT_QBASE_S)
2195#define SRQT_QBASE_G(x) (((x) >> SRQT_QBASE_S) & SRQT_QBASE_M)
2196
2197#define SRQT_PDID_S 0
2198#define SRQT_PDID_M 0xFF
2199#define SRQT_PDID_V(x) ((x) << SRQT_PDID_S)
2200#define SRQT_PDID_G(x) (((x) >> SRQT_PDID_S) & SRQT_PDID_M)
2201
2202#define SRQT_IDX_S 0
2203#define SRQT_IDX_M 0xF
2204#define SRQT_IDX_V(x) ((x) << SRQT_IDX_S)
2205#define SRQT_IDX_G(x) (((x) >> SRQT_IDX_S) & SRQT_IDX_M)
2206
2207struct cpl_tx_tls_sfo {
2208 __be32 op_to_seg_len;
2209 __be32 pld_len;
2210 __be32 type_protover;
2211 __be32 r1_lo;
2212 __be32 seqno_numivs;
2213 __be32 ivgen_hdrlen;
2214 __be64 scmd1;
2215};
2216
2217
2218#define CPL_TX_TLS_SFO_OPCODE_S 24
2219#define CPL_TX_TLS_SFO_OPCODE_V(x) ((x) << CPL_TX_TLS_SFO_OPCODE_S)
2220
2221#define CPL_TX_TLS_SFO_DATA_TYPE_S 20
2222#define CPL_TX_TLS_SFO_DATA_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_DATA_TYPE_S)
2223
2224#define CPL_TX_TLS_SFO_CPL_LEN_S 16
2225#define CPL_TX_TLS_SFO_CPL_LEN_V(x) ((x) << CPL_TX_TLS_SFO_CPL_LEN_S)
2226
2227#define CPL_TX_TLS_SFO_SEG_LEN_S 0
2228#define CPL_TX_TLS_SFO_SEG_LEN_M 0xffff
2229#define CPL_TX_TLS_SFO_SEG_LEN_V(x) ((x) << CPL_TX_TLS_SFO_SEG_LEN_S)
2230#define CPL_TX_TLS_SFO_SEG_LEN_G(x) \
2231 (((x) >> CPL_TX_TLS_SFO_SEG_LEN_S) & CPL_TX_TLS_SFO_SEG_LEN_M)
2232
2233#define CPL_TX_TLS_SFO_TYPE_S 24
2234#define CPL_TX_TLS_SFO_TYPE_M 0xff
2235#define CPL_TX_TLS_SFO_TYPE_V(x) ((x) << CPL_TX_TLS_SFO_TYPE_S)
2236#define CPL_TX_TLS_SFO_TYPE_G(x) \
2237 (((x) >> CPL_TX_TLS_SFO_TYPE_S) & CPL_TX_TLS_SFO_TYPE_M)
2238
2239#define CPL_TX_TLS_SFO_PROTOVER_S 8
2240#define CPL_TX_TLS_SFO_PROTOVER_M 0xffff
2241#define CPL_TX_TLS_SFO_PROTOVER_V(x) ((x) << CPL_TX_TLS_SFO_PROTOVER_S)
2242#define CPL_TX_TLS_SFO_PROTOVER_G(x) \
2243 (((x) >> CPL_TX_TLS_SFO_PROTOVER_S) & CPL_TX_TLS_SFO_PROTOVER_M)
2244
2245struct cpl_tls_data {
2246 struct rss_header rsshdr;
2247 union opcode_tid ot;
2248 __be32 length_pkd;
2249 __be32 seq;
2250 __be32 r1;
2251};
2252
2253#define CPL_TLS_DATA_OPCODE_S 24
2254#define CPL_TLS_DATA_OPCODE_M 0xff
2255#define CPL_TLS_DATA_OPCODE_V(x) ((x) << CPL_TLS_DATA_OPCODE_S)
2256#define CPL_TLS_DATA_OPCODE_G(x) \
2257 (((x) >> CPL_TLS_DATA_OPCODE_S) & CPL_TLS_DATA_OPCODE_M)
2258
2259#define CPL_TLS_DATA_TID_S 0
2260#define CPL_TLS_DATA_TID_M 0xffffff
2261#define CPL_TLS_DATA_TID_V(x) ((x) << CPL_TLS_DATA_TID_S)
2262#define CPL_TLS_DATA_TID_G(x) \
2263 (((x) >> CPL_TLS_DATA_TID_S) & CPL_TLS_DATA_TID_M)
2264
2265#define CPL_TLS_DATA_LENGTH_S 0
2266#define CPL_TLS_DATA_LENGTH_M 0xffff
2267#define CPL_TLS_DATA_LENGTH_V(x) ((x) << CPL_TLS_DATA_LENGTH_S)
2268#define CPL_TLS_DATA_LENGTH_G(x) \
2269 (((x) >> CPL_TLS_DATA_LENGTH_S) & CPL_TLS_DATA_LENGTH_M)
2270
2271struct cpl_rx_tls_cmp {
2272 struct rss_header rsshdr;
2273 union opcode_tid ot;
2274 __be32 pdulength_length;
2275 __be32 seq;
2276 __be32 ddp_report;
2277 __be32 r;
2278 __be32 ddp_valid;
2279};
2280
2281#define CPL_RX_TLS_CMP_OPCODE_S 24
2282#define CPL_RX_TLS_CMP_OPCODE_M 0xff
2283#define CPL_RX_TLS_CMP_OPCODE_V(x) ((x) << CPL_RX_TLS_CMP_OPCODE_S)
2284#define CPL_RX_TLS_CMP_OPCODE_G(x) \
2285 (((x) >> CPL_RX_TLS_CMP_OPCODE_S) & CPL_RX_TLS_CMP_OPCODE_M)
2286
2287#define CPL_RX_TLS_CMP_TID_S 0
2288#define CPL_RX_TLS_CMP_TID_M 0xffffff
2289#define CPL_RX_TLS_CMP_TID_V(x) ((x) << CPL_RX_TLS_CMP_TID_S)
2290#define CPL_RX_TLS_CMP_TID_G(x) \
2291 (((x) >> CPL_RX_TLS_CMP_TID_S) & CPL_RX_TLS_CMP_TID_M)
2292
2293#define CPL_RX_TLS_CMP_PDULENGTH_S 16
2294#define CPL_RX_TLS_CMP_PDULENGTH_M 0xffff
2295#define CPL_RX_TLS_CMP_PDULENGTH_V(x) ((x) << CPL_RX_TLS_CMP_PDULENGTH_S)
2296#define CPL_RX_TLS_CMP_PDULENGTH_G(x) \
2297 (((x) >> CPL_RX_TLS_CMP_PDULENGTH_S) & CPL_RX_TLS_CMP_PDULENGTH_M)
2298
2299#define CPL_RX_TLS_CMP_LENGTH_S 0
2300#define CPL_RX_TLS_CMP_LENGTH_M 0xffff
2301#define CPL_RX_TLS_CMP_LENGTH_V(x) ((x) << CPL_RX_TLS_CMP_LENGTH_S)
2302#define CPL_RX_TLS_CMP_LENGTH_G(x) \
2303 (((x) >> CPL_RX_TLS_CMP_LENGTH_S) & CPL_RX_TLS_CMP_LENGTH_M)
2304#endif
2305
