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10#include <linux/etherdevice.h>
11#include <linux/kernel.h>
12
13#include "hclge_cmd.h"
14#include "hclge_main.h"
15#include "hclge_mdio.h"
16
17#define HCLGE_PHY_SUPPORTED_FEATURES (SUPPORTED_Autoneg | \
18 SUPPORTED_TP | \
19 SUPPORTED_Pause | \
20 SUPPORTED_Asym_Pause | \
21 PHY_10BT_FEATURES | \
22 PHY_100BT_FEATURES | \
23 PHY_1000BT_FEATURES)
24
25enum hclge_mdio_c22_op_seq {
26 HCLGE_MDIO_C22_WRITE = 1,
27 HCLGE_MDIO_C22_READ = 2
28};
29
30#define HCLGE_MDIO_CTRL_START_B 0
31#define HCLGE_MDIO_CTRL_ST_S 1
32#define HCLGE_MDIO_CTRL_ST_M (0x3 << HCLGE_MDIO_CTRL_ST_S)
33#define HCLGE_MDIO_CTRL_OP_S 3
34#define HCLGE_MDIO_CTRL_OP_M (0x3 << HCLGE_MDIO_CTRL_OP_S)
35
36#define HCLGE_MDIO_PHYID_S 0
37#define HCLGE_MDIO_PHYID_M (0x1f << HCLGE_MDIO_PHYID_S)
38
39#define HCLGE_MDIO_PHYREG_S 0
40#define HCLGE_MDIO_PHYREG_M (0x1f << HCLGE_MDIO_PHYREG_S)
41
42#define HCLGE_MDIO_STA_B 0
43
44struct hclge_mdio_cfg_cmd {
45 u8 ctrl_bit;
46 u8 phyid;
47 u8 phyad;
48 u8 rsvd;
49 __le16 reserve;
50 __le16 data_wr;
51 __le16 data_rd;
52 __le16 sta;
53};
54
55static int hclge_mdio_write(struct mii_bus *bus, int phyid, int regnum,
56 u16 data)
57{
58 struct hclge_mdio_cfg_cmd *mdio_cmd;
59 struct hclge_dev *hdev = bus->priv;
60 struct hclge_desc desc;
61 int ret;
62
63 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
64 return 0;
65
66 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, false);
67
68 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
69
70 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
71 HCLGE_MDIO_PHYID_S, phyid);
72 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
73 HCLGE_MDIO_PHYREG_S, regnum);
74
75 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
76 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
77 HCLGE_MDIO_CTRL_ST_S, 1);
78 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
79 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_WRITE);
80
81 mdio_cmd->data_wr = cpu_to_le16(data);
82
83 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
84 if (ret) {
85 dev_err(&hdev->pdev->dev,
86 "mdio write fail when sending cmd, status is %d.\n",
87 ret);
88 return ret;
89 }
90
91 return 0;
92}
93
94static int hclge_mdio_read(struct mii_bus *bus, int phyid, int regnum)
95{
96 struct hclge_mdio_cfg_cmd *mdio_cmd;
97 struct hclge_dev *hdev = bus->priv;
98 struct hclge_desc desc;
99 int ret;
100
101 if (test_bit(HCLGE_STATE_RST_HANDLING, &hdev->state))
102 return 0;
103
104 hclge_cmd_setup_basic_desc(&desc, HCLGE_OPC_MDIO_CONFIG, true);
105
106 mdio_cmd = (struct hclge_mdio_cfg_cmd *)desc.data;
107
108 hnae_set_field(mdio_cmd->phyid, HCLGE_MDIO_PHYID_M,
109 HCLGE_MDIO_PHYID_S, phyid);
110 hnae_set_field(mdio_cmd->phyad, HCLGE_MDIO_PHYREG_M,
111 HCLGE_MDIO_PHYREG_S, regnum);
112
113 hnae_set_bit(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_START_B, 1);
114 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_ST_M,
115 HCLGE_MDIO_CTRL_ST_S, 1);
116 hnae_set_field(mdio_cmd->ctrl_bit, HCLGE_MDIO_CTRL_OP_M,
117 HCLGE_MDIO_CTRL_OP_S, HCLGE_MDIO_C22_READ);
118
119
120 ret = hclge_cmd_send(&hdev->hw, &desc, 1);
121 if (ret) {
122 dev_err(&hdev->pdev->dev,
123 "mdio read fail when get data, status is %d.\n",
124 ret);
125 return ret;
126 }
127
128 if (hnae_get_bit(le16_to_cpu(mdio_cmd->sta), HCLGE_MDIO_STA_B)) {
129 dev_err(&hdev->pdev->dev, "mdio read data error\n");
130 return -EIO;
131 }
132
133 return le16_to_cpu(mdio_cmd->data_rd);
134}
135
136int hclge_mac_mdio_config(struct hclge_dev *hdev)
137{
138 struct hclge_mac *mac = &hdev->hw.mac;
139 struct phy_device *phydev;
140 struct mii_bus *mdio_bus;
141 int ret;
142
143 if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR)
144 return 0;
145
146 mdio_bus = devm_mdiobus_alloc(&hdev->pdev->dev);
147 if (!mdio_bus)
148 return -ENOMEM;
149
150 mdio_bus->name = "hisilicon MII bus";
151 mdio_bus->read = hclge_mdio_read;
152 mdio_bus->write = hclge_mdio_write;
153 snprintf(mdio_bus->id, MII_BUS_ID_SIZE, "%s-%s", "mii",
154 dev_name(&hdev->pdev->dev));
155
156 mdio_bus->parent = &hdev->pdev->dev;
157 mdio_bus->priv = hdev;
158 mdio_bus->phy_mask = ~(1 << mac->phy_addr);
159 ret = mdiobus_register(mdio_bus);
160 if (ret) {
161 dev_err(mdio_bus->parent,
162 "Failed to register MDIO bus ret = %#x\n", ret);
163 return ret;
164 }
165
166 phydev = mdiobus_get_phy(mdio_bus, mac->phy_addr);
167 if (!phydev) {
168 dev_err(mdio_bus->parent, "Failed to get phy device\n");
169 mdiobus_unregister(mdio_bus);
170 return -EIO;
171 }
172
173 mac->phydev = phydev;
174 mac->mdio_bus = mdio_bus;
175
176 return 0;
177}
178
179static void hclge_mac_adjust_link(struct net_device *netdev)
180{
181 struct hnae3_handle *h = *((void **)netdev_priv(netdev));
182 struct hclge_vport *vport = hclge_get_vport(h);
183 struct hclge_dev *hdev = vport->back;
184 int duplex, speed;
185 int ret;
186
187 speed = netdev->phydev->speed;
188 duplex = netdev->phydev->duplex;
189
190 ret = hclge_cfg_mac_speed_dup(hdev, speed, duplex);
191 if (ret)
192 netdev_err(netdev, "failed to adjust link.\n");
193
194 ret = hclge_cfg_flowctrl(hdev);
195 if (ret)
196 netdev_err(netdev, "failed to configure flow control.\n");
197}
198
199int hclge_mac_start_phy(struct hclge_dev *hdev)
200{
201 struct net_device *netdev = hdev->vport[0].nic.netdev;
202 struct phy_device *phydev = hdev->hw.mac.phydev;
203 int ret;
204
205 if (!phydev)
206 return 0;
207
208 ret = phy_connect_direct(netdev, phydev,
209 hclge_mac_adjust_link,
210 PHY_INTERFACE_MODE_SGMII);
211 if (ret) {
212 netdev_err(netdev, "phy_connect_direct err.\n");
213 return ret;
214 }
215
216 phydev->supported &= HCLGE_PHY_SUPPORTED_FEATURES;
217 phydev->advertising = phydev->supported;
218
219 phy_start(phydev);
220
221 return 0;
222}
223
224void hclge_mac_stop_phy(struct hclge_dev *hdev)
225{
226 struct net_device *netdev = hdev->vport[0].nic.netdev;
227 struct phy_device *phydev = netdev->phydev;
228
229 if (!phydev)
230 return;
231
232 phy_stop(phydev);
233 phy_disconnect(phydev);
234}
235
