1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27#include "e1000.h"
28
29
30
31
32
33static const u16 e1000_gg82563_cable_length_table[] = {
34 0, 60, 115, 150, 150, 60, 115, 150, 180, 180, 0xFF
35};
36
37#define GG82563_CABLE_LENGTH_TABLE_SIZE \
38 ARRAY_SIZE(e1000_gg82563_cable_length_table)
39
40static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw);
41static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
42static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask);
43static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw);
44static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw);
45static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw);
46static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex);
47static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
48 u16 *data);
49static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
50 u16 data);
51static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw);
52
53
54
55
56
57static s32 e1000_init_phy_params_80003es2lan(struct e1000_hw *hw)
58{
59 struct e1000_phy_info *phy = &hw->phy;
60 s32 ret_val;
61
62 if (hw->phy.media_type != e1000_media_type_copper) {
63 phy->type = e1000_phy_none;
64 return 0;
65 } else {
66 phy->ops.power_up = e1000_power_up_phy_copper;
67 phy->ops.power_down = e1000_power_down_phy_copper_80003es2lan;
68 }
69
70 phy->addr = 1;
71 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
72 phy->reset_delay_us = 100;
73 phy->type = e1000_phy_gg82563;
74
75
76 ret_val = e1000e_get_phy_id(hw);
77
78
79 if (phy->id != GG82563_E_PHY_ID)
80 return -E1000_ERR_PHY;
81
82 return ret_val;
83}
84
85
86
87
88
89static s32 e1000_init_nvm_params_80003es2lan(struct e1000_hw *hw)
90{
91 struct e1000_nvm_info *nvm = &hw->nvm;
92 u32 eecd = er32(EECD);
93 u16 size;
94
95 nvm->opcode_bits = 8;
96 nvm->delay_usec = 1;
97 switch (nvm->override) {
98 case e1000_nvm_override_spi_large:
99 nvm->page_size = 32;
100 nvm->address_bits = 16;
101 break;
102 case e1000_nvm_override_spi_small:
103 nvm->page_size = 8;
104 nvm->address_bits = 8;
105 break;
106 default:
107 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
108 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
109 break;
110 }
111
112 nvm->type = e1000_nvm_eeprom_spi;
113
114 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
115 E1000_EECD_SIZE_EX_SHIFT);
116
117
118
119
120 size += NVM_WORD_SIZE_BASE_SHIFT;
121
122
123 if (size > 14)
124 size = 14;
125 nvm->word_size = BIT(size);
126
127 return 0;
128}
129
130
131
132
133
134static s32 e1000_init_mac_params_80003es2lan(struct e1000_hw *hw)
135{
136 struct e1000_mac_info *mac = &hw->mac;
137
138
139 switch (hw->adapter->pdev->device) {
140 case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
141 hw->phy.media_type = e1000_media_type_internal_serdes;
142 mac->ops.check_for_link = e1000e_check_for_serdes_link;
143 mac->ops.setup_physical_interface =
144 e1000e_setup_fiber_serdes_link;
145 break;
146 default:
147 hw->phy.media_type = e1000_media_type_copper;
148 mac->ops.check_for_link = e1000e_check_for_copper_link;
149 mac->ops.setup_physical_interface =
150 e1000_setup_copper_link_80003es2lan;
151 break;
152 }
153
154
155 mac->mta_reg_count = 128;
156
157 mac->rar_entry_count = E1000_RAR_ENTRIES;
158
159 mac->has_fwsm = true;
160
161 mac->arc_subsystem_valid = !!(er32(FWSM) & E1000_FWSM_MODE_MASK);
162
163 mac->adaptive_ifs = false;
164
165
166 hw->mac.ops.set_lan_id(hw);
167
168 return 0;
169}
170
171static s32 e1000_get_variants_80003es2lan(struct e1000_adapter *adapter)
172{
173 struct e1000_hw *hw = &adapter->hw;
174 s32 rc;
175
176 rc = e1000_init_mac_params_80003es2lan(hw);
177 if (rc)
178 return rc;
179
180 rc = e1000_init_nvm_params_80003es2lan(hw);
181 if (rc)
182 return rc;
183
184 rc = e1000_init_phy_params_80003es2lan(hw);
185 if (rc)
186 return rc;
187
188 return 0;
189}
190
191
192
193
194
195
196
197static s32 e1000_acquire_phy_80003es2lan(struct e1000_hw *hw)
198{
199 u16 mask;
200
201 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
202 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
203}
204
205
206
207
208
209
210
211static void e1000_release_phy_80003es2lan(struct e1000_hw *hw)
212{
213 u16 mask;
214
215 mask = hw->bus.func ? E1000_SWFW_PHY1_SM : E1000_SWFW_PHY0_SM;
216 e1000_release_swfw_sync_80003es2lan(hw, mask);
217}
218
219
220
221
222
223
224
225
226static s32 e1000_acquire_mac_csr_80003es2lan(struct e1000_hw *hw)
227{
228 u16 mask;
229
230 mask = E1000_SWFW_CSR_SM;
231
232 return e1000_acquire_swfw_sync_80003es2lan(hw, mask);
233}
234
235
236
237
238
239
240
241static void e1000_release_mac_csr_80003es2lan(struct e1000_hw *hw)
242{
243 u16 mask;
244
245 mask = E1000_SWFW_CSR_SM;
246
247 e1000_release_swfw_sync_80003es2lan(hw, mask);
248}
249
250
251
252
253
254
255
256static s32 e1000_acquire_nvm_80003es2lan(struct e1000_hw *hw)
257{
258 s32 ret_val;
259
260 ret_val = e1000_acquire_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
261 if (ret_val)
262 return ret_val;
263
264 ret_val = e1000e_acquire_nvm(hw);
265
266 if (ret_val)
267 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
268
269 return ret_val;
270}
271
272
273
274
275
276
277
278static void e1000_release_nvm_80003es2lan(struct e1000_hw *hw)
279{
280 e1000e_release_nvm(hw);
281 e1000_release_swfw_sync_80003es2lan(hw, E1000_SWFW_EEP_SM);
282}
283
284
285
286
287
288
289
290
291
292static s32 e1000_acquire_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
293{
294 u32 swfw_sync;
295 u32 swmask = mask;
296 u32 fwmask = mask << 16;
297 s32 i = 0;
298 s32 timeout = 50;
299
300 while (i < timeout) {
301 if (e1000e_get_hw_semaphore(hw))
302 return -E1000_ERR_SWFW_SYNC;
303
304 swfw_sync = er32(SW_FW_SYNC);
305 if (!(swfw_sync & (fwmask | swmask)))
306 break;
307
308
309
310
311 e1000e_put_hw_semaphore(hw);
312 mdelay(5);
313 i++;
314 }
315
316 if (i == timeout) {
317 e_dbg("Driver can't access resource, SW_FW_SYNC timeout.\n");
318 return -E1000_ERR_SWFW_SYNC;
319 }
320
321 swfw_sync |= swmask;
322 ew32(SW_FW_SYNC, swfw_sync);
323
324 e1000e_put_hw_semaphore(hw);
325
326 return 0;
327}
328
329
330
331
332
333
334
335
336
337static void e1000_release_swfw_sync_80003es2lan(struct e1000_hw *hw, u16 mask)
338{
339 u32 swfw_sync;
340
341 while (e1000e_get_hw_semaphore(hw) != 0)
342 ;
343
344 swfw_sync = er32(SW_FW_SYNC);
345 swfw_sync &= ~mask;
346 ew32(SW_FW_SYNC, swfw_sync);
347
348 e1000e_put_hw_semaphore(hw);
349}
350
351
352
353
354
355
356
357
358
359static s32 e1000_read_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
360 u32 offset, u16 *data)
361{
362 s32 ret_val;
363 u32 page_select;
364 u16 temp;
365
366 ret_val = e1000_acquire_phy_80003es2lan(hw);
367 if (ret_val)
368 return ret_val;
369
370
371 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
372 page_select = GG82563_PHY_PAGE_SELECT;
373 } else {
374
375
376
377 page_select = GG82563_PHY_PAGE_SELECT_ALT;
378 }
379
380 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
381 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
382 if (ret_val) {
383 e1000_release_phy_80003es2lan(hw);
384 return ret_val;
385 }
386
387 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
388
389
390
391
392 usleep_range(200, 400);
393
394
395 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
396
397 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
398 e1000_release_phy_80003es2lan(hw);
399 return -E1000_ERR_PHY;
400 }
401
402 usleep_range(200, 400);
403
404 ret_val = e1000e_read_phy_reg_mdic(hw,
405 MAX_PHY_REG_ADDRESS & offset,
406 data);
407
408 usleep_range(200, 400);
409 } else {
410 ret_val = e1000e_read_phy_reg_mdic(hw,
411 MAX_PHY_REG_ADDRESS & offset,
412 data);
413 }
414
415 e1000_release_phy_80003es2lan(hw);
416
417 return ret_val;
418}
419
420
421
422
423
424
425
426
427
428static s32 e1000_write_phy_reg_gg82563_80003es2lan(struct e1000_hw *hw,
429 u32 offset, u16 data)
430{
431 s32 ret_val;
432 u32 page_select;
433 u16 temp;
434
435 ret_val = e1000_acquire_phy_80003es2lan(hw);
436 if (ret_val)
437 return ret_val;
438
439
440 if ((offset & MAX_PHY_REG_ADDRESS) < GG82563_MIN_ALT_REG) {
441 page_select = GG82563_PHY_PAGE_SELECT;
442 } else {
443
444
445
446 page_select = GG82563_PHY_PAGE_SELECT_ALT;
447 }
448
449 temp = (u16)((u16)offset >> GG82563_PAGE_SHIFT);
450 ret_val = e1000e_write_phy_reg_mdic(hw, page_select, temp);
451 if (ret_val) {
452 e1000_release_phy_80003es2lan(hw);
453 return ret_val;
454 }
455
456 if (hw->dev_spec.e80003es2lan.mdic_wa_enable) {
457
458
459
460
461 usleep_range(200, 400);
462
463
464 ret_val = e1000e_read_phy_reg_mdic(hw, page_select, &temp);
465
466 if (((u16)offset >> GG82563_PAGE_SHIFT) != temp) {
467 e1000_release_phy_80003es2lan(hw);
468 return -E1000_ERR_PHY;
469 }
470
471 usleep_range(200, 400);
472
473 ret_val = e1000e_write_phy_reg_mdic(hw,
474 MAX_PHY_REG_ADDRESS &
475 offset, data);
476
477 usleep_range(200, 400);
478 } else {
479 ret_val = e1000e_write_phy_reg_mdic(hw,
480 MAX_PHY_REG_ADDRESS &
481 offset, data);
482 }
483
484 e1000_release_phy_80003es2lan(hw);
485
486 return ret_val;
487}
488
489
490
491
492
493
494
495
496
497
498static s32 e1000_write_nvm_80003es2lan(struct e1000_hw *hw, u16 offset,
499 u16 words, u16 *data)
500{
501 return e1000e_write_nvm_spi(hw, offset, words, data);
502}
503
504
505
506
507
508
509
510
511static s32 e1000_get_cfg_done_80003es2lan(struct e1000_hw *hw)
512{
513 s32 timeout = PHY_CFG_TIMEOUT;
514 u32 mask = E1000_NVM_CFG_DONE_PORT_0;
515
516 if (hw->bus.func == 1)
517 mask = E1000_NVM_CFG_DONE_PORT_1;
518
519 while (timeout) {
520 if (er32(EEMNGCTL) & mask)
521 break;
522 usleep_range(1000, 2000);
523 timeout--;
524 }
525 if (!timeout) {
526 e_dbg("MNG configuration cycle has not completed.\n");
527 return -E1000_ERR_RESET;
528 }
529
530 return 0;
531}
532
533
534
535
536
537
538
539
540static s32 e1000_phy_force_speed_duplex_80003es2lan(struct e1000_hw *hw)
541{
542 s32 ret_val;
543 u16 phy_data;
544 bool link;
545
546
547
548
549 ret_val = e1e_rphy(hw, M88E1000_PHY_SPEC_CTRL, &phy_data);
550 if (ret_val)
551 return ret_val;
552
553 phy_data &= ~GG82563_PSCR_CROSSOVER_MODE_AUTO;
554 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, phy_data);
555 if (ret_val)
556 return ret_val;
557
558 e_dbg("GG82563 PSCR: %X\n", phy_data);
559
560 ret_val = e1e_rphy(hw, MII_BMCR, &phy_data);
561 if (ret_val)
562 return ret_val;
563
564 e1000e_phy_force_speed_duplex_setup(hw, &phy_data);
565
566
567 phy_data |= BMCR_RESET;
568
569 ret_val = e1e_wphy(hw, MII_BMCR, phy_data);
570 if (ret_val)
571 return ret_val;
572
573 udelay(1);
574
575 if (hw->phy.autoneg_wait_to_complete) {
576 e_dbg("Waiting for forced speed/duplex link on GG82563 phy.\n");
577
578 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
579 100000, &link);
580 if (ret_val)
581 return ret_val;
582
583 if (!link) {
584
585
586
587 ret_val = e1000e_phy_reset_dsp(hw);
588 if (ret_val)
589 return ret_val;
590 }
591
592
593 ret_val = e1000e_phy_has_link_generic(hw, PHY_FORCE_LIMIT,
594 100000, &link);
595 if (ret_val)
596 return ret_val;
597 }
598
599 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &phy_data);
600 if (ret_val)
601 return ret_val;
602
603
604
605
606 phy_data &= ~GG82563_MSCR_TX_CLK_MASK;
607 if (hw->mac.forced_speed_duplex & E1000_ALL_10_SPEED)
608 phy_data |= GG82563_MSCR_TX_CLK_10MBPS_2_5;
609 else
610 phy_data |= GG82563_MSCR_TX_CLK_100MBPS_25;
611
612
613
614
615 phy_data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
616 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, phy_data);
617
618 return ret_val;
619}
620
621
622
623
624
625
626
627
628static s32 e1000_get_cable_length_80003es2lan(struct e1000_hw *hw)
629{
630 struct e1000_phy_info *phy = &hw->phy;
631 s32 ret_val;
632 u16 phy_data, index;
633
634 ret_val = e1e_rphy(hw, GG82563_PHY_DSP_DISTANCE, &phy_data);
635 if (ret_val)
636 return ret_val;
637
638 index = phy_data & GG82563_DSPD_CABLE_LENGTH;
639
640 if (index >= GG82563_CABLE_LENGTH_TABLE_SIZE - 5)
641 return -E1000_ERR_PHY;
642
643 phy->min_cable_length = e1000_gg82563_cable_length_table[index];
644 phy->max_cable_length = e1000_gg82563_cable_length_table[index + 5];
645
646 phy->cable_length = (phy->min_cable_length + phy->max_cable_length) / 2;
647
648 return 0;
649}
650
651
652
653
654
655
656
657
658
659static s32 e1000_get_link_up_info_80003es2lan(struct e1000_hw *hw, u16 *speed,
660 u16 *duplex)
661{
662 s32 ret_val;
663
664 if (hw->phy.media_type == e1000_media_type_copper) {
665 ret_val = e1000e_get_speed_and_duplex_copper(hw, speed, duplex);
666 hw->phy.ops.cfg_on_link_up(hw);
667 } else {
668 ret_val = e1000e_get_speed_and_duplex_fiber_serdes(hw,
669 speed,
670 duplex);
671 }
672
673 return ret_val;
674}
675
676
677
678
679
680
681
682static s32 e1000_reset_hw_80003es2lan(struct e1000_hw *hw)
683{
684 u32 ctrl;
685 s32 ret_val;
686 u16 kum_reg_data;
687
688
689
690
691 ret_val = e1000e_disable_pcie_master(hw);
692 if (ret_val)
693 e_dbg("PCI-E Master disable polling has failed.\n");
694
695 e_dbg("Masking off all interrupts\n");
696 ew32(IMC, 0xffffffff);
697
698 ew32(RCTL, 0);
699 ew32(TCTL, E1000_TCTL_PSP);
700 e1e_flush();
701
702 usleep_range(10000, 20000);
703
704 ctrl = er32(CTRL);
705
706 ret_val = e1000_acquire_phy_80003es2lan(hw);
707 if (ret_val)
708 return ret_val;
709
710 e_dbg("Issuing a global reset to MAC\n");
711 ew32(CTRL, ctrl | E1000_CTRL_RST);
712 e1000_release_phy_80003es2lan(hw);
713
714
715 ret_val =
716 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
717 &kum_reg_data);
718 if (ret_val)
719 return ret_val;
720 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
721 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
722 kum_reg_data);
723
724 ret_val = e1000e_get_auto_rd_done(hw);
725 if (ret_val)
726
727 return ret_val;
728
729
730 ew32(IMC, 0xffffffff);
731 er32(ICR);
732
733 return e1000_check_alt_mac_addr_generic(hw);
734}
735
736
737
738
739
740
741
742static s32 e1000_init_hw_80003es2lan(struct e1000_hw *hw)
743{
744 struct e1000_mac_info *mac = &hw->mac;
745 u32 reg_data;
746 s32 ret_val;
747 u16 kum_reg_data;
748 u16 i;
749
750 e1000_initialize_hw_bits_80003es2lan(hw);
751
752
753 ret_val = mac->ops.id_led_init(hw);
754
755 if (ret_val)
756 e_dbg("Error initializing identification LED\n");
757
758
759 e_dbg("Initializing the IEEE VLAN\n");
760 mac->ops.clear_vfta(hw);
761
762
763 e1000e_init_rx_addrs(hw, mac->rar_entry_count);
764
765
766 e_dbg("Zeroing the MTA\n");
767 for (i = 0; i < mac->mta_reg_count; i++)
768 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
769
770
771 ret_val = mac->ops.setup_link(hw);
772 if (ret_val)
773 return ret_val;
774
775
776 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
777 &kum_reg_data);
778 kum_reg_data |= E1000_KMRNCTRLSTA_IBIST_DISABLE;
779 e1000_write_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_INBAND_PARAM,
780 kum_reg_data);
781
782
783 reg_data = er32(TXDCTL(0));
784 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
785 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
786 ew32(TXDCTL(0), reg_data);
787
788
789 reg_data = er32(TXDCTL(1));
790 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
791 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
792 ew32(TXDCTL(1), reg_data);
793
794
795 reg_data = er32(TCTL);
796 reg_data |= E1000_TCTL_RTLC;
797 ew32(TCTL, reg_data);
798
799
800 reg_data = er32(TCTL_EXT);
801 reg_data &= ~E1000_TCTL_EXT_GCEX_MASK;
802 reg_data |= DEFAULT_TCTL_EXT_GCEX_80003ES2LAN;
803 ew32(TCTL_EXT, reg_data);
804
805
806 reg_data = er32(TIPG);
807 reg_data &= ~E1000_TIPG_IPGT_MASK;
808 reg_data |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
809 ew32(TIPG, reg_data);
810
811 reg_data = E1000_READ_REG_ARRAY(hw, E1000_FFLT, 0x0001);
812 reg_data &= ~0x00100000;
813 E1000_WRITE_REG_ARRAY(hw, E1000_FFLT, 0x0001, reg_data);
814
815
816 hw->dev_spec.e80003es2lan.mdic_wa_enable = true;
817
818 ret_val =
819 e1000_read_kmrn_reg_80003es2lan(hw, E1000_KMRNCTRLSTA_OFFSET >>
820 E1000_KMRNCTRLSTA_OFFSET_SHIFT, &i);
821 if (!ret_val) {
822 if ((i & E1000_KMRNCTRLSTA_OPMODE_MASK) ==
823 E1000_KMRNCTRLSTA_OPMODE_INBAND_MDIO)
824 hw->dev_spec.e80003es2lan.mdic_wa_enable = false;
825 }
826
827
828
829
830
831
832 e1000_clear_hw_cntrs_80003es2lan(hw);
833
834 return ret_val;
835}
836
837
838
839
840
841
842
843static void e1000_initialize_hw_bits_80003es2lan(struct e1000_hw *hw)
844{
845 u32 reg;
846
847
848 reg = er32(TXDCTL(0));
849 reg |= BIT(22);
850 ew32(TXDCTL(0), reg);
851
852
853 reg = er32(TXDCTL(1));
854 reg |= BIT(22);
855 ew32(TXDCTL(1), reg);
856
857
858 reg = er32(TARC(0));
859 reg &= ~(0xF << 27);
860 if (hw->phy.media_type != e1000_media_type_copper)
861 reg &= ~BIT(20);
862 ew32(TARC(0), reg);
863
864
865 reg = er32(TARC(1));
866 if (er32(TCTL) & E1000_TCTL_MULR)
867 reg &= ~BIT(28);
868 else
869 reg |= BIT(28);
870 ew32(TARC(1), reg);
871
872
873
874
875 reg = er32(RFCTL);
876 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
877 ew32(RFCTL, reg);
878}
879
880
881
882
883
884
885
886static s32 e1000_copper_link_setup_gg82563_80003es2lan(struct e1000_hw *hw)
887{
888 struct e1000_phy_info *phy = &hw->phy;
889 s32 ret_val;
890 u32 reg;
891 u16 data;
892
893 ret_val = e1e_rphy(hw, GG82563_PHY_MAC_SPEC_CTRL, &data);
894 if (ret_val)
895 return ret_val;
896
897 data |= GG82563_MSCR_ASSERT_CRS_ON_TX;
898
899 data |= GG82563_MSCR_TX_CLK_1000MBPS_25;
900
901 ret_val = e1e_wphy(hw, GG82563_PHY_MAC_SPEC_CTRL, data);
902 if (ret_val)
903 return ret_val;
904
905
906
907
908
909
910
911
912 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL, &data);
913 if (ret_val)
914 return ret_val;
915
916 data &= ~GG82563_PSCR_CROSSOVER_MODE_MASK;
917
918 switch (phy->mdix) {
919 case 1:
920 data |= GG82563_PSCR_CROSSOVER_MODE_MDI;
921 break;
922 case 2:
923 data |= GG82563_PSCR_CROSSOVER_MODE_MDIX;
924 break;
925 case 0:
926 default:
927 data |= GG82563_PSCR_CROSSOVER_MODE_AUTO;
928 break;
929 }
930
931
932
933
934
935
936
937 data &= ~GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
938 if (phy->disable_polarity_correction)
939 data |= GG82563_PSCR_POLARITY_REVERSAL_DISABLE;
940
941 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL, data);
942 if (ret_val)
943 return ret_val;
944
945
946 ret_val = hw->phy.ops.commit(hw);
947 if (ret_val) {
948 e_dbg("Error Resetting the PHY\n");
949 return ret_val;
950 }
951
952
953 reg = E1000_KMRNCTRLSTA_OFFSET_FIFO_CTRL;
954 data = (E1000_KMRNCTRLSTA_FIFO_CTRL_RX_BYPASS |
955 E1000_KMRNCTRLSTA_FIFO_CTRL_TX_BYPASS);
956 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
957 if (ret_val)
958 return ret_val;
959
960 reg = E1000_KMRNCTRLSTA_OFFSET_MAC2PHY_OPMODE;
961 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, reg, &data);
962 if (ret_val)
963 return ret_val;
964 data |= E1000_KMRNCTRLSTA_OPMODE_E_IDLE;
965 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, reg, data);
966 if (ret_val)
967 return ret_val;
968
969 ret_val = e1e_rphy(hw, GG82563_PHY_SPEC_CTRL_2, &data);
970 if (ret_val)
971 return ret_val;
972
973 data &= ~GG82563_PSCR2_REVERSE_AUTO_NEG;
974 ret_val = e1e_wphy(hw, GG82563_PHY_SPEC_CTRL_2, data);
975 if (ret_val)
976 return ret_val;
977
978 reg = er32(CTRL_EXT);
979 reg &= ~E1000_CTRL_EXT_LINK_MODE_MASK;
980 ew32(CTRL_EXT, reg);
981
982 ret_val = e1e_rphy(hw, GG82563_PHY_PWR_MGMT_CTRL, &data);
983 if (ret_val)
984 return ret_val;
985
986
987
988
989
990 if (!hw->mac.ops.check_mng_mode(hw)) {
991
992 data |= GG82563_PMCR_ENABLE_ELECTRICAL_IDLE;
993 ret_val = e1e_wphy(hw, GG82563_PHY_PWR_MGMT_CTRL, data);
994 if (ret_val)
995 return ret_val;
996
997 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, &data);
998 if (ret_val)
999 return ret_val;
1000
1001 data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1002 ret_val = e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, data);
1003 if (ret_val)
1004 return ret_val;
1005 }
1006
1007
1008
1009
1010 ret_val = e1e_rphy(hw, GG82563_PHY_INBAND_CTRL, &data);
1011 if (ret_val)
1012 return ret_val;
1013
1014 data |= GG82563_ICR_DIS_PADDING;
1015 ret_val = e1e_wphy(hw, GG82563_PHY_INBAND_CTRL, data);
1016 if (ret_val)
1017 return ret_val;
1018
1019 return 0;
1020}
1021
1022
1023
1024
1025
1026
1027
1028
1029static s32 e1000_setup_copper_link_80003es2lan(struct e1000_hw *hw)
1030{
1031 u32 ctrl;
1032 s32 ret_val;
1033 u16 reg_data;
1034
1035 ctrl = er32(CTRL);
1036 ctrl |= E1000_CTRL_SLU;
1037 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1038 ew32(CTRL, ctrl);
1039
1040
1041
1042
1043
1044 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 4),
1045 0xFFFF);
1046 if (ret_val)
1047 return ret_val;
1048 ret_val = e1000_read_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1049 ®_data);
1050 if (ret_val)
1051 return ret_val;
1052 reg_data |= 0x3F;
1053 ret_val = e1000_write_kmrn_reg_80003es2lan(hw, GG82563_REG(0x34, 9),
1054 reg_data);
1055 if (ret_val)
1056 return ret_val;
1057 ret_val =
1058 e1000_read_kmrn_reg_80003es2lan(hw,
1059 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1060 ®_data);
1061 if (ret_val)
1062 return ret_val;
1063 reg_data |= E1000_KMRNCTRLSTA_INB_CTRL_DIS_PADDING;
1064 ret_val =
1065 e1000_write_kmrn_reg_80003es2lan(hw,
1066 E1000_KMRNCTRLSTA_OFFSET_INB_CTRL,
1067 reg_data);
1068 if (ret_val)
1069 return ret_val;
1070
1071 ret_val = e1000_copper_link_setup_gg82563_80003es2lan(hw);
1072 if (ret_val)
1073 return ret_val;
1074
1075 return e1000e_setup_copper_link(hw);
1076}
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086static s32 e1000_cfg_on_link_up_80003es2lan(struct e1000_hw *hw)
1087{
1088 s32 ret_val = 0;
1089 u16 speed;
1090 u16 duplex;
1091
1092 if (hw->phy.media_type == e1000_media_type_copper) {
1093 ret_val = e1000e_get_speed_and_duplex_copper(hw, &speed,
1094 &duplex);
1095 if (ret_val)
1096 return ret_val;
1097
1098 if (speed == SPEED_1000)
1099 ret_val = e1000_cfg_kmrn_1000_80003es2lan(hw);
1100 else
1101 ret_val = e1000_cfg_kmrn_10_100_80003es2lan(hw, duplex);
1102 }
1103
1104 return ret_val;
1105}
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115static s32 e1000_cfg_kmrn_10_100_80003es2lan(struct e1000_hw *hw, u16 duplex)
1116{
1117 s32 ret_val;
1118 u32 tipg;
1119 u32 i = 0;
1120 u16 reg_data, reg_data2;
1121
1122 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_10_100_DEFAULT;
1123 ret_val =
1124 e1000_write_kmrn_reg_80003es2lan(hw,
1125 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1126 reg_data);
1127 if (ret_val)
1128 return ret_val;
1129
1130
1131 tipg = er32(TIPG);
1132 tipg &= ~E1000_TIPG_IPGT_MASK;
1133 tipg |= DEFAULT_TIPG_IPGT_10_100_80003ES2LAN;
1134 ew32(TIPG, tipg);
1135
1136 do {
1137 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1138 if (ret_val)
1139 return ret_val;
1140
1141 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1142 if (ret_val)
1143 return ret_val;
1144 i++;
1145 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1146
1147 if (duplex == HALF_DUPLEX)
1148 reg_data |= GG82563_KMCR_PASS_FALSE_CARRIER;
1149 else
1150 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1151
1152 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1153}
1154
1155
1156
1157
1158
1159
1160
1161
1162static s32 e1000_cfg_kmrn_1000_80003es2lan(struct e1000_hw *hw)
1163{
1164 s32 ret_val;
1165 u16 reg_data, reg_data2;
1166 u32 tipg;
1167 u32 i = 0;
1168
1169 reg_data = E1000_KMRNCTRLSTA_HD_CTRL_1000_DEFAULT;
1170 ret_val =
1171 e1000_write_kmrn_reg_80003es2lan(hw,
1172 E1000_KMRNCTRLSTA_OFFSET_HD_CTRL,
1173 reg_data);
1174 if (ret_val)
1175 return ret_val;
1176
1177
1178 tipg = er32(TIPG);
1179 tipg &= ~E1000_TIPG_IPGT_MASK;
1180 tipg |= DEFAULT_TIPG_IPGT_1000_80003ES2LAN;
1181 ew32(TIPG, tipg);
1182
1183 do {
1184 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data);
1185 if (ret_val)
1186 return ret_val;
1187
1188 ret_val = e1e_rphy(hw, GG82563_PHY_KMRN_MODE_CTRL, ®_data2);
1189 if (ret_val)
1190 return ret_val;
1191 i++;
1192 } while ((reg_data != reg_data2) && (i < GG82563_MAX_KMRN_RETRY));
1193
1194 reg_data &= ~GG82563_KMCR_PASS_FALSE_CARRIER;
1195
1196 return e1e_wphy(hw, GG82563_PHY_KMRN_MODE_CTRL, reg_data);
1197}
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209static s32 e1000_read_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1210 u16 *data)
1211{
1212 u32 kmrnctrlsta;
1213 s32 ret_val;
1214
1215 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1216 if (ret_val)
1217 return ret_val;
1218
1219 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1220 E1000_KMRNCTRLSTA_OFFSET) | E1000_KMRNCTRLSTA_REN;
1221 ew32(KMRNCTRLSTA, kmrnctrlsta);
1222 e1e_flush();
1223
1224 udelay(2);
1225
1226 kmrnctrlsta = er32(KMRNCTRLSTA);
1227 *data = (u16)kmrnctrlsta;
1228
1229 e1000_release_mac_csr_80003es2lan(hw);
1230
1231 return ret_val;
1232}
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244static s32 e1000_write_kmrn_reg_80003es2lan(struct e1000_hw *hw, u32 offset,
1245 u16 data)
1246{
1247 u32 kmrnctrlsta;
1248 s32 ret_val;
1249
1250 ret_val = e1000_acquire_mac_csr_80003es2lan(hw);
1251 if (ret_val)
1252 return ret_val;
1253
1254 kmrnctrlsta = ((offset << E1000_KMRNCTRLSTA_OFFSET_SHIFT) &
1255 E1000_KMRNCTRLSTA_OFFSET) | data;
1256 ew32(KMRNCTRLSTA, kmrnctrlsta);
1257 e1e_flush();
1258
1259 udelay(2);
1260
1261 e1000_release_mac_csr_80003es2lan(hw);
1262
1263 return ret_val;
1264}
1265
1266
1267
1268
1269
1270static s32 e1000_read_mac_addr_80003es2lan(struct e1000_hw *hw)
1271{
1272 s32 ret_val;
1273
1274
1275
1276
1277
1278 ret_val = e1000_check_alt_mac_addr_generic(hw);
1279 if (ret_val)
1280 return ret_val;
1281
1282 return e1000_read_mac_addr_generic(hw);
1283}
1284
1285
1286
1287
1288
1289
1290
1291
1292static void e1000_power_down_phy_copper_80003es2lan(struct e1000_hw *hw)
1293{
1294
1295 if (!(hw->mac.ops.check_mng_mode(hw) ||
1296 hw->phy.ops.check_reset_block(hw)))
1297 e1000_power_down_phy_copper(hw);
1298}
1299
1300
1301
1302
1303
1304
1305
1306static void e1000_clear_hw_cntrs_80003es2lan(struct e1000_hw *hw)
1307{
1308 e1000e_clear_hw_cntrs_base(hw);
1309
1310 er32(PRC64);
1311 er32(PRC127);
1312 er32(PRC255);
1313 er32(PRC511);
1314 er32(PRC1023);
1315 er32(PRC1522);
1316 er32(PTC64);
1317 er32(PTC127);
1318 er32(PTC255);
1319 er32(PTC511);
1320 er32(PTC1023);
1321 er32(PTC1522);
1322
1323 er32(ALGNERRC);
1324 er32(RXERRC);
1325 er32(TNCRS);
1326 er32(CEXTERR);
1327 er32(TSCTC);
1328 er32(TSCTFC);
1329
1330 er32(MGTPRC);
1331 er32(MGTPDC);
1332 er32(MGTPTC);
1333
1334 er32(IAC);
1335 er32(ICRXOC);
1336
1337 er32(ICRXPTC);
1338 er32(ICRXATC);
1339 er32(ICTXPTC);
1340 er32(ICTXATC);
1341 er32(ICTXQEC);
1342 er32(ICTXQMTC);
1343 er32(ICRXDMTC);
1344}
1345
1346static const struct e1000_mac_operations es2_mac_ops = {
1347 .read_mac_addr = e1000_read_mac_addr_80003es2lan,
1348 .id_led_init = e1000e_id_led_init_generic,
1349 .blink_led = e1000e_blink_led_generic,
1350 .check_mng_mode = e1000e_check_mng_mode_generic,
1351
1352 .cleanup_led = e1000e_cleanup_led_generic,
1353 .clear_hw_cntrs = e1000_clear_hw_cntrs_80003es2lan,
1354 .get_bus_info = e1000e_get_bus_info_pcie,
1355 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1356 .get_link_up_info = e1000_get_link_up_info_80003es2lan,
1357 .led_on = e1000e_led_on_generic,
1358 .led_off = e1000e_led_off_generic,
1359 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1360 .write_vfta = e1000_write_vfta_generic,
1361 .clear_vfta = e1000_clear_vfta_generic,
1362 .reset_hw = e1000_reset_hw_80003es2lan,
1363 .init_hw = e1000_init_hw_80003es2lan,
1364 .setup_link = e1000e_setup_link_generic,
1365
1366 .setup_led = e1000e_setup_led_generic,
1367 .config_collision_dist = e1000e_config_collision_dist_generic,
1368 .rar_set = e1000e_rar_set_generic,
1369 .rar_get_count = e1000e_rar_get_count_generic,
1370};
1371
1372static const struct e1000_phy_operations es2_phy_ops = {
1373 .acquire = e1000_acquire_phy_80003es2lan,
1374 .check_polarity = e1000_check_polarity_m88,
1375 .check_reset_block = e1000e_check_reset_block_generic,
1376 .commit = e1000e_phy_sw_reset,
1377 .force_speed_duplex = e1000_phy_force_speed_duplex_80003es2lan,
1378 .get_cfg_done = e1000_get_cfg_done_80003es2lan,
1379 .get_cable_length = e1000_get_cable_length_80003es2lan,
1380 .get_info = e1000e_get_phy_info_m88,
1381 .read_reg = e1000_read_phy_reg_gg82563_80003es2lan,
1382 .release = e1000_release_phy_80003es2lan,
1383 .reset = e1000e_phy_hw_reset_generic,
1384 .set_d0_lplu_state = NULL,
1385 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1386 .write_reg = e1000_write_phy_reg_gg82563_80003es2lan,
1387 .cfg_on_link_up = e1000_cfg_on_link_up_80003es2lan,
1388};
1389
1390static const struct e1000_nvm_operations es2_nvm_ops = {
1391 .acquire = e1000_acquire_nvm_80003es2lan,
1392 .read = e1000e_read_nvm_eerd,
1393 .release = e1000_release_nvm_80003es2lan,
1394 .reload = e1000e_reload_nvm_generic,
1395 .update = e1000e_update_nvm_checksum_generic,
1396 .valid_led_default = e1000e_valid_led_default,
1397 .validate = e1000e_validate_nvm_checksum_generic,
1398 .write = e1000_write_nvm_80003es2lan,
1399};
1400
1401const struct e1000_info e1000_es2_info = {
1402 .mac = e1000_80003es2lan,
1403 .flags = FLAG_HAS_HW_VLAN_FILTER
1404 | FLAG_HAS_JUMBO_FRAMES
1405 | FLAG_HAS_WOL
1406 | FLAG_APME_IN_CTRL3
1407 | FLAG_HAS_CTRLEXT_ON_LOAD
1408 | FLAG_RX_NEEDS_RESTART
1409 | FLAG_TARC_SET_BIT_ZERO
1410 | FLAG_APME_CHECK_PORT_B
1411 | FLAG_DISABLE_FC_PAUSE_TIME,
1412 .flags2 = FLAG2_DMA_BURST,
1413 .pba = 38,
1414 .max_hw_frame_size = DEFAULT_JUMBO,
1415 .get_variants = e1000_get_variants_80003es2lan,
1416 .mac_ops = &es2_mac_ops,
1417 .phy_ops = &es2_phy_ops,
1418 .nvm_ops = &es2_nvm_ops,
1419};
1420