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39#include "e1000.h"
40
41static s32 e1000_get_phy_id_82571(struct e1000_hw *hw);
42static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw);
43static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw);
44static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw);
45static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
46 u16 words, u16 *data);
47static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw);
48static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw);
49static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw);
50static bool e1000_check_mng_mode_82574(struct e1000_hw *hw);
51static s32 e1000_led_on_82574(struct e1000_hw *hw);
52static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw);
53static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw);
54static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw);
55static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw);
56static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw);
57static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active);
58static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active);
59
60
61
62
63
64static s32 e1000_init_phy_params_82571(struct e1000_hw *hw)
65{
66 struct e1000_phy_info *phy = &hw->phy;
67 s32 ret_val;
68
69 if (hw->phy.media_type != e1000_media_type_copper) {
70 phy->type = e1000_phy_none;
71 return 0;
72 }
73
74 phy->addr = 1;
75 phy->autoneg_mask = AUTONEG_ADVERTISE_SPEED_DEFAULT;
76 phy->reset_delay_us = 100;
77
78 phy->ops.power_up = e1000_power_up_phy_copper;
79 phy->ops.power_down = e1000_power_down_phy_copper_82571;
80
81 switch (hw->mac.type) {
82 case e1000_82571:
83 case e1000_82572:
84 phy->type = e1000_phy_igp_2;
85 break;
86 case e1000_82573:
87 phy->type = e1000_phy_m88;
88 break;
89 case e1000_82574:
90 case e1000_82583:
91 phy->type = e1000_phy_bm;
92 phy->ops.acquire = e1000_get_hw_semaphore_82574;
93 phy->ops.release = e1000_put_hw_semaphore_82574;
94 phy->ops.set_d0_lplu_state = e1000_set_d0_lplu_state_82574;
95 phy->ops.set_d3_lplu_state = e1000_set_d3_lplu_state_82574;
96 break;
97 default:
98 return -E1000_ERR_PHY;
99 }
100
101
102 ret_val = e1000_get_phy_id_82571(hw);
103 if (ret_val) {
104 e_dbg("Error getting PHY ID\n");
105 return ret_val;
106 }
107
108
109 switch (hw->mac.type) {
110 case e1000_82571:
111 case e1000_82572:
112 if (phy->id != IGP01E1000_I_PHY_ID)
113 ret_val = -E1000_ERR_PHY;
114 break;
115 case e1000_82573:
116 if (phy->id != M88E1111_I_PHY_ID)
117 ret_val = -E1000_ERR_PHY;
118 break;
119 case e1000_82574:
120 case e1000_82583:
121 if (phy->id != BME1000_E_PHY_ID_R2)
122 ret_val = -E1000_ERR_PHY;
123 break;
124 default:
125 ret_val = -E1000_ERR_PHY;
126 break;
127 }
128
129 if (ret_val)
130 e_dbg("PHY ID unknown: type = 0x%08x\n", phy->id);
131
132 return ret_val;
133}
134
135
136
137
138
139static s32 e1000_init_nvm_params_82571(struct e1000_hw *hw)
140{
141 struct e1000_nvm_info *nvm = &hw->nvm;
142 u32 eecd = er32(EECD);
143 u16 size;
144
145 nvm->opcode_bits = 8;
146 nvm->delay_usec = 1;
147 switch (nvm->override) {
148 case e1000_nvm_override_spi_large:
149 nvm->page_size = 32;
150 nvm->address_bits = 16;
151 break;
152 case e1000_nvm_override_spi_small:
153 nvm->page_size = 8;
154 nvm->address_bits = 8;
155 break;
156 default:
157 nvm->page_size = eecd & E1000_EECD_ADDR_BITS ? 32 : 8;
158 nvm->address_bits = eecd & E1000_EECD_ADDR_BITS ? 16 : 8;
159 break;
160 }
161
162 switch (hw->mac.type) {
163 case e1000_82573:
164 case e1000_82574:
165 case e1000_82583:
166 if (((eecd >> 15) & 0x3) == 0x3) {
167 nvm->type = e1000_nvm_flash_hw;
168 nvm->word_size = 2048;
169
170
171
172 eecd &= ~E1000_EECD_AUPDEN;
173 ew32(EECD, eecd);
174 break;
175 }
176
177 default:
178 nvm->type = e1000_nvm_eeprom_spi;
179 size = (u16)((eecd & E1000_EECD_SIZE_EX_MASK) >>
180 E1000_EECD_SIZE_EX_SHIFT);
181
182
183
184 size += NVM_WORD_SIZE_BASE_SHIFT;
185
186
187 if (size > 14)
188 size = 14;
189 nvm->word_size = BIT(size);
190 break;
191 }
192
193
194 switch (hw->mac.type) {
195 case e1000_82574:
196 case e1000_82583:
197 nvm->ops.acquire = e1000_get_hw_semaphore_82574;
198 nvm->ops.release = e1000_put_hw_semaphore_82574;
199 break;
200 default:
201 break;
202 }
203
204 return 0;
205}
206
207
208
209
210
211static s32 e1000_init_mac_params_82571(struct e1000_hw *hw)
212{
213 struct e1000_mac_info *mac = &hw->mac;
214 u32 swsm = 0;
215 u32 swsm2 = 0;
216 bool force_clear_smbi = false;
217
218
219 switch (hw->adapter->pdev->device) {
220 case E1000_DEV_ID_82571EB_FIBER:
221 case E1000_DEV_ID_82572EI_FIBER:
222 case E1000_DEV_ID_82571EB_QUAD_FIBER:
223 hw->phy.media_type = e1000_media_type_fiber;
224 mac->ops.setup_physical_interface =
225 e1000_setup_fiber_serdes_link_82571;
226 mac->ops.check_for_link = e1000e_check_for_fiber_link;
227 mac->ops.get_link_up_info =
228 e1000e_get_speed_and_duplex_fiber_serdes;
229 break;
230 case E1000_DEV_ID_82571EB_SERDES:
231 case E1000_DEV_ID_82571EB_SERDES_DUAL:
232 case E1000_DEV_ID_82571EB_SERDES_QUAD:
233 case E1000_DEV_ID_82572EI_SERDES:
234 hw->phy.media_type = e1000_media_type_internal_serdes;
235 mac->ops.setup_physical_interface =
236 e1000_setup_fiber_serdes_link_82571;
237 mac->ops.check_for_link = e1000_check_for_serdes_link_82571;
238 mac->ops.get_link_up_info =
239 e1000e_get_speed_and_duplex_fiber_serdes;
240 break;
241 default:
242 hw->phy.media_type = e1000_media_type_copper;
243 mac->ops.setup_physical_interface =
244 e1000_setup_copper_link_82571;
245 mac->ops.check_for_link = e1000e_check_for_copper_link;
246 mac->ops.get_link_up_info = e1000e_get_speed_and_duplex_copper;
247 break;
248 }
249
250
251 mac->mta_reg_count = 128;
252
253 mac->rar_entry_count = E1000_RAR_ENTRIES;
254
255 mac->adaptive_ifs = true;
256
257
258 switch (hw->mac.type) {
259 case e1000_82573:
260 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
261 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
262 mac->ops.led_on = e1000e_led_on_generic;
263 mac->ops.blink_led = e1000e_blink_led_generic;
264
265
266 mac->has_fwsm = true;
267
268
269
270 mac->arc_subsystem_valid = !!(er32(FWSM) &
271 E1000_FWSM_MODE_MASK);
272 break;
273 case e1000_82574:
274 case e1000_82583:
275 mac->ops.set_lan_id = e1000_set_lan_id_single_port;
276 mac->ops.check_mng_mode = e1000_check_mng_mode_82574;
277 mac->ops.led_on = e1000_led_on_82574;
278 break;
279 default:
280 mac->ops.check_mng_mode = e1000e_check_mng_mode_generic;
281 mac->ops.led_on = e1000e_led_on_generic;
282 mac->ops.blink_led = e1000e_blink_led_generic;
283
284
285 mac->has_fwsm = true;
286 break;
287 }
288
289
290
291
292
293
294
295 switch (hw->mac.type) {
296 case e1000_82571:
297 case e1000_82572:
298 swsm2 = er32(SWSM2);
299
300 if (!(swsm2 & E1000_SWSM2_LOCK)) {
301
302 ew32(SWSM2, swsm2 | E1000_SWSM2_LOCK);
303 force_clear_smbi = true;
304 } else {
305 force_clear_smbi = false;
306 }
307 break;
308 default:
309 force_clear_smbi = true;
310 break;
311 }
312
313 if (force_clear_smbi) {
314
315 swsm = er32(SWSM);
316 if (swsm & E1000_SWSM_SMBI) {
317
318
319
320
321 e_dbg("Please update your 82571 Bootagent\n");
322 }
323 ew32(SWSM, swsm & ~E1000_SWSM_SMBI);
324 }
325
326
327 hw->dev_spec.e82571.smb_counter = 0;
328
329 return 0;
330}
331
332static s32 e1000_get_variants_82571(struct e1000_adapter *adapter)
333{
334 struct e1000_hw *hw = &adapter->hw;
335 static int global_quad_port_a;
336 struct pci_dev *pdev = adapter->pdev;
337 int is_port_b = er32(STATUS) & E1000_STATUS_FUNC_1;
338 s32 rc;
339
340 rc = e1000_init_mac_params_82571(hw);
341 if (rc)
342 return rc;
343
344 rc = e1000_init_nvm_params_82571(hw);
345 if (rc)
346 return rc;
347
348 rc = e1000_init_phy_params_82571(hw);
349 if (rc)
350 return rc;
351
352
353 switch (pdev->device) {
354 case E1000_DEV_ID_82571EB_QUAD_COPPER:
355 case E1000_DEV_ID_82571EB_QUAD_FIBER:
356 case E1000_DEV_ID_82571EB_QUAD_COPPER_LP:
357 case E1000_DEV_ID_82571PT_QUAD_COPPER:
358 adapter->flags |= FLAG_IS_QUAD_PORT;
359
360 if (global_quad_port_a == 0)
361 adapter->flags |= FLAG_IS_QUAD_PORT_A;
362
363 global_quad_port_a++;
364 if (global_quad_port_a == 4)
365 global_quad_port_a = 0;
366 break;
367 default:
368 break;
369 }
370
371 switch (adapter->hw.mac.type) {
372 case e1000_82571:
373
374 if (((pdev->device == E1000_DEV_ID_82571EB_FIBER) ||
375 (pdev->device == E1000_DEV_ID_82571EB_SERDES) ||
376 (pdev->device == E1000_DEV_ID_82571EB_COPPER)) &&
377 (is_port_b))
378 adapter->flags &= ~FLAG_HAS_WOL;
379
380 if (adapter->flags & FLAG_IS_QUAD_PORT &&
381 (!(adapter->flags & FLAG_IS_QUAD_PORT_A)))
382 adapter->flags &= ~FLAG_HAS_WOL;
383
384 if (pdev->device == E1000_DEV_ID_82571EB_SERDES_QUAD)
385 adapter->flags &= ~FLAG_HAS_WOL;
386 break;
387 case e1000_82573:
388 if (pdev->device == E1000_DEV_ID_82573L) {
389 adapter->flags |= FLAG_HAS_JUMBO_FRAMES;
390 adapter->max_hw_frame_size = DEFAULT_JUMBO;
391 }
392 break;
393 default:
394 break;
395 }
396
397 return 0;
398}
399
400
401
402
403
404
405
406
407static s32 e1000_get_phy_id_82571(struct e1000_hw *hw)
408{
409 struct e1000_phy_info *phy = &hw->phy;
410 s32 ret_val;
411 u16 phy_id = 0;
412
413 switch (hw->mac.type) {
414 case e1000_82571:
415 case e1000_82572:
416
417
418
419
420
421 phy->id = IGP01E1000_I_PHY_ID;
422 break;
423 case e1000_82573:
424 return e1000e_get_phy_id(hw);
425 case e1000_82574:
426 case e1000_82583:
427 ret_val = e1e_rphy(hw, MII_PHYSID1, &phy_id);
428 if (ret_val)
429 return ret_val;
430
431 phy->id = (u32)(phy_id << 16);
432 usleep_range(20, 40);
433 ret_val = e1e_rphy(hw, MII_PHYSID2, &phy_id);
434 if (ret_val)
435 return ret_val;
436
437 phy->id |= (u32)(phy_id);
438 phy->revision = (u32)(phy_id & ~PHY_REVISION_MASK);
439 break;
440 default:
441 return -E1000_ERR_PHY;
442 }
443
444 return 0;
445}
446
447
448
449
450
451
452
453static s32 e1000_get_hw_semaphore_82571(struct e1000_hw *hw)
454{
455 u32 swsm;
456 s32 sw_timeout = hw->nvm.word_size + 1;
457 s32 fw_timeout = hw->nvm.word_size + 1;
458 s32 i = 0;
459
460
461
462
463
464
465
466
467 if (hw->dev_spec.e82571.smb_counter > 2)
468 sw_timeout = 1;
469
470
471 while (i < sw_timeout) {
472 swsm = er32(SWSM);
473 if (!(swsm & E1000_SWSM_SMBI))
474 break;
475
476 usleep_range(50, 100);
477 i++;
478 }
479
480 if (i == sw_timeout) {
481 e_dbg("Driver can't access device - SMBI bit is set.\n");
482 hw->dev_spec.e82571.smb_counter++;
483 }
484
485 for (i = 0; i < fw_timeout; i++) {
486 swsm = er32(SWSM);
487 ew32(SWSM, swsm | E1000_SWSM_SWESMBI);
488
489
490 if (er32(SWSM) & E1000_SWSM_SWESMBI)
491 break;
492
493 usleep_range(50, 100);
494 }
495
496 if (i == fw_timeout) {
497
498 e1000_put_hw_semaphore_82571(hw);
499 e_dbg("Driver can't access the NVM\n");
500 return -E1000_ERR_NVM;
501 }
502
503 return 0;
504}
505
506
507
508
509
510
511
512static void e1000_put_hw_semaphore_82571(struct e1000_hw *hw)
513{
514 u32 swsm;
515
516 swsm = er32(SWSM);
517 swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
518 ew32(SWSM, swsm);
519}
520
521
522
523
524
525
526
527
528static s32 e1000_get_hw_semaphore_82573(struct e1000_hw *hw)
529{
530 u32 extcnf_ctrl;
531 s32 i = 0;
532
533 extcnf_ctrl = er32(EXTCNF_CTRL);
534 do {
535 extcnf_ctrl |= E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
536 ew32(EXTCNF_CTRL, extcnf_ctrl);
537 extcnf_ctrl = er32(EXTCNF_CTRL);
538
539 if (extcnf_ctrl & E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP)
540 break;
541
542 usleep_range(2000, 4000);
543 i++;
544 } while (i < MDIO_OWNERSHIP_TIMEOUT);
545
546 if (i == MDIO_OWNERSHIP_TIMEOUT) {
547
548 e1000_put_hw_semaphore_82573(hw);
549 e_dbg("Driver can't access the PHY\n");
550 return -E1000_ERR_PHY;
551 }
552
553 return 0;
554}
555
556
557
558
559
560
561
562
563static void e1000_put_hw_semaphore_82573(struct e1000_hw *hw)
564{
565 u32 extcnf_ctrl;
566
567 extcnf_ctrl = er32(EXTCNF_CTRL);
568 extcnf_ctrl &= ~E1000_EXTCNF_CTRL_MDIO_SW_OWNERSHIP;
569 ew32(EXTCNF_CTRL, extcnf_ctrl);
570}
571
572static DEFINE_MUTEX(swflag_mutex);
573
574
575
576
577
578
579
580
581static s32 e1000_get_hw_semaphore_82574(struct e1000_hw *hw)
582{
583 s32 ret_val;
584
585 mutex_lock(&swflag_mutex);
586 ret_val = e1000_get_hw_semaphore_82573(hw);
587 if (ret_val)
588 mutex_unlock(&swflag_mutex);
589 return ret_val;
590}
591
592
593
594
595
596
597
598
599static void e1000_put_hw_semaphore_82574(struct e1000_hw *hw)
600{
601 e1000_put_hw_semaphore_82573(hw);
602 mutex_unlock(&swflag_mutex);
603}
604
605
606
607
608
609
610
611
612
613
614
615
616
617static s32 e1000_set_d0_lplu_state_82574(struct e1000_hw *hw, bool active)
618{
619 u32 data = er32(POEMB);
620
621 if (active)
622 data |= E1000_PHY_CTRL_D0A_LPLU;
623 else
624 data &= ~E1000_PHY_CTRL_D0A_LPLU;
625
626 ew32(POEMB, data);
627 return 0;
628}
629
630
631
632
633
634
635
636
637
638
639
640
641static s32 e1000_set_d3_lplu_state_82574(struct e1000_hw *hw, bool active)
642{
643 u32 data = er32(POEMB);
644
645 if (!active) {
646 data &= ~E1000_PHY_CTRL_NOND0A_LPLU;
647 } else if ((hw->phy.autoneg_advertised == E1000_ALL_SPEED_DUPLEX) ||
648 (hw->phy.autoneg_advertised == E1000_ALL_NOT_GIG) ||
649 (hw->phy.autoneg_advertised == E1000_ALL_10_SPEED)) {
650 data |= E1000_PHY_CTRL_NOND0A_LPLU;
651 }
652
653 ew32(POEMB, data);
654 return 0;
655}
656
657
658
659
660
661
662
663
664
665
666static s32 e1000_acquire_nvm_82571(struct e1000_hw *hw)
667{
668 s32 ret_val;
669
670 ret_val = e1000_get_hw_semaphore_82571(hw);
671 if (ret_val)
672 return ret_val;
673
674 switch (hw->mac.type) {
675 case e1000_82573:
676 break;
677 default:
678 ret_val = e1000e_acquire_nvm(hw);
679 break;
680 }
681
682 if (ret_val)
683 e1000_put_hw_semaphore_82571(hw);
684
685 return ret_val;
686}
687
688
689
690
691
692
693
694static void e1000_release_nvm_82571(struct e1000_hw *hw)
695{
696 e1000e_release_nvm(hw);
697 e1000_put_hw_semaphore_82571(hw);
698}
699
700
701
702
703
704
705
706
707
708
709
710
711
712static s32 e1000_write_nvm_82571(struct e1000_hw *hw, u16 offset, u16 words,
713 u16 *data)
714{
715 s32 ret_val;
716
717 switch (hw->mac.type) {
718 case e1000_82573:
719 case e1000_82574:
720 case e1000_82583:
721 ret_val = e1000_write_nvm_eewr_82571(hw, offset, words, data);
722 break;
723 case e1000_82571:
724 case e1000_82572:
725 ret_val = e1000e_write_nvm_spi(hw, offset, words, data);
726 break;
727 default:
728 ret_val = -E1000_ERR_NVM;
729 break;
730 }
731
732 return ret_val;
733}
734
735
736
737
738
739
740
741
742
743static s32 e1000_update_nvm_checksum_82571(struct e1000_hw *hw)
744{
745 u32 eecd;
746 s32 ret_val;
747 u16 i;
748
749 ret_val = e1000e_update_nvm_checksum_generic(hw);
750 if (ret_val)
751 return ret_val;
752
753
754
755
756 if (hw->nvm.type != e1000_nvm_flash_hw)
757 return 0;
758
759
760 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
761 usleep_range(1000, 2000);
762 if (!(er32(EECD) & E1000_EECD_FLUPD))
763 break;
764 }
765
766 if (i == E1000_FLASH_UPDATES)
767 return -E1000_ERR_NVM;
768
769
770 if ((er32(FLOP) & 0xFF00) == E1000_STM_OPCODE) {
771
772
773
774 ew32(HICR, E1000_HICR_FW_RESET_ENABLE);
775 e1e_flush();
776 ew32(HICR, E1000_HICR_FW_RESET);
777 }
778
779
780 eecd = er32(EECD) | E1000_EECD_FLUPD;
781 ew32(EECD, eecd);
782
783 for (i = 0; i < E1000_FLASH_UPDATES; i++) {
784 usleep_range(1000, 2000);
785 if (!(er32(EECD) & E1000_EECD_FLUPD))
786 break;
787 }
788
789 if (i == E1000_FLASH_UPDATES)
790 return -E1000_ERR_NVM;
791
792 return 0;
793}
794
795
796
797
798
799
800
801
802static s32 e1000_validate_nvm_checksum_82571(struct e1000_hw *hw)
803{
804 if (hw->nvm.type == e1000_nvm_flash_hw)
805 e1000_fix_nvm_checksum_82571(hw);
806
807 return e1000e_validate_nvm_checksum_generic(hw);
808}
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824static s32 e1000_write_nvm_eewr_82571(struct e1000_hw *hw, u16 offset,
825 u16 words, u16 *data)
826{
827 struct e1000_nvm_info *nvm = &hw->nvm;
828 u32 i, eewr = 0;
829 s32 ret_val = 0;
830
831
832
833
834 if ((offset >= nvm->word_size) || (words > (nvm->word_size - offset)) ||
835 (words == 0)) {
836 e_dbg("nvm parameter(s) out of bounds\n");
837 return -E1000_ERR_NVM;
838 }
839
840 for (i = 0; i < words; i++) {
841 eewr = ((data[i] << E1000_NVM_RW_REG_DATA) |
842 ((offset + i) << E1000_NVM_RW_ADDR_SHIFT) |
843 E1000_NVM_RW_REG_START);
844
845 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
846 if (ret_val)
847 break;
848
849 ew32(EEWR, eewr);
850
851 ret_val = e1000e_poll_eerd_eewr_done(hw, E1000_NVM_POLL_WRITE);
852 if (ret_val)
853 break;
854 }
855
856 return ret_val;
857}
858
859
860
861
862
863
864
865static s32 e1000_get_cfg_done_82571(struct e1000_hw *hw)
866{
867 s32 timeout = PHY_CFG_TIMEOUT;
868
869 while (timeout) {
870 if (er32(EEMNGCTL) & E1000_NVM_CFG_DONE_PORT_0)
871 break;
872 usleep_range(1000, 2000);
873 timeout--;
874 }
875 if (!timeout) {
876 e_dbg("MNG configuration cycle has not completed.\n");
877 return -E1000_ERR_RESET;
878 }
879
880 return 0;
881}
882
883
884
885
886
887
888
889
890
891
892
893
894static s32 e1000_set_d0_lplu_state_82571(struct e1000_hw *hw, bool active)
895{
896 struct e1000_phy_info *phy = &hw->phy;
897 s32 ret_val;
898 u16 data;
899
900 ret_val = e1e_rphy(hw, IGP02E1000_PHY_POWER_MGMT, &data);
901 if (ret_val)
902 return ret_val;
903
904 if (active) {
905 data |= IGP02E1000_PM_D0_LPLU;
906 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
907 if (ret_val)
908 return ret_val;
909
910
911 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG, &data);
912 if (ret_val)
913 return ret_val;
914 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
915 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG, data);
916 if (ret_val)
917 return ret_val;
918 } else {
919 data &= ~IGP02E1000_PM_D0_LPLU;
920 ret_val = e1e_wphy(hw, IGP02E1000_PHY_POWER_MGMT, data);
921
922
923
924
925
926 if (phy->smart_speed == e1000_smart_speed_on) {
927 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
928 &data);
929 if (ret_val)
930 return ret_val;
931
932 data |= IGP01E1000_PSCFR_SMART_SPEED;
933 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
934 data);
935 if (ret_val)
936 return ret_val;
937 } else if (phy->smart_speed == e1000_smart_speed_off) {
938 ret_val = e1e_rphy(hw, IGP01E1000_PHY_PORT_CONFIG,
939 &data);
940 if (ret_val)
941 return ret_val;
942
943 data &= ~IGP01E1000_PSCFR_SMART_SPEED;
944 ret_val = e1e_wphy(hw, IGP01E1000_PHY_PORT_CONFIG,
945 data);
946 if (ret_val)
947 return ret_val;
948 }
949 }
950
951 return 0;
952}
953
954
955
956
957
958
959
960static s32 e1000_reset_hw_82571(struct e1000_hw *hw)
961{
962 u32 ctrl, ctrl_ext, eecd, tctl;
963 s32 ret_val;
964
965
966
967
968 ret_val = e1000e_disable_pcie_master(hw);
969 if (ret_val)
970 e_dbg("PCI-E Master disable polling has failed.\n");
971
972 e_dbg("Masking off all interrupts\n");
973 ew32(IMC, 0xffffffff);
974
975 ew32(RCTL, 0);
976 tctl = er32(TCTL);
977 tctl &= ~E1000_TCTL_EN;
978 ew32(TCTL, tctl);
979 e1e_flush();
980
981 usleep_range(10000, 20000);
982
983
984
985
986 switch (hw->mac.type) {
987 case e1000_82573:
988 ret_val = e1000_get_hw_semaphore_82573(hw);
989 break;
990 case e1000_82574:
991 case e1000_82583:
992 ret_val = e1000_get_hw_semaphore_82574(hw);
993 break;
994 default:
995 break;
996 }
997
998 ctrl = er32(CTRL);
999
1000 e_dbg("Issuing a global reset to MAC\n");
1001 ew32(CTRL, ctrl | E1000_CTRL_RST);
1002
1003
1004 switch (hw->mac.type) {
1005 case e1000_82573:
1006
1007 if (!ret_val)
1008 e1000_put_hw_semaphore_82573(hw);
1009 break;
1010 case e1000_82574:
1011 case e1000_82583:
1012
1013 if (!ret_val)
1014 e1000_put_hw_semaphore_82574(hw);
1015 break;
1016 default:
1017 break;
1018 }
1019
1020 if (hw->nvm.type == e1000_nvm_flash_hw) {
1021 usleep_range(10, 20);
1022 ctrl_ext = er32(CTRL_EXT);
1023 ctrl_ext |= E1000_CTRL_EXT_EE_RST;
1024 ew32(CTRL_EXT, ctrl_ext);
1025 e1e_flush();
1026 }
1027
1028 ret_val = e1000e_get_auto_rd_done(hw);
1029 if (ret_val)
1030
1031 return ret_val;
1032
1033
1034
1035
1036
1037
1038 switch (hw->mac.type) {
1039 case e1000_82571:
1040 case e1000_82572:
1041
1042
1043
1044 eecd = er32(EECD);
1045 eecd &= ~(E1000_EECD_REQ | E1000_EECD_GNT);
1046 ew32(EECD, eecd);
1047 break;
1048 case e1000_82573:
1049 case e1000_82574:
1050 case e1000_82583:
1051 msleep(25);
1052 break;
1053 default:
1054 break;
1055 }
1056
1057
1058 ew32(IMC, 0xffffffff);
1059 er32(ICR);
1060
1061 if (hw->mac.type == e1000_82571) {
1062
1063 ret_val = e1000_check_alt_mac_addr_generic(hw);
1064 if (ret_val)
1065 return ret_val;
1066
1067 e1000e_set_laa_state_82571(hw, true);
1068 }
1069
1070
1071 if (hw->phy.media_type == e1000_media_type_internal_serdes)
1072 hw->mac.serdes_link_state = e1000_serdes_link_down;
1073
1074 return 0;
1075}
1076
1077
1078
1079
1080
1081
1082
1083static s32 e1000_init_hw_82571(struct e1000_hw *hw)
1084{
1085 struct e1000_mac_info *mac = &hw->mac;
1086 u32 reg_data;
1087 s32 ret_val;
1088 u16 i, rar_count = mac->rar_entry_count;
1089
1090 e1000_initialize_hw_bits_82571(hw);
1091
1092
1093 ret_val = mac->ops.id_led_init(hw);
1094
1095 if (ret_val)
1096 e_dbg("Error initializing identification LED\n");
1097
1098
1099 e_dbg("Initializing the IEEE VLAN\n");
1100 mac->ops.clear_vfta(hw);
1101
1102
1103
1104
1105
1106
1107 if (e1000e_get_laa_state_82571(hw))
1108 rar_count--;
1109 e1000e_init_rx_addrs(hw, rar_count);
1110
1111
1112 e_dbg("Zeroing the MTA\n");
1113 for (i = 0; i < mac->mta_reg_count; i++)
1114 E1000_WRITE_REG_ARRAY(hw, E1000_MTA, i, 0);
1115
1116
1117 ret_val = mac->ops.setup_link(hw);
1118
1119
1120 reg_data = er32(TXDCTL(0));
1121 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1122 E1000_TXDCTL_FULL_TX_DESC_WB | E1000_TXDCTL_COUNT_DESC);
1123 ew32(TXDCTL(0), reg_data);
1124
1125
1126 switch (mac->type) {
1127 case e1000_82573:
1128 e1000e_enable_tx_pkt_filtering(hw);
1129
1130 case e1000_82574:
1131 case e1000_82583:
1132 reg_data = er32(GCR);
1133 reg_data |= E1000_GCR_L1_ACT_WITHOUT_L0S_RX;
1134 ew32(GCR, reg_data);
1135 break;
1136 default:
1137 reg_data = er32(TXDCTL(1));
1138 reg_data = ((reg_data & ~E1000_TXDCTL_WTHRESH) |
1139 E1000_TXDCTL_FULL_TX_DESC_WB |
1140 E1000_TXDCTL_COUNT_DESC);
1141 ew32(TXDCTL(1), reg_data);
1142 break;
1143 }
1144
1145
1146
1147
1148
1149
1150 e1000_clear_hw_cntrs_82571(hw);
1151
1152 return ret_val;
1153}
1154
1155
1156
1157
1158
1159
1160
1161static void e1000_initialize_hw_bits_82571(struct e1000_hw *hw)
1162{
1163 u32 reg;
1164
1165
1166 reg = er32(TXDCTL(0));
1167 reg |= BIT(22);
1168 ew32(TXDCTL(0), reg);
1169
1170
1171 reg = er32(TXDCTL(1));
1172 reg |= BIT(22);
1173 ew32(TXDCTL(1), reg);
1174
1175
1176 reg = er32(TARC(0));
1177 reg &= ~(0xF << 27);
1178 switch (hw->mac.type) {
1179 case e1000_82571:
1180 case e1000_82572:
1181 reg |= BIT(23) | BIT(24) | BIT(25) | BIT(26);
1182 break;
1183 case e1000_82574:
1184 case e1000_82583:
1185 reg |= BIT(26);
1186 break;
1187 default:
1188 break;
1189 }
1190 ew32(TARC(0), reg);
1191
1192
1193 reg = er32(TARC(1));
1194 switch (hw->mac.type) {
1195 case e1000_82571:
1196 case e1000_82572:
1197 reg &= ~(BIT(29) | BIT(30));
1198 reg |= BIT(22) | BIT(24) | BIT(25) | BIT(26);
1199 if (er32(TCTL) & E1000_TCTL_MULR)
1200 reg &= ~BIT(28);
1201 else
1202 reg |= BIT(28);
1203 ew32(TARC(1), reg);
1204 break;
1205 default:
1206 break;
1207 }
1208
1209
1210 switch (hw->mac.type) {
1211 case e1000_82573:
1212 case e1000_82574:
1213 case e1000_82583:
1214 reg = er32(CTRL);
1215 reg &= ~BIT(29);
1216 ew32(CTRL, reg);
1217 break;
1218 default:
1219 break;
1220 }
1221
1222
1223 switch (hw->mac.type) {
1224 case e1000_82573:
1225 case e1000_82574:
1226 case e1000_82583:
1227 reg = er32(CTRL_EXT);
1228 reg &= ~BIT(23);
1229 reg |= BIT(22);
1230 ew32(CTRL_EXT, reg);
1231 break;
1232 default:
1233 break;
1234 }
1235
1236 if (hw->mac.type == e1000_82571) {
1237 reg = er32(PBA_ECC);
1238 reg |= E1000_PBA_ECC_CORR_EN;
1239 ew32(PBA_ECC, reg);
1240 }
1241
1242
1243
1244
1245 if ((hw->mac.type == e1000_82571) || (hw->mac.type == e1000_82572)) {
1246 reg = er32(CTRL_EXT);
1247 reg &= ~E1000_CTRL_EXT_DMA_DYN_CLK_EN;
1248 ew32(CTRL_EXT, reg);
1249 }
1250
1251
1252
1253
1254 if (hw->mac.type <= e1000_82573) {
1255 reg = er32(RFCTL);
1256 reg |= (E1000_RFCTL_IPV6_EX_DIS | E1000_RFCTL_NEW_IPV6_EXT_DIS);
1257 ew32(RFCTL, reg);
1258 }
1259
1260
1261 switch (hw->mac.type) {
1262 case e1000_82574:
1263 case e1000_82583:
1264 reg = er32(GCR);
1265 reg |= BIT(22);
1266 ew32(GCR, reg);
1267
1268
1269
1270
1271
1272
1273
1274 reg = er32(GCR2);
1275 reg |= 1;
1276 ew32(GCR2, reg);
1277 break;
1278 default:
1279 break;
1280 }
1281}
1282
1283
1284
1285
1286
1287
1288
1289
1290static void e1000_clear_vfta_82571(struct e1000_hw *hw)
1291{
1292 u32 offset;
1293 u32 vfta_value = 0;
1294 u32 vfta_offset = 0;
1295 u32 vfta_bit_in_reg = 0;
1296
1297 switch (hw->mac.type) {
1298 case e1000_82573:
1299 case e1000_82574:
1300 case e1000_82583:
1301 if (hw->mng_cookie.vlan_id != 0) {
1302
1303
1304
1305
1306
1307
1308 vfta_offset = (hw->mng_cookie.vlan_id >>
1309 E1000_VFTA_ENTRY_SHIFT) &
1310 E1000_VFTA_ENTRY_MASK;
1311 vfta_bit_in_reg =
1312 BIT(hw->mng_cookie.vlan_id &
1313 E1000_VFTA_ENTRY_BIT_SHIFT_MASK);
1314 }
1315 break;
1316 default:
1317 break;
1318 }
1319 for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++) {
1320
1321
1322
1323
1324 vfta_value = (offset == vfta_offset) ? vfta_bit_in_reg : 0;
1325 E1000_WRITE_REG_ARRAY(hw, E1000_VFTA, offset, vfta_value);
1326 e1e_flush();
1327 }
1328}
1329
1330
1331
1332
1333
1334
1335
1336
1337static bool e1000_check_mng_mode_82574(struct e1000_hw *hw)
1338{
1339 u16 data;
1340
1341 e1000_read_nvm(hw, NVM_INIT_CONTROL2_REG, 1, &data);
1342 return (data & E1000_NVM_INIT_CTRL2_MNGM) != 0;
1343}
1344
1345
1346
1347
1348
1349
1350
1351static s32 e1000_led_on_82574(struct e1000_hw *hw)
1352{
1353 u32 ctrl;
1354 u32 i;
1355
1356 ctrl = hw->mac.ledctl_mode2;
1357 if (!(E1000_STATUS_LU & er32(STATUS))) {
1358
1359
1360
1361 for (i = 0; i < 4; i++)
1362 if (((hw->mac.ledctl_mode2 >> (i * 8)) & 0xFF) ==
1363 E1000_LEDCTL_MODE_LED_ON)
1364 ctrl |= (E1000_LEDCTL_LED0_IVRT << (i * 8));
1365 }
1366 ew32(LEDCTL, ctrl);
1367
1368 return 0;
1369}
1370
1371
1372
1373
1374
1375
1376
1377bool e1000_check_phy_82574(struct e1000_hw *hw)
1378{
1379 u16 status_1kbt = 0;
1380 u16 receive_errors = 0;
1381 s32 ret_val;
1382
1383
1384
1385
1386 ret_val = e1e_rphy(hw, E1000_RECEIVE_ERROR_COUNTER, &receive_errors);
1387 if (ret_val)
1388 return false;
1389 if (receive_errors == E1000_RECEIVE_ERROR_MAX) {
1390 ret_val = e1e_rphy(hw, E1000_BASE1000T_STATUS, &status_1kbt);
1391 if (ret_val)
1392 return false;
1393 if ((status_1kbt & E1000_IDLE_ERROR_COUNT_MASK) ==
1394 E1000_IDLE_ERROR_COUNT_MASK)
1395 return true;
1396 }
1397
1398 return false;
1399}
1400
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411static s32 e1000_setup_link_82571(struct e1000_hw *hw)
1412{
1413
1414
1415
1416
1417 switch (hw->mac.type) {
1418 case e1000_82573:
1419 case e1000_82574:
1420 case e1000_82583:
1421 if (hw->fc.requested_mode == e1000_fc_default)
1422 hw->fc.requested_mode = e1000_fc_full;
1423 break;
1424 default:
1425 break;
1426 }
1427
1428 return e1000e_setup_link_generic(hw);
1429}
1430
1431
1432
1433
1434
1435
1436
1437
1438
1439static s32 e1000_setup_copper_link_82571(struct e1000_hw *hw)
1440{
1441 u32 ctrl;
1442 s32 ret_val;
1443
1444 ctrl = er32(CTRL);
1445 ctrl |= E1000_CTRL_SLU;
1446 ctrl &= ~(E1000_CTRL_FRCSPD | E1000_CTRL_FRCDPX);
1447 ew32(CTRL, ctrl);
1448
1449 switch (hw->phy.type) {
1450 case e1000_phy_m88:
1451 case e1000_phy_bm:
1452 ret_val = e1000e_copper_link_setup_m88(hw);
1453 break;
1454 case e1000_phy_igp_2:
1455 ret_val = e1000e_copper_link_setup_igp(hw);
1456 break;
1457 default:
1458 return -E1000_ERR_PHY;
1459 }
1460
1461 if (ret_val)
1462 return ret_val;
1463
1464 return e1000e_setup_copper_link(hw);
1465}
1466
1467
1468
1469
1470
1471
1472
1473
1474static s32 e1000_setup_fiber_serdes_link_82571(struct e1000_hw *hw)
1475{
1476 switch (hw->mac.type) {
1477 case e1000_82571:
1478 case e1000_82572:
1479
1480
1481
1482
1483
1484
1485 ew32(SCTL, E1000_SCTL_DISABLE_SERDES_LOOPBACK);
1486 break;
1487 default:
1488 break;
1489 }
1490
1491 return e1000e_setup_fiber_serdes_link(hw);
1492}
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508
1509
1510
1511
1512
1513static s32 e1000_check_for_serdes_link_82571(struct e1000_hw *hw)
1514{
1515 struct e1000_mac_info *mac = &hw->mac;
1516 u32 rxcw;
1517 u32 ctrl;
1518 u32 status;
1519 u32 txcw;
1520 u32 i;
1521 s32 ret_val = 0;
1522
1523 ctrl = er32(CTRL);
1524 status = er32(STATUS);
1525 er32(RXCW);
1526
1527 usleep_range(10, 20);
1528 rxcw = er32(RXCW);
1529
1530 if ((rxcw & E1000_RXCW_SYNCH) && !(rxcw & E1000_RXCW_IV)) {
1531
1532 switch (mac->serdes_link_state) {
1533 case e1000_serdes_link_autoneg_complete:
1534 if (!(status & E1000_STATUS_LU)) {
1535
1536
1537
1538 mac->serdes_link_state =
1539 e1000_serdes_link_autoneg_progress;
1540 mac->serdes_has_link = false;
1541 e_dbg("AN_UP -> AN_PROG\n");
1542 } else {
1543 mac->serdes_has_link = true;
1544 }
1545 break;
1546
1547 case e1000_serdes_link_forced_up:
1548
1549
1550
1551
1552
1553 if (rxcw & E1000_RXCW_C) {
1554
1555 ew32(TXCW, mac->txcw);
1556 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1557 mac->serdes_link_state =
1558 e1000_serdes_link_autoneg_progress;
1559 mac->serdes_has_link = false;
1560 e_dbg("FORCED_UP -> AN_PROG\n");
1561 } else {
1562 mac->serdes_has_link = true;
1563 }
1564 break;
1565
1566 case e1000_serdes_link_autoneg_progress:
1567 if (rxcw & E1000_RXCW_C) {
1568
1569
1570
1571
1572 if (status & E1000_STATUS_LU) {
1573 mac->serdes_link_state =
1574 e1000_serdes_link_autoneg_complete;
1575 e_dbg("AN_PROG -> AN_UP\n");
1576 mac->serdes_has_link = true;
1577 } else {
1578
1579 mac->serdes_link_state =
1580 e1000_serdes_link_down;
1581 e_dbg("AN_PROG -> DOWN\n");
1582 }
1583 } else {
1584
1585
1586
1587
1588 ew32(TXCW, (mac->txcw & ~E1000_TXCW_ANE));
1589 ctrl |= (E1000_CTRL_SLU | E1000_CTRL_FD);
1590 ew32(CTRL, ctrl);
1591
1592
1593 ret_val = e1000e_config_fc_after_link_up(hw);
1594 if (ret_val) {
1595 e_dbg("Error config flow control\n");
1596 break;
1597 }
1598 mac->serdes_link_state =
1599 e1000_serdes_link_forced_up;
1600 mac->serdes_has_link = true;
1601 e_dbg("AN_PROG -> FORCED_UP\n");
1602 }
1603 break;
1604
1605 case e1000_serdes_link_down:
1606 default:
1607
1608
1609
1610
1611 ew32(TXCW, mac->txcw);
1612 ew32(CTRL, (ctrl & ~E1000_CTRL_SLU));
1613 mac->serdes_link_state =
1614 e1000_serdes_link_autoneg_progress;
1615 mac->serdes_has_link = false;
1616 e_dbg("DOWN -> AN_PROG\n");
1617 break;
1618 }
1619 } else {
1620 if (!(rxcw & E1000_RXCW_SYNCH)) {
1621 mac->serdes_has_link = false;
1622 mac->serdes_link_state = e1000_serdes_link_down;
1623 e_dbg("ANYSTATE -> DOWN\n");
1624 } else {
1625
1626
1627
1628
1629 for (i = 0; i < AN_RETRY_COUNT; i++) {
1630 usleep_range(10, 20);
1631 rxcw = er32(RXCW);
1632 if ((rxcw & E1000_RXCW_SYNCH) &&
1633 (rxcw & E1000_RXCW_C))
1634 continue;
1635
1636 if (rxcw & E1000_RXCW_IV) {
1637 mac->serdes_has_link = false;
1638 mac->serdes_link_state =
1639 e1000_serdes_link_down;
1640 e_dbg("ANYSTATE -> DOWN\n");
1641 break;
1642 }
1643 }
1644
1645 if (i == AN_RETRY_COUNT) {
1646 txcw = er32(TXCW);
1647 txcw |= E1000_TXCW_ANE;
1648 ew32(TXCW, txcw);
1649 mac->serdes_link_state =
1650 e1000_serdes_link_autoneg_progress;
1651 mac->serdes_has_link = false;
1652 e_dbg("ANYSTATE -> AN_PROG\n");
1653 }
1654 }
1655 }
1656
1657 return ret_val;
1658}
1659
1660
1661
1662
1663
1664
1665
1666
1667
1668static s32 e1000_valid_led_default_82571(struct e1000_hw *hw, u16 *data)
1669{
1670 s32 ret_val;
1671
1672 ret_val = e1000_read_nvm(hw, NVM_ID_LED_SETTINGS, 1, data);
1673 if (ret_val) {
1674 e_dbg("NVM Read Error\n");
1675 return ret_val;
1676 }
1677
1678 switch (hw->mac.type) {
1679 case e1000_82573:
1680 case e1000_82574:
1681 case e1000_82583:
1682 if (*data == ID_LED_RESERVED_F746)
1683 *data = ID_LED_DEFAULT_82573;
1684 break;
1685 default:
1686 if (*data == ID_LED_RESERVED_0000 ||
1687 *data == ID_LED_RESERVED_FFFF)
1688 *data = ID_LED_DEFAULT;
1689 break;
1690 }
1691
1692 return 0;
1693}
1694
1695
1696
1697
1698
1699
1700
1701bool e1000e_get_laa_state_82571(struct e1000_hw *hw)
1702{
1703 if (hw->mac.type != e1000_82571)
1704 return false;
1705
1706 return hw->dev_spec.e82571.laa_is_present;
1707}
1708
1709
1710
1711
1712
1713
1714
1715
1716void e1000e_set_laa_state_82571(struct e1000_hw *hw, bool state)
1717{
1718 if (hw->mac.type != e1000_82571)
1719 return;
1720
1721 hw->dev_spec.e82571.laa_is_present = state;
1722
1723
1724 if (state)
1725
1726
1727
1728
1729
1730
1731 hw->mac.ops.rar_set(hw, hw->mac.addr,
1732 hw->mac.rar_entry_count - 1);
1733}
1734
1735
1736
1737
1738
1739
1740
1741
1742
1743
1744
1745static s32 e1000_fix_nvm_checksum_82571(struct e1000_hw *hw)
1746{
1747 struct e1000_nvm_info *nvm = &hw->nvm;
1748 s32 ret_val;
1749 u16 data;
1750
1751 if (nvm->type != e1000_nvm_flash_hw)
1752 return 0;
1753
1754
1755
1756
1757 ret_val = e1000_read_nvm(hw, 0x10, 1, &data);
1758 if (ret_val)
1759 return ret_val;
1760
1761 if (!(data & 0x10)) {
1762
1763
1764
1765
1766
1767
1768
1769 ret_val = e1000_read_nvm(hw, 0x23, 1, &data);
1770 if (ret_val)
1771 return ret_val;
1772
1773 if (!(data & 0x8000)) {
1774 data |= 0x8000;
1775 ret_val = e1000_write_nvm(hw, 0x23, 1, &data);
1776 if (ret_val)
1777 return ret_val;
1778 ret_val = e1000e_update_nvm_checksum(hw);
1779 if (ret_val)
1780 return ret_val;
1781 }
1782 }
1783
1784 return 0;
1785}
1786
1787
1788
1789
1790
1791static s32 e1000_read_mac_addr_82571(struct e1000_hw *hw)
1792{
1793 if (hw->mac.type == e1000_82571) {
1794 s32 ret_val;
1795
1796
1797
1798
1799
1800 ret_val = e1000_check_alt_mac_addr_generic(hw);
1801 if (ret_val)
1802 return ret_val;
1803 }
1804
1805 return e1000_read_mac_addr_generic(hw);
1806}
1807
1808
1809
1810
1811
1812
1813
1814
1815static void e1000_power_down_phy_copper_82571(struct e1000_hw *hw)
1816{
1817 struct e1000_phy_info *phy = &hw->phy;
1818 struct e1000_mac_info *mac = &hw->mac;
1819
1820 if (!phy->ops.check_reset_block)
1821 return;
1822
1823
1824 if (!(mac->ops.check_mng_mode(hw) || phy->ops.check_reset_block(hw)))
1825 e1000_power_down_phy_copper(hw);
1826}
1827
1828
1829
1830
1831
1832
1833
1834static void e1000_clear_hw_cntrs_82571(struct e1000_hw *hw)
1835{
1836 e1000e_clear_hw_cntrs_base(hw);
1837
1838 er32(PRC64);
1839 er32(PRC127);
1840 er32(PRC255);
1841 er32(PRC511);
1842 er32(PRC1023);
1843 er32(PRC1522);
1844 er32(PTC64);
1845 er32(PTC127);
1846 er32(PTC255);
1847 er32(PTC511);
1848 er32(PTC1023);
1849 er32(PTC1522);
1850
1851 er32(ALGNERRC);
1852 er32(RXERRC);
1853 er32(TNCRS);
1854 er32(CEXTERR);
1855 er32(TSCTC);
1856 er32(TSCTFC);
1857
1858 er32(MGTPRC);
1859 er32(MGTPDC);
1860 er32(MGTPTC);
1861
1862 er32(IAC);
1863 er32(ICRXOC);
1864
1865 er32(ICRXPTC);
1866 er32(ICRXATC);
1867 er32(ICTXPTC);
1868 er32(ICTXATC);
1869 er32(ICTXQEC);
1870 er32(ICTXQMTC);
1871 er32(ICRXDMTC);
1872}
1873
1874static const struct e1000_mac_operations e82571_mac_ops = {
1875
1876
1877 .id_led_init = e1000e_id_led_init_generic,
1878 .cleanup_led = e1000e_cleanup_led_generic,
1879 .clear_hw_cntrs = e1000_clear_hw_cntrs_82571,
1880 .get_bus_info = e1000e_get_bus_info_pcie,
1881 .set_lan_id = e1000_set_lan_id_multi_port_pcie,
1882
1883
1884 .led_off = e1000e_led_off_generic,
1885 .update_mc_addr_list = e1000e_update_mc_addr_list_generic,
1886 .write_vfta = e1000_write_vfta_generic,
1887 .clear_vfta = e1000_clear_vfta_82571,
1888 .reset_hw = e1000_reset_hw_82571,
1889 .init_hw = e1000_init_hw_82571,
1890 .setup_link = e1000_setup_link_82571,
1891
1892 .setup_led = e1000e_setup_led_generic,
1893 .config_collision_dist = e1000e_config_collision_dist_generic,
1894 .read_mac_addr = e1000_read_mac_addr_82571,
1895 .rar_set = e1000e_rar_set_generic,
1896 .rar_get_count = e1000e_rar_get_count_generic,
1897};
1898
1899static const struct e1000_phy_operations e82_phy_ops_igp = {
1900 .acquire = e1000_get_hw_semaphore_82571,
1901 .check_polarity = e1000_check_polarity_igp,
1902 .check_reset_block = e1000e_check_reset_block_generic,
1903 .commit = NULL,
1904 .force_speed_duplex = e1000e_phy_force_speed_duplex_igp,
1905 .get_cfg_done = e1000_get_cfg_done_82571,
1906 .get_cable_length = e1000e_get_cable_length_igp_2,
1907 .get_info = e1000e_get_phy_info_igp,
1908 .read_reg = e1000e_read_phy_reg_igp,
1909 .release = e1000_put_hw_semaphore_82571,
1910 .reset = e1000e_phy_hw_reset_generic,
1911 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1912 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1913 .write_reg = e1000e_write_phy_reg_igp,
1914 .cfg_on_link_up = NULL,
1915};
1916
1917static const struct e1000_phy_operations e82_phy_ops_m88 = {
1918 .acquire = e1000_get_hw_semaphore_82571,
1919 .check_polarity = e1000_check_polarity_m88,
1920 .check_reset_block = e1000e_check_reset_block_generic,
1921 .commit = e1000e_phy_sw_reset,
1922 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1923 .get_cfg_done = e1000e_get_cfg_done_generic,
1924 .get_cable_length = e1000e_get_cable_length_m88,
1925 .get_info = e1000e_get_phy_info_m88,
1926 .read_reg = e1000e_read_phy_reg_m88,
1927 .release = e1000_put_hw_semaphore_82571,
1928 .reset = e1000e_phy_hw_reset_generic,
1929 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1930 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1931 .write_reg = e1000e_write_phy_reg_m88,
1932 .cfg_on_link_up = NULL,
1933};
1934
1935static const struct e1000_phy_operations e82_phy_ops_bm = {
1936 .acquire = e1000_get_hw_semaphore_82571,
1937 .check_polarity = e1000_check_polarity_m88,
1938 .check_reset_block = e1000e_check_reset_block_generic,
1939 .commit = e1000e_phy_sw_reset,
1940 .force_speed_duplex = e1000e_phy_force_speed_duplex_m88,
1941 .get_cfg_done = e1000e_get_cfg_done_generic,
1942 .get_cable_length = e1000e_get_cable_length_m88,
1943 .get_info = e1000e_get_phy_info_m88,
1944 .read_reg = e1000e_read_phy_reg_bm2,
1945 .release = e1000_put_hw_semaphore_82571,
1946 .reset = e1000e_phy_hw_reset_generic,
1947 .set_d0_lplu_state = e1000_set_d0_lplu_state_82571,
1948 .set_d3_lplu_state = e1000e_set_d3_lplu_state,
1949 .write_reg = e1000e_write_phy_reg_bm2,
1950 .cfg_on_link_up = NULL,
1951};
1952
1953static const struct e1000_nvm_operations e82571_nvm_ops = {
1954 .acquire = e1000_acquire_nvm_82571,
1955 .read = e1000e_read_nvm_eerd,
1956 .release = e1000_release_nvm_82571,
1957 .reload = e1000e_reload_nvm_generic,
1958 .update = e1000_update_nvm_checksum_82571,
1959 .valid_led_default = e1000_valid_led_default_82571,
1960 .validate = e1000_validate_nvm_checksum_82571,
1961 .write = e1000_write_nvm_82571,
1962};
1963
1964const struct e1000_info e1000_82571_info = {
1965 .mac = e1000_82571,
1966 .flags = FLAG_HAS_HW_VLAN_FILTER
1967 | FLAG_HAS_JUMBO_FRAMES
1968 | FLAG_HAS_WOL
1969 | FLAG_APME_IN_CTRL3
1970 | FLAG_HAS_CTRLEXT_ON_LOAD
1971 | FLAG_HAS_SMART_POWER_DOWN
1972 | FLAG_RESET_OVERWRITES_LAA
1973 | FLAG_TARC_SPEED_MODE_BIT
1974 | FLAG_APME_CHECK_PORT_B,
1975 .flags2 = FLAG2_DISABLE_ASPM_L1
1976 | FLAG2_DMA_BURST,
1977 .pba = 38,
1978 .max_hw_frame_size = DEFAULT_JUMBO,
1979 .get_variants = e1000_get_variants_82571,
1980 .mac_ops = &e82571_mac_ops,
1981 .phy_ops = &e82_phy_ops_igp,
1982 .nvm_ops = &e82571_nvm_ops,
1983};
1984
1985const struct e1000_info e1000_82572_info = {
1986 .mac = e1000_82572,
1987 .flags = FLAG_HAS_HW_VLAN_FILTER
1988 | FLAG_HAS_JUMBO_FRAMES
1989 | FLAG_HAS_WOL
1990 | FLAG_APME_IN_CTRL3
1991 | FLAG_HAS_CTRLEXT_ON_LOAD
1992 | FLAG_TARC_SPEED_MODE_BIT,
1993 .flags2 = FLAG2_DISABLE_ASPM_L1
1994 | FLAG2_DMA_BURST,
1995 .pba = 38,
1996 .max_hw_frame_size = DEFAULT_JUMBO,
1997 .get_variants = e1000_get_variants_82571,
1998 .mac_ops = &e82571_mac_ops,
1999 .phy_ops = &e82_phy_ops_igp,
2000 .nvm_ops = &e82571_nvm_ops,
2001};
2002
2003const struct e1000_info e1000_82573_info = {
2004 .mac = e1000_82573,
2005 .flags = FLAG_HAS_HW_VLAN_FILTER
2006 | FLAG_HAS_WOL
2007 | FLAG_APME_IN_CTRL3
2008 | FLAG_HAS_SMART_POWER_DOWN
2009 | FLAG_HAS_AMT
2010 | FLAG_HAS_SWSM_ON_LOAD,
2011 .flags2 = FLAG2_DISABLE_ASPM_L1
2012 | FLAG2_DISABLE_ASPM_L0S,
2013 .pba = 20,
2014 .max_hw_frame_size = VLAN_ETH_FRAME_LEN + ETH_FCS_LEN,
2015 .get_variants = e1000_get_variants_82571,
2016 .mac_ops = &e82571_mac_ops,
2017 .phy_ops = &e82_phy_ops_m88,
2018 .nvm_ops = &e82571_nvm_ops,
2019};
2020
2021const struct e1000_info e1000_82574_info = {
2022 .mac = e1000_82574,
2023 .flags = FLAG_HAS_HW_VLAN_FILTER
2024 | FLAG_HAS_MSIX
2025 | FLAG_HAS_JUMBO_FRAMES
2026 | FLAG_HAS_WOL
2027 | FLAG_HAS_HW_TIMESTAMP
2028 | FLAG_APME_IN_CTRL3
2029 | FLAG_HAS_SMART_POWER_DOWN
2030 | FLAG_HAS_AMT
2031 | FLAG_HAS_CTRLEXT_ON_LOAD,
2032 .flags2 = FLAG2_CHECK_PHY_HANG
2033 | FLAG2_DISABLE_ASPM_L0S
2034 | FLAG2_DISABLE_ASPM_L1
2035 | FLAG2_NO_DISABLE_RX
2036 | FLAG2_DMA_BURST
2037 | FLAG2_CHECK_SYSTIM_OVERFLOW,
2038 .pba = 32,
2039 .max_hw_frame_size = DEFAULT_JUMBO,
2040 .get_variants = e1000_get_variants_82571,
2041 .mac_ops = &e82571_mac_ops,
2042 .phy_ops = &e82_phy_ops_bm,
2043 .nvm_ops = &e82571_nvm_ops,
2044};
2045
2046const struct e1000_info e1000_82583_info = {
2047 .mac = e1000_82583,
2048 .flags = FLAG_HAS_HW_VLAN_FILTER
2049 | FLAG_HAS_WOL
2050 | FLAG_HAS_HW_TIMESTAMP
2051 | FLAG_APME_IN_CTRL3
2052 | FLAG_HAS_SMART_POWER_DOWN
2053 | FLAG_HAS_AMT
2054 | FLAG_HAS_JUMBO_FRAMES
2055 | FLAG_HAS_CTRLEXT_ON_LOAD,
2056 .flags2 = FLAG2_DISABLE_ASPM_L0S
2057 | FLAG2_DISABLE_ASPM_L1
2058 | FLAG2_NO_DISABLE_RX
2059 | FLAG2_CHECK_SYSTIM_OVERFLOW,
2060 .pba = 32,
2061 .max_hw_frame_size = DEFAULT_JUMBO,
2062 .get_variants = e1000_get_variants_82571,
2063 .mac_ops = &e82571_mac_ops,
2064 .phy_ops = &e82_phy_ops_bm,
2065 .nvm_ops = &e82571_nvm_ops,
2066};
2067