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28#include <linux/etherdevice.h>
29#include <linux/of_net.h>
30#include <linux/pci.h>
31#include <linux/bpf.h>
32
33
34#include "i40e.h"
35#include "i40e_diag.h"
36#include <net/udp_tunnel.h>
37
38
39
40
41#define CREATE_TRACE_POINTS
42#include "i40e_trace.h"
43
44const char i40e_driver_name[] = "i40e";
45static const char i40e_driver_string[] =
46 "Intel(R) Ethernet Connection XL710 Network Driver";
47
48#define DRV_KERN "-k"
49
50#define DRV_VERSION_MAJOR 2
51#define DRV_VERSION_MINOR 3
52#define DRV_VERSION_BUILD 2
53#define DRV_VERSION __stringify(DRV_VERSION_MAJOR) "." \
54 __stringify(DRV_VERSION_MINOR) "." \
55 __stringify(DRV_VERSION_BUILD) DRV_KERN
56const char i40e_driver_version_str[] = DRV_VERSION;
57static const char i40e_copyright[] = "Copyright (c) 2013 - 2014 Intel Corporation.";
58
59
60static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi);
61static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired);
62static int i40e_add_vsi(struct i40e_vsi *vsi);
63static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi);
64static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit);
65static int i40e_setup_misc_vector(struct i40e_pf *pf);
66static void i40e_determine_queue_usage(struct i40e_pf *pf);
67static int i40e_setup_pf_filter_control(struct i40e_pf *pf);
68static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired);
69static int i40e_reset(struct i40e_pf *pf);
70static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired);
71static void i40e_fdir_sb_setup(struct i40e_pf *pf);
72static int i40e_veb_get_bw_info(struct i40e_veb *veb);
73static int i40e_get_capabilities(struct i40e_pf *pf,
74 enum i40e_admin_queue_opc list_type);
75
76
77
78
79
80
81
82
83
84static const struct pci_device_id i40e_pci_tbl[] = {
85 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_XL710), 0},
86 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QEMU), 0},
87 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_B), 0},
88 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_C), 0},
89 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_A), 0},
90 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_B), 0},
91 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_C), 0},
92 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T), 0},
93 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T4), 0},
94 {PCI_VDEVICE(INTEL, I40E_DEV_ID_KX_X722), 0},
95 {PCI_VDEVICE(INTEL, I40E_DEV_ID_QSFP_X722), 0},
96 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_X722), 0},
97 {PCI_VDEVICE(INTEL, I40E_DEV_ID_1G_BASE_T_X722), 0},
98 {PCI_VDEVICE(INTEL, I40E_DEV_ID_10G_BASE_T_X722), 0},
99 {PCI_VDEVICE(INTEL, I40E_DEV_ID_SFP_I_X722), 0},
100 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2), 0},
101 {PCI_VDEVICE(INTEL, I40E_DEV_ID_20G_KR2_A), 0},
102 {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_B), 0},
103 {PCI_VDEVICE(INTEL, I40E_DEV_ID_25G_SFP28), 0},
104
105 {0, }
106};
107MODULE_DEVICE_TABLE(pci, i40e_pci_tbl);
108
109#define I40E_MAX_VF_COUNT 128
110static int debug = -1;
111module_param(debug, uint, 0);
112MODULE_PARM_DESC(debug, "Debug level (0=none,...,16=all), Debug mask (0x8XXXXXXX)");
113
114MODULE_AUTHOR("Intel Corporation, <e1000-devel@lists.sourceforge.net>");
115MODULE_DESCRIPTION("Intel(R) Ethernet Connection XL710 Network Driver");
116MODULE_LICENSE("GPL");
117MODULE_VERSION(DRV_VERSION);
118
119static struct workqueue_struct *i40e_wq;
120
121
122
123
124
125
126
127
128int i40e_allocate_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem,
129 u64 size, u32 alignment)
130{
131 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
132
133 mem->size = ALIGN(size, alignment);
134 mem->va = dma_zalloc_coherent(&pf->pdev->dev, mem->size,
135 &mem->pa, GFP_KERNEL);
136 if (!mem->va)
137 return -ENOMEM;
138
139 return 0;
140}
141
142
143
144
145
146
147int i40e_free_dma_mem_d(struct i40e_hw *hw, struct i40e_dma_mem *mem)
148{
149 struct i40e_pf *pf = (struct i40e_pf *)hw->back;
150
151 dma_free_coherent(&pf->pdev->dev, mem->size, mem->va, mem->pa);
152 mem->va = NULL;
153 mem->pa = 0;
154 mem->size = 0;
155
156 return 0;
157}
158
159
160
161
162
163
164
165int i40e_allocate_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem,
166 u32 size)
167{
168 mem->size = size;
169 mem->va = kzalloc(size, GFP_KERNEL);
170
171 if (!mem->va)
172 return -ENOMEM;
173
174 return 0;
175}
176
177
178
179
180
181
182int i40e_free_virt_mem_d(struct i40e_hw *hw, struct i40e_virt_mem *mem)
183{
184
185 kfree(mem->va);
186 mem->va = NULL;
187 mem->size = 0;
188
189 return 0;
190}
191
192
193
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196
197
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202
203
204
205static int i40e_get_lump(struct i40e_pf *pf, struct i40e_lump_tracking *pile,
206 u16 needed, u16 id)
207{
208 int ret = -ENOMEM;
209 int i, j;
210
211 if (!pile || needed == 0 || id >= I40E_PILE_VALID_BIT) {
212 dev_info(&pf->pdev->dev,
213 "param err: pile=%s needed=%d id=0x%04x\n",
214 pile ? "<valid>" : "<null>", needed, id);
215 return -EINVAL;
216 }
217
218
219 i = pile->search_hint;
220 while (i < pile->num_entries) {
221
222 if (pile->list[i] & I40E_PILE_VALID_BIT) {
223 i++;
224 continue;
225 }
226
227
228 for (j = 0; (j < needed) && ((i+j) < pile->num_entries); j++) {
229 if (pile->list[i+j] & I40E_PILE_VALID_BIT)
230 break;
231 }
232
233 if (j == needed) {
234
235 for (j = 0; j < needed; j++)
236 pile->list[i+j] = id | I40E_PILE_VALID_BIT;
237 ret = i;
238 pile->search_hint = i + j;
239 break;
240 }
241
242
243 i += j;
244 }
245
246 return ret;
247}
248
249
250
251
252
253
254
255
256
257static int i40e_put_lump(struct i40e_lump_tracking *pile, u16 index, u16 id)
258{
259 int valid_id = (id | I40E_PILE_VALID_BIT);
260 int count = 0;
261 int i;
262
263 if (!pile || index >= pile->num_entries)
264 return -EINVAL;
265
266 for (i = index;
267 i < pile->num_entries && pile->list[i] == valid_id;
268 i++) {
269 pile->list[i] = 0;
270 count++;
271 }
272
273 if (count && index < pile->search_hint)
274 pile->search_hint = index;
275
276 return count;
277}
278
279
280
281
282
283
284struct i40e_vsi *i40e_find_vsi_from_id(struct i40e_pf *pf, u16 id)
285{
286 int i;
287
288 for (i = 0; i < pf->num_alloc_vsi; i++)
289 if (pf->vsi[i] && (pf->vsi[i]->id == id))
290 return pf->vsi[i];
291
292 return NULL;
293}
294
295
296
297
298
299
300
301void i40e_service_event_schedule(struct i40e_pf *pf)
302{
303 if (!test_bit(__I40E_DOWN, pf->state) &&
304 !test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
305 queue_work(i40e_wq, &pf->service_task);
306}
307
308
309
310
311
312
313
314
315
316static void i40e_tx_timeout(struct net_device *netdev)
317{
318 struct i40e_netdev_priv *np = netdev_priv(netdev);
319 struct i40e_vsi *vsi = np->vsi;
320 struct i40e_pf *pf = vsi->back;
321 struct i40e_ring *tx_ring = NULL;
322 unsigned int i, hung_queue = 0;
323 u32 head, val;
324
325 pf->tx_timeout_count++;
326
327
328 for (i = 0; i < netdev->num_tx_queues; i++) {
329 struct netdev_queue *q;
330 unsigned long trans_start;
331
332 q = netdev_get_tx_queue(netdev, i);
333 trans_start = q->trans_start;
334 if (netif_xmit_stopped(q) &&
335 time_after(jiffies,
336 (trans_start + netdev->watchdog_timeo))) {
337 hung_queue = i;
338 break;
339 }
340 }
341
342 if (i == netdev->num_tx_queues) {
343 netdev_info(netdev, "tx_timeout: no netdev hung queue found\n");
344 } else {
345
346 for (i = 0; i < vsi->num_queue_pairs; i++) {
347 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc) {
348 if (hung_queue ==
349 vsi->tx_rings[i]->queue_index) {
350 tx_ring = vsi->tx_rings[i];
351 break;
352 }
353 }
354 }
355 }
356
357 if (time_after(jiffies, (pf->tx_timeout_last_recovery + HZ*20)))
358 pf->tx_timeout_recovery_level = 1;
359 else if (time_before(jiffies,
360 (pf->tx_timeout_last_recovery + netdev->watchdog_timeo)))
361 return;
362
363 if (tx_ring) {
364 head = i40e_get_head(tx_ring);
365
366 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
367 val = rd32(&pf->hw,
368 I40E_PFINT_DYN_CTLN(tx_ring->q_vector->v_idx +
369 tx_ring->vsi->base_vector - 1));
370 else
371 val = rd32(&pf->hw, I40E_PFINT_DYN_CTL0);
372
373 netdev_info(netdev, "tx_timeout: VSI_seid: %d, Q %d, NTC: 0x%x, HWB: 0x%x, NTU: 0x%x, TAIL: 0x%x, INT: 0x%x\n",
374 vsi->seid, hung_queue, tx_ring->next_to_clean,
375 head, tx_ring->next_to_use,
376 readl(tx_ring->tail), val);
377 }
378
379 pf->tx_timeout_last_recovery = jiffies;
380 netdev_info(netdev, "tx_timeout recovery level %d, hung_queue %d\n",
381 pf->tx_timeout_recovery_level, hung_queue);
382
383 switch (pf->tx_timeout_recovery_level) {
384 case 1:
385 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
386 break;
387 case 2:
388 set_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
389 break;
390 case 3:
391 set_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state);
392 break;
393 default:
394 netdev_err(netdev, "tx_timeout recovery unsuccessful\n");
395 break;
396 }
397
398 i40e_service_event_schedule(pf);
399 pf->tx_timeout_recovery_level++;
400}
401
402
403
404
405
406
407
408
409struct rtnl_link_stats64 *i40e_get_vsi_stats_struct(struct i40e_vsi *vsi)
410{
411 return &vsi->net_stats;
412}
413
414
415
416
417
418
419static void i40e_get_netdev_stats_struct_tx(struct i40e_ring *ring,
420 struct rtnl_link_stats64 *stats)
421{
422 u64 bytes, packets;
423 unsigned int start;
424
425 do {
426 start = u64_stats_fetch_begin_irq(&ring->syncp);
427 packets = ring->stats.packets;
428 bytes = ring->stats.bytes;
429 } while (u64_stats_fetch_retry_irq(&ring->syncp, start));
430
431 stats->tx_packets += packets;
432 stats->tx_bytes += bytes;
433}
434
435
436
437
438
439
440
441
442static void i40e_get_netdev_stats_struct(struct net_device *netdev,
443 struct rtnl_link_stats64 *stats)
444{
445 struct i40e_netdev_priv *np = netdev_priv(netdev);
446 struct i40e_ring *tx_ring, *rx_ring;
447 struct i40e_vsi *vsi = np->vsi;
448 struct rtnl_link_stats64 *vsi_stats = i40e_get_vsi_stats_struct(vsi);
449 int i;
450
451 if (test_bit(__I40E_VSI_DOWN, vsi->state))
452 return;
453
454 if (!vsi->tx_rings)
455 return;
456
457 rcu_read_lock();
458 for (i = 0; i < vsi->num_queue_pairs; i++) {
459 u64 bytes, packets;
460 unsigned int start;
461
462 tx_ring = READ_ONCE(vsi->tx_rings[i]);
463 if (!tx_ring)
464 continue;
465 i40e_get_netdev_stats_struct_tx(tx_ring, stats);
466
467 rx_ring = &tx_ring[1];
468
469 do {
470 start = u64_stats_fetch_begin_irq(&rx_ring->syncp);
471 packets = rx_ring->stats.packets;
472 bytes = rx_ring->stats.bytes;
473 } while (u64_stats_fetch_retry_irq(&rx_ring->syncp, start));
474
475 stats->rx_packets += packets;
476 stats->rx_bytes += bytes;
477
478 if (i40e_enabled_xdp_vsi(vsi))
479 i40e_get_netdev_stats_struct_tx(&rx_ring[1], stats);
480 }
481 rcu_read_unlock();
482
483
484 stats->multicast = vsi_stats->multicast;
485 stats->tx_errors = vsi_stats->tx_errors;
486 stats->tx_dropped = vsi_stats->tx_dropped;
487 stats->rx_errors = vsi_stats->rx_errors;
488 stats->rx_dropped = vsi_stats->rx_dropped;
489 stats->rx_crc_errors = vsi_stats->rx_crc_errors;
490 stats->rx_length_errors = vsi_stats->rx_length_errors;
491}
492
493
494
495
496
497void i40e_vsi_reset_stats(struct i40e_vsi *vsi)
498{
499 struct rtnl_link_stats64 *ns;
500 int i;
501
502 if (!vsi)
503 return;
504
505 ns = i40e_get_vsi_stats_struct(vsi);
506 memset(ns, 0, sizeof(*ns));
507 memset(&vsi->net_stats_offsets, 0, sizeof(vsi->net_stats_offsets));
508 memset(&vsi->eth_stats, 0, sizeof(vsi->eth_stats));
509 memset(&vsi->eth_stats_offsets, 0, sizeof(vsi->eth_stats_offsets));
510 if (vsi->rx_rings && vsi->rx_rings[0]) {
511 for (i = 0; i < vsi->num_queue_pairs; i++) {
512 memset(&vsi->rx_rings[i]->stats, 0,
513 sizeof(vsi->rx_rings[i]->stats));
514 memset(&vsi->rx_rings[i]->rx_stats, 0,
515 sizeof(vsi->rx_rings[i]->rx_stats));
516 memset(&vsi->tx_rings[i]->stats, 0,
517 sizeof(vsi->tx_rings[i]->stats));
518 memset(&vsi->tx_rings[i]->tx_stats, 0,
519 sizeof(vsi->tx_rings[i]->tx_stats));
520 }
521 }
522 vsi->stat_offsets_loaded = false;
523}
524
525
526
527
528
529void i40e_pf_reset_stats(struct i40e_pf *pf)
530{
531 int i;
532
533 memset(&pf->stats, 0, sizeof(pf->stats));
534 memset(&pf->stats_offsets, 0, sizeof(pf->stats_offsets));
535 pf->stat_offsets_loaded = false;
536
537 for (i = 0; i < I40E_MAX_VEB; i++) {
538 if (pf->veb[i]) {
539 memset(&pf->veb[i]->stats, 0,
540 sizeof(pf->veb[i]->stats));
541 memset(&pf->veb[i]->stats_offsets, 0,
542 sizeof(pf->veb[i]->stats_offsets));
543 pf->veb[i]->stat_offsets_loaded = false;
544 }
545 }
546 pf->hw_csum_rx_error = 0;
547}
548
549
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559
560
561
562
563
564static void i40e_stat_update48(struct i40e_hw *hw, u32 hireg, u32 loreg,
565 bool offset_loaded, u64 *offset, u64 *stat)
566{
567 u64 new_data;
568
569 if (hw->device_id == I40E_DEV_ID_QEMU) {
570 new_data = rd32(hw, loreg);
571 new_data |= ((u64)(rd32(hw, hireg) & 0xFFFF)) << 32;
572 } else {
573 new_data = rd64(hw, loreg);
574 }
575 if (!offset_loaded)
576 *offset = new_data;
577 if (likely(new_data >= *offset))
578 *stat = new_data - *offset;
579 else
580 *stat = (new_data + BIT_ULL(48)) - *offset;
581 *stat &= 0xFFFFFFFFFFFFULL;
582}
583
584
585
586
587
588
589
590
591
592static void i40e_stat_update32(struct i40e_hw *hw, u32 reg,
593 bool offset_loaded, u64 *offset, u64 *stat)
594{
595 u32 new_data;
596
597 new_data = rd32(hw, reg);
598 if (!offset_loaded)
599 *offset = new_data;
600 if (likely(new_data >= *offset))
601 *stat = (u32)(new_data - *offset);
602 else
603 *stat = (u32)((new_data + BIT_ULL(32)) - *offset);
604}
605
606
607
608
609
610
611
612static void i40e_stat_update_and_clear32(struct i40e_hw *hw, u32 reg, u64 *stat)
613{
614 u32 new_data = rd32(hw, reg);
615
616 wr32(hw, reg, 1);
617 *stat += new_data;
618}
619
620
621
622
623
624void i40e_update_eth_stats(struct i40e_vsi *vsi)
625{
626 int stat_idx = le16_to_cpu(vsi->info.stat_counter_idx);
627 struct i40e_pf *pf = vsi->back;
628 struct i40e_hw *hw = &pf->hw;
629 struct i40e_eth_stats *oes;
630 struct i40e_eth_stats *es;
631
632 es = &vsi->eth_stats;
633 oes = &vsi->eth_stats_offsets;
634
635
636 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
637 vsi->stat_offsets_loaded,
638 &oes->tx_errors, &es->tx_errors);
639 i40e_stat_update32(hw, I40E_GLV_RDPC(stat_idx),
640 vsi->stat_offsets_loaded,
641 &oes->rx_discards, &es->rx_discards);
642 i40e_stat_update32(hw, I40E_GLV_RUPP(stat_idx),
643 vsi->stat_offsets_loaded,
644 &oes->rx_unknown_protocol, &es->rx_unknown_protocol);
645 i40e_stat_update32(hw, I40E_GLV_TEPC(stat_idx),
646 vsi->stat_offsets_loaded,
647 &oes->tx_errors, &es->tx_errors);
648
649 i40e_stat_update48(hw, I40E_GLV_GORCH(stat_idx),
650 I40E_GLV_GORCL(stat_idx),
651 vsi->stat_offsets_loaded,
652 &oes->rx_bytes, &es->rx_bytes);
653 i40e_stat_update48(hw, I40E_GLV_UPRCH(stat_idx),
654 I40E_GLV_UPRCL(stat_idx),
655 vsi->stat_offsets_loaded,
656 &oes->rx_unicast, &es->rx_unicast);
657 i40e_stat_update48(hw, I40E_GLV_MPRCH(stat_idx),
658 I40E_GLV_MPRCL(stat_idx),
659 vsi->stat_offsets_loaded,
660 &oes->rx_multicast, &es->rx_multicast);
661 i40e_stat_update48(hw, I40E_GLV_BPRCH(stat_idx),
662 I40E_GLV_BPRCL(stat_idx),
663 vsi->stat_offsets_loaded,
664 &oes->rx_broadcast, &es->rx_broadcast);
665
666 i40e_stat_update48(hw, I40E_GLV_GOTCH(stat_idx),
667 I40E_GLV_GOTCL(stat_idx),
668 vsi->stat_offsets_loaded,
669 &oes->tx_bytes, &es->tx_bytes);
670 i40e_stat_update48(hw, I40E_GLV_UPTCH(stat_idx),
671 I40E_GLV_UPTCL(stat_idx),
672 vsi->stat_offsets_loaded,
673 &oes->tx_unicast, &es->tx_unicast);
674 i40e_stat_update48(hw, I40E_GLV_MPTCH(stat_idx),
675 I40E_GLV_MPTCL(stat_idx),
676 vsi->stat_offsets_loaded,
677 &oes->tx_multicast, &es->tx_multicast);
678 i40e_stat_update48(hw, I40E_GLV_BPTCH(stat_idx),
679 I40E_GLV_BPTCL(stat_idx),
680 vsi->stat_offsets_loaded,
681 &oes->tx_broadcast, &es->tx_broadcast);
682 vsi->stat_offsets_loaded = true;
683}
684
685
686
687
688
689static void i40e_update_veb_stats(struct i40e_veb *veb)
690{
691 struct i40e_pf *pf = veb->pf;
692 struct i40e_hw *hw = &pf->hw;
693 struct i40e_eth_stats *oes;
694 struct i40e_eth_stats *es;
695 struct i40e_veb_tc_stats *veb_oes;
696 struct i40e_veb_tc_stats *veb_es;
697 int i, idx = 0;
698
699 idx = veb->stats_idx;
700 es = &veb->stats;
701 oes = &veb->stats_offsets;
702 veb_es = &veb->tc_stats;
703 veb_oes = &veb->tc_stats_offsets;
704
705
706 i40e_stat_update32(hw, I40E_GLSW_TDPC(idx),
707 veb->stat_offsets_loaded,
708 &oes->tx_discards, &es->tx_discards);
709 if (hw->revision_id > 0)
710 i40e_stat_update32(hw, I40E_GLSW_RUPP(idx),
711 veb->stat_offsets_loaded,
712 &oes->rx_unknown_protocol,
713 &es->rx_unknown_protocol);
714 i40e_stat_update48(hw, I40E_GLSW_GORCH(idx), I40E_GLSW_GORCL(idx),
715 veb->stat_offsets_loaded,
716 &oes->rx_bytes, &es->rx_bytes);
717 i40e_stat_update48(hw, I40E_GLSW_UPRCH(idx), I40E_GLSW_UPRCL(idx),
718 veb->stat_offsets_loaded,
719 &oes->rx_unicast, &es->rx_unicast);
720 i40e_stat_update48(hw, I40E_GLSW_MPRCH(idx), I40E_GLSW_MPRCL(idx),
721 veb->stat_offsets_loaded,
722 &oes->rx_multicast, &es->rx_multicast);
723 i40e_stat_update48(hw, I40E_GLSW_BPRCH(idx), I40E_GLSW_BPRCL(idx),
724 veb->stat_offsets_loaded,
725 &oes->rx_broadcast, &es->rx_broadcast);
726
727 i40e_stat_update48(hw, I40E_GLSW_GOTCH(idx), I40E_GLSW_GOTCL(idx),
728 veb->stat_offsets_loaded,
729 &oes->tx_bytes, &es->tx_bytes);
730 i40e_stat_update48(hw, I40E_GLSW_UPTCH(idx), I40E_GLSW_UPTCL(idx),
731 veb->stat_offsets_loaded,
732 &oes->tx_unicast, &es->tx_unicast);
733 i40e_stat_update48(hw, I40E_GLSW_MPTCH(idx), I40E_GLSW_MPTCL(idx),
734 veb->stat_offsets_loaded,
735 &oes->tx_multicast, &es->tx_multicast);
736 i40e_stat_update48(hw, I40E_GLSW_BPTCH(idx), I40E_GLSW_BPTCL(idx),
737 veb->stat_offsets_loaded,
738 &oes->tx_broadcast, &es->tx_broadcast);
739 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
740 i40e_stat_update48(hw, I40E_GLVEBTC_RPCH(i, idx),
741 I40E_GLVEBTC_RPCL(i, idx),
742 veb->stat_offsets_loaded,
743 &veb_oes->tc_rx_packets[i],
744 &veb_es->tc_rx_packets[i]);
745 i40e_stat_update48(hw, I40E_GLVEBTC_RBCH(i, idx),
746 I40E_GLVEBTC_RBCL(i, idx),
747 veb->stat_offsets_loaded,
748 &veb_oes->tc_rx_bytes[i],
749 &veb_es->tc_rx_bytes[i]);
750 i40e_stat_update48(hw, I40E_GLVEBTC_TPCH(i, idx),
751 I40E_GLVEBTC_TPCL(i, idx),
752 veb->stat_offsets_loaded,
753 &veb_oes->tc_tx_packets[i],
754 &veb_es->tc_tx_packets[i]);
755 i40e_stat_update48(hw, I40E_GLVEBTC_TBCH(i, idx),
756 I40E_GLVEBTC_TBCL(i, idx),
757 veb->stat_offsets_loaded,
758 &veb_oes->tc_tx_bytes[i],
759 &veb_es->tc_tx_bytes[i]);
760 }
761 veb->stat_offsets_loaded = true;
762}
763
764
765
766
767
768
769
770
771
772
773
774static void i40e_update_vsi_stats(struct i40e_vsi *vsi)
775{
776 struct i40e_pf *pf = vsi->back;
777 struct rtnl_link_stats64 *ons;
778 struct rtnl_link_stats64 *ns;
779 struct i40e_eth_stats *oes;
780 struct i40e_eth_stats *es;
781 u32 tx_restart, tx_busy;
782 struct i40e_ring *p;
783 u32 rx_page, rx_buf;
784 u64 bytes, packets;
785 unsigned int start;
786 u64 tx_linearize;
787 u64 tx_force_wb;
788 u64 rx_p, rx_b;
789 u64 tx_p, tx_b;
790 u16 q;
791
792 if (test_bit(__I40E_VSI_DOWN, vsi->state) ||
793 test_bit(__I40E_CONFIG_BUSY, pf->state))
794 return;
795
796 ns = i40e_get_vsi_stats_struct(vsi);
797 ons = &vsi->net_stats_offsets;
798 es = &vsi->eth_stats;
799 oes = &vsi->eth_stats_offsets;
800
801
802
803
804 rx_b = rx_p = 0;
805 tx_b = tx_p = 0;
806 tx_restart = tx_busy = tx_linearize = tx_force_wb = 0;
807 rx_page = 0;
808 rx_buf = 0;
809 rcu_read_lock();
810 for (q = 0; q < vsi->num_queue_pairs; q++) {
811
812 p = READ_ONCE(vsi->tx_rings[q]);
813
814 do {
815 start = u64_stats_fetch_begin_irq(&p->syncp);
816 packets = p->stats.packets;
817 bytes = p->stats.bytes;
818 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
819 tx_b += bytes;
820 tx_p += packets;
821 tx_restart += p->tx_stats.restart_queue;
822 tx_busy += p->tx_stats.tx_busy;
823 tx_linearize += p->tx_stats.tx_linearize;
824 tx_force_wb += p->tx_stats.tx_force_wb;
825
826
827 p = &p[1];
828 do {
829 start = u64_stats_fetch_begin_irq(&p->syncp);
830 packets = p->stats.packets;
831 bytes = p->stats.bytes;
832 } while (u64_stats_fetch_retry_irq(&p->syncp, start));
833 rx_b += bytes;
834 rx_p += packets;
835 rx_buf += p->rx_stats.alloc_buff_failed;
836 rx_page += p->rx_stats.alloc_page_failed;
837 }
838 rcu_read_unlock();
839 vsi->tx_restart = tx_restart;
840 vsi->tx_busy = tx_busy;
841 vsi->tx_linearize = tx_linearize;
842 vsi->tx_force_wb = tx_force_wb;
843 vsi->rx_page_failed = rx_page;
844 vsi->rx_buf_failed = rx_buf;
845
846 ns->rx_packets = rx_p;
847 ns->rx_bytes = rx_b;
848 ns->tx_packets = tx_p;
849 ns->tx_bytes = tx_b;
850
851
852 i40e_update_eth_stats(vsi);
853 ons->tx_errors = oes->tx_errors;
854 ns->tx_errors = es->tx_errors;
855 ons->multicast = oes->rx_multicast;
856 ns->multicast = es->rx_multicast;
857 ons->rx_dropped = oes->rx_discards;
858 ns->rx_dropped = es->rx_discards;
859 ons->tx_dropped = oes->tx_discards;
860 ns->tx_dropped = es->tx_discards;
861
862
863 if (vsi == pf->vsi[pf->lan_vsi]) {
864 ns->rx_crc_errors = pf->stats.crc_errors;
865 ns->rx_errors = pf->stats.crc_errors + pf->stats.illegal_bytes;
866 ns->rx_length_errors = pf->stats.rx_length_errors;
867 }
868}
869
870
871
872
873
874static void i40e_update_pf_stats(struct i40e_pf *pf)
875{
876 struct i40e_hw_port_stats *osd = &pf->stats_offsets;
877 struct i40e_hw_port_stats *nsd = &pf->stats;
878 struct i40e_hw *hw = &pf->hw;
879 u32 val;
880 int i;
881
882 i40e_stat_update48(hw, I40E_GLPRT_GORCH(hw->port),
883 I40E_GLPRT_GORCL(hw->port),
884 pf->stat_offsets_loaded,
885 &osd->eth.rx_bytes, &nsd->eth.rx_bytes);
886 i40e_stat_update48(hw, I40E_GLPRT_GOTCH(hw->port),
887 I40E_GLPRT_GOTCL(hw->port),
888 pf->stat_offsets_loaded,
889 &osd->eth.tx_bytes, &nsd->eth.tx_bytes);
890 i40e_stat_update32(hw, I40E_GLPRT_RDPC(hw->port),
891 pf->stat_offsets_loaded,
892 &osd->eth.rx_discards,
893 &nsd->eth.rx_discards);
894 i40e_stat_update48(hw, I40E_GLPRT_UPRCH(hw->port),
895 I40E_GLPRT_UPRCL(hw->port),
896 pf->stat_offsets_loaded,
897 &osd->eth.rx_unicast,
898 &nsd->eth.rx_unicast);
899 i40e_stat_update48(hw, I40E_GLPRT_MPRCH(hw->port),
900 I40E_GLPRT_MPRCL(hw->port),
901 pf->stat_offsets_loaded,
902 &osd->eth.rx_multicast,
903 &nsd->eth.rx_multicast);
904 i40e_stat_update48(hw, I40E_GLPRT_BPRCH(hw->port),
905 I40E_GLPRT_BPRCL(hw->port),
906 pf->stat_offsets_loaded,
907 &osd->eth.rx_broadcast,
908 &nsd->eth.rx_broadcast);
909 i40e_stat_update48(hw, I40E_GLPRT_UPTCH(hw->port),
910 I40E_GLPRT_UPTCL(hw->port),
911 pf->stat_offsets_loaded,
912 &osd->eth.tx_unicast,
913 &nsd->eth.tx_unicast);
914 i40e_stat_update48(hw, I40E_GLPRT_MPTCH(hw->port),
915 I40E_GLPRT_MPTCL(hw->port),
916 pf->stat_offsets_loaded,
917 &osd->eth.tx_multicast,
918 &nsd->eth.tx_multicast);
919 i40e_stat_update48(hw, I40E_GLPRT_BPTCH(hw->port),
920 I40E_GLPRT_BPTCL(hw->port),
921 pf->stat_offsets_loaded,
922 &osd->eth.tx_broadcast,
923 &nsd->eth.tx_broadcast);
924
925 i40e_stat_update32(hw, I40E_GLPRT_TDOLD(hw->port),
926 pf->stat_offsets_loaded,
927 &osd->tx_dropped_link_down,
928 &nsd->tx_dropped_link_down);
929
930 i40e_stat_update32(hw, I40E_GLPRT_CRCERRS(hw->port),
931 pf->stat_offsets_loaded,
932 &osd->crc_errors, &nsd->crc_errors);
933
934 i40e_stat_update32(hw, I40E_GLPRT_ILLERRC(hw->port),
935 pf->stat_offsets_loaded,
936 &osd->illegal_bytes, &nsd->illegal_bytes);
937
938 i40e_stat_update32(hw, I40E_GLPRT_MLFC(hw->port),
939 pf->stat_offsets_loaded,
940 &osd->mac_local_faults,
941 &nsd->mac_local_faults);
942 i40e_stat_update32(hw, I40E_GLPRT_MRFC(hw->port),
943 pf->stat_offsets_loaded,
944 &osd->mac_remote_faults,
945 &nsd->mac_remote_faults);
946
947 i40e_stat_update32(hw, I40E_GLPRT_RLEC(hw->port),
948 pf->stat_offsets_loaded,
949 &osd->rx_length_errors,
950 &nsd->rx_length_errors);
951
952 i40e_stat_update32(hw, I40E_GLPRT_LXONRXC(hw->port),
953 pf->stat_offsets_loaded,
954 &osd->link_xon_rx, &nsd->link_xon_rx);
955 i40e_stat_update32(hw, I40E_GLPRT_LXONTXC(hw->port),
956 pf->stat_offsets_loaded,
957 &osd->link_xon_tx, &nsd->link_xon_tx);
958 i40e_stat_update32(hw, I40E_GLPRT_LXOFFRXC(hw->port),
959 pf->stat_offsets_loaded,
960 &osd->link_xoff_rx, &nsd->link_xoff_rx);
961 i40e_stat_update32(hw, I40E_GLPRT_LXOFFTXC(hw->port),
962 pf->stat_offsets_loaded,
963 &osd->link_xoff_tx, &nsd->link_xoff_tx);
964
965 for (i = 0; i < 8; i++) {
966 i40e_stat_update32(hw, I40E_GLPRT_PXOFFRXC(hw->port, i),
967 pf->stat_offsets_loaded,
968 &osd->priority_xoff_rx[i],
969 &nsd->priority_xoff_rx[i]);
970 i40e_stat_update32(hw, I40E_GLPRT_PXONRXC(hw->port, i),
971 pf->stat_offsets_loaded,
972 &osd->priority_xon_rx[i],
973 &nsd->priority_xon_rx[i]);
974 i40e_stat_update32(hw, I40E_GLPRT_PXONTXC(hw->port, i),
975 pf->stat_offsets_loaded,
976 &osd->priority_xon_tx[i],
977 &nsd->priority_xon_tx[i]);
978 i40e_stat_update32(hw, I40E_GLPRT_PXOFFTXC(hw->port, i),
979 pf->stat_offsets_loaded,
980 &osd->priority_xoff_tx[i],
981 &nsd->priority_xoff_tx[i]);
982 i40e_stat_update32(hw,
983 I40E_GLPRT_RXON2OFFCNT(hw->port, i),
984 pf->stat_offsets_loaded,
985 &osd->priority_xon_2_xoff[i],
986 &nsd->priority_xon_2_xoff[i]);
987 }
988
989 i40e_stat_update48(hw, I40E_GLPRT_PRC64H(hw->port),
990 I40E_GLPRT_PRC64L(hw->port),
991 pf->stat_offsets_loaded,
992 &osd->rx_size_64, &nsd->rx_size_64);
993 i40e_stat_update48(hw, I40E_GLPRT_PRC127H(hw->port),
994 I40E_GLPRT_PRC127L(hw->port),
995 pf->stat_offsets_loaded,
996 &osd->rx_size_127, &nsd->rx_size_127);
997 i40e_stat_update48(hw, I40E_GLPRT_PRC255H(hw->port),
998 I40E_GLPRT_PRC255L(hw->port),
999 pf->stat_offsets_loaded,
1000 &osd->rx_size_255, &nsd->rx_size_255);
1001 i40e_stat_update48(hw, I40E_GLPRT_PRC511H(hw->port),
1002 I40E_GLPRT_PRC511L(hw->port),
1003 pf->stat_offsets_loaded,
1004 &osd->rx_size_511, &nsd->rx_size_511);
1005 i40e_stat_update48(hw, I40E_GLPRT_PRC1023H(hw->port),
1006 I40E_GLPRT_PRC1023L(hw->port),
1007 pf->stat_offsets_loaded,
1008 &osd->rx_size_1023, &nsd->rx_size_1023);
1009 i40e_stat_update48(hw, I40E_GLPRT_PRC1522H(hw->port),
1010 I40E_GLPRT_PRC1522L(hw->port),
1011 pf->stat_offsets_loaded,
1012 &osd->rx_size_1522, &nsd->rx_size_1522);
1013 i40e_stat_update48(hw, I40E_GLPRT_PRC9522H(hw->port),
1014 I40E_GLPRT_PRC9522L(hw->port),
1015 pf->stat_offsets_loaded,
1016 &osd->rx_size_big, &nsd->rx_size_big);
1017
1018 i40e_stat_update48(hw, I40E_GLPRT_PTC64H(hw->port),
1019 I40E_GLPRT_PTC64L(hw->port),
1020 pf->stat_offsets_loaded,
1021 &osd->tx_size_64, &nsd->tx_size_64);
1022 i40e_stat_update48(hw, I40E_GLPRT_PTC127H(hw->port),
1023 I40E_GLPRT_PTC127L(hw->port),
1024 pf->stat_offsets_loaded,
1025 &osd->tx_size_127, &nsd->tx_size_127);
1026 i40e_stat_update48(hw, I40E_GLPRT_PTC255H(hw->port),
1027 I40E_GLPRT_PTC255L(hw->port),
1028 pf->stat_offsets_loaded,
1029 &osd->tx_size_255, &nsd->tx_size_255);
1030 i40e_stat_update48(hw, I40E_GLPRT_PTC511H(hw->port),
1031 I40E_GLPRT_PTC511L(hw->port),
1032 pf->stat_offsets_loaded,
1033 &osd->tx_size_511, &nsd->tx_size_511);
1034 i40e_stat_update48(hw, I40E_GLPRT_PTC1023H(hw->port),
1035 I40E_GLPRT_PTC1023L(hw->port),
1036 pf->stat_offsets_loaded,
1037 &osd->tx_size_1023, &nsd->tx_size_1023);
1038 i40e_stat_update48(hw, I40E_GLPRT_PTC1522H(hw->port),
1039 I40E_GLPRT_PTC1522L(hw->port),
1040 pf->stat_offsets_loaded,
1041 &osd->tx_size_1522, &nsd->tx_size_1522);
1042 i40e_stat_update48(hw, I40E_GLPRT_PTC9522H(hw->port),
1043 I40E_GLPRT_PTC9522L(hw->port),
1044 pf->stat_offsets_loaded,
1045 &osd->tx_size_big, &nsd->tx_size_big);
1046
1047 i40e_stat_update32(hw, I40E_GLPRT_RUC(hw->port),
1048 pf->stat_offsets_loaded,
1049 &osd->rx_undersize, &nsd->rx_undersize);
1050 i40e_stat_update32(hw, I40E_GLPRT_RFC(hw->port),
1051 pf->stat_offsets_loaded,
1052 &osd->rx_fragments, &nsd->rx_fragments);
1053 i40e_stat_update32(hw, I40E_GLPRT_ROC(hw->port),
1054 pf->stat_offsets_loaded,
1055 &osd->rx_oversize, &nsd->rx_oversize);
1056 i40e_stat_update32(hw, I40E_GLPRT_RJC(hw->port),
1057 pf->stat_offsets_loaded,
1058 &osd->rx_jabber, &nsd->rx_jabber);
1059
1060
1061 i40e_stat_update_and_clear32(hw,
1062 I40E_GLQF_PCNT(I40E_FD_ATR_STAT_IDX(hw->pf_id)),
1063 &nsd->fd_atr_match);
1064 i40e_stat_update_and_clear32(hw,
1065 I40E_GLQF_PCNT(I40E_FD_SB_STAT_IDX(hw->pf_id)),
1066 &nsd->fd_sb_match);
1067 i40e_stat_update_and_clear32(hw,
1068 I40E_GLQF_PCNT(I40E_FD_ATR_TUNNEL_STAT_IDX(hw->pf_id)),
1069 &nsd->fd_atr_tunnel_match);
1070
1071 val = rd32(hw, I40E_PRTPM_EEE_STAT);
1072 nsd->tx_lpi_status =
1073 (val & I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_MASK) >>
1074 I40E_PRTPM_EEE_STAT_TX_LPI_STATUS_SHIFT;
1075 nsd->rx_lpi_status =
1076 (val & I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_MASK) >>
1077 I40E_PRTPM_EEE_STAT_RX_LPI_STATUS_SHIFT;
1078 i40e_stat_update32(hw, I40E_PRTPM_TLPIC,
1079 pf->stat_offsets_loaded,
1080 &osd->tx_lpi_count, &nsd->tx_lpi_count);
1081 i40e_stat_update32(hw, I40E_PRTPM_RLPIC,
1082 pf->stat_offsets_loaded,
1083 &osd->rx_lpi_count, &nsd->rx_lpi_count);
1084
1085 if (pf->flags & I40E_FLAG_FD_SB_ENABLED &&
1086 !test_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
1087 nsd->fd_sb_status = true;
1088 else
1089 nsd->fd_sb_status = false;
1090
1091 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED &&
1092 !test_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
1093 nsd->fd_atr_status = true;
1094 else
1095 nsd->fd_atr_status = false;
1096
1097 pf->stat_offsets_loaded = true;
1098}
1099
1100
1101
1102
1103
1104
1105
1106void i40e_update_stats(struct i40e_vsi *vsi)
1107{
1108 struct i40e_pf *pf = vsi->back;
1109
1110 if (vsi == pf->vsi[pf->lan_vsi])
1111 i40e_update_pf_stats(pf);
1112
1113 i40e_update_vsi_stats(vsi);
1114}
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124static struct i40e_mac_filter *i40e_find_filter(struct i40e_vsi *vsi,
1125 const u8 *macaddr, s16 vlan)
1126{
1127 struct i40e_mac_filter *f;
1128 u64 key;
1129
1130 if (!vsi || !macaddr)
1131 return NULL;
1132
1133 key = i40e_addr_to_hkey(macaddr);
1134 hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) {
1135 if ((ether_addr_equal(macaddr, f->macaddr)) &&
1136 (vlan == f->vlan))
1137 return f;
1138 }
1139 return NULL;
1140}
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150struct i40e_mac_filter *i40e_find_mac(struct i40e_vsi *vsi, const u8 *macaddr)
1151{
1152 struct i40e_mac_filter *f;
1153 u64 key;
1154
1155 if (!vsi || !macaddr)
1156 return NULL;
1157
1158 key = i40e_addr_to_hkey(macaddr);
1159 hash_for_each_possible(vsi->mac_filter_hash, f, hlist, key) {
1160 if ((ether_addr_equal(macaddr, f->macaddr)))
1161 return f;
1162 }
1163 return NULL;
1164}
1165
1166
1167
1168
1169
1170
1171
1172bool i40e_is_vsi_in_vlan(struct i40e_vsi *vsi)
1173{
1174
1175 if (vsi->info.pvid)
1176 return true;
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198 return vsi->has_vlan_filter;
1199}
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230static int i40e_correct_mac_vlan_filters(struct i40e_vsi *vsi,
1231 struct hlist_head *tmp_add_list,
1232 struct hlist_head *tmp_del_list,
1233 int vlan_filters)
1234{
1235 s16 pvid = le16_to_cpu(vsi->info.pvid);
1236 struct i40e_mac_filter *f, *add_head;
1237 struct i40e_new_mac_filter *new;
1238 struct hlist_node *h;
1239 int bkt, new_vlan;
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256 hlist_for_each_entry(new, tmp_add_list, hlist) {
1257 if (pvid && new->f->vlan != pvid)
1258 new->f->vlan = pvid;
1259 else if (vlan_filters && new->f->vlan == I40E_VLAN_ANY)
1260 new->f->vlan = 0;
1261 else if (!vlan_filters && new->f->vlan == 0)
1262 new->f->vlan = I40E_VLAN_ANY;
1263 }
1264
1265
1266 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1267
1268
1269
1270
1271
1272 if ((pvid && f->vlan != pvid) ||
1273 (vlan_filters && f->vlan == I40E_VLAN_ANY) ||
1274 (!vlan_filters && f->vlan == 0)) {
1275
1276 if (pvid)
1277 new_vlan = pvid;
1278 else if (vlan_filters)
1279 new_vlan = 0;
1280 else
1281 new_vlan = I40E_VLAN_ANY;
1282
1283
1284 add_head = i40e_add_filter(vsi, f->macaddr, new_vlan);
1285 if (!add_head)
1286 return -ENOMEM;
1287
1288
1289 new = kzalloc(sizeof(*new), GFP_ATOMIC);
1290 if (!new)
1291 return -ENOMEM;
1292
1293 new->f = add_head;
1294 new->state = add_head->state;
1295
1296
1297 hlist_add_head(&new->hlist, tmp_add_list);
1298
1299
1300 f->state = I40E_FILTER_REMOVE;
1301 hash_del(&f->hlist);
1302 hlist_add_head(&f->hlist, tmp_del_list);
1303 }
1304 }
1305
1306 vsi->has_vlan_filter = !!vlan_filters;
1307
1308 return 0;
1309}
1310
1311
1312
1313
1314
1315
1316
1317
1318
1319static void i40e_rm_default_mac_filter(struct i40e_vsi *vsi, u8 *macaddr)
1320{
1321 struct i40e_aqc_remove_macvlan_element_data element;
1322 struct i40e_pf *pf = vsi->back;
1323
1324
1325 if (vsi->type != I40E_VSI_MAIN)
1326 return;
1327
1328 memset(&element, 0, sizeof(element));
1329 ether_addr_copy(element.mac_addr, macaddr);
1330 element.vlan_tag = 0;
1331
1332 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
1333 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1334
1335 memset(&element, 0, sizeof(element));
1336 ether_addr_copy(element.mac_addr, macaddr);
1337 element.vlan_tag = 0;
1338
1339 element.flags = I40E_AQC_MACVLAN_DEL_PERFECT_MATCH |
1340 I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
1341 i40e_aq_remove_macvlan(&pf->hw, vsi->seid, &element, 1, NULL);
1342}
1343
1344
1345
1346
1347
1348
1349
1350
1351
1352
1353
1354
1355struct i40e_mac_filter *i40e_add_filter(struct i40e_vsi *vsi,
1356 const u8 *macaddr, s16 vlan)
1357{
1358 struct i40e_mac_filter *f;
1359 u64 key;
1360
1361 if (!vsi || !macaddr)
1362 return NULL;
1363
1364 f = i40e_find_filter(vsi, macaddr, vlan);
1365 if (!f) {
1366 f = kzalloc(sizeof(*f), GFP_ATOMIC);
1367 if (!f)
1368 return NULL;
1369
1370
1371
1372
1373 if (vlan >= 0)
1374 vsi->has_vlan_filter = true;
1375
1376 ether_addr_copy(f->macaddr, macaddr);
1377 f->vlan = vlan;
1378 f->state = I40E_FILTER_NEW;
1379 INIT_HLIST_NODE(&f->hlist);
1380
1381 key = i40e_addr_to_hkey(macaddr);
1382 hash_add(vsi->mac_filter_hash, &f->hlist, key);
1383
1384 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1385 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state);
1386 }
1387
1388
1389
1390
1391
1392
1393
1394
1395
1396 if (f->state == I40E_FILTER_REMOVE)
1397 f->state = I40E_FILTER_ACTIVE;
1398
1399 return f;
1400}
1401
1402
1403
1404
1405
1406
1407
1408
1409
1410
1411
1412
1413
1414
1415
1416
1417void __i40e_del_filter(struct i40e_vsi *vsi, struct i40e_mac_filter *f)
1418{
1419 if (!f)
1420 return;
1421
1422
1423
1424
1425
1426 if ((f->state == I40E_FILTER_FAILED) ||
1427 (f->state == I40E_FILTER_NEW)) {
1428 hash_del(&f->hlist);
1429 kfree(f);
1430 } else {
1431 f->state = I40E_FILTER_REMOVE;
1432 }
1433
1434 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1435 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->state);
1436}
1437
1438
1439
1440
1441
1442
1443
1444
1445
1446
1447
1448
1449
1450void i40e_del_filter(struct i40e_vsi *vsi, const u8 *macaddr, s16 vlan)
1451{
1452 struct i40e_mac_filter *f;
1453
1454 if (!vsi || !macaddr)
1455 return;
1456
1457 f = i40e_find_filter(vsi, macaddr, vlan);
1458 __i40e_del_filter(vsi, f);
1459}
1460
1461
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471
1472
1473struct i40e_mac_filter *i40e_add_mac_filter(struct i40e_vsi *vsi,
1474 const u8 *macaddr)
1475{
1476 struct i40e_mac_filter *f, *add = NULL;
1477 struct hlist_node *h;
1478 int bkt;
1479
1480 if (vsi->info.pvid)
1481 return i40e_add_filter(vsi, macaddr,
1482 le16_to_cpu(vsi->info.pvid));
1483
1484 if (!i40e_is_vsi_in_vlan(vsi))
1485 return i40e_add_filter(vsi, macaddr, I40E_VLAN_ANY);
1486
1487 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1488 if (f->state == I40E_FILTER_REMOVE)
1489 continue;
1490 add = i40e_add_filter(vsi, macaddr, f->vlan);
1491 if (!add)
1492 return NULL;
1493 }
1494
1495 return add;
1496}
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508int i40e_del_mac_filter(struct i40e_vsi *vsi, const u8 *macaddr)
1509{
1510 struct i40e_mac_filter *f;
1511 struct hlist_node *h;
1512 bool found = false;
1513 int bkt;
1514
1515 WARN(!spin_is_locked(&vsi->mac_filter_hash_lock),
1516 "Missing mac_filter_hash_lock\n");
1517 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
1518 if (ether_addr_equal(macaddr, f->macaddr)) {
1519 __i40e_del_filter(vsi, f);
1520 found = true;
1521 }
1522 }
1523
1524 if (found)
1525 return 0;
1526 else
1527 return -ENOENT;
1528}
1529
1530
1531
1532
1533
1534
1535
1536
1537static int i40e_set_mac(struct net_device *netdev, void *p)
1538{
1539 struct i40e_netdev_priv *np = netdev_priv(netdev);
1540 struct i40e_vsi *vsi = np->vsi;
1541 struct i40e_pf *pf = vsi->back;
1542 struct i40e_hw *hw = &pf->hw;
1543 struct sockaddr *addr = p;
1544
1545 if (!is_valid_ether_addr(addr->sa_data))
1546 return -EADDRNOTAVAIL;
1547
1548 if (ether_addr_equal(netdev->dev_addr, addr->sa_data)) {
1549 netdev_info(netdev, "already using mac address %pM\n",
1550 addr->sa_data);
1551 return 0;
1552 }
1553
1554 if (test_bit(__I40E_VSI_DOWN, vsi->back->state) ||
1555 test_bit(__I40E_RESET_RECOVERY_PENDING, vsi->back->state))
1556 return -EADDRNOTAVAIL;
1557
1558 if (ether_addr_equal(hw->mac.addr, addr->sa_data))
1559 netdev_info(netdev, "returning to hw mac address %pM\n",
1560 hw->mac.addr);
1561 else
1562 netdev_info(netdev, "set new mac address %pM\n", addr->sa_data);
1563
1564
1565
1566
1567
1568
1569
1570 ether_addr_copy(netdev->dev_addr, addr->sa_data);
1571
1572 spin_lock_bh(&vsi->mac_filter_hash_lock);
1573 i40e_del_mac_filter(vsi, netdev->dev_addr);
1574 i40e_add_mac_filter(vsi, addr->sa_data);
1575 spin_unlock_bh(&vsi->mac_filter_hash_lock);
1576 if (vsi->type == I40E_VSI_MAIN) {
1577 i40e_status ret;
1578
1579 ret = i40e_aq_mac_address_write(&vsi->back->hw,
1580 I40E_AQC_WRITE_TYPE_LAA_WOL,
1581 addr->sa_data, NULL);
1582 if (ret)
1583 netdev_info(netdev, "Ignoring error from firmware on LAA update, status %s, AQ ret %s\n",
1584 i40e_stat_str(hw, ret),
1585 i40e_aq_str(hw, hw->aq.asq_last_status));
1586 }
1587
1588
1589
1590
1591 i40e_service_event_schedule(vsi->back);
1592 return 0;
1593}
1594
1595
1596
1597
1598
1599
1600static int i40e_config_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
1601 u8 *lut, u16 lut_size)
1602{
1603 struct i40e_pf *pf = vsi->back;
1604 struct i40e_hw *hw = &pf->hw;
1605 int ret = 0;
1606
1607 if (seed) {
1608 struct i40e_aqc_get_set_rss_key_data *seed_dw =
1609 (struct i40e_aqc_get_set_rss_key_data *)seed;
1610 ret = i40e_aq_set_rss_key(hw, vsi->id, seed_dw);
1611 if (ret) {
1612 dev_info(&pf->pdev->dev,
1613 "Cannot set RSS key, err %s aq_err %s\n",
1614 i40e_stat_str(hw, ret),
1615 i40e_aq_str(hw, hw->aq.asq_last_status));
1616 return ret;
1617 }
1618 }
1619 if (lut) {
1620 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
1621
1622 ret = i40e_aq_set_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
1623 if (ret) {
1624 dev_info(&pf->pdev->dev,
1625 "Cannot set RSS lut, err %s aq_err %s\n",
1626 i40e_stat_str(hw, ret),
1627 i40e_aq_str(hw, hw->aq.asq_last_status));
1628 return ret;
1629 }
1630 }
1631 return ret;
1632}
1633
1634
1635
1636
1637
1638static int i40e_vsi_config_rss(struct i40e_vsi *vsi)
1639{
1640 struct i40e_pf *pf = vsi->back;
1641 u8 seed[I40E_HKEY_ARRAY_SIZE];
1642 u8 *lut;
1643 int ret;
1644
1645 if (!(pf->hw_features & I40E_HW_RSS_AQ_CAPABLE))
1646 return 0;
1647 if (!vsi->rss_size)
1648 vsi->rss_size = min_t(int, pf->alloc_rss_size,
1649 vsi->num_queue_pairs);
1650 if (!vsi->rss_size)
1651 return -EINVAL;
1652 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
1653 if (!lut)
1654 return -ENOMEM;
1655
1656
1657
1658
1659 if (vsi->rss_lut_user)
1660 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
1661 else
1662 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
1663 if (vsi->rss_hkey_user)
1664 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
1665 else
1666 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
1667 ret = i40e_config_rss_aq(vsi, seed, lut, vsi->rss_table_size);
1668 kfree(lut);
1669 return ret;
1670}
1671
1672
1673
1674
1675
1676
1677
1678
1679
1680static int i40e_vsi_setup_queue_map_mqprio(struct i40e_vsi *vsi,
1681 struct i40e_vsi_context *ctxt,
1682 u8 enabled_tc)
1683{
1684 u16 qcount = 0, max_qcount, qmap, sections = 0;
1685 int i, override_q, pow, num_qps, ret;
1686 u8 netdev_tc = 0, offset = 0;
1687
1688 if (vsi->type != I40E_VSI_MAIN)
1689 return -EINVAL;
1690 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1691 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1692 vsi->tc_config.numtc = vsi->mqprio_qopt.qopt.num_tc;
1693 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1694 num_qps = vsi->mqprio_qopt.qopt.count[0];
1695
1696
1697 pow = ilog2(num_qps);
1698 if (!is_power_of_2(num_qps))
1699 pow++;
1700 qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1701 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1702
1703
1704 max_qcount = vsi->mqprio_qopt.qopt.count[0];
1705 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1706
1707 if (vsi->tc_config.enabled_tc & BIT(i)) {
1708 offset = vsi->mqprio_qopt.qopt.offset[i];
1709 qcount = vsi->mqprio_qopt.qopt.count[i];
1710 if (qcount > max_qcount)
1711 max_qcount = qcount;
1712 vsi->tc_config.tc_info[i].qoffset = offset;
1713 vsi->tc_config.tc_info[i].qcount = qcount;
1714 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1715 } else {
1716
1717
1718
1719
1720 vsi->tc_config.tc_info[i].qoffset = 0;
1721 vsi->tc_config.tc_info[i].qcount = 1;
1722 vsi->tc_config.tc_info[i].netdev_tc = 0;
1723 }
1724 }
1725
1726
1727 vsi->num_queue_pairs = offset + qcount;
1728
1729
1730 ctxt->info.tc_mapping[0] = cpu_to_le16(qmap);
1731 ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1732 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1733 ctxt->info.valid_sections |= cpu_to_le16(sections);
1734
1735
1736 vsi->rss_size = max_qcount;
1737 ret = i40e_vsi_config_rss(vsi);
1738 if (ret) {
1739 dev_info(&vsi->back->pdev->dev,
1740 "Failed to reconfig rss for num_queues (%u)\n",
1741 max_qcount);
1742 return ret;
1743 }
1744 vsi->reconfig_rss = true;
1745 dev_dbg(&vsi->back->pdev->dev,
1746 "Reconfigured rss with num_queues (%u)\n", max_qcount);
1747
1748
1749
1750
1751 override_q = vsi->mqprio_qopt.qopt.count[0];
1752 if (override_q && override_q < vsi->num_queue_pairs) {
1753 vsi->cnt_q_avail = vsi->num_queue_pairs - override_q;
1754 vsi->next_base_queue = override_q;
1755 }
1756 return 0;
1757}
1758
1759
1760
1761
1762
1763
1764
1765
1766
1767
1768static void i40e_vsi_setup_queue_map(struct i40e_vsi *vsi,
1769 struct i40e_vsi_context *ctxt,
1770 u8 enabled_tc,
1771 bool is_add)
1772{
1773 struct i40e_pf *pf = vsi->back;
1774 u16 sections = 0;
1775 u8 netdev_tc = 0;
1776 u16 numtc = 1;
1777 u16 qcount;
1778 u8 offset;
1779 u16 qmap;
1780 int i;
1781 u16 num_tc_qps = 0;
1782
1783 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
1784 offset = 0;
1785
1786
1787 num_tc_qps = vsi->alloc_queue_pairs;
1788 if (enabled_tc && (vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
1789
1790 for (i = 0, numtc = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1791 if (enabled_tc & BIT(i))
1792 numtc++;
1793 }
1794 if (!numtc) {
1795 dev_warn(&pf->pdev->dev, "DCB is enabled but no TC enabled, forcing TC0\n");
1796 numtc = 1;
1797 }
1798 num_tc_qps = num_tc_qps / numtc;
1799 num_tc_qps = min_t(int, num_tc_qps,
1800 i40e_pf_get_max_q_per_tc(pf));
1801 }
1802
1803 vsi->tc_config.numtc = numtc;
1804 vsi->tc_config.enabled_tc = enabled_tc ? enabled_tc : 1;
1805
1806
1807 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1808 num_tc_qps = min_t(int, num_tc_qps, pf->num_lan_msix);
1809
1810
1811 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
1812
1813 if (vsi->tc_config.enabled_tc & BIT(i)) {
1814
1815 int pow, num_qps;
1816
1817 switch (vsi->type) {
1818 case I40E_VSI_MAIN:
1819 if (!(pf->flags & (I40E_FLAG_FD_SB_ENABLED |
1820 I40E_FLAG_FD_ATR_ENABLED)) ||
1821 vsi->tc_config.enabled_tc != 1) {
1822 qcount = min_t(int, pf->alloc_rss_size,
1823 num_tc_qps);
1824 break;
1825 }
1826 case I40E_VSI_FDIR:
1827 case I40E_VSI_SRIOV:
1828 case I40E_VSI_VMDQ2:
1829 default:
1830 qcount = num_tc_qps;
1831 WARN_ON(i != 0);
1832 break;
1833 }
1834 vsi->tc_config.tc_info[i].qoffset = offset;
1835 vsi->tc_config.tc_info[i].qcount = qcount;
1836
1837
1838 num_qps = qcount;
1839 pow = 0;
1840 while (num_qps && (BIT_ULL(pow) < qcount)) {
1841 pow++;
1842 num_qps >>= 1;
1843 }
1844
1845 vsi->tc_config.tc_info[i].netdev_tc = netdev_tc++;
1846 qmap =
1847 (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
1848 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
1849
1850 offset += qcount;
1851 } else {
1852
1853
1854
1855
1856 vsi->tc_config.tc_info[i].qoffset = 0;
1857 vsi->tc_config.tc_info[i].qcount = 1;
1858 vsi->tc_config.tc_info[i].netdev_tc = 0;
1859
1860 qmap = 0;
1861 }
1862 ctxt->info.tc_mapping[i] = cpu_to_le16(qmap);
1863 }
1864
1865
1866 vsi->num_queue_pairs = offset;
1867 if ((vsi->type == I40E_VSI_MAIN) && (numtc == 1)) {
1868 if (vsi->req_queue_pairs > 0)
1869 vsi->num_queue_pairs = vsi->req_queue_pairs;
1870 else if (pf->flags & I40E_FLAG_MSIX_ENABLED)
1871 vsi->num_queue_pairs = pf->num_lan_msix;
1872 }
1873
1874
1875 if (is_add) {
1876 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
1877
1878 ctxt->info.up_enable_bits = enabled_tc;
1879 }
1880 if (vsi->type == I40E_VSI_SRIOV) {
1881 ctxt->info.mapping_flags |=
1882 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_NONCONTIG);
1883 for (i = 0; i < vsi->num_queue_pairs; i++)
1884 ctxt->info.queue_mapping[i] =
1885 cpu_to_le16(vsi->base_queue + i);
1886 } else {
1887 ctxt->info.mapping_flags |=
1888 cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
1889 ctxt->info.queue_mapping[0] = cpu_to_le16(vsi->base_queue);
1890 }
1891 ctxt->info.valid_sections |= cpu_to_le16(sections);
1892}
1893
1894
1895
1896
1897
1898
1899
1900
1901
1902static int i40e_addr_sync(struct net_device *netdev, const u8 *addr)
1903{
1904 struct i40e_netdev_priv *np = netdev_priv(netdev);
1905 struct i40e_vsi *vsi = np->vsi;
1906
1907 if (i40e_add_mac_filter(vsi, addr))
1908 return 0;
1909 else
1910 return -ENOMEM;
1911}
1912
1913
1914
1915
1916
1917
1918
1919
1920
1921static int i40e_addr_unsync(struct net_device *netdev, const u8 *addr)
1922{
1923 struct i40e_netdev_priv *np = netdev_priv(netdev);
1924 struct i40e_vsi *vsi = np->vsi;
1925
1926
1927
1928
1929
1930
1931 if (ether_addr_equal(addr, netdev->dev_addr))
1932 return 0;
1933
1934 i40e_del_mac_filter(vsi, addr);
1935
1936 return 0;
1937}
1938
1939
1940
1941
1942
1943static void i40e_set_rx_mode(struct net_device *netdev)
1944{
1945 struct i40e_netdev_priv *np = netdev_priv(netdev);
1946 struct i40e_vsi *vsi = np->vsi;
1947
1948 spin_lock_bh(&vsi->mac_filter_hash_lock);
1949
1950 __dev_uc_sync(netdev, i40e_addr_sync, i40e_addr_unsync);
1951 __dev_mc_sync(netdev, i40e_addr_sync, i40e_addr_unsync);
1952
1953 spin_unlock_bh(&vsi->mac_filter_hash_lock);
1954
1955
1956 if (vsi->current_netdev_flags != vsi->netdev->flags) {
1957 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
1958 set_bit(__I40E_MACVLAN_SYNC_PENDING, vsi->back->state);
1959 }
1960}
1961
1962
1963
1964
1965
1966
1967
1968
1969
1970static void i40e_undo_del_filter_entries(struct i40e_vsi *vsi,
1971 struct hlist_head *from)
1972{
1973 struct i40e_mac_filter *f;
1974 struct hlist_node *h;
1975
1976 hlist_for_each_entry_safe(f, h, from, hlist) {
1977 u64 key = i40e_addr_to_hkey(f->macaddr);
1978
1979
1980 hlist_del(&f->hlist);
1981 hash_add(vsi->mac_filter_hash, &f->hlist, key);
1982 }
1983}
1984
1985
1986
1987
1988
1989
1990
1991
1992
1993static void i40e_undo_add_filter_entries(struct i40e_vsi *vsi,
1994 struct hlist_head *from)
1995{
1996 struct i40e_new_mac_filter *new;
1997 struct hlist_node *h;
1998
1999 hlist_for_each_entry_safe(new, h, from, hlist) {
2000
2001 hlist_del(&new->hlist);
2002 kfree(new);
2003 }
2004}
2005
2006
2007
2008
2009
2010
2011
2012
2013
2014static
2015struct i40e_new_mac_filter *i40e_next_filter(struct i40e_new_mac_filter *next)
2016{
2017 hlist_for_each_entry_continue(next, hlist) {
2018 if (!is_broadcast_ether_addr(next->f->macaddr))
2019 return next;
2020 }
2021
2022 return NULL;
2023}
2024
2025
2026
2027
2028
2029
2030
2031
2032
2033
2034
2035static int
2036i40e_update_filter_state(int count,
2037 struct i40e_aqc_add_macvlan_element_data *add_list,
2038 struct i40e_new_mac_filter *add_head)
2039{
2040 int retval = 0;
2041 int i;
2042
2043 for (i = 0; i < count; i++) {
2044
2045
2046
2047
2048
2049
2050 if (add_list[i].match_method == I40E_AQC_MM_ERR_NO_RES) {
2051 add_head->state = I40E_FILTER_FAILED;
2052 } else {
2053 add_head->state = I40E_FILTER_ACTIVE;
2054 retval++;
2055 }
2056
2057 add_head = i40e_next_filter(add_head);
2058 if (!add_head)
2059 break;
2060 }
2061
2062 return retval;
2063}
2064
2065
2066
2067
2068
2069
2070
2071
2072
2073
2074
2075
2076
2077
2078static
2079void i40e_aqc_del_filters(struct i40e_vsi *vsi, const char *vsi_name,
2080 struct i40e_aqc_remove_macvlan_element_data *list,
2081 int num_del, int *retval)
2082{
2083 struct i40e_hw *hw = &vsi->back->hw;
2084 i40e_status aq_ret;
2085 int aq_err;
2086
2087 aq_ret = i40e_aq_remove_macvlan(hw, vsi->seid, list, num_del, NULL);
2088 aq_err = hw->aq.asq_last_status;
2089
2090
2091 if (aq_ret && !(aq_err == I40E_AQ_RC_ENOENT)) {
2092 *retval = -EIO;
2093 dev_info(&vsi->back->pdev->dev,
2094 "ignoring delete macvlan error on %s, err %s, aq_err %s\n",
2095 vsi_name, i40e_stat_str(hw, aq_ret),
2096 i40e_aq_str(hw, aq_err));
2097 }
2098}
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112static
2113void i40e_aqc_add_filters(struct i40e_vsi *vsi, const char *vsi_name,
2114 struct i40e_aqc_add_macvlan_element_data *list,
2115 struct i40e_new_mac_filter *add_head,
2116 int num_add)
2117{
2118 struct i40e_hw *hw = &vsi->back->hw;
2119 int aq_err, fcnt;
2120
2121 i40e_aq_add_macvlan(hw, vsi->seid, list, num_add, NULL);
2122 aq_err = hw->aq.asq_last_status;
2123 fcnt = i40e_update_filter_state(num_add, list, add_head);
2124
2125 if (fcnt != num_add) {
2126 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2127 dev_warn(&vsi->back->pdev->dev,
2128 "Error %s adding RX filters on %s, promiscuous mode forced on\n",
2129 i40e_aq_str(hw, aq_err),
2130 vsi_name);
2131 }
2132}
2133
2134
2135
2136
2137
2138
2139
2140
2141
2142
2143
2144
2145static i40e_status
2146i40e_aqc_broadcast_filter(struct i40e_vsi *vsi, const char *vsi_name,
2147 struct i40e_mac_filter *f)
2148{
2149 bool enable = f->state == I40E_FILTER_NEW;
2150 struct i40e_hw *hw = &vsi->back->hw;
2151 i40e_status aq_ret;
2152
2153 if (f->vlan == I40E_VLAN_ANY) {
2154 aq_ret = i40e_aq_set_vsi_broadcast(hw,
2155 vsi->seid,
2156 enable,
2157 NULL);
2158 } else {
2159 aq_ret = i40e_aq_set_vsi_bc_promisc_on_vlan(hw,
2160 vsi->seid,
2161 enable,
2162 f->vlan,
2163 NULL);
2164 }
2165
2166 if (aq_ret) {
2167 set_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2168 dev_warn(&vsi->back->pdev->dev,
2169 "Error %s, forcing overflow promiscuous on %s\n",
2170 i40e_aq_str(hw, hw->aq.asq_last_status),
2171 vsi_name);
2172 }
2173
2174 return aq_ret;
2175}
2176
2177
2178
2179
2180
2181
2182
2183
2184
2185
2186static int i40e_set_promiscuous(struct i40e_pf *pf, bool promisc)
2187{
2188 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
2189 struct i40e_hw *hw = &pf->hw;
2190 i40e_status aq_ret;
2191
2192 if (vsi->type == I40E_VSI_MAIN &&
2193 pf->lan_veb != I40E_NO_VEB &&
2194 !(pf->flags & I40E_FLAG_MFP_ENABLED)) {
2195
2196
2197
2198
2199
2200 if (promisc)
2201 aq_ret = i40e_aq_set_default_vsi(hw,
2202 vsi->seid,
2203 NULL);
2204 else
2205 aq_ret = i40e_aq_clear_default_vsi(hw,
2206 vsi->seid,
2207 NULL);
2208 if (aq_ret) {
2209 dev_info(&pf->pdev->dev,
2210 "Set default VSI failed, err %s, aq_err %s\n",
2211 i40e_stat_str(hw, aq_ret),
2212 i40e_aq_str(hw, hw->aq.asq_last_status));
2213 }
2214 } else {
2215 aq_ret = i40e_aq_set_vsi_unicast_promiscuous(
2216 hw,
2217 vsi->seid,
2218 promisc, NULL,
2219 true);
2220 if (aq_ret) {
2221 dev_info(&pf->pdev->dev,
2222 "set unicast promisc failed, err %s, aq_err %s\n",
2223 i40e_stat_str(hw, aq_ret),
2224 i40e_aq_str(hw, hw->aq.asq_last_status));
2225 }
2226 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(
2227 hw,
2228 vsi->seid,
2229 promisc, NULL);
2230 if (aq_ret) {
2231 dev_info(&pf->pdev->dev,
2232 "set multicast promisc failed, err %s, aq_err %s\n",
2233 i40e_stat_str(hw, aq_ret),
2234 i40e_aq_str(hw, hw->aq.asq_last_status));
2235 }
2236 }
2237
2238 if (!aq_ret)
2239 pf->cur_promisc = promisc;
2240
2241 return aq_ret;
2242}
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252int i40e_sync_vsi_filters(struct i40e_vsi *vsi)
2253{
2254 struct hlist_head tmp_add_list, tmp_del_list;
2255 struct i40e_mac_filter *f;
2256 struct i40e_new_mac_filter *new, *add_head = NULL;
2257 struct i40e_hw *hw = &vsi->back->hw;
2258 bool old_overflow, new_overflow;
2259 unsigned int failed_filters = 0;
2260 unsigned int vlan_filters = 0;
2261 char vsi_name[16] = "PF";
2262 int filter_list_len = 0;
2263 i40e_status aq_ret = 0;
2264 u32 changed_flags = 0;
2265 struct hlist_node *h;
2266 struct i40e_pf *pf;
2267 int num_add = 0;
2268 int num_del = 0;
2269 int retval = 0;
2270 u16 cmd_flags;
2271 int list_size;
2272 int bkt;
2273
2274
2275 struct i40e_aqc_add_macvlan_element_data *add_list;
2276 struct i40e_aqc_remove_macvlan_element_data *del_list;
2277
2278 while (test_and_set_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state))
2279 usleep_range(1000, 2000);
2280 pf = vsi->back;
2281
2282 old_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2283
2284 if (vsi->netdev) {
2285 changed_flags = vsi->current_netdev_flags ^ vsi->netdev->flags;
2286 vsi->current_netdev_flags = vsi->netdev->flags;
2287 }
2288
2289 INIT_HLIST_HEAD(&tmp_add_list);
2290 INIT_HLIST_HEAD(&tmp_del_list);
2291
2292 if (vsi->type == I40E_VSI_SRIOV)
2293 snprintf(vsi_name, sizeof(vsi_name) - 1, "VF %d", vsi->vf_id);
2294 else if (vsi->type != I40E_VSI_MAIN)
2295 snprintf(vsi_name, sizeof(vsi_name) - 1, "vsi %d", vsi->seid);
2296
2297 if (vsi->flags & I40E_VSI_FLAG_FILTER_CHANGED) {
2298 vsi->flags &= ~I40E_VSI_FLAG_FILTER_CHANGED;
2299
2300 spin_lock_bh(&vsi->mac_filter_hash_lock);
2301
2302 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
2303 if (f->state == I40E_FILTER_REMOVE) {
2304
2305 hash_del(&f->hlist);
2306 hlist_add_head(&f->hlist, &tmp_del_list);
2307
2308
2309 continue;
2310 }
2311 if (f->state == I40E_FILTER_NEW) {
2312
2313 new = kzalloc(sizeof(*new), GFP_ATOMIC);
2314 if (!new)
2315 goto err_no_memory_locked;
2316
2317
2318 new->f = f;
2319 new->state = f->state;
2320
2321
2322 hlist_add_head(&new->hlist, &tmp_add_list);
2323 }
2324
2325
2326
2327
2328
2329 if (f->vlan > 0)
2330 vlan_filters++;
2331 }
2332
2333 retval = i40e_correct_mac_vlan_filters(vsi,
2334 &tmp_add_list,
2335 &tmp_del_list,
2336 vlan_filters);
2337 if (retval)
2338 goto err_no_memory_locked;
2339
2340 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2341 }
2342
2343
2344 if (!hlist_empty(&tmp_del_list)) {
2345 filter_list_len = hw->aq.asq_buf_size /
2346 sizeof(struct i40e_aqc_remove_macvlan_element_data);
2347 list_size = filter_list_len *
2348 sizeof(struct i40e_aqc_remove_macvlan_element_data);
2349 del_list = kzalloc(list_size, GFP_ATOMIC);
2350 if (!del_list)
2351 goto err_no_memory;
2352
2353 hlist_for_each_entry_safe(f, h, &tmp_del_list, hlist) {
2354 cmd_flags = 0;
2355
2356
2357
2358
2359 if (is_broadcast_ether_addr(f->macaddr)) {
2360 i40e_aqc_broadcast_filter(vsi, vsi_name, f);
2361
2362 hlist_del(&f->hlist);
2363 kfree(f);
2364 continue;
2365 }
2366
2367
2368 ether_addr_copy(del_list[num_del].mac_addr, f->macaddr);
2369 if (f->vlan == I40E_VLAN_ANY) {
2370 del_list[num_del].vlan_tag = 0;
2371 cmd_flags |= I40E_AQC_MACVLAN_DEL_IGNORE_VLAN;
2372 } else {
2373 del_list[num_del].vlan_tag =
2374 cpu_to_le16((u16)(f->vlan));
2375 }
2376
2377 cmd_flags |= I40E_AQC_MACVLAN_DEL_PERFECT_MATCH;
2378 del_list[num_del].flags = cmd_flags;
2379 num_del++;
2380
2381
2382 if (num_del == filter_list_len) {
2383 i40e_aqc_del_filters(vsi, vsi_name, del_list,
2384 num_del, &retval);
2385 memset(del_list, 0, list_size);
2386 num_del = 0;
2387 }
2388
2389
2390
2391 hlist_del(&f->hlist);
2392 kfree(f);
2393 }
2394
2395 if (num_del) {
2396 i40e_aqc_del_filters(vsi, vsi_name, del_list,
2397 num_del, &retval);
2398 }
2399
2400 kfree(del_list);
2401 del_list = NULL;
2402 }
2403
2404 if (!hlist_empty(&tmp_add_list)) {
2405
2406 filter_list_len = hw->aq.asq_buf_size /
2407 sizeof(struct i40e_aqc_add_macvlan_element_data);
2408 list_size = filter_list_len *
2409 sizeof(struct i40e_aqc_add_macvlan_element_data);
2410 add_list = kzalloc(list_size, GFP_ATOMIC);
2411 if (!add_list)
2412 goto err_no_memory;
2413
2414 num_add = 0;
2415 hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) {
2416
2417
2418
2419 if (is_broadcast_ether_addr(new->f->macaddr)) {
2420 if (i40e_aqc_broadcast_filter(vsi, vsi_name,
2421 new->f))
2422 new->state = I40E_FILTER_FAILED;
2423 else
2424 new->state = I40E_FILTER_ACTIVE;
2425 continue;
2426 }
2427
2428
2429 if (num_add == 0)
2430 add_head = new;
2431 cmd_flags = 0;
2432 ether_addr_copy(add_list[num_add].mac_addr,
2433 new->f->macaddr);
2434 if (new->f->vlan == I40E_VLAN_ANY) {
2435 add_list[num_add].vlan_tag = 0;
2436 cmd_flags |= I40E_AQC_MACVLAN_ADD_IGNORE_VLAN;
2437 } else {
2438 add_list[num_add].vlan_tag =
2439 cpu_to_le16((u16)(new->f->vlan));
2440 }
2441 add_list[num_add].queue_number = 0;
2442
2443 add_list[num_add].match_method = I40E_AQC_MM_ERR_NO_RES;
2444 cmd_flags |= I40E_AQC_MACVLAN_ADD_PERFECT_MATCH;
2445 add_list[num_add].flags = cpu_to_le16(cmd_flags);
2446 num_add++;
2447
2448
2449 if (num_add == filter_list_len) {
2450 i40e_aqc_add_filters(vsi, vsi_name, add_list,
2451 add_head, num_add);
2452 memset(add_list, 0, list_size);
2453 num_add = 0;
2454 }
2455 }
2456 if (num_add) {
2457 i40e_aqc_add_filters(vsi, vsi_name, add_list, add_head,
2458 num_add);
2459 }
2460
2461
2462
2463 spin_lock_bh(&vsi->mac_filter_hash_lock);
2464 hlist_for_each_entry_safe(new, h, &tmp_add_list, hlist) {
2465
2466 if (new->f->state == I40E_FILTER_NEW)
2467 new->f->state = new->state;
2468 hlist_del(&new->hlist);
2469 kfree(new);
2470 }
2471 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2472 kfree(add_list);
2473 add_list = NULL;
2474 }
2475
2476
2477 spin_lock_bh(&vsi->mac_filter_hash_lock);
2478 vsi->active_filters = 0;
2479 hash_for_each(vsi->mac_filter_hash, bkt, f, hlist) {
2480 if (f->state == I40E_FILTER_ACTIVE)
2481 vsi->active_filters++;
2482 else if (f->state == I40E_FILTER_FAILED)
2483 failed_filters++;
2484 }
2485 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2486
2487
2488
2489
2490
2491 if (old_overflow && !failed_filters &&
2492 vsi->active_filters < vsi->promisc_threshold) {
2493 dev_info(&pf->pdev->dev,
2494 "filter logjam cleared on %s, leaving overflow promiscuous mode\n",
2495 vsi_name);
2496 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2497 vsi->promisc_threshold = 0;
2498 }
2499
2500
2501 if ((vsi->type == I40E_VSI_SRIOV) && !pf->vf[vsi->vf_id].trusted) {
2502 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2503 goto out;
2504 }
2505
2506 new_overflow = test_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
2507
2508
2509
2510
2511 if (!old_overflow && new_overflow)
2512 vsi->promisc_threshold = (vsi->active_filters * 3) / 4;
2513
2514
2515 if (changed_flags & IFF_ALLMULTI) {
2516 bool cur_multipromisc;
2517
2518 cur_multipromisc = !!(vsi->current_netdev_flags & IFF_ALLMULTI);
2519 aq_ret = i40e_aq_set_vsi_multicast_promiscuous(&vsi->back->hw,
2520 vsi->seid,
2521 cur_multipromisc,
2522 NULL);
2523 if (aq_ret) {
2524 retval = i40e_aq_rc_to_posix(aq_ret,
2525 hw->aq.asq_last_status);
2526 dev_info(&pf->pdev->dev,
2527 "set multi promisc failed on %s, err %s aq_err %s\n",
2528 vsi_name,
2529 i40e_stat_str(hw, aq_ret),
2530 i40e_aq_str(hw, hw->aq.asq_last_status));
2531 }
2532 }
2533
2534 if ((changed_flags & IFF_PROMISC) || old_overflow != new_overflow) {
2535 bool cur_promisc;
2536
2537 cur_promisc = (!!(vsi->current_netdev_flags & IFF_PROMISC) ||
2538 new_overflow);
2539 aq_ret = i40e_set_promiscuous(pf, cur_promisc);
2540 if (aq_ret) {
2541 retval = i40e_aq_rc_to_posix(aq_ret,
2542 hw->aq.asq_last_status);
2543 dev_info(&pf->pdev->dev,
2544 "Setting promiscuous %s failed on %s, err %s aq_err %s\n",
2545 cur_promisc ? "on" : "off",
2546 vsi_name,
2547 i40e_stat_str(hw, aq_ret),
2548 i40e_aq_str(hw, hw->aq.asq_last_status));
2549 }
2550 }
2551out:
2552
2553 if (retval)
2554 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2555
2556 clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state);
2557 return retval;
2558
2559err_no_memory:
2560
2561 spin_lock_bh(&vsi->mac_filter_hash_lock);
2562err_no_memory_locked:
2563 i40e_undo_del_filter_entries(vsi, &tmp_del_list);
2564 i40e_undo_add_filter_entries(vsi, &tmp_add_list);
2565 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2566
2567 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
2568 clear_bit(__I40E_VSI_SYNCING_FILTERS, vsi->state);
2569 return -ENOMEM;
2570}
2571
2572
2573
2574
2575
2576static void i40e_sync_filters_subtask(struct i40e_pf *pf)
2577{
2578 int v;
2579
2580 if (!pf)
2581 return;
2582 if (!test_and_clear_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state))
2583 return;
2584
2585 for (v = 0; v < pf->num_alloc_vsi; v++) {
2586 if (pf->vsi[v] &&
2587 (pf->vsi[v]->flags & I40E_VSI_FLAG_FILTER_CHANGED)) {
2588 int ret = i40e_sync_vsi_filters(pf->vsi[v]);
2589
2590 if (ret) {
2591
2592 set_bit(__I40E_MACVLAN_SYNC_PENDING,
2593 pf->state);
2594 break;
2595 }
2596 }
2597 }
2598}
2599
2600
2601
2602
2603
2604static int i40e_max_xdp_frame_size(struct i40e_vsi *vsi)
2605{
2606 if (PAGE_SIZE >= 8192 || (vsi->back->flags & I40E_FLAG_LEGACY_RX))
2607 return I40E_RXBUFFER_2048;
2608 else
2609 return I40E_RXBUFFER_3072;
2610}
2611
2612
2613
2614
2615
2616
2617
2618
2619static int i40e_change_mtu(struct net_device *netdev, int new_mtu)
2620{
2621 struct i40e_netdev_priv *np = netdev_priv(netdev);
2622 struct i40e_vsi *vsi = np->vsi;
2623 struct i40e_pf *pf = vsi->back;
2624
2625 if (i40e_enabled_xdp_vsi(vsi)) {
2626 int frame_size = new_mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
2627
2628 if (frame_size > i40e_max_xdp_frame_size(vsi))
2629 return -EINVAL;
2630 }
2631
2632 netdev_info(netdev, "changing MTU from %d to %d\n",
2633 netdev->mtu, new_mtu);
2634 netdev->mtu = new_mtu;
2635 if (netif_running(netdev))
2636 i40e_vsi_reinit_locked(vsi);
2637 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
2638 set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
2639 return 0;
2640}
2641
2642
2643
2644
2645
2646
2647
2648int i40e_ioctl(struct net_device *netdev, struct ifreq *ifr, int cmd)
2649{
2650 struct i40e_netdev_priv *np = netdev_priv(netdev);
2651 struct i40e_pf *pf = np->vsi->back;
2652
2653 switch (cmd) {
2654 case SIOCGHWTSTAMP:
2655 return i40e_ptp_get_ts_config(pf, ifr);
2656 case SIOCSHWTSTAMP:
2657 return i40e_ptp_set_ts_config(pf, ifr);
2658 default:
2659 return -EOPNOTSUPP;
2660 }
2661}
2662
2663
2664
2665
2666
2667void i40e_vlan_stripping_enable(struct i40e_vsi *vsi)
2668{
2669 struct i40e_vsi_context ctxt;
2670 i40e_status ret;
2671
2672 if ((vsi->info.valid_sections &
2673 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2674 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_MODE_MASK) == 0))
2675 return;
2676
2677 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2678 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2679 I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH;
2680
2681 ctxt.seid = vsi->seid;
2682 ctxt.info = vsi->info;
2683 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2684 if (ret) {
2685 dev_info(&vsi->back->pdev->dev,
2686 "update vlan stripping failed, err %s aq_err %s\n",
2687 i40e_stat_str(&vsi->back->hw, ret),
2688 i40e_aq_str(&vsi->back->hw,
2689 vsi->back->hw.aq.asq_last_status));
2690 }
2691}
2692
2693
2694
2695
2696
2697void i40e_vlan_stripping_disable(struct i40e_vsi *vsi)
2698{
2699 struct i40e_vsi_context ctxt;
2700 i40e_status ret;
2701
2702 if ((vsi->info.valid_sections &
2703 cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID)) &&
2704 ((vsi->info.port_vlan_flags & I40E_AQ_VSI_PVLAN_EMOD_MASK) ==
2705 I40E_AQ_VSI_PVLAN_EMOD_MASK))
2706 return;
2707
2708 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2709 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_ALL |
2710 I40E_AQ_VSI_PVLAN_EMOD_NOTHING;
2711
2712 ctxt.seid = vsi->seid;
2713 ctxt.info = vsi->info;
2714 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2715 if (ret) {
2716 dev_info(&vsi->back->pdev->dev,
2717 "update vlan stripping failed, err %s aq_err %s\n",
2718 i40e_stat_str(&vsi->back->hw, ret),
2719 i40e_aq_str(&vsi->back->hw,
2720 vsi->back->hw.aq.asq_last_status));
2721 }
2722}
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737int i40e_add_vlan_all_mac(struct i40e_vsi *vsi, s16 vid)
2738{
2739 struct i40e_mac_filter *f, *add_f;
2740 struct hlist_node *h;
2741 int bkt;
2742
2743 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
2744 if (f->state == I40E_FILTER_REMOVE)
2745 continue;
2746 add_f = i40e_add_filter(vsi, f->macaddr, vid);
2747 if (!add_f) {
2748 dev_info(&vsi->back->pdev->dev,
2749 "Could not add vlan filter %d for %pM\n",
2750 vid, f->macaddr);
2751 return -ENOMEM;
2752 }
2753 }
2754
2755 return 0;
2756}
2757
2758
2759
2760
2761
2762
2763int i40e_vsi_add_vlan(struct i40e_vsi *vsi, u16 vid)
2764{
2765 int err;
2766
2767 if (vsi->info.pvid)
2768 return -EINVAL;
2769
2770
2771
2772
2773
2774
2775
2776
2777
2778 if (!vid)
2779 return 0;
2780
2781
2782 spin_lock_bh(&vsi->mac_filter_hash_lock);
2783 err = i40e_add_vlan_all_mac(vsi, vid);
2784 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2785 if (err)
2786 return err;
2787
2788
2789
2790
2791 i40e_service_event_schedule(vsi->back);
2792 return 0;
2793}
2794
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807
2808void i40e_rm_vlan_all_mac(struct i40e_vsi *vsi, s16 vid)
2809{
2810 struct i40e_mac_filter *f;
2811 struct hlist_node *h;
2812 int bkt;
2813
2814 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
2815 if (f->vlan == vid)
2816 __i40e_del_filter(vsi, f);
2817 }
2818}
2819
2820
2821
2822
2823
2824
2825void i40e_vsi_kill_vlan(struct i40e_vsi *vsi, u16 vid)
2826{
2827 if (!vid || vsi->info.pvid)
2828 return;
2829
2830 spin_lock_bh(&vsi->mac_filter_hash_lock);
2831 i40e_rm_vlan_all_mac(vsi, vid);
2832 spin_unlock_bh(&vsi->mac_filter_hash_lock);
2833
2834
2835
2836
2837 i40e_service_event_schedule(vsi->back);
2838}
2839
2840
2841
2842
2843
2844
2845
2846
2847static int i40e_vlan_rx_add_vid(struct net_device *netdev,
2848 __always_unused __be16 proto, u16 vid)
2849{
2850 struct i40e_netdev_priv *np = netdev_priv(netdev);
2851 struct i40e_vsi *vsi = np->vsi;
2852 int ret = 0;
2853
2854 if (vid >= VLAN_N_VID)
2855 return -EINVAL;
2856
2857 ret = i40e_vsi_add_vlan(vsi, vid);
2858 if (!ret)
2859 set_bit(vid, vsi->active_vlans);
2860
2861 return ret;
2862}
2863
2864
2865
2866
2867
2868
2869
2870
2871static int i40e_vlan_rx_kill_vid(struct net_device *netdev,
2872 __always_unused __be16 proto, u16 vid)
2873{
2874 struct i40e_netdev_priv *np = netdev_priv(netdev);
2875 struct i40e_vsi *vsi = np->vsi;
2876
2877
2878
2879
2880
2881 i40e_vsi_kill_vlan(vsi, vid);
2882
2883 clear_bit(vid, vsi->active_vlans);
2884
2885 return 0;
2886}
2887
2888
2889
2890
2891
2892static void i40e_restore_vlan(struct i40e_vsi *vsi)
2893{
2894 u16 vid;
2895
2896 if (!vsi->netdev)
2897 return;
2898
2899 if (vsi->netdev->features & NETIF_F_HW_VLAN_CTAG_RX)
2900 i40e_vlan_stripping_enable(vsi);
2901 else
2902 i40e_vlan_stripping_disable(vsi);
2903
2904 for_each_set_bit(vid, vsi->active_vlans, VLAN_N_VID)
2905 i40e_vlan_rx_add_vid(vsi->netdev, htons(ETH_P_8021Q),
2906 vid);
2907}
2908
2909
2910
2911
2912
2913
2914int i40e_vsi_add_pvid(struct i40e_vsi *vsi, u16 vid)
2915{
2916 struct i40e_vsi_context ctxt;
2917 i40e_status ret;
2918
2919 vsi->info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
2920 vsi->info.pvid = cpu_to_le16(vid);
2921 vsi->info.port_vlan_flags = I40E_AQ_VSI_PVLAN_MODE_TAGGED |
2922 I40E_AQ_VSI_PVLAN_INSERT_PVID |
2923 I40E_AQ_VSI_PVLAN_EMOD_STR;
2924
2925 ctxt.seid = vsi->seid;
2926 ctxt.info = vsi->info;
2927 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
2928 if (ret) {
2929 dev_info(&vsi->back->pdev->dev,
2930 "add pvid failed, err %s aq_err %s\n",
2931 i40e_stat_str(&vsi->back->hw, ret),
2932 i40e_aq_str(&vsi->back->hw,
2933 vsi->back->hw.aq.asq_last_status));
2934 return -ENOENT;
2935 }
2936
2937 return 0;
2938}
2939
2940
2941
2942
2943
2944
2945
2946void i40e_vsi_remove_pvid(struct i40e_vsi *vsi)
2947{
2948 i40e_vlan_stripping_disable(vsi);
2949
2950 vsi->info.pvid = 0;
2951}
2952
2953
2954
2955
2956
2957
2958
2959
2960
2961
2962
2963static int i40e_vsi_setup_tx_resources(struct i40e_vsi *vsi)
2964{
2965 int i, err = 0;
2966
2967 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
2968 err = i40e_setup_tx_descriptors(vsi->tx_rings[i]);
2969
2970 if (!i40e_enabled_xdp_vsi(vsi))
2971 return err;
2972
2973 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
2974 err = i40e_setup_tx_descriptors(vsi->xdp_rings[i]);
2975
2976 return err;
2977}
2978
2979
2980
2981
2982
2983
2984
2985static void i40e_vsi_free_tx_resources(struct i40e_vsi *vsi)
2986{
2987 int i;
2988
2989 if (vsi->tx_rings) {
2990 for (i = 0; i < vsi->num_queue_pairs; i++)
2991 if (vsi->tx_rings[i] && vsi->tx_rings[i]->desc)
2992 i40e_free_tx_resources(vsi->tx_rings[i]);
2993 }
2994
2995 if (vsi->xdp_rings) {
2996 for (i = 0; i < vsi->num_queue_pairs; i++)
2997 if (vsi->xdp_rings[i] && vsi->xdp_rings[i]->desc)
2998 i40e_free_tx_resources(vsi->xdp_rings[i]);
2999 }
3000}
3001
3002
3003
3004
3005
3006
3007
3008
3009
3010
3011
3012static int i40e_vsi_setup_rx_resources(struct i40e_vsi *vsi)
3013{
3014 int i, err = 0;
3015
3016 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3017 err = i40e_setup_rx_descriptors(vsi->rx_rings[i]);
3018 return err;
3019}
3020
3021
3022
3023
3024
3025
3026
3027static void i40e_vsi_free_rx_resources(struct i40e_vsi *vsi)
3028{
3029 int i;
3030
3031 if (!vsi->rx_rings)
3032 return;
3033
3034 for (i = 0; i < vsi->num_queue_pairs; i++)
3035 if (vsi->rx_rings[i] && vsi->rx_rings[i]->desc)
3036 i40e_free_rx_resources(vsi->rx_rings[i]);
3037}
3038
3039
3040
3041
3042
3043
3044
3045
3046static void i40e_config_xps_tx_ring(struct i40e_ring *ring)
3047{
3048 int cpu;
3049
3050 if (!ring->q_vector || !ring->netdev || ring->ch)
3051 return;
3052
3053
3054 if (test_and_set_bit(__I40E_TX_XPS_INIT_DONE, ring->state))
3055 return;
3056
3057 cpu = cpumask_local_spread(ring->q_vector->v_idx, -1);
3058 netif_set_xps_queue(ring->netdev, get_cpu_mask(cpu),
3059 ring->queue_index);
3060}
3061
3062
3063
3064
3065
3066
3067
3068static int i40e_configure_tx_ring(struct i40e_ring *ring)
3069{
3070 struct i40e_vsi *vsi = ring->vsi;
3071 u16 pf_q = vsi->base_queue + ring->queue_index;
3072 struct i40e_hw *hw = &vsi->back->hw;
3073 struct i40e_hmc_obj_txq tx_ctx;
3074 i40e_status err = 0;
3075 u32 qtx_ctl = 0;
3076
3077
3078 if (vsi->back->flags & I40E_FLAG_FD_ATR_ENABLED) {
3079 ring->atr_sample_rate = vsi->back->atr_sample_rate;
3080 ring->atr_count = 0;
3081 } else {
3082 ring->atr_sample_rate = 0;
3083 }
3084
3085
3086 i40e_config_xps_tx_ring(ring);
3087
3088
3089 memset(&tx_ctx, 0, sizeof(tx_ctx));
3090
3091 tx_ctx.new_context = 1;
3092 tx_ctx.base = (ring->dma / 128);
3093 tx_ctx.qlen = ring->count;
3094 tx_ctx.fd_ena = !!(vsi->back->flags & (I40E_FLAG_FD_SB_ENABLED |
3095 I40E_FLAG_FD_ATR_ENABLED));
3096 tx_ctx.timesync_ena = !!(vsi->back->flags & I40E_FLAG_PTP);
3097
3098 if (vsi->type != I40E_VSI_FDIR)
3099 tx_ctx.head_wb_ena = 1;
3100 tx_ctx.head_wb_addr = ring->dma +
3101 (ring->count * sizeof(struct i40e_tx_desc));
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114 if (ring->ch)
3115 tx_ctx.rdylist =
3116 le16_to_cpu(ring->ch->info.qs_handle[ring->dcb_tc]);
3117
3118 else
3119 tx_ctx.rdylist = le16_to_cpu(vsi->info.qs_handle[ring->dcb_tc]);
3120
3121 tx_ctx.rdylist_act = 0;
3122
3123
3124 err = i40e_clear_lan_tx_queue_context(hw, pf_q);
3125 if (err) {
3126 dev_info(&vsi->back->pdev->dev,
3127 "Failed to clear LAN Tx queue context on Tx ring %d (pf_q %d), error: %d\n",
3128 ring->queue_index, pf_q, err);
3129 return -ENOMEM;
3130 }
3131
3132
3133 err = i40e_set_lan_tx_queue_context(hw, pf_q, &tx_ctx);
3134 if (err) {
3135 dev_info(&vsi->back->pdev->dev,
3136 "Failed to set LAN Tx queue context on Tx ring %d (pf_q %d, error: %d\n",
3137 ring->queue_index, pf_q, err);
3138 return -ENOMEM;
3139 }
3140
3141
3142 if (ring->ch) {
3143 if (ring->ch->type == I40E_VSI_VMDQ2)
3144 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
3145 else
3146 return -EINVAL;
3147
3148 qtx_ctl |= (ring->ch->vsi_number <<
3149 I40E_QTX_CTL_VFVM_INDX_SHIFT) &
3150 I40E_QTX_CTL_VFVM_INDX_MASK;
3151 } else {
3152 if (vsi->type == I40E_VSI_VMDQ2) {
3153 qtx_ctl = I40E_QTX_CTL_VM_QUEUE;
3154 qtx_ctl |= ((vsi->id) << I40E_QTX_CTL_VFVM_INDX_SHIFT) &
3155 I40E_QTX_CTL_VFVM_INDX_MASK;
3156 } else {
3157 qtx_ctl = I40E_QTX_CTL_PF_QUEUE;
3158 }
3159 }
3160
3161 qtx_ctl |= ((hw->pf_id << I40E_QTX_CTL_PF_INDX_SHIFT) &
3162 I40E_QTX_CTL_PF_INDX_MASK);
3163 wr32(hw, I40E_QTX_CTL(pf_q), qtx_ctl);
3164 i40e_flush(hw);
3165
3166
3167 ring->tail = hw->hw_addr + I40E_QTX_TAIL(pf_q);
3168
3169 return 0;
3170}
3171
3172
3173
3174
3175
3176
3177
3178static int i40e_configure_rx_ring(struct i40e_ring *ring)
3179{
3180 struct i40e_vsi *vsi = ring->vsi;
3181 u32 chain_len = vsi->back->hw.func_caps.rx_buf_chain_len;
3182 u16 pf_q = vsi->base_queue + ring->queue_index;
3183 struct i40e_hw *hw = &vsi->back->hw;
3184 struct i40e_hmc_obj_rxq rx_ctx;
3185 i40e_status err = 0;
3186
3187 bitmap_zero(ring->state, __I40E_RING_STATE_NBITS);
3188
3189
3190 memset(&rx_ctx, 0, sizeof(rx_ctx));
3191
3192 ring->rx_buf_len = vsi->rx_buf_len;
3193
3194 rx_ctx.dbuff = DIV_ROUND_UP(ring->rx_buf_len,
3195 BIT_ULL(I40E_RXQ_CTX_DBUFF_SHIFT));
3196
3197 rx_ctx.base = (ring->dma / 128);
3198 rx_ctx.qlen = ring->count;
3199
3200
3201 rx_ctx.dsize = 1;
3202
3203
3204
3205
3206 rx_ctx.hsplit_0 = 0;
3207
3208 rx_ctx.rxmax = min_t(u16, vsi->max_frame, chain_len * ring->rx_buf_len);
3209 if (hw->revision_id == 0)
3210 rx_ctx.lrxqthresh = 0;
3211 else
3212 rx_ctx.lrxqthresh = 1;
3213 rx_ctx.crcstrip = 1;
3214 rx_ctx.l2tsel = 1;
3215
3216 rx_ctx.showiv = 0;
3217
3218 rx_ctx.prefena = 1;
3219
3220
3221 err = i40e_clear_lan_rx_queue_context(hw, pf_q);
3222 if (err) {
3223 dev_info(&vsi->back->pdev->dev,
3224 "Failed to clear LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
3225 ring->queue_index, pf_q, err);
3226 return -ENOMEM;
3227 }
3228
3229
3230 err = i40e_set_lan_rx_queue_context(hw, pf_q, &rx_ctx);
3231 if (err) {
3232 dev_info(&vsi->back->pdev->dev,
3233 "Failed to set LAN Rx queue context on Rx ring %d (pf_q %d), error: %d\n",
3234 ring->queue_index, pf_q, err);
3235 return -ENOMEM;
3236 }
3237
3238
3239 if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX))
3240 clear_ring_build_skb_enabled(ring);
3241 else
3242 set_ring_build_skb_enabled(ring);
3243
3244
3245 ring->tail = hw->hw_addr + I40E_QRX_TAIL(pf_q);
3246 writel(0, ring->tail);
3247
3248 i40e_alloc_rx_buffers(ring, I40E_DESC_UNUSED(ring));
3249
3250 return 0;
3251}
3252
3253
3254
3255
3256
3257
3258
3259static int i40e_vsi_configure_tx(struct i40e_vsi *vsi)
3260{
3261 int err = 0;
3262 u16 i;
3263
3264 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
3265 err = i40e_configure_tx_ring(vsi->tx_rings[i]);
3266
3267 if (!i40e_enabled_xdp_vsi(vsi))
3268 return err;
3269
3270 for (i = 0; (i < vsi->num_queue_pairs) && !err; i++)
3271 err = i40e_configure_tx_ring(vsi->xdp_rings[i]);
3272
3273 return err;
3274}
3275
3276
3277
3278
3279
3280
3281
3282static int i40e_vsi_configure_rx(struct i40e_vsi *vsi)
3283{
3284 int err = 0;
3285 u16 i;
3286
3287 if (!vsi->netdev || (vsi->back->flags & I40E_FLAG_LEGACY_RX)) {
3288 vsi->max_frame = I40E_MAX_RXBUFFER;
3289 vsi->rx_buf_len = I40E_RXBUFFER_2048;
3290#if (PAGE_SIZE < 8192)
3291 } else if (!I40E_2K_TOO_SMALL_WITH_PADDING &&
3292 (vsi->netdev->mtu <= ETH_DATA_LEN)) {
3293 vsi->max_frame = I40E_RXBUFFER_1536 - NET_IP_ALIGN;
3294 vsi->rx_buf_len = I40E_RXBUFFER_1536 - NET_IP_ALIGN;
3295#endif
3296 } else {
3297 vsi->max_frame = I40E_MAX_RXBUFFER;
3298 vsi->rx_buf_len = (PAGE_SIZE < 8192) ? I40E_RXBUFFER_3072 :
3299 I40E_RXBUFFER_2048;
3300 }
3301
3302
3303 for (i = 0; i < vsi->num_queue_pairs && !err; i++)
3304 err = i40e_configure_rx_ring(vsi->rx_rings[i]);
3305
3306 return err;
3307}
3308
3309
3310
3311
3312
3313static void i40e_vsi_config_dcb_rings(struct i40e_vsi *vsi)
3314{
3315 struct i40e_ring *tx_ring, *rx_ring;
3316 u16 qoffset, qcount;
3317 int i, n;
3318
3319 if (!(vsi->back->flags & I40E_FLAG_DCB_ENABLED)) {
3320
3321 for (i = 0; i < vsi->num_queue_pairs; i++) {
3322 rx_ring = vsi->rx_rings[i];
3323 tx_ring = vsi->tx_rings[i];
3324 rx_ring->dcb_tc = 0;
3325 tx_ring->dcb_tc = 0;
3326 }
3327 return;
3328 }
3329
3330 for (n = 0; n < I40E_MAX_TRAFFIC_CLASS; n++) {
3331 if (!(vsi->tc_config.enabled_tc & BIT_ULL(n)))
3332 continue;
3333
3334 qoffset = vsi->tc_config.tc_info[n].qoffset;
3335 qcount = vsi->tc_config.tc_info[n].qcount;
3336 for (i = qoffset; i < (qoffset + qcount); i++) {
3337 rx_ring = vsi->rx_rings[i];
3338 tx_ring = vsi->tx_rings[i];
3339 rx_ring->dcb_tc = n;
3340 tx_ring->dcb_tc = n;
3341 }
3342 }
3343}
3344
3345
3346
3347
3348
3349static void i40e_set_vsi_rx_mode(struct i40e_vsi *vsi)
3350{
3351 if (vsi->netdev)
3352 i40e_set_rx_mode(vsi->netdev);
3353}
3354
3355
3356
3357
3358
3359
3360
3361
3362static void i40e_fdir_filter_restore(struct i40e_vsi *vsi)
3363{
3364 struct i40e_fdir_filter *filter;
3365 struct i40e_pf *pf = vsi->back;
3366 struct hlist_node *node;
3367
3368 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
3369 return;
3370
3371
3372 pf->fd_tcp4_filter_cnt = 0;
3373 pf->fd_udp4_filter_cnt = 0;
3374 pf->fd_sctp4_filter_cnt = 0;
3375 pf->fd_ip4_filter_cnt = 0;
3376
3377 hlist_for_each_entry_safe(filter, node,
3378 &pf->fdir_filter_list, fdir_node) {
3379 i40e_add_del_fdir(vsi, filter, true);
3380 }
3381}
3382
3383
3384
3385
3386
3387static int i40e_vsi_configure(struct i40e_vsi *vsi)
3388{
3389 int err;
3390
3391 i40e_set_vsi_rx_mode(vsi);
3392 i40e_restore_vlan(vsi);
3393 i40e_vsi_config_dcb_rings(vsi);
3394 err = i40e_vsi_configure_tx(vsi);
3395 if (!err)
3396 err = i40e_vsi_configure_rx(vsi);
3397
3398 return err;
3399}
3400
3401
3402
3403
3404
3405static void i40e_vsi_configure_msix(struct i40e_vsi *vsi)
3406{
3407 bool has_xdp = i40e_enabled_xdp_vsi(vsi);
3408 struct i40e_pf *pf = vsi->back;
3409 struct i40e_hw *hw = &pf->hw;
3410 u16 vector;
3411 int i, q;
3412 u32 qp;
3413
3414
3415
3416
3417
3418 qp = vsi->base_queue;
3419 vector = vsi->base_vector;
3420 for (i = 0; i < vsi->num_q_vectors; i++, vector++) {
3421 struct i40e_q_vector *q_vector = vsi->q_vectors[i];
3422
3423 q_vector->rx.next_update = jiffies + 1;
3424 q_vector->rx.target_itr =
3425 ITR_TO_REG(vsi->rx_rings[i]->itr_setting);
3426 wr32(hw, I40E_PFINT_ITRN(I40E_RX_ITR, vector - 1),
3427 q_vector->rx.target_itr);
3428 q_vector->rx.current_itr = q_vector->rx.target_itr;
3429
3430 q_vector->tx.next_update = jiffies + 1;
3431 q_vector->tx.target_itr =
3432 ITR_TO_REG(vsi->tx_rings[i]->itr_setting);
3433 wr32(hw, I40E_PFINT_ITRN(I40E_TX_ITR, vector - 1),
3434 q_vector->tx.target_itr);
3435 q_vector->tx.current_itr = q_vector->tx.target_itr;
3436
3437 wr32(hw, I40E_PFINT_RATEN(vector - 1),
3438 i40e_intrl_usec_to_reg(vsi->int_rate_limit));
3439
3440
3441 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), qp);
3442 for (q = 0; q < q_vector->num_ringpairs; q++) {
3443 u32 nextqp = has_xdp ? qp + vsi->alloc_queue_pairs : qp;
3444 u32 val;
3445
3446 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3447 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3448 (vector << I40E_QINT_RQCTL_MSIX_INDX_SHIFT) |
3449 (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT) |
3450 (I40E_QUEUE_TYPE_TX <<
3451 I40E_QINT_RQCTL_NEXTQ_TYPE_SHIFT);
3452
3453 wr32(hw, I40E_QINT_RQCTL(qp), val);
3454
3455 if (has_xdp) {
3456 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3457 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3458 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3459 (qp << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
3460 (I40E_QUEUE_TYPE_TX <<
3461 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3462
3463 wr32(hw, I40E_QINT_TQCTL(nextqp), val);
3464 }
3465
3466 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3467 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3468 (vector << I40E_QINT_TQCTL_MSIX_INDX_SHIFT) |
3469 ((qp + 1) << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT) |
3470 (I40E_QUEUE_TYPE_RX <<
3471 I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3472
3473
3474 if (q == (q_vector->num_ringpairs - 1))
3475 val |= (I40E_QUEUE_END_OF_LIST <<
3476 I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3477
3478 wr32(hw, I40E_QINT_TQCTL(qp), val);
3479 qp++;
3480 }
3481 }
3482
3483 i40e_flush(hw);
3484}
3485
3486
3487
3488
3489
3490static void i40e_enable_misc_int_causes(struct i40e_pf *pf)
3491{
3492 struct i40e_hw *hw = &pf->hw;
3493 u32 val;
3494
3495
3496 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3497 rd32(hw, I40E_PFINT_ICR0);
3498
3499 val = I40E_PFINT_ICR0_ENA_ECC_ERR_MASK |
3500 I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK |
3501 I40E_PFINT_ICR0_ENA_GRST_MASK |
3502 I40E_PFINT_ICR0_ENA_PCI_EXCEPTION_MASK |
3503 I40E_PFINT_ICR0_ENA_GPIO_MASK |
3504 I40E_PFINT_ICR0_ENA_HMC_ERR_MASK |
3505 I40E_PFINT_ICR0_ENA_VFLR_MASK |
3506 I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3507
3508 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
3509 val |= I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3510
3511 if (pf->flags & I40E_FLAG_PTP)
3512 val |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3513
3514 wr32(hw, I40E_PFINT_ICR0_ENA, val);
3515
3516
3517 wr32(hw, I40E_PFINT_DYN_CTL0, I40E_PFINT_DYN_CTL0_SW_ITR_INDX_MASK |
3518 I40E_PFINT_DYN_CTL0_INTENA_MSK_MASK);
3519
3520
3521 wr32(hw, I40E_PFINT_STAT_CTL0, 0);
3522}
3523
3524
3525
3526
3527
3528static void i40e_configure_msi_and_legacy(struct i40e_vsi *vsi)
3529{
3530 u32 nextqp = i40e_enabled_xdp_vsi(vsi) ? vsi->alloc_queue_pairs : 0;
3531 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
3532 struct i40e_pf *pf = vsi->back;
3533 struct i40e_hw *hw = &pf->hw;
3534 u32 val;
3535
3536
3537 q_vector->rx.next_update = jiffies + 1;
3538 q_vector->rx.target_itr = ITR_TO_REG(vsi->rx_rings[0]->itr_setting);
3539 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), q_vector->rx.target_itr);
3540 q_vector->rx.current_itr = q_vector->rx.target_itr;
3541 q_vector->tx.next_update = jiffies + 1;
3542 q_vector->tx.target_itr = ITR_TO_REG(vsi->tx_rings[0]->itr_setting);
3543 wr32(hw, I40E_PFINT_ITR0(I40E_TX_ITR), q_vector->tx.target_itr);
3544 q_vector->tx.current_itr = q_vector->tx.target_itr;
3545
3546 i40e_enable_misc_int_causes(pf);
3547
3548
3549 wr32(hw, I40E_PFINT_LNKLST0, 0);
3550
3551
3552 val = I40E_QINT_RQCTL_CAUSE_ENA_MASK |
3553 (I40E_RX_ITR << I40E_QINT_RQCTL_ITR_INDX_SHIFT) |
3554 (nextqp << I40E_QINT_RQCTL_NEXTQ_INDX_SHIFT)|
3555 (I40E_QUEUE_TYPE_TX << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3556
3557 wr32(hw, I40E_QINT_RQCTL(0), val);
3558
3559 if (i40e_enabled_xdp_vsi(vsi)) {
3560 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3561 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT)|
3562 (I40E_QUEUE_TYPE_TX
3563 << I40E_QINT_TQCTL_NEXTQ_TYPE_SHIFT);
3564
3565 wr32(hw, I40E_QINT_TQCTL(nextqp), val);
3566 }
3567
3568 val = I40E_QINT_TQCTL_CAUSE_ENA_MASK |
3569 (I40E_TX_ITR << I40E_QINT_TQCTL_ITR_INDX_SHIFT) |
3570 (I40E_QUEUE_END_OF_LIST << I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT);
3571
3572 wr32(hw, I40E_QINT_TQCTL(0), val);
3573 i40e_flush(hw);
3574}
3575
3576
3577
3578
3579
3580void i40e_irq_dynamic_disable_icr0(struct i40e_pf *pf)
3581{
3582 struct i40e_hw *hw = &pf->hw;
3583
3584 wr32(hw, I40E_PFINT_DYN_CTL0,
3585 I40E_ITR_NONE << I40E_PFINT_DYN_CTLN_ITR_INDX_SHIFT);
3586 i40e_flush(hw);
3587}
3588
3589
3590
3591
3592
3593void i40e_irq_dynamic_enable_icr0(struct i40e_pf *pf)
3594{
3595 struct i40e_hw *hw = &pf->hw;
3596 u32 val;
3597
3598 val = I40E_PFINT_DYN_CTL0_INTENA_MASK |
3599 I40E_PFINT_DYN_CTL0_CLEARPBA_MASK |
3600 (I40E_ITR_NONE << I40E_PFINT_DYN_CTL0_ITR_INDX_SHIFT);
3601
3602 wr32(hw, I40E_PFINT_DYN_CTL0, val);
3603 i40e_flush(hw);
3604}
3605
3606
3607
3608
3609
3610
3611static irqreturn_t i40e_msix_clean_rings(int irq, void *data)
3612{
3613 struct i40e_q_vector *q_vector = data;
3614
3615 if (!q_vector->tx.ring && !q_vector->rx.ring)
3616 return IRQ_HANDLED;
3617
3618 napi_schedule_irqoff(&q_vector->napi);
3619
3620 return IRQ_HANDLED;
3621}
3622
3623
3624
3625
3626
3627
3628
3629
3630
3631static void i40e_irq_affinity_notify(struct irq_affinity_notify *notify,
3632 const cpumask_t *mask)
3633{
3634 struct i40e_q_vector *q_vector =
3635 container_of(notify, struct i40e_q_vector, affinity_notify);
3636
3637 cpumask_copy(&q_vector->affinity_mask, mask);
3638}
3639
3640
3641
3642
3643
3644
3645
3646
3647
3648static void i40e_irq_affinity_release(struct kref *ref) {}
3649
3650
3651
3652
3653
3654
3655
3656
3657static int i40e_vsi_request_irq_msix(struct i40e_vsi *vsi, char *basename)
3658{
3659 int q_vectors = vsi->num_q_vectors;
3660 struct i40e_pf *pf = vsi->back;
3661 int base = vsi->base_vector;
3662 int rx_int_idx = 0;
3663 int tx_int_idx = 0;
3664 int vector, err;
3665 int irq_num;
3666 int cpu;
3667
3668 for (vector = 0; vector < q_vectors; vector++) {
3669 struct i40e_q_vector *q_vector = vsi->q_vectors[vector];
3670
3671 irq_num = pf->msix_entries[base + vector].vector;
3672
3673 if (q_vector->tx.ring && q_vector->rx.ring) {
3674 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3675 "%s-%s-%d", basename, "TxRx", rx_int_idx++);
3676 tx_int_idx++;
3677 } else if (q_vector->rx.ring) {
3678 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3679 "%s-%s-%d", basename, "rx", rx_int_idx++);
3680 } else if (q_vector->tx.ring) {
3681 snprintf(q_vector->name, sizeof(q_vector->name) - 1,
3682 "%s-%s-%d", basename, "tx", tx_int_idx++);
3683 } else {
3684
3685 continue;
3686 }
3687 err = request_irq(irq_num,
3688 vsi->irq_handler,
3689 0,
3690 q_vector->name,
3691 q_vector);
3692 if (err) {
3693 dev_info(&pf->pdev->dev,
3694 "MSIX request_irq failed, error: %d\n", err);
3695 goto free_queue_irqs;
3696 }
3697
3698
3699 q_vector->affinity_notify.notify = i40e_irq_affinity_notify;
3700 q_vector->affinity_notify.release = i40e_irq_affinity_release;
3701 irq_set_affinity_notifier(irq_num, &q_vector->affinity_notify);
3702
3703
3704
3705
3706
3707
3708 cpu = cpumask_local_spread(q_vector->v_idx, -1);
3709 irq_set_affinity_hint(irq_num, get_cpu_mask(cpu));
3710 }
3711
3712 vsi->irqs_ready = true;
3713 return 0;
3714
3715free_queue_irqs:
3716 while (vector) {
3717 vector--;
3718 irq_num = pf->msix_entries[base + vector].vector;
3719 irq_set_affinity_notifier(irq_num, NULL);
3720 irq_set_affinity_hint(irq_num, NULL);
3721 free_irq(irq_num, &vsi->q_vectors[vector]);
3722 }
3723 return err;
3724}
3725
3726
3727
3728
3729
3730static void i40e_vsi_disable_irq(struct i40e_vsi *vsi)
3731{
3732 struct i40e_pf *pf = vsi->back;
3733 struct i40e_hw *hw = &pf->hw;
3734 int base = vsi->base_vector;
3735 int i;
3736
3737
3738 for (i = 0; i < vsi->num_queue_pairs; i++) {
3739 u32 val;
3740
3741 val = rd32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx));
3742 val &= ~I40E_QINT_TQCTL_CAUSE_ENA_MASK;
3743 wr32(hw, I40E_QINT_TQCTL(vsi->tx_rings[i]->reg_idx), val);
3744
3745 val = rd32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx));
3746 val &= ~I40E_QINT_RQCTL_CAUSE_ENA_MASK;
3747 wr32(hw, I40E_QINT_RQCTL(vsi->rx_rings[i]->reg_idx), val);
3748
3749 if (!i40e_enabled_xdp_vsi(vsi))
3750 continue;
3751 wr32(hw, I40E_QINT_TQCTL(vsi->xdp_rings[i]->reg_idx), 0);
3752 }
3753
3754
3755 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3756 for (i = vsi->base_vector;
3757 i < (vsi->num_q_vectors + vsi->base_vector); i++)
3758 wr32(hw, I40E_PFINT_DYN_CTLN(i - 1), 0);
3759
3760 i40e_flush(hw);
3761 for (i = 0; i < vsi->num_q_vectors; i++)
3762 synchronize_irq(pf->msix_entries[i + base].vector);
3763 } else {
3764
3765 wr32(hw, I40E_PFINT_ICR0_ENA, 0);
3766 wr32(hw, I40E_PFINT_DYN_CTL0, 0);
3767 i40e_flush(hw);
3768 synchronize_irq(pf->pdev->irq);
3769 }
3770}
3771
3772
3773
3774
3775
3776static int i40e_vsi_enable_irq(struct i40e_vsi *vsi)
3777{
3778 struct i40e_pf *pf = vsi->back;
3779 int i;
3780
3781 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
3782 for (i = 0; i < vsi->num_q_vectors; i++)
3783 i40e_irq_dynamic_enable(vsi, i);
3784 } else {
3785 i40e_irq_dynamic_enable_icr0(pf);
3786 }
3787
3788 i40e_flush(&pf->hw);
3789 return 0;
3790}
3791
3792
3793
3794
3795
3796static void i40e_free_misc_vector(struct i40e_pf *pf)
3797{
3798
3799 wr32(&pf->hw, I40E_PFINT_ICR0_ENA, 0);
3800 i40e_flush(&pf->hw);
3801
3802 if (pf->flags & I40E_FLAG_MSIX_ENABLED && pf->msix_entries) {
3803 synchronize_irq(pf->msix_entries[0].vector);
3804 free_irq(pf->msix_entries[0].vector, pf);
3805 clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state);
3806 }
3807}
3808
3809
3810
3811
3812
3813
3814
3815
3816
3817
3818static irqreturn_t i40e_intr(int irq, void *data)
3819{
3820 struct i40e_pf *pf = (struct i40e_pf *)data;
3821 struct i40e_hw *hw = &pf->hw;
3822 irqreturn_t ret = IRQ_NONE;
3823 u32 icr0, icr0_remaining;
3824 u32 val, ena_mask;
3825
3826 icr0 = rd32(hw, I40E_PFINT_ICR0);
3827 ena_mask = rd32(hw, I40E_PFINT_ICR0_ENA);
3828
3829
3830 if ((icr0 & I40E_PFINT_ICR0_INTEVENT_MASK) == 0)
3831 goto enable_intr;
3832
3833
3834 if (((icr0 & ~I40E_PFINT_ICR0_INTEVENT_MASK) == 0) ||
3835 (icr0 & I40E_PFINT_ICR0_SWINT_MASK))
3836 pf->sw_int_count++;
3837
3838 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
3839 (icr0 & I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK)) {
3840 ena_mask &= ~I40E_PFINT_ICR0_ENA_PE_CRITERR_MASK;
3841 dev_dbg(&pf->pdev->dev, "cleared PE_CRITERR\n");
3842 set_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
3843 }
3844
3845
3846 if (icr0 & I40E_PFINT_ICR0_QUEUE_0_MASK) {
3847 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
3848 struct i40e_q_vector *q_vector = vsi->q_vectors[0];
3849
3850
3851
3852
3853
3854
3855
3856 if (!test_bit(__I40E_DOWN, pf->state))
3857 napi_schedule_irqoff(&q_vector->napi);
3858 }
3859
3860 if (icr0 & I40E_PFINT_ICR0_ADMINQ_MASK) {
3861 ena_mask &= ~I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
3862 set_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state);
3863 i40e_debug(&pf->hw, I40E_DEBUG_NVM, "AdminQ event\n");
3864 }
3865
3866 if (icr0 & I40E_PFINT_ICR0_MAL_DETECT_MASK) {
3867 ena_mask &= ~I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
3868 set_bit(__I40E_MDD_EVENT_PENDING, pf->state);
3869 }
3870
3871 if (icr0 & I40E_PFINT_ICR0_VFLR_MASK) {
3872 ena_mask &= ~I40E_PFINT_ICR0_ENA_VFLR_MASK;
3873 set_bit(__I40E_VFLR_EVENT_PENDING, pf->state);
3874 }
3875
3876 if (icr0 & I40E_PFINT_ICR0_GRST_MASK) {
3877 if (!test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
3878 set_bit(__I40E_RESET_INTR_RECEIVED, pf->state);
3879 ena_mask &= ~I40E_PFINT_ICR0_ENA_GRST_MASK;
3880 val = rd32(hw, I40E_GLGEN_RSTAT);
3881 val = (val & I40E_GLGEN_RSTAT_RESET_TYPE_MASK)
3882 >> I40E_GLGEN_RSTAT_RESET_TYPE_SHIFT;
3883 if (val == I40E_RESET_CORER) {
3884 pf->corer_count++;
3885 } else if (val == I40E_RESET_GLOBR) {
3886 pf->globr_count++;
3887 } else if (val == I40E_RESET_EMPR) {
3888 pf->empr_count++;
3889 set_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state);
3890 }
3891 }
3892
3893 if (icr0 & I40E_PFINT_ICR0_HMC_ERR_MASK) {
3894 icr0 &= ~I40E_PFINT_ICR0_HMC_ERR_MASK;
3895 dev_info(&pf->pdev->dev, "HMC error interrupt\n");
3896 dev_info(&pf->pdev->dev, "HMC error info 0x%x, HMC error data 0x%x\n",
3897 rd32(hw, I40E_PFHMC_ERRORINFO),
3898 rd32(hw, I40E_PFHMC_ERRORDATA));
3899 }
3900
3901 if (icr0 & I40E_PFINT_ICR0_TIMESYNC_MASK) {
3902 u32 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_0);
3903
3904 if (prttsyn_stat & I40E_PRTTSYN_STAT_0_TXTIME_MASK) {
3905 icr0 &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
3906 i40e_ptp_tx_hwtstamp(pf);
3907 }
3908 }
3909
3910
3911
3912
3913
3914 icr0_remaining = icr0 & ena_mask;
3915 if (icr0_remaining) {
3916 dev_info(&pf->pdev->dev, "unhandled interrupt icr0=0x%08x\n",
3917 icr0_remaining);
3918 if ((icr0_remaining & I40E_PFINT_ICR0_PE_CRITERR_MASK) ||
3919 (icr0_remaining & I40E_PFINT_ICR0_PCI_EXCEPTION_MASK) ||
3920 (icr0_remaining & I40E_PFINT_ICR0_ECC_ERR_MASK)) {
3921 dev_info(&pf->pdev->dev, "device will be reset\n");
3922 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
3923 i40e_service_event_schedule(pf);
3924 }
3925 ena_mask &= ~icr0_remaining;
3926 }
3927 ret = IRQ_HANDLED;
3928
3929enable_intr:
3930
3931 wr32(hw, I40E_PFINT_ICR0_ENA, ena_mask);
3932 if (!test_bit(__I40E_DOWN, pf->state)) {
3933 i40e_service_event_schedule(pf);
3934 i40e_irq_dynamic_enable_icr0(pf);
3935 }
3936
3937 return ret;
3938}
3939
3940
3941
3942
3943
3944
3945
3946
3947static bool i40e_clean_fdir_tx_irq(struct i40e_ring *tx_ring, int budget)
3948{
3949 struct i40e_vsi *vsi = tx_ring->vsi;
3950 u16 i = tx_ring->next_to_clean;
3951 struct i40e_tx_buffer *tx_buf;
3952 struct i40e_tx_desc *tx_desc;
3953
3954 tx_buf = &tx_ring->tx_bi[i];
3955 tx_desc = I40E_TX_DESC(tx_ring, i);
3956 i -= tx_ring->count;
3957
3958 do {
3959 struct i40e_tx_desc *eop_desc = tx_buf->next_to_watch;
3960
3961
3962 if (!eop_desc)
3963 break;
3964
3965
3966 smp_rmb();
3967
3968
3969 if (!(eop_desc->cmd_type_offset_bsz &
3970 cpu_to_le64(I40E_TX_DESC_DTYPE_DESC_DONE)))
3971 break;
3972
3973
3974 tx_buf->next_to_watch = NULL;
3975
3976 tx_desc->buffer_addr = 0;
3977 tx_desc->cmd_type_offset_bsz = 0;
3978
3979 tx_buf++;
3980 tx_desc++;
3981 i++;
3982 if (unlikely(!i)) {
3983 i -= tx_ring->count;
3984 tx_buf = tx_ring->tx_bi;
3985 tx_desc = I40E_TX_DESC(tx_ring, 0);
3986 }
3987
3988 dma_unmap_single(tx_ring->dev,
3989 dma_unmap_addr(tx_buf, dma),
3990 dma_unmap_len(tx_buf, len),
3991 DMA_TO_DEVICE);
3992 if (tx_buf->tx_flags & I40E_TX_FLAGS_FD_SB)
3993 kfree(tx_buf->raw_buf);
3994
3995 tx_buf->raw_buf = NULL;
3996 tx_buf->tx_flags = 0;
3997 tx_buf->next_to_watch = NULL;
3998 dma_unmap_len_set(tx_buf, len, 0);
3999 tx_desc->buffer_addr = 0;
4000 tx_desc->cmd_type_offset_bsz = 0;
4001
4002
4003 tx_buf++;
4004 tx_desc++;
4005 i++;
4006 if (unlikely(!i)) {
4007 i -= tx_ring->count;
4008 tx_buf = tx_ring->tx_bi;
4009 tx_desc = I40E_TX_DESC(tx_ring, 0);
4010 }
4011
4012
4013 budget--;
4014 } while (likely(budget));
4015
4016 i += tx_ring->count;
4017 tx_ring->next_to_clean = i;
4018
4019 if (vsi->back->flags & I40E_FLAG_MSIX_ENABLED)
4020 i40e_irq_dynamic_enable(vsi, tx_ring->q_vector->v_idx);
4021
4022 return budget > 0;
4023}
4024
4025
4026
4027
4028
4029
4030static irqreturn_t i40e_fdir_clean_ring(int irq, void *data)
4031{
4032 struct i40e_q_vector *q_vector = data;
4033 struct i40e_vsi *vsi;
4034
4035 if (!q_vector->tx.ring)
4036 return IRQ_HANDLED;
4037
4038 vsi = q_vector->tx.ring->vsi;
4039 i40e_clean_fdir_tx_irq(q_vector->tx.ring, vsi->work_limit);
4040
4041 return IRQ_HANDLED;
4042}
4043
4044
4045
4046
4047
4048
4049
4050static void i40e_map_vector_to_qp(struct i40e_vsi *vsi, int v_idx, int qp_idx)
4051{
4052 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
4053 struct i40e_ring *tx_ring = vsi->tx_rings[qp_idx];
4054 struct i40e_ring *rx_ring = vsi->rx_rings[qp_idx];
4055
4056 tx_ring->q_vector = q_vector;
4057 tx_ring->next = q_vector->tx.ring;
4058 q_vector->tx.ring = tx_ring;
4059 q_vector->tx.count++;
4060
4061
4062 if (i40e_enabled_xdp_vsi(vsi)) {
4063 struct i40e_ring *xdp_ring = vsi->xdp_rings[qp_idx];
4064
4065 xdp_ring->q_vector = q_vector;
4066 xdp_ring->next = q_vector->tx.ring;
4067 q_vector->tx.ring = xdp_ring;
4068 q_vector->tx.count++;
4069 }
4070
4071 rx_ring->q_vector = q_vector;
4072 rx_ring->next = q_vector->rx.ring;
4073 q_vector->rx.ring = rx_ring;
4074 q_vector->rx.count++;
4075}
4076
4077
4078
4079
4080
4081
4082
4083
4084
4085
4086static void i40e_vsi_map_rings_to_vectors(struct i40e_vsi *vsi)
4087{
4088 int qp_remaining = vsi->num_queue_pairs;
4089 int q_vectors = vsi->num_q_vectors;
4090 int num_ringpairs;
4091 int v_start = 0;
4092 int qp_idx = 0;
4093
4094
4095
4096
4097
4098
4099
4100
4101 for (; v_start < q_vectors; v_start++) {
4102 struct i40e_q_vector *q_vector = vsi->q_vectors[v_start];
4103
4104 num_ringpairs = DIV_ROUND_UP(qp_remaining, q_vectors - v_start);
4105
4106 q_vector->num_ringpairs = num_ringpairs;
4107 q_vector->reg_idx = q_vector->v_idx + vsi->base_vector - 1;
4108
4109 q_vector->rx.count = 0;
4110 q_vector->tx.count = 0;
4111 q_vector->rx.ring = NULL;
4112 q_vector->tx.ring = NULL;
4113
4114 while (num_ringpairs--) {
4115 i40e_map_vector_to_qp(vsi, v_start, qp_idx);
4116 qp_idx++;
4117 qp_remaining--;
4118 }
4119 }
4120}
4121
4122
4123
4124
4125
4126
4127static int i40e_vsi_request_irq(struct i40e_vsi *vsi, char *basename)
4128{
4129 struct i40e_pf *pf = vsi->back;
4130 int err;
4131
4132 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
4133 err = i40e_vsi_request_irq_msix(vsi, basename);
4134 else if (pf->flags & I40E_FLAG_MSI_ENABLED)
4135 err = request_irq(pf->pdev->irq, i40e_intr, 0,
4136 pf->int_name, pf);
4137 else
4138 err = request_irq(pf->pdev->irq, i40e_intr, IRQF_SHARED,
4139 pf->int_name, pf);
4140
4141 if (err)
4142 dev_info(&pf->pdev->dev, "request_irq failed, Error %d\n", err);
4143
4144 return err;
4145}
4146
4147#ifdef CONFIG_NET_POLL_CONTROLLER
4148
4149
4150
4151
4152
4153
4154
4155static void i40e_netpoll(struct net_device *netdev)
4156{
4157 struct i40e_netdev_priv *np = netdev_priv(netdev);
4158 struct i40e_vsi *vsi = np->vsi;
4159 struct i40e_pf *pf = vsi->back;
4160 int i;
4161
4162
4163 if (test_bit(__I40E_VSI_DOWN, vsi->state))
4164 return;
4165
4166 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4167 for (i = 0; i < vsi->num_q_vectors; i++)
4168 i40e_msix_clean_rings(0, vsi->q_vectors[i]);
4169 } else {
4170 i40e_intr(pf->pdev->irq, netdev);
4171 }
4172}
4173#endif
4174
4175#define I40E_QTX_ENA_WAIT_COUNT 50
4176
4177
4178
4179
4180
4181
4182
4183
4184
4185
4186
4187
4188static int i40e_pf_txq_wait(struct i40e_pf *pf, int pf_q, bool enable)
4189{
4190 int i;
4191 u32 tx_reg;
4192
4193 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
4194 tx_reg = rd32(&pf->hw, I40E_QTX_ENA(pf_q));
4195 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
4196 break;
4197
4198 usleep_range(10, 20);
4199 }
4200 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
4201 return -ETIMEDOUT;
4202
4203 return 0;
4204}
4205
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216static void i40e_control_tx_q(struct i40e_pf *pf, int pf_q, bool enable)
4217{
4218 struct i40e_hw *hw = &pf->hw;
4219 u32 tx_reg;
4220 int i;
4221
4222
4223 i40e_pre_tx_queue_cfg(&pf->hw, pf_q, enable);
4224 if (!enable)
4225 usleep_range(10, 20);
4226
4227 for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) {
4228 tx_reg = rd32(hw, I40E_QTX_ENA(pf_q));
4229 if (((tx_reg >> I40E_QTX_ENA_QENA_REQ_SHIFT) & 1) ==
4230 ((tx_reg >> I40E_QTX_ENA_QENA_STAT_SHIFT) & 1))
4231 break;
4232 usleep_range(1000, 2000);
4233 }
4234
4235
4236 if (enable == !!(tx_reg & I40E_QTX_ENA_QENA_STAT_MASK))
4237 return;
4238
4239
4240 if (enable) {
4241 wr32(hw, I40E_QTX_HEAD(pf_q), 0);
4242 tx_reg |= I40E_QTX_ENA_QENA_REQ_MASK;
4243 } else {
4244 tx_reg &= ~I40E_QTX_ENA_QENA_REQ_MASK;
4245 }
4246
4247 wr32(hw, I40E_QTX_ENA(pf_q), tx_reg);
4248}
4249
4250
4251
4252
4253
4254
4255
4256
4257
4258static int i40e_control_wait_tx_q(int seid, struct i40e_pf *pf, int pf_q,
4259 bool is_xdp, bool enable)
4260{
4261 int ret;
4262
4263 i40e_control_tx_q(pf, pf_q, enable);
4264
4265
4266 ret = i40e_pf_txq_wait(pf, pf_q, enable);
4267 if (ret) {
4268 dev_info(&pf->pdev->dev,
4269 "VSI seid %d %sTx ring %d %sable timeout\n",
4270 seid, (is_xdp ? "XDP " : ""), pf_q,
4271 (enable ? "en" : "dis"));
4272 }
4273
4274 return ret;
4275}
4276
4277
4278
4279
4280
4281
4282static int i40e_vsi_control_tx(struct i40e_vsi *vsi, bool enable)
4283{
4284 struct i40e_pf *pf = vsi->back;
4285 int i, pf_q, ret = 0;
4286
4287 pf_q = vsi->base_queue;
4288 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4289 ret = i40e_control_wait_tx_q(vsi->seid, pf,
4290 pf_q,
4291 false , enable);
4292 if (ret)
4293 break;
4294
4295 if (!i40e_enabled_xdp_vsi(vsi))
4296 continue;
4297
4298 ret = i40e_control_wait_tx_q(vsi->seid, pf,
4299 pf_q + vsi->alloc_queue_pairs,
4300 true , enable);
4301 if (ret)
4302 break;
4303 }
4304
4305 return ret;
4306}
4307
4308
4309
4310
4311
4312
4313
4314
4315
4316
4317
4318
4319static int i40e_pf_rxq_wait(struct i40e_pf *pf, int pf_q, bool enable)
4320{
4321 int i;
4322 u32 rx_reg;
4323
4324 for (i = 0; i < I40E_QUEUE_WAIT_RETRY_LIMIT; i++) {
4325 rx_reg = rd32(&pf->hw, I40E_QRX_ENA(pf_q));
4326 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
4327 break;
4328
4329 usleep_range(10, 20);
4330 }
4331 if (i >= I40E_QUEUE_WAIT_RETRY_LIMIT)
4332 return -ETIMEDOUT;
4333
4334 return 0;
4335}
4336
4337
4338
4339
4340
4341
4342
4343
4344
4345
4346
4347static void i40e_control_rx_q(struct i40e_pf *pf, int pf_q, bool enable)
4348{
4349 struct i40e_hw *hw = &pf->hw;
4350 u32 rx_reg;
4351 int i;
4352
4353 for (i = 0; i < I40E_QTX_ENA_WAIT_COUNT; i++) {
4354 rx_reg = rd32(hw, I40E_QRX_ENA(pf_q));
4355 if (((rx_reg >> I40E_QRX_ENA_QENA_REQ_SHIFT) & 1) ==
4356 ((rx_reg >> I40E_QRX_ENA_QENA_STAT_SHIFT) & 1))
4357 break;
4358 usleep_range(1000, 2000);
4359 }
4360
4361
4362 if (enable == !!(rx_reg & I40E_QRX_ENA_QENA_STAT_MASK))
4363 return;
4364
4365
4366 if (enable)
4367 rx_reg |= I40E_QRX_ENA_QENA_REQ_MASK;
4368 else
4369 rx_reg &= ~I40E_QRX_ENA_QENA_REQ_MASK;
4370
4371 wr32(hw, I40E_QRX_ENA(pf_q), rx_reg);
4372}
4373
4374
4375
4376
4377
4378
4379static int i40e_vsi_control_rx(struct i40e_vsi *vsi, bool enable)
4380{
4381 struct i40e_pf *pf = vsi->back;
4382 int i, pf_q, ret = 0;
4383
4384 pf_q = vsi->base_queue;
4385 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4386 i40e_control_rx_q(pf, pf_q, enable);
4387
4388
4389 ret = i40e_pf_rxq_wait(pf, pf_q, enable);
4390 if (ret) {
4391 dev_info(&pf->pdev->dev,
4392 "VSI seid %d Rx ring %d %sable timeout\n",
4393 vsi->seid, pf_q, (enable ? "en" : "dis"));
4394 break;
4395 }
4396 }
4397
4398
4399
4400
4401 if (!enable)
4402 mdelay(50);
4403
4404 return ret;
4405}
4406
4407
4408
4409
4410
4411int i40e_vsi_start_rings(struct i40e_vsi *vsi)
4412{
4413 int ret = 0;
4414
4415
4416 ret = i40e_vsi_control_rx(vsi, true);
4417 if (ret)
4418 return ret;
4419 ret = i40e_vsi_control_tx(vsi, true);
4420
4421 return ret;
4422}
4423
4424
4425
4426
4427
4428void i40e_vsi_stop_rings(struct i40e_vsi *vsi)
4429{
4430
4431 if (test_bit(__I40E_PORT_SUSPENDED, vsi->back->state))
4432 return i40e_vsi_stop_rings_no_wait(vsi);
4433
4434
4435
4436
4437 i40e_vsi_control_tx(vsi, false);
4438 i40e_vsi_control_rx(vsi, false);
4439}
4440
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450
4451
4452void i40e_vsi_stop_rings_no_wait(struct i40e_vsi *vsi)
4453{
4454 struct i40e_pf *pf = vsi->back;
4455 int i, pf_q;
4456
4457 pf_q = vsi->base_queue;
4458 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4459 i40e_control_tx_q(pf, pf_q, false);
4460 i40e_control_rx_q(pf, pf_q, false);
4461 }
4462}
4463
4464
4465
4466
4467
4468static void i40e_vsi_free_irq(struct i40e_vsi *vsi)
4469{
4470 struct i40e_pf *pf = vsi->back;
4471 struct i40e_hw *hw = &pf->hw;
4472 int base = vsi->base_vector;
4473 u32 val, qp;
4474 int i;
4475
4476 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4477 if (!vsi->q_vectors)
4478 return;
4479
4480 if (!vsi->irqs_ready)
4481 return;
4482
4483 vsi->irqs_ready = false;
4484 for (i = 0; i < vsi->num_q_vectors; i++) {
4485 int irq_num;
4486 u16 vector;
4487
4488 vector = i + base;
4489 irq_num = pf->msix_entries[vector].vector;
4490
4491
4492 if (!vsi->q_vectors[i] ||
4493 !vsi->q_vectors[i]->num_ringpairs)
4494 continue;
4495
4496
4497 irq_set_affinity_notifier(irq_num, NULL);
4498
4499 irq_set_affinity_hint(irq_num, NULL);
4500 synchronize_irq(irq_num);
4501 free_irq(irq_num, vsi->q_vectors[i]);
4502
4503
4504
4505
4506
4507
4508
4509
4510 val = rd32(hw, I40E_PFINT_LNKLSTN(vector - 1));
4511 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4512 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4513 val |= I40E_QUEUE_END_OF_LIST
4514 << I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4515 wr32(hw, I40E_PFINT_LNKLSTN(vector - 1), val);
4516
4517 while (qp != I40E_QUEUE_END_OF_LIST) {
4518 u32 next;
4519
4520 val = rd32(hw, I40E_QINT_RQCTL(qp));
4521
4522 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4523 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4524 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4525 I40E_QINT_RQCTL_INTEVENT_MASK);
4526
4527 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4528 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4529
4530 wr32(hw, I40E_QINT_RQCTL(qp), val);
4531
4532 val = rd32(hw, I40E_QINT_TQCTL(qp));
4533
4534 next = (val & I40E_QINT_TQCTL_NEXTQ_INDX_MASK)
4535 >> I40E_QINT_TQCTL_NEXTQ_INDX_SHIFT;
4536
4537 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4538 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4539 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4540 I40E_QINT_TQCTL_INTEVENT_MASK);
4541
4542 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4543 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4544
4545 wr32(hw, I40E_QINT_TQCTL(qp), val);
4546 qp = next;
4547 }
4548 }
4549 } else {
4550 free_irq(pf->pdev->irq, pf);
4551
4552 val = rd32(hw, I40E_PFINT_LNKLST0);
4553 qp = (val & I40E_PFINT_LNKLSTN_FIRSTQ_INDX_MASK)
4554 >> I40E_PFINT_LNKLSTN_FIRSTQ_INDX_SHIFT;
4555 val |= I40E_QUEUE_END_OF_LIST
4556 << I40E_PFINT_LNKLST0_FIRSTQ_INDX_SHIFT;
4557 wr32(hw, I40E_PFINT_LNKLST0, val);
4558
4559 val = rd32(hw, I40E_QINT_RQCTL(qp));
4560 val &= ~(I40E_QINT_RQCTL_MSIX_INDX_MASK |
4561 I40E_QINT_RQCTL_MSIX0_INDX_MASK |
4562 I40E_QINT_RQCTL_CAUSE_ENA_MASK |
4563 I40E_QINT_RQCTL_INTEVENT_MASK);
4564
4565 val |= (I40E_QINT_RQCTL_ITR_INDX_MASK |
4566 I40E_QINT_RQCTL_NEXTQ_INDX_MASK);
4567
4568 wr32(hw, I40E_QINT_RQCTL(qp), val);
4569
4570 val = rd32(hw, I40E_QINT_TQCTL(qp));
4571
4572 val &= ~(I40E_QINT_TQCTL_MSIX_INDX_MASK |
4573 I40E_QINT_TQCTL_MSIX0_INDX_MASK |
4574 I40E_QINT_TQCTL_CAUSE_ENA_MASK |
4575 I40E_QINT_TQCTL_INTEVENT_MASK);
4576
4577 val |= (I40E_QINT_TQCTL_ITR_INDX_MASK |
4578 I40E_QINT_TQCTL_NEXTQ_INDX_MASK);
4579
4580 wr32(hw, I40E_QINT_TQCTL(qp), val);
4581 }
4582}
4583
4584
4585
4586
4587
4588
4589
4590
4591
4592
4593static void i40e_free_q_vector(struct i40e_vsi *vsi, int v_idx)
4594{
4595 struct i40e_q_vector *q_vector = vsi->q_vectors[v_idx];
4596 struct i40e_ring *ring;
4597
4598 if (!q_vector)
4599 return;
4600
4601
4602 i40e_for_each_ring(ring, q_vector->tx)
4603 ring->q_vector = NULL;
4604
4605 i40e_for_each_ring(ring, q_vector->rx)
4606 ring->q_vector = NULL;
4607
4608
4609 if (vsi->netdev)
4610 netif_napi_del(&q_vector->napi);
4611
4612 vsi->q_vectors[v_idx] = NULL;
4613
4614 kfree_rcu(q_vector, rcu);
4615}
4616
4617
4618
4619
4620
4621
4622
4623
4624static void i40e_vsi_free_q_vectors(struct i40e_vsi *vsi)
4625{
4626 int v_idx;
4627
4628 for (v_idx = 0; v_idx < vsi->num_q_vectors; v_idx++)
4629 i40e_free_q_vector(vsi, v_idx);
4630}
4631
4632
4633
4634
4635
4636static void i40e_reset_interrupt_capability(struct i40e_pf *pf)
4637{
4638
4639 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
4640 pci_disable_msix(pf->pdev);
4641 kfree(pf->msix_entries);
4642 pf->msix_entries = NULL;
4643 kfree(pf->irq_pile);
4644 pf->irq_pile = NULL;
4645 } else if (pf->flags & I40E_FLAG_MSI_ENABLED) {
4646 pci_disable_msi(pf->pdev);
4647 }
4648 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
4649}
4650
4651
4652
4653
4654
4655
4656
4657
4658static void i40e_clear_interrupt_scheme(struct i40e_pf *pf)
4659{
4660 int i;
4661
4662 i40e_free_misc_vector(pf);
4663
4664 i40e_put_lump(pf->irq_pile, pf->iwarp_base_vector,
4665 I40E_IWARP_IRQ_PILE_ID);
4666
4667 i40e_put_lump(pf->irq_pile, 0, I40E_PILE_VALID_BIT-1);
4668 for (i = 0; i < pf->num_alloc_vsi; i++)
4669 if (pf->vsi[i])
4670 i40e_vsi_free_q_vectors(pf->vsi[i]);
4671 i40e_reset_interrupt_capability(pf);
4672}
4673
4674
4675
4676
4677
4678static void i40e_napi_enable_all(struct i40e_vsi *vsi)
4679{
4680 int q_idx;
4681
4682 if (!vsi->netdev)
4683 return;
4684
4685 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) {
4686 struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx];
4687
4688 if (q_vector->rx.ring || q_vector->tx.ring)
4689 napi_enable(&q_vector->napi);
4690 }
4691}
4692
4693
4694
4695
4696
4697static void i40e_napi_disable_all(struct i40e_vsi *vsi)
4698{
4699 int q_idx;
4700
4701 if (!vsi->netdev)
4702 return;
4703
4704 for (q_idx = 0; q_idx < vsi->num_q_vectors; q_idx++) {
4705 struct i40e_q_vector *q_vector = vsi->q_vectors[q_idx];
4706
4707 if (q_vector->rx.ring || q_vector->tx.ring)
4708 napi_disable(&q_vector->napi);
4709 }
4710}
4711
4712
4713
4714
4715
4716static void i40e_vsi_close(struct i40e_vsi *vsi)
4717{
4718 struct i40e_pf *pf = vsi->back;
4719 if (!test_and_set_bit(__I40E_VSI_DOWN, vsi->state))
4720 i40e_down(vsi);
4721 i40e_vsi_free_irq(vsi);
4722 i40e_vsi_free_tx_resources(vsi);
4723 i40e_vsi_free_rx_resources(vsi);
4724 vsi->current_netdev_flags = 0;
4725 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
4726 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
4727 set_bit(__I40E_CLIENT_RESET, pf->state);
4728}
4729
4730
4731
4732
4733
4734static void i40e_quiesce_vsi(struct i40e_vsi *vsi)
4735{
4736 if (test_bit(__I40E_VSI_DOWN, vsi->state))
4737 return;
4738
4739 set_bit(__I40E_VSI_NEEDS_RESTART, vsi->state);
4740 if (vsi->netdev && netif_running(vsi->netdev))
4741 vsi->netdev->netdev_ops->ndo_stop(vsi->netdev);
4742 else
4743 i40e_vsi_close(vsi);
4744}
4745
4746
4747
4748
4749
4750static void i40e_unquiesce_vsi(struct i40e_vsi *vsi)
4751{
4752 if (!test_and_clear_bit(__I40E_VSI_NEEDS_RESTART, vsi->state))
4753 return;
4754
4755 if (vsi->netdev && netif_running(vsi->netdev))
4756 vsi->netdev->netdev_ops->ndo_open(vsi->netdev);
4757 else
4758 i40e_vsi_open(vsi);
4759}
4760
4761
4762
4763
4764
4765static void i40e_pf_quiesce_all_vsi(struct i40e_pf *pf)
4766{
4767 int v;
4768
4769 for (v = 0; v < pf->num_alloc_vsi; v++) {
4770 if (pf->vsi[v])
4771 i40e_quiesce_vsi(pf->vsi[v]);
4772 }
4773}
4774
4775
4776
4777
4778
4779static void i40e_pf_unquiesce_all_vsi(struct i40e_pf *pf)
4780{
4781 int v;
4782
4783 for (v = 0; v < pf->num_alloc_vsi; v++) {
4784 if (pf->vsi[v])
4785 i40e_unquiesce_vsi(pf->vsi[v]);
4786 }
4787}
4788
4789
4790
4791
4792
4793
4794
4795int i40e_vsi_wait_queues_disabled(struct i40e_vsi *vsi)
4796{
4797 struct i40e_pf *pf = vsi->back;
4798 int i, pf_q, ret;
4799
4800 pf_q = vsi->base_queue;
4801 for (i = 0; i < vsi->num_queue_pairs; i++, pf_q++) {
4802
4803 ret = i40e_pf_txq_wait(pf, pf_q, false);
4804 if (ret) {
4805 dev_info(&pf->pdev->dev,
4806 "VSI seid %d Tx ring %d disable timeout\n",
4807 vsi->seid, pf_q);
4808 return ret;
4809 }
4810
4811 if (!i40e_enabled_xdp_vsi(vsi))
4812 goto wait_rx;
4813
4814
4815 ret = i40e_pf_txq_wait(pf, pf_q + vsi->alloc_queue_pairs,
4816 false);
4817 if (ret) {
4818 dev_info(&pf->pdev->dev,
4819 "VSI seid %d XDP Tx ring %d disable timeout\n",
4820 vsi->seid, pf_q);
4821 return ret;
4822 }
4823wait_rx:
4824
4825 ret = i40e_pf_rxq_wait(pf, pf_q, false);
4826 if (ret) {
4827 dev_info(&pf->pdev->dev,
4828 "VSI seid %d Rx ring %d disable timeout\n",
4829 vsi->seid, pf_q);
4830 return ret;
4831 }
4832 }
4833
4834 return 0;
4835}
4836
4837#ifdef CONFIG_I40E_DCB
4838
4839
4840
4841
4842
4843
4844
4845static int i40e_pf_wait_queues_disabled(struct i40e_pf *pf)
4846{
4847 int v, ret = 0;
4848
4849 for (v = 0; v < pf->hw.func_caps.num_vsis; v++) {
4850 if (pf->vsi[v]) {
4851 ret = i40e_vsi_wait_queues_disabled(pf->vsi[v]);
4852 if (ret)
4853 break;
4854 }
4855 }
4856
4857 return ret;
4858}
4859
4860#endif
4861
4862
4863
4864
4865
4866
4867
4868
4869static u8 i40e_get_iscsi_tc_map(struct i40e_pf *pf)
4870{
4871 struct i40e_dcb_app_priority_table app;
4872 struct i40e_hw *hw = &pf->hw;
4873 u8 enabled_tc = 1;
4874 u8 tc, i;
4875
4876 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4877
4878 for (i = 0; i < dcbcfg->numapps; i++) {
4879 app = dcbcfg->app[i];
4880 if (app.selector == I40E_APP_SEL_TCPIP &&
4881 app.protocolid == I40E_APP_PROTOID_ISCSI) {
4882 tc = dcbcfg->etscfg.prioritytable[app.priority];
4883 enabled_tc |= BIT(tc);
4884 break;
4885 }
4886 }
4887
4888 return enabled_tc;
4889}
4890
4891
4892
4893
4894
4895
4896
4897static u8 i40e_dcb_get_num_tc(struct i40e_dcbx_config *dcbcfg)
4898{
4899 int i, tc_unused = 0;
4900 u8 num_tc = 0;
4901 u8 ret = 0;
4902
4903
4904
4905
4906
4907 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++)
4908 num_tc |= BIT(dcbcfg->etscfg.prioritytable[i]);
4909
4910
4911
4912
4913 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
4914 if (num_tc & BIT(i)) {
4915 if (!tc_unused) {
4916 ret++;
4917 } else {
4918 pr_err("Non-contiguous TC - Disabling DCB\n");
4919 return 1;
4920 }
4921 } else {
4922 tc_unused = 1;
4923 }
4924 }
4925
4926
4927 if (!ret)
4928 ret = 1;
4929
4930 return ret;
4931}
4932
4933
4934
4935
4936
4937
4938
4939
4940static u8 i40e_dcb_get_enabled_tc(struct i40e_dcbx_config *dcbcfg)
4941{
4942 u8 num_tc = i40e_dcb_get_num_tc(dcbcfg);
4943 u8 enabled_tc = 1;
4944 u8 i;
4945
4946 for (i = 0; i < num_tc; i++)
4947 enabled_tc |= BIT(i);
4948
4949 return enabled_tc;
4950}
4951
4952
4953
4954
4955
4956
4957
4958
4959static u8 i40e_mqprio_get_enabled_tc(struct i40e_pf *pf)
4960{
4961 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
4962 u8 num_tc = vsi->mqprio_qopt.qopt.num_tc;
4963 u8 enabled_tc = 1, i;
4964
4965 for (i = 1; i < num_tc; i++)
4966 enabled_tc |= BIT(i);
4967 return enabled_tc;
4968}
4969
4970
4971
4972
4973
4974
4975
4976static u8 i40e_pf_get_num_tc(struct i40e_pf *pf)
4977{
4978 struct i40e_hw *hw = &pf->hw;
4979 u8 i, enabled_tc = 1;
4980 u8 num_tc = 0;
4981 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
4982
4983 if (pf->flags & I40E_FLAG_TC_MQPRIO)
4984 return pf->vsi[pf->lan_vsi]->mqprio_qopt.qopt.num_tc;
4985
4986
4987 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
4988 return 1;
4989
4990
4991 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
4992 return i40e_dcb_get_num_tc(dcbcfg);
4993
4994
4995 if (pf->hw.func_caps.iscsi)
4996 enabled_tc = i40e_get_iscsi_tc_map(pf);
4997 else
4998 return 1;
4999
5000 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5001 if (enabled_tc & BIT(i))
5002 num_tc++;
5003 }
5004 return num_tc;
5005}
5006
5007
5008
5009
5010
5011
5012
5013static u8 i40e_pf_get_tc_map(struct i40e_pf *pf)
5014{
5015 if (pf->flags & I40E_FLAG_TC_MQPRIO)
5016 return i40e_mqprio_get_enabled_tc(pf);
5017
5018
5019
5020
5021 if (!(pf->flags & I40E_FLAG_DCB_ENABLED))
5022 return I40E_DEFAULT_TRAFFIC_CLASS;
5023
5024
5025 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
5026 return i40e_dcb_get_enabled_tc(&pf->hw.local_dcbx_config);
5027
5028
5029 if (pf->hw.func_caps.iscsi)
5030 return i40e_get_iscsi_tc_map(pf);
5031 else
5032 return I40E_DEFAULT_TRAFFIC_CLASS;
5033}
5034
5035
5036
5037
5038
5039
5040
5041static int i40e_vsi_get_bw_info(struct i40e_vsi *vsi)
5042{
5043 struct i40e_aqc_query_vsi_ets_sla_config_resp bw_ets_config = {0};
5044 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
5045 struct i40e_pf *pf = vsi->back;
5046 struct i40e_hw *hw = &pf->hw;
5047 i40e_status ret;
5048 u32 tc_bw_max;
5049 int i;
5050
5051
5052 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid, &bw_config, NULL);
5053 if (ret) {
5054 dev_info(&pf->pdev->dev,
5055 "couldn't get PF vsi bw config, err %s aq_err %s\n",
5056 i40e_stat_str(&pf->hw, ret),
5057 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5058 return -EINVAL;
5059 }
5060
5061
5062 ret = i40e_aq_query_vsi_ets_sla_config(hw, vsi->seid, &bw_ets_config,
5063 NULL);
5064 if (ret) {
5065 dev_info(&pf->pdev->dev,
5066 "couldn't get PF vsi ets bw config, err %s aq_err %s\n",
5067 i40e_stat_str(&pf->hw, ret),
5068 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5069 return -EINVAL;
5070 }
5071
5072 if (bw_config.tc_valid_bits != bw_ets_config.tc_valid_bits) {
5073 dev_info(&pf->pdev->dev,
5074 "Enabled TCs mismatch from querying VSI BW info 0x%08x 0x%08x\n",
5075 bw_config.tc_valid_bits,
5076 bw_ets_config.tc_valid_bits);
5077
5078 }
5079
5080 vsi->bw_limit = le16_to_cpu(bw_config.port_bw_limit);
5081 vsi->bw_max_quanta = bw_config.max_bw;
5082 tc_bw_max = le16_to_cpu(bw_ets_config.tc_bw_max[0]) |
5083 (le16_to_cpu(bw_ets_config.tc_bw_max[1]) << 16);
5084 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5085 vsi->bw_ets_share_credits[i] = bw_ets_config.share_credits[i];
5086 vsi->bw_ets_limit_credits[i] =
5087 le16_to_cpu(bw_ets_config.credits[i]);
5088
5089 vsi->bw_ets_max_quanta[i] = (u8)((tc_bw_max >> (i*4)) & 0x7);
5090 }
5091
5092 return 0;
5093}
5094
5095
5096
5097
5098
5099
5100
5101
5102
5103static int i40e_vsi_configure_bw_alloc(struct i40e_vsi *vsi, u8 enabled_tc,
5104 u8 *bw_share)
5105{
5106 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
5107 i40e_status ret;
5108 int i;
5109
5110 if (vsi->back->flags & I40E_FLAG_TC_MQPRIO)
5111 return 0;
5112 if (!vsi->mqprio_qopt.qopt.hw) {
5113 ret = i40e_set_bw_limit(vsi, vsi->seid, 0);
5114 if (ret)
5115 dev_info(&vsi->back->pdev->dev,
5116 "Failed to reset tx rate for vsi->seid %u\n",
5117 vsi->seid);
5118 return ret;
5119 }
5120 bw_data.tc_valid_bits = enabled_tc;
5121 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5122 bw_data.tc_bw_credits[i] = bw_share[i];
5123
5124 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, vsi->seid, &bw_data,
5125 NULL);
5126 if (ret) {
5127 dev_info(&vsi->back->pdev->dev,
5128 "AQ command Config VSI BW allocation per TC failed = %d\n",
5129 vsi->back->hw.aq.asq_last_status);
5130 return -EINVAL;
5131 }
5132
5133 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5134 vsi->info.qs_handle[i] = bw_data.qs_handles[i];
5135
5136 return 0;
5137}
5138
5139
5140
5141
5142
5143
5144
5145static void i40e_vsi_config_netdev_tc(struct i40e_vsi *vsi, u8 enabled_tc)
5146{
5147 struct net_device *netdev = vsi->netdev;
5148 struct i40e_pf *pf = vsi->back;
5149 struct i40e_hw *hw = &pf->hw;
5150 u8 netdev_tc = 0;
5151 int i;
5152 struct i40e_dcbx_config *dcbcfg = &hw->local_dcbx_config;
5153
5154 if (!netdev)
5155 return;
5156
5157 if (!enabled_tc) {
5158 netdev_reset_tc(netdev);
5159 return;
5160 }
5161
5162
5163 if (netdev_set_num_tc(netdev, vsi->tc_config.numtc))
5164 return;
5165
5166
5167 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5168
5169
5170
5171
5172
5173
5174
5175 if (vsi->tc_config.enabled_tc & BIT(i))
5176 netdev_set_tc_queue(netdev,
5177 vsi->tc_config.tc_info[i].netdev_tc,
5178 vsi->tc_config.tc_info[i].qcount,
5179 vsi->tc_config.tc_info[i].qoffset);
5180 }
5181
5182 if (pf->flags & I40E_FLAG_TC_MQPRIO)
5183 return;
5184
5185
5186 for (i = 0; i < I40E_MAX_USER_PRIORITY; i++) {
5187
5188 u8 ets_tc = dcbcfg->etscfg.prioritytable[i];
5189
5190 netdev_tc = vsi->tc_config.tc_info[ets_tc].netdev_tc;
5191 netdev_set_prio_tc_map(netdev, i, netdev_tc);
5192 }
5193}
5194
5195
5196
5197
5198
5199
5200static void i40e_vsi_update_queue_map(struct i40e_vsi *vsi,
5201 struct i40e_vsi_context *ctxt)
5202{
5203
5204
5205
5206
5207 vsi->info.mapping_flags = ctxt->info.mapping_flags;
5208 memcpy(&vsi->info.queue_mapping,
5209 &ctxt->info.queue_mapping, sizeof(vsi->info.queue_mapping));
5210 memcpy(&vsi->info.tc_mapping, ctxt->info.tc_mapping,
5211 sizeof(vsi->info.tc_mapping));
5212}
5213
5214
5215
5216
5217
5218
5219
5220
5221
5222
5223
5224
5225
5226
5227static int i40e_vsi_config_tc(struct i40e_vsi *vsi, u8 enabled_tc)
5228{
5229 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
5230 struct i40e_pf *pf = vsi->back;
5231 struct i40e_hw *hw = &pf->hw;
5232 struct i40e_vsi_context ctxt;
5233 int ret = 0;
5234 int i;
5235
5236
5237 if (vsi->tc_config.enabled_tc == enabled_tc &&
5238 vsi->mqprio_qopt.mode != TC_MQPRIO_MODE_CHANNEL)
5239 return ret;
5240
5241
5242 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5243 if (enabled_tc & BIT(i))
5244 bw_share[i] = 1;
5245 }
5246
5247 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
5248 if (ret) {
5249 struct i40e_aqc_query_vsi_bw_config_resp bw_config = {0};
5250
5251 dev_info(&pf->pdev->dev,
5252 "Failed configuring TC map %d for VSI %d\n",
5253 enabled_tc, vsi->seid);
5254 ret = i40e_aq_query_vsi_bw_config(hw, vsi->seid,
5255 &bw_config, NULL);
5256 if (ret) {
5257 dev_info(&pf->pdev->dev,
5258 "Failed querying vsi bw info, err %s aq_err %s\n",
5259 i40e_stat_str(hw, ret),
5260 i40e_aq_str(hw, hw->aq.asq_last_status));
5261 goto out;
5262 }
5263 if ((bw_config.tc_valid_bits & enabled_tc) != enabled_tc) {
5264 u8 valid_tc = bw_config.tc_valid_bits & enabled_tc;
5265
5266 if (!valid_tc)
5267 valid_tc = bw_config.tc_valid_bits;
5268
5269 valid_tc |= 1;
5270 dev_info(&pf->pdev->dev,
5271 "Requested tc 0x%x, but FW reports 0x%x as valid. Attempting to use 0x%x.\n",
5272 enabled_tc, bw_config.tc_valid_bits, valid_tc);
5273 enabled_tc = valid_tc;
5274 }
5275
5276 ret = i40e_vsi_configure_bw_alloc(vsi, enabled_tc, bw_share);
5277 if (ret) {
5278 dev_err(&pf->pdev->dev,
5279 "Unable to configure TC map %d for VSI %d\n",
5280 enabled_tc, vsi->seid);
5281 goto out;
5282 }
5283 }
5284
5285
5286 ctxt.seid = vsi->seid;
5287 ctxt.pf_num = vsi->back->hw.pf_id;
5288 ctxt.vf_num = 0;
5289 ctxt.uplink_seid = vsi->uplink_seid;
5290 ctxt.info = vsi->info;
5291 if (vsi->back->flags & I40E_FLAG_TC_MQPRIO) {
5292 ret = i40e_vsi_setup_queue_map_mqprio(vsi, &ctxt, enabled_tc);
5293 if (ret)
5294 goto out;
5295 } else {
5296 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
5297 }
5298
5299
5300
5301
5302 if (!vsi->mqprio_qopt.qopt.hw && vsi->reconfig_rss) {
5303 vsi->rss_size = min_t(int, vsi->back->alloc_rss_size,
5304 vsi->num_queue_pairs);
5305 ret = i40e_vsi_config_rss(vsi);
5306 if (ret) {
5307 dev_info(&vsi->back->pdev->dev,
5308 "Failed to reconfig rss for num_queues\n");
5309 return ret;
5310 }
5311 vsi->reconfig_rss = false;
5312 }
5313 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
5314 ctxt.info.valid_sections |=
5315 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
5316 ctxt.info.queueing_opt_flags |= I40E_AQ_VSI_QUE_OPT_TCP_ENA;
5317 }
5318
5319
5320
5321
5322 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
5323 if (ret) {
5324 dev_info(&pf->pdev->dev,
5325 "Update vsi tc config failed, err %s aq_err %s\n",
5326 i40e_stat_str(hw, ret),
5327 i40e_aq_str(hw, hw->aq.asq_last_status));
5328 goto out;
5329 }
5330
5331 i40e_vsi_update_queue_map(vsi, &ctxt);
5332 vsi->info.valid_sections = 0;
5333
5334
5335 ret = i40e_vsi_get_bw_info(vsi);
5336 if (ret) {
5337 dev_info(&pf->pdev->dev,
5338 "Failed updating vsi bw info, err %s aq_err %s\n",
5339 i40e_stat_str(hw, ret),
5340 i40e_aq_str(hw, hw->aq.asq_last_status));
5341 goto out;
5342 }
5343
5344
5345 i40e_vsi_config_netdev_tc(vsi, enabled_tc);
5346out:
5347 return ret;
5348}
5349
5350
5351
5352
5353
5354
5355static int i40e_get_link_speed(struct i40e_vsi *vsi)
5356{
5357 struct i40e_pf *pf = vsi->back;
5358
5359 switch (pf->hw.phy.link_info.link_speed) {
5360 case I40E_LINK_SPEED_40GB:
5361 return 40000;
5362 case I40E_LINK_SPEED_25GB:
5363 return 25000;
5364 case I40E_LINK_SPEED_20GB:
5365 return 20000;
5366 case I40E_LINK_SPEED_10GB:
5367 return 10000;
5368 case I40E_LINK_SPEED_1GB:
5369 return 1000;
5370 default:
5371 return -EINVAL;
5372 }
5373}
5374
5375
5376
5377
5378
5379
5380
5381
5382
5383int i40e_set_bw_limit(struct i40e_vsi *vsi, u16 seid, u64 max_tx_rate)
5384{
5385 struct i40e_pf *pf = vsi->back;
5386 u64 credits = 0;
5387 int speed = 0;
5388 int ret = 0;
5389
5390 speed = i40e_get_link_speed(vsi);
5391 if (max_tx_rate > speed) {
5392 dev_err(&pf->pdev->dev,
5393 "Invalid max tx rate %llu specified for VSI seid %d.",
5394 max_tx_rate, seid);
5395 return -EINVAL;
5396 }
5397 if (max_tx_rate && max_tx_rate < 50) {
5398 dev_warn(&pf->pdev->dev,
5399 "Setting max tx rate to minimum usable value of 50Mbps.\n");
5400 max_tx_rate = 50;
5401 }
5402
5403
5404 credits = max_tx_rate;
5405 do_div(credits, I40E_BW_CREDIT_DIVISOR);
5406 ret = i40e_aq_config_vsi_bw_limit(&pf->hw, seid, credits,
5407 I40E_MAX_BW_INACTIVE_ACCUM, NULL);
5408 if (ret)
5409 dev_err(&pf->pdev->dev,
5410 "Failed set tx rate (%llu Mbps) for vsi->seid %u, err %s aq_err %s\n",
5411 max_tx_rate, seid, i40e_stat_str(&pf->hw, ret),
5412 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
5413 return ret;
5414}
5415
5416
5417
5418
5419
5420
5421
5422static void i40e_remove_queue_channels(struct i40e_vsi *vsi)
5423{
5424 enum i40e_admin_queue_err last_aq_status;
5425 struct i40e_cloud_filter *cfilter;
5426 struct i40e_channel *ch, *ch_tmp;
5427 struct i40e_pf *pf = vsi->back;
5428 struct hlist_node *node;
5429 int ret, i;
5430
5431
5432
5433
5434 vsi->current_rss_size = 0;
5435
5436
5437 if (list_empty(&vsi->ch_list))
5438 return;
5439
5440 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
5441 struct i40e_vsi *p_vsi;
5442
5443 list_del(&ch->list);
5444 p_vsi = ch->parent_vsi;
5445 if (!p_vsi || !ch->initialized) {
5446 kfree(ch);
5447 continue;
5448 }
5449
5450 for (i = 0; i < ch->num_queue_pairs; i++) {
5451 struct i40e_ring *tx_ring, *rx_ring;
5452 u16 pf_q;
5453
5454 pf_q = ch->base_queue + i;
5455 tx_ring = vsi->tx_rings[pf_q];
5456 tx_ring->ch = NULL;
5457
5458 rx_ring = vsi->rx_rings[pf_q];
5459 rx_ring->ch = NULL;
5460 }
5461
5462
5463 ret = i40e_set_bw_limit(vsi, ch->seid, 0);
5464 if (ret)
5465 dev_info(&vsi->back->pdev->dev,
5466 "Failed to reset tx rate for ch->seid %u\n",
5467 ch->seid);
5468
5469
5470 hlist_for_each_entry_safe(cfilter, node,
5471 &pf->cloud_filter_list, cloud_node) {
5472 if (cfilter->seid != ch->seid)
5473 continue;
5474
5475 hash_del(&cfilter->cloud_node);
5476 if (cfilter->dst_port)
5477 ret = i40e_add_del_cloud_filter_big_buf(vsi,
5478 cfilter,
5479 false);
5480 else
5481 ret = i40e_add_del_cloud_filter(vsi, cfilter,
5482 false);
5483 last_aq_status = pf->hw.aq.asq_last_status;
5484 if (ret)
5485 dev_info(&pf->pdev->dev,
5486 "Failed to delete cloud filter, err %s aq_err %s\n",
5487 i40e_stat_str(&pf->hw, ret),
5488 i40e_aq_str(&pf->hw, last_aq_status));
5489 kfree(cfilter);
5490 }
5491
5492
5493 ret = i40e_aq_delete_element(&vsi->back->hw, ch->seid,
5494 NULL);
5495 if (ret)
5496 dev_err(&vsi->back->pdev->dev,
5497 "unable to remove channel (%d) for parent VSI(%d)\n",
5498 ch->seid, p_vsi->seid);
5499 kfree(ch);
5500 }
5501 INIT_LIST_HEAD(&vsi->ch_list);
5502}
5503
5504
5505
5506
5507
5508
5509
5510static bool i40e_is_any_channel(struct i40e_vsi *vsi)
5511{
5512 struct i40e_channel *ch, *ch_tmp;
5513
5514 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
5515 if (ch->initialized)
5516 return true;
5517 }
5518
5519 return false;
5520}
5521
5522
5523
5524
5525
5526
5527
5528
5529static int i40e_get_max_queues_for_channel(struct i40e_vsi *vsi)
5530{
5531 struct i40e_channel *ch, *ch_tmp;
5532 int max = 0;
5533
5534 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
5535 if (!ch->initialized)
5536 continue;
5537 if (ch->num_queue_pairs > max)
5538 max = ch->num_queue_pairs;
5539 }
5540
5541 return max;
5542}
5543
5544
5545
5546
5547
5548
5549
5550
5551
5552
5553
5554
5555static int i40e_validate_num_queues(struct i40e_pf *pf, int num_queues,
5556 struct i40e_vsi *vsi, bool *reconfig_rss)
5557{
5558 int max_ch_queues;
5559
5560 if (!reconfig_rss)
5561 return -EINVAL;
5562
5563 *reconfig_rss = false;
5564 if (vsi->current_rss_size) {
5565 if (num_queues > vsi->current_rss_size) {
5566 dev_dbg(&pf->pdev->dev,
5567 "Error: num_queues (%d) > vsi's current_size(%d)\n",
5568 num_queues, vsi->current_rss_size);
5569 return -EINVAL;
5570 } else if ((num_queues < vsi->current_rss_size) &&
5571 (!is_power_of_2(num_queues))) {
5572 dev_dbg(&pf->pdev->dev,
5573 "Error: num_queues (%d) < vsi's current_size(%d), but not power of 2\n",
5574 num_queues, vsi->current_rss_size);
5575 return -EINVAL;
5576 }
5577 }
5578
5579 if (!is_power_of_2(num_queues)) {
5580
5581
5582
5583
5584
5585 max_ch_queues = i40e_get_max_queues_for_channel(vsi);
5586 if (num_queues < max_ch_queues) {
5587 dev_dbg(&pf->pdev->dev,
5588 "Error: num_queues (%d) < max queues configured for channel(%d)\n",
5589 num_queues, max_ch_queues);
5590 return -EINVAL;
5591 }
5592 *reconfig_rss = true;
5593 }
5594
5595 return 0;
5596}
5597
5598
5599
5600
5601
5602
5603
5604
5605static int i40e_vsi_reconfig_rss(struct i40e_vsi *vsi, u16 rss_size)
5606{
5607 struct i40e_pf *pf = vsi->back;
5608 u8 seed[I40E_HKEY_ARRAY_SIZE];
5609 struct i40e_hw *hw = &pf->hw;
5610 int local_rss_size;
5611 u8 *lut;
5612 int ret;
5613
5614 if (!vsi->rss_size)
5615 return -EINVAL;
5616
5617 if (rss_size > vsi->rss_size)
5618 return -EINVAL;
5619
5620 local_rss_size = min_t(int, vsi->rss_size, rss_size);
5621 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
5622 if (!lut)
5623 return -ENOMEM;
5624
5625
5626 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, local_rss_size);
5627
5628
5629
5630
5631 if (vsi->rss_hkey_user)
5632 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
5633 else
5634 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
5635
5636 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
5637 if (ret) {
5638 dev_info(&pf->pdev->dev,
5639 "Cannot set RSS lut, err %s aq_err %s\n",
5640 i40e_stat_str(hw, ret),
5641 i40e_aq_str(hw, hw->aq.asq_last_status));
5642 kfree(lut);
5643 return ret;
5644 }
5645 kfree(lut);
5646
5647
5648 if (!vsi->orig_rss_size)
5649 vsi->orig_rss_size = vsi->rss_size;
5650 vsi->current_rss_size = local_rss_size;
5651
5652 return ret;
5653}
5654
5655
5656
5657
5658
5659
5660
5661
5662
5663
5664static void i40e_channel_setup_queue_map(struct i40e_pf *pf,
5665 struct i40e_vsi_context *ctxt,
5666 struct i40e_channel *ch)
5667{
5668 u16 qcount, qmap, sections = 0;
5669 u8 offset = 0;
5670 int pow;
5671
5672 sections = I40E_AQ_VSI_PROP_QUEUE_MAP_VALID;
5673 sections |= I40E_AQ_VSI_PROP_SCHED_VALID;
5674
5675 qcount = min_t(int, ch->num_queue_pairs, pf->num_lan_msix);
5676 ch->num_queue_pairs = qcount;
5677
5678
5679 pow = ilog2(qcount);
5680 if (!is_power_of_2(qcount))
5681 pow++;
5682
5683 qmap = (offset << I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) |
5684 (pow << I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT);
5685
5686
5687 ctxt->info.tc_mapping[0] = cpu_to_le16(qmap);
5688
5689 ctxt->info.up_enable_bits = 0x1;
5690 ctxt->info.mapping_flags |= cpu_to_le16(I40E_AQ_VSI_QUE_MAP_CONTIG);
5691 ctxt->info.queue_mapping[0] = cpu_to_le16(ch->base_queue);
5692 ctxt->info.valid_sections |= cpu_to_le16(sections);
5693}
5694
5695
5696
5697
5698
5699
5700
5701
5702
5703static int i40e_add_channel(struct i40e_pf *pf, u16 uplink_seid,
5704 struct i40e_channel *ch)
5705{
5706 struct i40e_hw *hw = &pf->hw;
5707 struct i40e_vsi_context ctxt;
5708 u8 enabled_tc = 0x1;
5709 int ret;
5710
5711 if (ch->type != I40E_VSI_VMDQ2) {
5712 dev_info(&pf->pdev->dev,
5713 "add new vsi failed, ch->type %d\n", ch->type);
5714 return -EINVAL;
5715 }
5716
5717 memset(&ctxt, 0, sizeof(ctxt));
5718 ctxt.pf_num = hw->pf_id;
5719 ctxt.vf_num = 0;
5720 ctxt.uplink_seid = uplink_seid;
5721 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
5722 if (ch->type == I40E_VSI_VMDQ2)
5723 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
5724
5725 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED) {
5726 ctxt.info.valid_sections |=
5727 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
5728 ctxt.info.switch_id =
5729 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
5730 }
5731
5732
5733 i40e_channel_setup_queue_map(pf, &ctxt, ch);
5734
5735
5736 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
5737 if (ret) {
5738 dev_info(&pf->pdev->dev,
5739 "add new vsi failed, err %s aq_err %s\n",
5740 i40e_stat_str(&pf->hw, ret),
5741 i40e_aq_str(&pf->hw,
5742 pf->hw.aq.asq_last_status));
5743 return -ENOENT;
5744 }
5745
5746
5747 ch->enabled_tc = enabled_tc;
5748 ch->seid = ctxt.seid;
5749 ch->vsi_number = ctxt.vsi_number;
5750 ch->stat_counter_idx = cpu_to_le16(ctxt.info.stat_counter_idx);
5751
5752
5753
5754
5755
5756 ch->info.mapping_flags = ctxt.info.mapping_flags;
5757 memcpy(&ch->info.queue_mapping,
5758 &ctxt.info.queue_mapping, sizeof(ctxt.info.queue_mapping));
5759 memcpy(&ch->info.tc_mapping, ctxt.info.tc_mapping,
5760 sizeof(ctxt.info.tc_mapping));
5761
5762 return 0;
5763}
5764
5765static int i40e_channel_config_bw(struct i40e_vsi *vsi, struct i40e_channel *ch,
5766 u8 *bw_share)
5767{
5768 struct i40e_aqc_configure_vsi_tc_bw_data bw_data;
5769 i40e_status ret;
5770 int i;
5771
5772 bw_data.tc_valid_bits = ch->enabled_tc;
5773 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5774 bw_data.tc_bw_credits[i] = bw_share[i];
5775
5776 ret = i40e_aq_config_vsi_tc_bw(&vsi->back->hw, ch->seid,
5777 &bw_data, NULL);
5778 if (ret) {
5779 dev_info(&vsi->back->pdev->dev,
5780 "Config VSI BW allocation per TC failed, aq_err: %d for new_vsi->seid %u\n",
5781 vsi->back->hw.aq.asq_last_status, ch->seid);
5782 return -EINVAL;
5783 }
5784
5785 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++)
5786 ch->info.qs_handle[i] = bw_data.qs_handles[i];
5787
5788 return 0;
5789}
5790
5791
5792
5793
5794
5795
5796
5797
5798
5799
5800static int i40e_channel_config_tx_ring(struct i40e_pf *pf,
5801 struct i40e_vsi *vsi,
5802 struct i40e_channel *ch)
5803{
5804 i40e_status ret;
5805 int i;
5806 u8 bw_share[I40E_MAX_TRAFFIC_CLASS] = {0};
5807
5808
5809 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
5810 if (ch->enabled_tc & BIT(i))
5811 bw_share[i] = 1;
5812 }
5813
5814
5815 ret = i40e_channel_config_bw(vsi, ch, bw_share);
5816 if (ret) {
5817 dev_info(&vsi->back->pdev->dev,
5818 "Failed configuring TC map %d for channel (seid %u)\n",
5819 ch->enabled_tc, ch->seid);
5820 return ret;
5821 }
5822
5823 for (i = 0; i < ch->num_queue_pairs; i++) {
5824 struct i40e_ring *tx_ring, *rx_ring;
5825 u16 pf_q;
5826
5827 pf_q = ch->base_queue + i;
5828
5829
5830
5831
5832 tx_ring = vsi->tx_rings[pf_q];
5833 tx_ring->ch = ch;
5834
5835
5836 rx_ring = vsi->rx_rings[pf_q];
5837 rx_ring->ch = ch;
5838 }
5839
5840 return 0;
5841}
5842
5843
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854static inline int i40e_setup_hw_channel(struct i40e_pf *pf,
5855 struct i40e_vsi *vsi,
5856 struct i40e_channel *ch,
5857 u16 uplink_seid, u8 type)
5858{
5859 int ret;
5860
5861 ch->initialized = false;
5862 ch->base_queue = vsi->next_base_queue;
5863 ch->type = type;
5864
5865
5866 ret = i40e_add_channel(pf, uplink_seid, ch);
5867 if (ret) {
5868 dev_info(&pf->pdev->dev,
5869 "failed to add_channel using uplink_seid %u\n",
5870 uplink_seid);
5871 return ret;
5872 }
5873
5874
5875 ch->initialized = true;
5876
5877
5878 ret = i40e_channel_config_tx_ring(pf, vsi, ch);
5879 if (ret) {
5880 dev_info(&pf->pdev->dev,
5881 "failed to configure TX rings for channel %u\n",
5882 ch->seid);
5883 return ret;
5884 }
5885
5886
5887 vsi->next_base_queue = vsi->next_base_queue + ch->num_queue_pairs;
5888 dev_dbg(&pf->pdev->dev,
5889 "Added channel: vsi_seid %u, vsi_number %u, stat_counter_idx %u, num_queue_pairs %u, pf->next_base_queue %d\n",
5890 ch->seid, ch->vsi_number, ch->stat_counter_idx,
5891 ch->num_queue_pairs,
5892 vsi->next_base_queue);
5893 return ret;
5894}
5895
5896
5897
5898
5899
5900
5901
5902
5903
5904
5905
5906static bool i40e_setup_channel(struct i40e_pf *pf, struct i40e_vsi *vsi,
5907 struct i40e_channel *ch)
5908{
5909 u8 vsi_type;
5910 u16 seid;
5911 int ret;
5912
5913 if (vsi->type == I40E_VSI_MAIN) {
5914 vsi_type = I40E_VSI_VMDQ2;
5915 } else {
5916 dev_err(&pf->pdev->dev, "unsupported parent vsi type(%d)\n",
5917 vsi->type);
5918 return false;
5919 }
5920
5921
5922 seid = pf->vsi[pf->lan_vsi]->uplink_seid;
5923
5924
5925 ret = i40e_setup_hw_channel(pf, vsi, ch, seid, vsi_type);
5926 if (ret) {
5927 dev_err(&pf->pdev->dev, "failed to setup hw_channel\n");
5928 return false;
5929 }
5930
5931 return ch->initialized ? true : false;
5932}
5933
5934
5935
5936
5937
5938
5939
5940
5941static int i40e_validate_and_set_switch_mode(struct i40e_vsi *vsi)
5942{
5943 u8 mode;
5944 struct i40e_pf *pf = vsi->back;
5945 struct i40e_hw *hw = &pf->hw;
5946 int ret;
5947
5948 ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_dev_capabilities);
5949 if (ret)
5950 return -EINVAL;
5951
5952 if (hw->dev_caps.switch_mode) {
5953
5954
5955
5956 u32 switch_mode = hw->dev_caps.switch_mode &
5957 I40E_SWITCH_MODE_MASK;
5958 if (switch_mode >= I40E_CLOUD_FILTER_MODE1) {
5959 if (switch_mode == I40E_CLOUD_FILTER_MODE2)
5960 return 0;
5961 dev_err(&pf->pdev->dev,
5962 "Invalid switch_mode (%d), only non-tunneled mode for cloud filter is supported\n",
5963 hw->dev_caps.switch_mode);
5964 return -EINVAL;
5965 }
5966 }
5967
5968
5969 mode = I40E_AQ_SET_SWITCH_BIT7_VALID;
5970
5971
5972 mode |= I40E_AQ_SET_SWITCH_L4_TYPE_TCP;
5973
5974
5975 mode |= I40E_AQ_SET_SWITCH_MODE_NON_TUNNEL;
5976
5977
5978 ret = i40e_aq_set_switch_config(hw, pf->last_sw_conf_flags,
5979 pf->last_sw_conf_valid_flags,
5980 mode, NULL);
5981 if (ret && hw->aq.asq_last_status != I40E_AQ_RC_ESRCH)
5982 dev_err(&pf->pdev->dev,
5983 "couldn't set switch config bits, err %s aq_err %s\n",
5984 i40e_stat_str(hw, ret),
5985 i40e_aq_str(hw,
5986 hw->aq.asq_last_status));
5987
5988 return ret;
5989}
5990
5991
5992
5993
5994
5995
5996
5997
5998
5999int i40e_create_queue_channel(struct i40e_vsi *vsi,
6000 struct i40e_channel *ch)
6001{
6002 struct i40e_pf *pf = vsi->back;
6003 bool reconfig_rss;
6004 int err;
6005
6006 if (!ch)
6007 return -EINVAL;
6008
6009 if (!ch->num_queue_pairs) {
6010 dev_err(&pf->pdev->dev, "Invalid num_queues requested: %d\n",
6011 ch->num_queue_pairs);
6012 return -EINVAL;
6013 }
6014
6015
6016 err = i40e_validate_num_queues(pf, ch->num_queue_pairs, vsi,
6017 &reconfig_rss);
6018 if (err) {
6019 dev_info(&pf->pdev->dev, "Failed to validate num_queues (%d)\n",
6020 ch->num_queue_pairs);
6021 return -EINVAL;
6022 }
6023
6024
6025
6026
6027 if ((!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) ||
6028 (!i40e_is_any_channel(vsi))) {
6029 if (!is_power_of_2(vsi->tc_config.tc_info[0].qcount)) {
6030 dev_dbg(&pf->pdev->dev,
6031 "Failed to create channel. Override queues (%u) not power of 2\n",
6032 vsi->tc_config.tc_info[0].qcount);
6033 return -EINVAL;
6034 }
6035
6036 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
6037 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
6038
6039 if (vsi->type == I40E_VSI_MAIN) {
6040 if (pf->flags & I40E_FLAG_TC_MQPRIO)
6041 i40e_do_reset(pf, I40E_PF_RESET_FLAG,
6042 true);
6043 else
6044 i40e_do_reset_safe(pf,
6045 I40E_PF_RESET_FLAG);
6046 }
6047 }
6048
6049
6050
6051 }
6052
6053
6054
6055
6056 if (!vsi->cnt_q_avail || vsi->cnt_q_avail < ch->num_queue_pairs) {
6057 dev_dbg(&pf->pdev->dev,
6058 "Error: cnt_q_avail (%u) less than num_queues %d\n",
6059 vsi->cnt_q_avail, ch->num_queue_pairs);
6060 return -EINVAL;
6061 }
6062
6063
6064 if (reconfig_rss && (vsi->type == I40E_VSI_MAIN)) {
6065 err = i40e_vsi_reconfig_rss(vsi, ch->num_queue_pairs);
6066 if (err) {
6067 dev_info(&pf->pdev->dev,
6068 "Error: unable to reconfig rss for num_queues (%u)\n",
6069 ch->num_queue_pairs);
6070 return -EINVAL;
6071 }
6072 }
6073
6074 if (!i40e_setup_channel(pf, vsi, ch)) {
6075 dev_info(&pf->pdev->dev, "Failed to setup channel\n");
6076 return -EINVAL;
6077 }
6078
6079 dev_info(&pf->pdev->dev,
6080 "Setup channel (id:%u) utilizing num_queues %d\n",
6081 ch->seid, ch->num_queue_pairs);
6082
6083
6084 if (ch->max_tx_rate) {
6085 u64 credits = ch->max_tx_rate;
6086
6087 if (i40e_set_bw_limit(vsi, ch->seid, ch->max_tx_rate))
6088 return -EINVAL;
6089
6090 do_div(credits, I40E_BW_CREDIT_DIVISOR);
6091 dev_dbg(&pf->pdev->dev,
6092 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
6093 ch->max_tx_rate,
6094 credits,
6095 ch->seid);
6096 }
6097
6098
6099 ch->parent_vsi = vsi;
6100
6101
6102 vsi->cnt_q_avail -= ch->num_queue_pairs;
6103
6104 return 0;
6105}
6106
6107
6108
6109
6110
6111
6112
6113static int i40e_configure_queue_channels(struct i40e_vsi *vsi)
6114{
6115 struct i40e_channel *ch;
6116 u64 max_rate = 0;
6117 int ret = 0, i;
6118
6119
6120 vsi->tc_seid_map[0] = vsi->seid;
6121 for (i = 1; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6122 if (vsi->tc_config.enabled_tc & BIT(i)) {
6123 ch = kzalloc(sizeof(*ch), GFP_KERNEL);
6124 if (!ch) {
6125 ret = -ENOMEM;
6126 goto err_free;
6127 }
6128
6129 INIT_LIST_HEAD(&ch->list);
6130 ch->num_queue_pairs =
6131 vsi->tc_config.tc_info[i].qcount;
6132 ch->base_queue =
6133 vsi->tc_config.tc_info[i].qoffset;
6134
6135
6136
6137
6138 max_rate = vsi->mqprio_qopt.max_rate[i];
6139 do_div(max_rate, I40E_BW_MBPS_DIVISOR);
6140 ch->max_tx_rate = max_rate;
6141
6142 list_add_tail(&ch->list, &vsi->ch_list);
6143
6144 ret = i40e_create_queue_channel(vsi, ch);
6145 if (ret) {
6146 dev_err(&vsi->back->pdev->dev,
6147 "Failed creating queue channel with TC%d: queues %d\n",
6148 i, ch->num_queue_pairs);
6149 goto err_free;
6150 }
6151 vsi->tc_seid_map[i] = ch->seid;
6152 }
6153 }
6154 return ret;
6155
6156err_free:
6157 i40e_remove_queue_channels(vsi);
6158 return ret;
6159}
6160
6161
6162
6163
6164
6165
6166
6167
6168int i40e_veb_config_tc(struct i40e_veb *veb, u8 enabled_tc)
6169{
6170 struct i40e_aqc_configure_switching_comp_bw_config_data bw_data = {0};
6171 struct i40e_pf *pf = veb->pf;
6172 int ret = 0;
6173 int i;
6174
6175
6176 if (!enabled_tc || veb->enabled_tc == enabled_tc)
6177 return ret;
6178
6179 bw_data.tc_valid_bits = enabled_tc;
6180
6181
6182
6183 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6184 if (enabled_tc & BIT(i))
6185 bw_data.tc_bw_share_credits[i] = 1;
6186 }
6187
6188 ret = i40e_aq_config_switch_comp_bw_config(&pf->hw, veb->seid,
6189 &bw_data, NULL);
6190 if (ret) {
6191 dev_info(&pf->pdev->dev,
6192 "VEB bw config failed, err %s aq_err %s\n",
6193 i40e_stat_str(&pf->hw, ret),
6194 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6195 goto out;
6196 }
6197
6198
6199 ret = i40e_veb_get_bw_info(veb);
6200 if (ret) {
6201 dev_info(&pf->pdev->dev,
6202 "Failed getting veb bw config, err %s aq_err %s\n",
6203 i40e_stat_str(&pf->hw, ret),
6204 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6205 }
6206
6207out:
6208 return ret;
6209}
6210
6211#ifdef CONFIG_I40E_DCB
6212
6213
6214
6215
6216
6217
6218
6219
6220static void i40e_dcb_reconfigure(struct i40e_pf *pf)
6221{
6222 u8 tc_map = 0;
6223 int ret;
6224 u8 v;
6225
6226
6227 tc_map = i40e_pf_get_tc_map(pf);
6228 for (v = 0; v < I40E_MAX_VEB; v++) {
6229 if (!pf->veb[v])
6230 continue;
6231 ret = i40e_veb_config_tc(pf->veb[v], tc_map);
6232 if (ret) {
6233 dev_info(&pf->pdev->dev,
6234 "Failed configuring TC for VEB seid=%d\n",
6235 pf->veb[v]->seid);
6236
6237 }
6238 }
6239
6240
6241 for (v = 0; v < pf->num_alloc_vsi; v++) {
6242 if (!pf->vsi[v])
6243 continue;
6244
6245
6246
6247
6248 if (v == pf->lan_vsi)
6249 tc_map = i40e_pf_get_tc_map(pf);
6250 else
6251 tc_map = I40E_DEFAULT_TRAFFIC_CLASS;
6252
6253 ret = i40e_vsi_config_tc(pf->vsi[v], tc_map);
6254 if (ret) {
6255 dev_info(&pf->pdev->dev,
6256 "Failed configuring TC for VSI seid=%d\n",
6257 pf->vsi[v]->seid);
6258
6259 } else {
6260
6261 i40e_vsi_map_rings_to_vectors(pf->vsi[v]);
6262 if (pf->vsi[v]->netdev)
6263 i40e_dcbnl_set_all(pf->vsi[v]);
6264 }
6265 }
6266}
6267
6268
6269
6270
6271
6272
6273
6274
6275static int i40e_resume_port_tx(struct i40e_pf *pf)
6276{
6277 struct i40e_hw *hw = &pf->hw;
6278 int ret;
6279
6280 ret = i40e_aq_resume_port_tx(hw, NULL);
6281 if (ret) {
6282 dev_info(&pf->pdev->dev,
6283 "Resume Port Tx failed, err %s aq_err %s\n",
6284 i40e_stat_str(&pf->hw, ret),
6285 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6286
6287 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
6288 i40e_service_event_schedule(pf);
6289 }
6290
6291 return ret;
6292}
6293
6294
6295
6296
6297
6298
6299
6300
6301static int i40e_init_pf_dcb(struct i40e_pf *pf)
6302{
6303 struct i40e_hw *hw = &pf->hw;
6304 int err = 0;
6305
6306
6307
6308
6309 if ((pf->hw_features & I40E_HW_NO_DCB_SUPPORT) ||
6310 (pf->flags & I40E_FLAG_DISABLE_FW_LLDP))
6311 goto out;
6312
6313
6314 err = i40e_init_dcb(hw);
6315 if (!err) {
6316
6317 if ((!hw->func_caps.dcb) ||
6318 (hw->dcbx_status == I40E_DCBX_STATUS_DISABLED)) {
6319 dev_info(&pf->pdev->dev,
6320 "DCBX offload is not supported or is disabled for this PF.\n");
6321 } else {
6322
6323 pf->dcbx_cap = DCB_CAP_DCBX_LLD_MANAGED |
6324 DCB_CAP_DCBX_VER_IEEE;
6325
6326 pf->flags |= I40E_FLAG_DCB_CAPABLE;
6327
6328
6329
6330 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
6331 pf->flags |= I40E_FLAG_DCB_ENABLED;
6332 else
6333 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
6334 dev_dbg(&pf->pdev->dev,
6335 "DCBX offload is supported for this PF.\n");
6336 }
6337 } else if (pf->hw.aq.asq_last_status == I40E_AQ_RC_EPERM) {
6338 dev_info(&pf->pdev->dev, "FW LLDP disabled for this PF.\n");
6339 pf->flags |= I40E_FLAG_DISABLE_FW_LLDP;
6340 } else {
6341 dev_info(&pf->pdev->dev,
6342 "Query for DCB configuration failed, err %s aq_err %s\n",
6343 i40e_stat_str(&pf->hw, err),
6344 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6345 }
6346
6347out:
6348 return err;
6349}
6350#endif
6351#define SPEED_SIZE 14
6352#define FC_SIZE 8
6353
6354
6355
6356
6357void i40e_print_link_message(struct i40e_vsi *vsi, bool isup)
6358{
6359 enum i40e_aq_link_speed new_speed;
6360 struct i40e_pf *pf = vsi->back;
6361 char *speed = "Unknown";
6362 char *fc = "Unknown";
6363 char *fec = "";
6364 char *req_fec = "";
6365 char *an = "";
6366
6367 new_speed = pf->hw.phy.link_info.link_speed;
6368
6369 if ((vsi->current_isup == isup) && (vsi->current_speed == new_speed))
6370 return;
6371 vsi->current_isup = isup;
6372 vsi->current_speed = new_speed;
6373 if (!isup) {
6374 netdev_info(vsi->netdev, "NIC Link is Down\n");
6375 return;
6376 }
6377
6378
6379
6380
6381 if (pf->hw.func_caps.npar_enable &&
6382 (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_1GB ||
6383 pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_100MB))
6384 netdev_warn(vsi->netdev,
6385 "The partition detected link speed that is less than 10Gbps\n");
6386
6387 switch (pf->hw.phy.link_info.link_speed) {
6388 case I40E_LINK_SPEED_40GB:
6389 speed = "40 G";
6390 break;
6391 case I40E_LINK_SPEED_20GB:
6392 speed = "20 G";
6393 break;
6394 case I40E_LINK_SPEED_25GB:
6395 speed = "25 G";
6396 break;
6397 case I40E_LINK_SPEED_10GB:
6398 speed = "10 G";
6399 break;
6400 case I40E_LINK_SPEED_1GB:
6401 speed = "1000 M";
6402 break;
6403 case I40E_LINK_SPEED_100MB:
6404 speed = "100 M";
6405 break;
6406 default:
6407 break;
6408 }
6409
6410 switch (pf->hw.fc.current_mode) {
6411 case I40E_FC_FULL:
6412 fc = "RX/TX";
6413 break;
6414 case I40E_FC_TX_PAUSE:
6415 fc = "TX";
6416 break;
6417 case I40E_FC_RX_PAUSE:
6418 fc = "RX";
6419 break;
6420 default:
6421 fc = "None";
6422 break;
6423 }
6424
6425 if (pf->hw.phy.link_info.link_speed == I40E_LINK_SPEED_25GB) {
6426 req_fec = ", Requested FEC: None";
6427 fec = ", FEC: None";
6428 an = ", Autoneg: False";
6429
6430 if (pf->hw.phy.link_info.an_info & I40E_AQ_AN_COMPLETED)
6431 an = ", Autoneg: True";
6432
6433 if (pf->hw.phy.link_info.fec_info &
6434 I40E_AQ_CONFIG_FEC_KR_ENA)
6435 fec = ", FEC: CL74 FC-FEC/BASE-R";
6436 else if (pf->hw.phy.link_info.fec_info &
6437 I40E_AQ_CONFIG_FEC_RS_ENA)
6438 fec = ", FEC: CL108 RS-FEC";
6439
6440
6441
6442
6443 if (vsi->back->hw.phy.link_info.req_fec_info &
6444 (I40E_AQ_REQUEST_FEC_KR | I40E_AQ_REQUEST_FEC_RS)) {
6445 if (vsi->back->hw.phy.link_info.req_fec_info &
6446 I40E_AQ_REQUEST_FEC_RS)
6447 req_fec = ", Requested FEC: CL108 RS-FEC";
6448 else
6449 req_fec = ", Requested FEC: CL74 FC-FEC/BASE-R";
6450 }
6451 }
6452
6453 netdev_info(vsi->netdev, "NIC Link is Up, %sbps Full Duplex%s%s%s, Flow Control: %s\n",
6454 speed, req_fec, fec, an, fc);
6455}
6456
6457
6458
6459
6460
6461static int i40e_up_complete(struct i40e_vsi *vsi)
6462{
6463 struct i40e_pf *pf = vsi->back;
6464 int err;
6465
6466 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
6467 i40e_vsi_configure_msix(vsi);
6468 else
6469 i40e_configure_msi_and_legacy(vsi);
6470
6471
6472 err = i40e_vsi_start_rings(vsi);
6473 if (err)
6474 return err;
6475
6476 clear_bit(__I40E_VSI_DOWN, vsi->state);
6477 i40e_napi_enable_all(vsi);
6478 i40e_vsi_enable_irq(vsi);
6479
6480 if ((pf->hw.phy.link_info.link_info & I40E_AQ_LINK_UP) &&
6481 (vsi->netdev)) {
6482 i40e_print_link_message(vsi, true);
6483 netif_tx_start_all_queues(vsi->netdev);
6484 netif_carrier_on(vsi->netdev);
6485 }
6486
6487
6488 if (vsi->type == I40E_VSI_FDIR) {
6489
6490 pf->fd_add_err = 0;
6491 pf->fd_atr_cnt = 0;
6492 i40e_fdir_filter_restore(vsi);
6493 }
6494
6495
6496
6497
6498 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
6499 i40e_service_event_schedule(pf);
6500
6501 return 0;
6502}
6503
6504
6505
6506
6507
6508
6509
6510
6511static void i40e_vsi_reinit_locked(struct i40e_vsi *vsi)
6512{
6513 struct i40e_pf *pf = vsi->back;
6514
6515 WARN_ON(in_interrupt());
6516 while (test_and_set_bit(__I40E_CONFIG_BUSY, pf->state))
6517 usleep_range(1000, 2000);
6518 i40e_down(vsi);
6519
6520 i40e_up(vsi);
6521 clear_bit(__I40E_CONFIG_BUSY, pf->state);
6522}
6523
6524
6525
6526
6527
6528int i40e_up(struct i40e_vsi *vsi)
6529{
6530 int err;
6531
6532 err = i40e_vsi_configure(vsi);
6533 if (!err)
6534 err = i40e_up_complete(vsi);
6535
6536 return err;
6537}
6538
6539
6540
6541
6542
6543
6544static i40e_status i40e_force_link_state(struct i40e_pf *pf, bool is_up)
6545{
6546 struct i40e_aq_get_phy_abilities_resp abilities;
6547 struct i40e_aq_set_phy_config config = {0};
6548 struct i40e_hw *hw = &pf->hw;
6549 i40e_status err;
6550 u64 mask;
6551
6552
6553 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities,
6554 NULL);
6555 if (err) {
6556 dev_err(&pf->pdev->dev,
6557 "failed to get phy cap., ret = %s last_status = %s\n",
6558 i40e_stat_str(hw, err),
6559 i40e_aq_str(hw, hw->aq.asq_last_status));
6560 return err;
6561 }
6562
6563
6564
6565
6566 if (is_up && abilities.phy_type != 0)
6567 return I40E_SUCCESS;
6568
6569
6570
6571
6572
6573 mask = I40E_PHY_TYPES_BITMASK;
6574 config.phy_type = is_up ? cpu_to_le32((u32)(mask & 0xffffffff)) : 0;
6575 config.phy_type_ext = is_up ? (u8)((mask >> 32) & 0xff) : 0;
6576
6577 config.abilities = abilities.abilities;
6578 config.link_speed = abilities.link_speed;
6579 config.eee_capability = abilities.eee_capability;
6580 config.eeer = abilities.eeer_val;
6581 config.low_power_ctrl = abilities.d3_lpan;
6582 err = i40e_aq_set_phy_config(hw, &config, NULL);
6583
6584 if (err) {
6585 dev_err(&pf->pdev->dev,
6586 "set phy config ret = %s last_status = %s\n",
6587 i40e_stat_str(&pf->hw, err),
6588 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
6589 return err;
6590 }
6591
6592
6593 err = i40e_update_link_info(hw);
6594 if (err) {
6595
6596
6597
6598
6599 msleep(1000);
6600 i40e_update_link_info(hw);
6601 }
6602
6603 i40e_aq_set_link_restart_an(hw, true, NULL);
6604
6605 return I40E_SUCCESS;
6606}
6607
6608
6609
6610
6611
6612void i40e_down(struct i40e_vsi *vsi)
6613{
6614 int i;
6615
6616
6617
6618
6619 if (vsi->netdev) {
6620 netif_carrier_off(vsi->netdev);
6621 netif_tx_disable(vsi->netdev);
6622 }
6623 i40e_vsi_disable_irq(vsi);
6624 i40e_vsi_stop_rings(vsi);
6625 if (vsi->type == I40E_VSI_MAIN &&
6626 vsi->back->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED)
6627 i40e_force_link_state(vsi->back, false);
6628 i40e_napi_disable_all(vsi);
6629
6630 for (i = 0; i < vsi->num_queue_pairs; i++) {
6631 i40e_clean_tx_ring(vsi->tx_rings[i]);
6632 if (i40e_enabled_xdp_vsi(vsi))
6633 i40e_clean_tx_ring(vsi->xdp_rings[i]);
6634 i40e_clean_rx_ring(vsi->rx_rings[i]);
6635 }
6636
6637}
6638
6639
6640
6641
6642
6643
6644static int i40e_validate_mqprio_qopt(struct i40e_vsi *vsi,
6645 struct tc_mqprio_qopt_offload *mqprio_qopt)
6646{
6647 u64 sum_max_rate = 0;
6648 u64 max_rate = 0;
6649 int i;
6650
6651 if (mqprio_qopt->qopt.offset[0] != 0 ||
6652 mqprio_qopt->qopt.num_tc < 1 ||
6653 mqprio_qopt->qopt.num_tc > I40E_MAX_TRAFFIC_CLASS)
6654 return -EINVAL;
6655 for (i = 0; ; i++) {
6656 if (!mqprio_qopt->qopt.count[i])
6657 return -EINVAL;
6658 if (mqprio_qopt->min_rate[i]) {
6659 dev_err(&vsi->back->pdev->dev,
6660 "Invalid min tx rate (greater than 0) specified\n");
6661 return -EINVAL;
6662 }
6663 max_rate = mqprio_qopt->max_rate[i];
6664 do_div(max_rate, I40E_BW_MBPS_DIVISOR);
6665 sum_max_rate += max_rate;
6666
6667 if (i >= mqprio_qopt->qopt.num_tc - 1)
6668 break;
6669 if (mqprio_qopt->qopt.offset[i + 1] !=
6670 (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i]))
6671 return -EINVAL;
6672 }
6673 if (vsi->num_queue_pairs <
6674 (mqprio_qopt->qopt.offset[i] + mqprio_qopt->qopt.count[i])) {
6675 return -EINVAL;
6676 }
6677 if (sum_max_rate > i40e_get_link_speed(vsi)) {
6678 dev_err(&vsi->back->pdev->dev,
6679 "Invalid max tx rate specified\n");
6680 return -EINVAL;
6681 }
6682 return 0;
6683}
6684
6685
6686
6687
6688
6689static void i40e_vsi_set_default_tc_config(struct i40e_vsi *vsi)
6690{
6691 u16 qcount;
6692 int i;
6693
6694
6695 vsi->tc_config.numtc = 1;
6696 vsi->tc_config.enabled_tc = 1;
6697 qcount = min_t(int, vsi->alloc_queue_pairs,
6698 i40e_pf_get_max_q_per_tc(vsi->back));
6699 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
6700
6701
6702
6703 vsi->tc_config.tc_info[i].qoffset = 0;
6704 if (i == 0)
6705 vsi->tc_config.tc_info[i].qcount = qcount;
6706 else
6707 vsi->tc_config.tc_info[i].qcount = 1;
6708 vsi->tc_config.tc_info[i].netdev_tc = 0;
6709 }
6710}
6711
6712
6713
6714
6715
6716
6717static int i40e_setup_tc(struct net_device *netdev, void *type_data)
6718{
6719 struct tc_mqprio_qopt_offload *mqprio_qopt = type_data;
6720 struct i40e_netdev_priv *np = netdev_priv(netdev);
6721 struct i40e_vsi *vsi = np->vsi;
6722 struct i40e_pf *pf = vsi->back;
6723 u8 enabled_tc = 0, num_tc, hw;
6724 bool need_reset = false;
6725 int ret = -EINVAL;
6726 u16 mode;
6727 int i;
6728
6729 num_tc = mqprio_qopt->qopt.num_tc;
6730 hw = mqprio_qopt->qopt.hw;
6731 mode = mqprio_qopt->mode;
6732 if (!hw) {
6733 pf->flags &= ~I40E_FLAG_TC_MQPRIO;
6734 memcpy(&vsi->mqprio_qopt, mqprio_qopt, sizeof(*mqprio_qopt));
6735 goto config_tc;
6736 }
6737
6738
6739 if (pf->flags & I40E_FLAG_MFP_ENABLED) {
6740 netdev_info(netdev,
6741 "Configuring TC not supported in MFP mode\n");
6742 return ret;
6743 }
6744 switch (mode) {
6745 case TC_MQPRIO_MODE_DCB:
6746 pf->flags &= ~I40E_FLAG_TC_MQPRIO;
6747
6748
6749 if (!(pf->flags & I40E_FLAG_DCB_ENABLED)) {
6750 netdev_info(netdev,
6751 "DCB is not enabled for adapter\n");
6752 return ret;
6753 }
6754
6755
6756 if (num_tc > i40e_pf_get_num_tc(pf)) {
6757 netdev_info(netdev,
6758 "TC count greater than enabled on link for adapter\n");
6759 return ret;
6760 }
6761 break;
6762 case TC_MQPRIO_MODE_CHANNEL:
6763 if (pf->flags & I40E_FLAG_DCB_ENABLED) {
6764 netdev_info(netdev,
6765 "Full offload of TC Mqprio options is not supported when DCB is enabled\n");
6766 return ret;
6767 }
6768 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
6769 return ret;
6770 ret = i40e_validate_mqprio_qopt(vsi, mqprio_qopt);
6771 if (ret)
6772 return ret;
6773 memcpy(&vsi->mqprio_qopt, mqprio_qopt,
6774 sizeof(*mqprio_qopt));
6775 pf->flags |= I40E_FLAG_TC_MQPRIO;
6776 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
6777 break;
6778 default:
6779 return -EINVAL;
6780 }
6781
6782config_tc:
6783
6784 for (i = 0; i < num_tc; i++)
6785 enabled_tc |= BIT(i);
6786
6787
6788 if (enabled_tc == vsi->tc_config.enabled_tc &&
6789 mode != TC_MQPRIO_MODE_CHANNEL)
6790 return 0;
6791
6792
6793 i40e_quiesce_vsi(vsi);
6794
6795 if (!hw && !(pf->flags & I40E_FLAG_TC_MQPRIO))
6796 i40e_remove_queue_channels(vsi);
6797
6798
6799 ret = i40e_vsi_config_tc(vsi, enabled_tc);
6800 if (ret) {
6801 netdev_info(netdev, "Failed configuring TC for VSI seid=%d\n",
6802 vsi->seid);
6803 need_reset = true;
6804 goto exit;
6805 }
6806
6807 if (pf->flags & I40E_FLAG_TC_MQPRIO) {
6808 if (vsi->mqprio_qopt.max_rate[0]) {
6809 u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0];
6810
6811 do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR);
6812 ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate);
6813 if (!ret) {
6814 u64 credits = max_tx_rate;
6815
6816 do_div(credits, I40E_BW_CREDIT_DIVISOR);
6817 dev_dbg(&vsi->back->pdev->dev,
6818 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
6819 max_tx_rate,
6820 credits,
6821 vsi->seid);
6822 } else {
6823 need_reset = true;
6824 goto exit;
6825 }
6826 }
6827 ret = i40e_configure_queue_channels(vsi);
6828 if (ret) {
6829 netdev_info(netdev,
6830 "Failed configuring queue channels\n");
6831 need_reset = true;
6832 goto exit;
6833 }
6834 }
6835
6836exit:
6837
6838 if (need_reset) {
6839 i40e_vsi_set_default_tc_config(vsi);
6840 need_reset = false;
6841 }
6842
6843
6844 i40e_unquiesce_vsi(vsi);
6845 return ret;
6846}
6847
6848
6849
6850
6851
6852
6853
6854
6855static inline void
6856i40e_set_cld_element(struct i40e_cloud_filter *filter,
6857 struct i40e_aqc_cloud_filters_element_data *cld)
6858{
6859 int i, j;
6860 u32 ipa;
6861
6862 memset(cld, 0, sizeof(*cld));
6863 ether_addr_copy(cld->outer_mac, filter->dst_mac);
6864 ether_addr_copy(cld->inner_mac, filter->src_mac);
6865
6866 if (filter->n_proto != ETH_P_IP && filter->n_proto != ETH_P_IPV6)
6867 return;
6868
6869 if (filter->n_proto == ETH_P_IPV6) {
6870#define IPV6_MAX_INDEX (ARRAY_SIZE(filter->dst_ipv6) - 1)
6871 for (i = 0, j = 0; i < ARRAY_SIZE(filter->dst_ipv6);
6872 i++, j += 2) {
6873 ipa = be32_to_cpu(filter->dst_ipv6[IPV6_MAX_INDEX - i]);
6874 ipa = cpu_to_le32(ipa);
6875 memcpy(&cld->ipaddr.raw_v6.data[j], &ipa, sizeof(ipa));
6876 }
6877 } else {
6878 ipa = be32_to_cpu(filter->dst_ipv4);
6879 memcpy(&cld->ipaddr.v4.data, &ipa, sizeof(ipa));
6880 }
6881
6882 cld->inner_vlan = cpu_to_le16(ntohs(filter->vlan_id));
6883
6884
6885
6886
6887 if (filter->tenant_id)
6888 return;
6889}
6890
6891
6892
6893
6894
6895
6896
6897
6898
6899
6900int i40e_add_del_cloud_filter(struct i40e_vsi *vsi,
6901 struct i40e_cloud_filter *filter, bool add)
6902{
6903 struct i40e_aqc_cloud_filters_element_data cld_filter;
6904 struct i40e_pf *pf = vsi->back;
6905 int ret;
6906 static const u16 flag_table[128] = {
6907 [I40E_CLOUD_FILTER_FLAGS_OMAC] =
6908 I40E_AQC_ADD_CLOUD_FILTER_OMAC,
6909 [I40E_CLOUD_FILTER_FLAGS_IMAC] =
6910 I40E_AQC_ADD_CLOUD_FILTER_IMAC,
6911 [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN] =
6912 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN,
6913 [I40E_CLOUD_FILTER_FLAGS_IMAC_TEN_ID] =
6914 I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID,
6915 [I40E_CLOUD_FILTER_FLAGS_OMAC_TEN_ID_IMAC] =
6916 I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC,
6917 [I40E_CLOUD_FILTER_FLAGS_IMAC_IVLAN_TEN_ID] =
6918 I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID,
6919 [I40E_CLOUD_FILTER_FLAGS_IIP] =
6920 I40E_AQC_ADD_CLOUD_FILTER_IIP,
6921 };
6922
6923 if (filter->flags >= ARRAY_SIZE(flag_table))
6924 return I40E_ERR_CONFIG;
6925
6926
6927 i40e_set_cld_element(filter, &cld_filter);
6928
6929 if (filter->tunnel_type != I40E_CLOUD_TNL_TYPE_NONE)
6930 cld_filter.flags = cpu_to_le16(filter->tunnel_type <<
6931 I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT);
6932
6933 if (filter->n_proto == ETH_P_IPV6)
6934 cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] |
6935 I40E_AQC_ADD_CLOUD_FLAGS_IPV6);
6936 else
6937 cld_filter.flags |= cpu_to_le16(flag_table[filter->flags] |
6938 I40E_AQC_ADD_CLOUD_FLAGS_IPV4);
6939
6940 if (add)
6941 ret = i40e_aq_add_cloud_filters(&pf->hw, filter->seid,
6942 &cld_filter, 1);
6943 else
6944 ret = i40e_aq_rem_cloud_filters(&pf->hw, filter->seid,
6945 &cld_filter, 1);
6946 if (ret)
6947 dev_dbg(&pf->pdev->dev,
6948 "Failed to %s cloud filter using l4 port %u, err %d aq_err %d\n",
6949 add ? "add" : "delete", filter->dst_port, ret,
6950 pf->hw.aq.asq_last_status);
6951 else
6952 dev_info(&pf->pdev->dev,
6953 "%s cloud filter for VSI: %d\n",
6954 add ? "Added" : "Deleted", filter->seid);
6955 return ret;
6956}
6957
6958
6959
6960
6961
6962
6963
6964
6965
6966
6967int i40e_add_del_cloud_filter_big_buf(struct i40e_vsi *vsi,
6968 struct i40e_cloud_filter *filter,
6969 bool add)
6970{
6971 struct i40e_aqc_cloud_filters_element_bb cld_filter;
6972 struct i40e_pf *pf = vsi->back;
6973 int ret;
6974
6975
6976 if ((is_valid_ether_addr(filter->dst_mac) &&
6977 is_valid_ether_addr(filter->src_mac)) ||
6978 (is_multicast_ether_addr(filter->dst_mac) &&
6979 is_multicast_ether_addr(filter->src_mac)))
6980 return -EOPNOTSUPP;
6981
6982
6983
6984
6985 if (!filter->dst_port || filter->ip_proto == IPPROTO_UDP)
6986 return -EOPNOTSUPP;
6987
6988
6989 if (filter->src_port || filter->src_ipv4 ||
6990 !ipv6_addr_any(&filter->ip.v6.src_ip6))
6991 return -EOPNOTSUPP;
6992
6993
6994 i40e_set_cld_element(filter, &cld_filter.element);
6995
6996 if (is_valid_ether_addr(filter->dst_mac) ||
6997 is_valid_ether_addr(filter->src_mac) ||
6998 is_multicast_ether_addr(filter->dst_mac) ||
6999 is_multicast_ether_addr(filter->src_mac)) {
7000
7001 if (filter->dst_ipv4)
7002 return -EOPNOTSUPP;
7003
7004
7005
7006
7007
7008 cld_filter.element.flags =
7009 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_PORT);
7010
7011 if (filter->vlan_id) {
7012 cld_filter.element.flags =
7013 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_MAC_VLAN_PORT);
7014 }
7015
7016 } else if (filter->dst_ipv4 ||
7017 !ipv6_addr_any(&filter->ip.v6.dst_ip6)) {
7018 cld_filter.element.flags =
7019 cpu_to_le16(I40E_AQC_ADD_CLOUD_FILTER_IP_PORT);
7020 if (filter->n_proto == ETH_P_IPV6)
7021 cld_filter.element.flags |=
7022 cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV6);
7023 else
7024 cld_filter.element.flags |=
7025 cpu_to_le16(I40E_AQC_ADD_CLOUD_FLAGS_IPV4);
7026 } else {
7027 dev_err(&pf->pdev->dev,
7028 "either mac or ip has to be valid for cloud filter\n");
7029 return -EINVAL;
7030 }
7031
7032
7033 cld_filter.general_fields[I40E_AQC_ADD_CLOUD_FV_FLU_0X16_WORD0] =
7034 be16_to_cpu(filter->dst_port);
7035
7036 if (add) {
7037
7038 ret = i40e_validate_and_set_switch_mode(vsi);
7039 if (ret) {
7040 dev_err(&pf->pdev->dev,
7041 "failed to set switch mode, ret %d\n",
7042 ret);
7043 return ret;
7044 }
7045
7046 ret = i40e_aq_add_cloud_filters_bb(&pf->hw, filter->seid,
7047 &cld_filter, 1);
7048 } else {
7049 ret = i40e_aq_rem_cloud_filters_bb(&pf->hw, filter->seid,
7050 &cld_filter, 1);
7051 }
7052
7053 if (ret)
7054 dev_dbg(&pf->pdev->dev,
7055 "Failed to %s cloud filter(big buffer) err %d aq_err %d\n",
7056 add ? "add" : "delete", ret, pf->hw.aq.asq_last_status);
7057 else
7058 dev_info(&pf->pdev->dev,
7059 "%s cloud filter for VSI: %d, L4 port: %d\n",
7060 add ? "add" : "delete", filter->seid,
7061 ntohs(filter->dst_port));
7062 return ret;
7063}
7064
7065
7066
7067
7068
7069
7070
7071
7072static int i40e_parse_cls_flower(struct i40e_vsi *vsi,
7073 struct tc_cls_flower_offload *f,
7074 struct i40e_cloud_filter *filter)
7075{
7076 u16 n_proto_mask = 0, n_proto_key = 0, addr_type = 0;
7077 struct i40e_pf *pf = vsi->back;
7078 u8 field_flags = 0;
7079
7080 if (f->dissector->used_keys &
7081 ~(BIT(FLOW_DISSECTOR_KEY_CONTROL) |
7082 BIT(FLOW_DISSECTOR_KEY_BASIC) |
7083 BIT(FLOW_DISSECTOR_KEY_ETH_ADDRS) |
7084 BIT(FLOW_DISSECTOR_KEY_VLAN) |
7085 BIT(FLOW_DISSECTOR_KEY_IPV4_ADDRS) |
7086 BIT(FLOW_DISSECTOR_KEY_IPV6_ADDRS) |
7087 BIT(FLOW_DISSECTOR_KEY_PORTS) |
7088 BIT(FLOW_DISSECTOR_KEY_ENC_KEYID))) {
7089 dev_err(&pf->pdev->dev, "Unsupported key used: 0x%x\n",
7090 f->dissector->used_keys);
7091 return -EOPNOTSUPP;
7092 }
7093
7094 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ENC_KEYID)) {
7095 struct flow_dissector_key_keyid *key =
7096 skb_flow_dissector_target(f->dissector,
7097 FLOW_DISSECTOR_KEY_ENC_KEYID,
7098 f->key);
7099
7100 struct flow_dissector_key_keyid *mask =
7101 skb_flow_dissector_target(f->dissector,
7102 FLOW_DISSECTOR_KEY_ENC_KEYID,
7103 f->mask);
7104
7105 if (mask->keyid != 0)
7106 field_flags |= I40E_CLOUD_FIELD_TEN_ID;
7107
7108 filter->tenant_id = be32_to_cpu(key->keyid);
7109 }
7110
7111 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_BASIC)) {
7112 struct flow_dissector_key_basic *key =
7113 skb_flow_dissector_target(f->dissector,
7114 FLOW_DISSECTOR_KEY_BASIC,
7115 f->key);
7116
7117 struct flow_dissector_key_basic *mask =
7118 skb_flow_dissector_target(f->dissector,
7119 FLOW_DISSECTOR_KEY_BASIC,
7120 f->mask);
7121
7122 n_proto_key = ntohs(key->n_proto);
7123 n_proto_mask = ntohs(mask->n_proto);
7124
7125 if (n_proto_key == ETH_P_ALL) {
7126 n_proto_key = 0;
7127 n_proto_mask = 0;
7128 }
7129 filter->n_proto = n_proto_key & n_proto_mask;
7130 filter->ip_proto = key->ip_proto;
7131 }
7132
7133 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_ETH_ADDRS)) {
7134 struct flow_dissector_key_eth_addrs *key =
7135 skb_flow_dissector_target(f->dissector,
7136 FLOW_DISSECTOR_KEY_ETH_ADDRS,
7137 f->key);
7138
7139 struct flow_dissector_key_eth_addrs *mask =
7140 skb_flow_dissector_target(f->dissector,
7141 FLOW_DISSECTOR_KEY_ETH_ADDRS,
7142 f->mask);
7143
7144
7145 if (!is_zero_ether_addr(mask->dst)) {
7146 if (is_broadcast_ether_addr(mask->dst)) {
7147 field_flags |= I40E_CLOUD_FIELD_OMAC;
7148 } else {
7149 dev_err(&pf->pdev->dev, "Bad ether dest mask %pM\n",
7150 mask->dst);
7151 return I40E_ERR_CONFIG;
7152 }
7153 }
7154
7155 if (!is_zero_ether_addr(mask->src)) {
7156 if (is_broadcast_ether_addr(mask->src)) {
7157 field_flags |= I40E_CLOUD_FIELD_IMAC;
7158 } else {
7159 dev_err(&pf->pdev->dev, "Bad ether src mask %pM\n",
7160 mask->src);
7161 return I40E_ERR_CONFIG;
7162 }
7163 }
7164 ether_addr_copy(filter->dst_mac, key->dst);
7165 ether_addr_copy(filter->src_mac, key->src);
7166 }
7167
7168 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_VLAN)) {
7169 struct flow_dissector_key_vlan *key =
7170 skb_flow_dissector_target(f->dissector,
7171 FLOW_DISSECTOR_KEY_VLAN,
7172 f->key);
7173 struct flow_dissector_key_vlan *mask =
7174 skb_flow_dissector_target(f->dissector,
7175 FLOW_DISSECTOR_KEY_VLAN,
7176 f->mask);
7177
7178 if (mask->vlan_id) {
7179 if (mask->vlan_id == VLAN_VID_MASK) {
7180 field_flags |= I40E_CLOUD_FIELD_IVLAN;
7181
7182 } else {
7183 dev_err(&pf->pdev->dev, "Bad vlan mask 0x%04x\n",
7184 mask->vlan_id);
7185 return I40E_ERR_CONFIG;
7186 }
7187 }
7188
7189 filter->vlan_id = cpu_to_be16(key->vlan_id);
7190 }
7191
7192 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_CONTROL)) {
7193 struct flow_dissector_key_control *key =
7194 skb_flow_dissector_target(f->dissector,
7195 FLOW_DISSECTOR_KEY_CONTROL,
7196 f->key);
7197
7198 addr_type = key->addr_type;
7199 }
7200
7201 if (addr_type == FLOW_DISSECTOR_KEY_IPV4_ADDRS) {
7202 struct flow_dissector_key_ipv4_addrs *key =
7203 skb_flow_dissector_target(f->dissector,
7204 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
7205 f->key);
7206 struct flow_dissector_key_ipv4_addrs *mask =
7207 skb_flow_dissector_target(f->dissector,
7208 FLOW_DISSECTOR_KEY_IPV4_ADDRS,
7209 f->mask);
7210
7211 if (mask->dst) {
7212 if (mask->dst == cpu_to_be32(0xffffffff)) {
7213 field_flags |= I40E_CLOUD_FIELD_IIP;
7214 } else {
7215 mask->dst = be32_to_cpu(mask->dst);
7216 dev_err(&pf->pdev->dev, "Bad ip dst mask %pI4\n",
7217 &mask->dst);
7218 return I40E_ERR_CONFIG;
7219 }
7220 }
7221
7222 if (mask->src) {
7223 if (mask->src == cpu_to_be32(0xffffffff)) {
7224 field_flags |= I40E_CLOUD_FIELD_IIP;
7225 } else {
7226 mask->src = be32_to_cpu(mask->src);
7227 dev_err(&pf->pdev->dev, "Bad ip src mask %pI4\n",
7228 &mask->src);
7229 return I40E_ERR_CONFIG;
7230 }
7231 }
7232
7233 if (field_flags & I40E_CLOUD_FIELD_TEN_ID) {
7234 dev_err(&pf->pdev->dev, "Tenant id not allowed for ip filter\n");
7235 return I40E_ERR_CONFIG;
7236 }
7237 filter->dst_ipv4 = key->dst;
7238 filter->src_ipv4 = key->src;
7239 }
7240
7241 if (addr_type == FLOW_DISSECTOR_KEY_IPV6_ADDRS) {
7242 struct flow_dissector_key_ipv6_addrs *key =
7243 skb_flow_dissector_target(f->dissector,
7244 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
7245 f->key);
7246 struct flow_dissector_key_ipv6_addrs *mask =
7247 skb_flow_dissector_target(f->dissector,
7248 FLOW_DISSECTOR_KEY_IPV6_ADDRS,
7249 f->mask);
7250
7251
7252
7253
7254 if (ipv6_addr_loopback(&key->dst) ||
7255 ipv6_addr_loopback(&key->src)) {
7256 dev_err(&pf->pdev->dev,
7257 "Bad ipv6, addr is LOOPBACK\n");
7258 return I40E_ERR_CONFIG;
7259 }
7260 if (!ipv6_addr_any(&mask->dst) || !ipv6_addr_any(&mask->src))
7261 field_flags |= I40E_CLOUD_FIELD_IIP;
7262
7263 memcpy(&filter->src_ipv6, &key->src.s6_addr32,
7264 sizeof(filter->src_ipv6));
7265 memcpy(&filter->dst_ipv6, &key->dst.s6_addr32,
7266 sizeof(filter->dst_ipv6));
7267 }
7268
7269 if (dissector_uses_key(f->dissector, FLOW_DISSECTOR_KEY_PORTS)) {
7270 struct flow_dissector_key_ports *key =
7271 skb_flow_dissector_target(f->dissector,
7272 FLOW_DISSECTOR_KEY_PORTS,
7273 f->key);
7274 struct flow_dissector_key_ports *mask =
7275 skb_flow_dissector_target(f->dissector,
7276 FLOW_DISSECTOR_KEY_PORTS,
7277 f->mask);
7278
7279 if (mask->src) {
7280 if (mask->src == cpu_to_be16(0xffff)) {
7281 field_flags |= I40E_CLOUD_FIELD_IIP;
7282 } else {
7283 dev_err(&pf->pdev->dev, "Bad src port mask 0x%04x\n",
7284 be16_to_cpu(mask->src));
7285 return I40E_ERR_CONFIG;
7286 }
7287 }
7288
7289 if (mask->dst) {
7290 if (mask->dst == cpu_to_be16(0xffff)) {
7291 field_flags |= I40E_CLOUD_FIELD_IIP;
7292 } else {
7293 dev_err(&pf->pdev->dev, "Bad dst port mask 0x%04x\n",
7294 be16_to_cpu(mask->dst));
7295 return I40E_ERR_CONFIG;
7296 }
7297 }
7298
7299 filter->dst_port = key->dst;
7300 filter->src_port = key->src;
7301
7302 switch (filter->ip_proto) {
7303 case IPPROTO_TCP:
7304 case IPPROTO_UDP:
7305 break;
7306 default:
7307 dev_err(&pf->pdev->dev,
7308 "Only UDP and TCP transport are supported\n");
7309 return -EINVAL;
7310 }
7311 }
7312 filter->flags = field_flags;
7313 return 0;
7314}
7315
7316
7317
7318
7319
7320
7321
7322
7323static int i40e_handle_tclass(struct i40e_vsi *vsi, u32 tc,
7324 struct i40e_cloud_filter *filter)
7325{
7326 struct i40e_channel *ch, *ch_tmp;
7327
7328
7329 if (tc == 0) {
7330 filter->seid = vsi->seid;
7331 return 0;
7332 } else if (vsi->tc_config.enabled_tc & BIT(tc)) {
7333 if (!filter->dst_port) {
7334 dev_err(&vsi->back->pdev->dev,
7335 "Specify destination port to direct to traffic class that is not default\n");
7336 return -EINVAL;
7337 }
7338 if (list_empty(&vsi->ch_list))
7339 return -EINVAL;
7340 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list,
7341 list) {
7342 if (ch->seid == vsi->tc_seid_map[tc])
7343 filter->seid = ch->seid;
7344 }
7345 return 0;
7346 }
7347 dev_err(&vsi->back->pdev->dev, "TC is not enabled\n");
7348 return -EINVAL;
7349}
7350
7351
7352
7353
7354
7355
7356
7357static int i40e_configure_clsflower(struct i40e_vsi *vsi,
7358 struct tc_cls_flower_offload *cls_flower)
7359{
7360 int tc = tc_classid_to_hwtc(vsi->netdev, cls_flower->classid);
7361 struct i40e_cloud_filter *filter = NULL;
7362 struct i40e_pf *pf = vsi->back;
7363 int err = 0;
7364
7365 if (tc < 0) {
7366 dev_err(&vsi->back->pdev->dev, "Invalid traffic class\n");
7367 return -EOPNOTSUPP;
7368 }
7369
7370 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state) ||
7371 test_bit(__I40E_RESET_INTR_RECEIVED, pf->state))
7372 return -EBUSY;
7373
7374 if (pf->fdir_pf_active_filters ||
7375 (!hlist_empty(&pf->fdir_filter_list))) {
7376 dev_err(&vsi->back->pdev->dev,
7377 "Flow Director Sideband filters exists, turn ntuple off to configure cloud filters\n");
7378 return -EINVAL;
7379 }
7380
7381 if (vsi->back->flags & I40E_FLAG_FD_SB_ENABLED) {
7382 dev_err(&vsi->back->pdev->dev,
7383 "Disable Flow Director Sideband, configuring Cloud filters via tc-flower\n");
7384 vsi->back->flags &= ~I40E_FLAG_FD_SB_ENABLED;
7385 vsi->back->flags |= I40E_FLAG_FD_SB_TO_CLOUD_FILTER;
7386 }
7387
7388 filter = kzalloc(sizeof(*filter), GFP_KERNEL);
7389 if (!filter)
7390 return -ENOMEM;
7391
7392 filter->cookie = cls_flower->cookie;
7393
7394 err = i40e_parse_cls_flower(vsi, cls_flower, filter);
7395 if (err < 0)
7396 goto err;
7397
7398 err = i40e_handle_tclass(vsi, tc, filter);
7399 if (err < 0)
7400 goto err;
7401
7402
7403 if (filter->dst_port)
7404 err = i40e_add_del_cloud_filter_big_buf(vsi, filter, true);
7405 else
7406 err = i40e_add_del_cloud_filter(vsi, filter, true);
7407
7408 if (err) {
7409 dev_err(&pf->pdev->dev,
7410 "Failed to add cloud filter, err %s\n",
7411 i40e_stat_str(&pf->hw, err));
7412 goto err;
7413 }
7414
7415
7416 INIT_HLIST_NODE(&filter->cloud_node);
7417
7418 hlist_add_head(&filter->cloud_node, &pf->cloud_filter_list);
7419
7420 pf->num_cloud_filters++;
7421
7422 return err;
7423err:
7424 kfree(filter);
7425 return err;
7426}
7427
7428
7429
7430
7431
7432
7433
7434static struct i40e_cloud_filter *i40e_find_cloud_filter(struct i40e_vsi *vsi,
7435 unsigned long *cookie)
7436{
7437 struct i40e_cloud_filter *filter = NULL;
7438 struct hlist_node *node2;
7439
7440 hlist_for_each_entry_safe(filter, node2,
7441 &vsi->back->cloud_filter_list, cloud_node)
7442 if (!memcmp(cookie, &filter->cookie, sizeof(filter->cookie)))
7443 return filter;
7444 return NULL;
7445}
7446
7447
7448
7449
7450
7451
7452
7453static int i40e_delete_clsflower(struct i40e_vsi *vsi,
7454 struct tc_cls_flower_offload *cls_flower)
7455{
7456 struct i40e_cloud_filter *filter = NULL;
7457 struct i40e_pf *pf = vsi->back;
7458 int err = 0;
7459
7460 filter = i40e_find_cloud_filter(vsi, &cls_flower->cookie);
7461
7462 if (!filter)
7463 return -EINVAL;
7464
7465 hash_del(&filter->cloud_node);
7466
7467 if (filter->dst_port)
7468 err = i40e_add_del_cloud_filter_big_buf(vsi, filter, false);
7469 else
7470 err = i40e_add_del_cloud_filter(vsi, filter, false);
7471
7472 kfree(filter);
7473 if (err) {
7474 dev_err(&pf->pdev->dev,
7475 "Failed to delete cloud filter, err %s\n",
7476 i40e_stat_str(&pf->hw, err));
7477 return i40e_aq_rc_to_posix(err, pf->hw.aq.asq_last_status);
7478 }
7479
7480 pf->num_cloud_filters--;
7481 if (!pf->num_cloud_filters)
7482 if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) &&
7483 !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) {
7484 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7485 pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER;
7486 pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE;
7487 }
7488 return 0;
7489}
7490
7491
7492
7493
7494
7495
7496static int i40e_setup_tc_cls_flower(struct i40e_netdev_priv *np,
7497 struct tc_cls_flower_offload *cls_flower)
7498{
7499 struct i40e_vsi *vsi = np->vsi;
7500
7501 switch (cls_flower->command) {
7502 case TC_CLSFLOWER_REPLACE:
7503 return i40e_configure_clsflower(vsi, cls_flower);
7504 case TC_CLSFLOWER_DESTROY:
7505 return i40e_delete_clsflower(vsi, cls_flower);
7506 case TC_CLSFLOWER_STATS:
7507 return -EOPNOTSUPP;
7508 default:
7509 return -EINVAL;
7510 }
7511}
7512
7513static int i40e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
7514 void *cb_priv)
7515{
7516 struct i40e_netdev_priv *np = cb_priv;
7517
7518 if (!tc_cls_can_offload_and_chain0(np->vsi->netdev, type_data))
7519 return -EOPNOTSUPP;
7520
7521 switch (type) {
7522 case TC_SETUP_CLSFLOWER:
7523 return i40e_setup_tc_cls_flower(np, type_data);
7524
7525 default:
7526 return -EOPNOTSUPP;
7527 }
7528}
7529
7530static int i40e_setup_tc_block(struct net_device *dev,
7531 struct tc_block_offload *f)
7532{
7533 struct i40e_netdev_priv *np = netdev_priv(dev);
7534
7535 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
7536 return -EOPNOTSUPP;
7537
7538 switch (f->command) {
7539 case TC_BLOCK_BIND:
7540 return tcf_block_cb_register(f->block, i40e_setup_tc_block_cb,
7541 np, np);
7542 case TC_BLOCK_UNBIND:
7543 tcf_block_cb_unregister(f->block, i40e_setup_tc_block_cb, np);
7544 return 0;
7545 default:
7546 return -EOPNOTSUPP;
7547 }
7548}
7549
7550static int __i40e_setup_tc(struct net_device *netdev, enum tc_setup_type type,
7551 void *type_data)
7552{
7553 switch (type) {
7554 case TC_SETUP_QDISC_MQPRIO:
7555 return i40e_setup_tc(netdev, type_data);
7556 case TC_SETUP_BLOCK:
7557 return i40e_setup_tc_block(netdev, type_data);
7558 default:
7559 return -EOPNOTSUPP;
7560 }
7561}
7562
7563
7564
7565
7566
7567
7568
7569
7570
7571
7572
7573
7574
7575int i40e_open(struct net_device *netdev)
7576{
7577 struct i40e_netdev_priv *np = netdev_priv(netdev);
7578 struct i40e_vsi *vsi = np->vsi;
7579 struct i40e_pf *pf = vsi->back;
7580 int err;
7581
7582
7583 if (test_bit(__I40E_TESTING, pf->state) ||
7584 test_bit(__I40E_BAD_EEPROM, pf->state))
7585 return -EBUSY;
7586
7587 netif_carrier_off(netdev);
7588
7589 if (i40e_force_link_state(pf, true))
7590 return -EAGAIN;
7591
7592 err = i40e_vsi_open(vsi);
7593 if (err)
7594 return err;
7595
7596
7597 wr32(&pf->hw, I40E_GLLAN_TSOMSK_F, be32_to_cpu(TCP_FLAG_PSH |
7598 TCP_FLAG_FIN) >> 16);
7599 wr32(&pf->hw, I40E_GLLAN_TSOMSK_M, be32_to_cpu(TCP_FLAG_PSH |
7600 TCP_FLAG_FIN |
7601 TCP_FLAG_CWR) >> 16);
7602 wr32(&pf->hw, I40E_GLLAN_TSOMSK_L, be32_to_cpu(TCP_FLAG_CWR) >> 16);
7603
7604 udp_tunnel_get_rx_info(netdev);
7605
7606 return 0;
7607}
7608
7609
7610
7611
7612
7613
7614
7615
7616
7617
7618
7619int i40e_vsi_open(struct i40e_vsi *vsi)
7620{
7621 struct i40e_pf *pf = vsi->back;
7622 char int_name[I40E_INT_NAME_STR_LEN];
7623 int err;
7624
7625
7626 err = i40e_vsi_setup_tx_resources(vsi);
7627 if (err)
7628 goto err_setup_tx;
7629 err = i40e_vsi_setup_rx_resources(vsi);
7630 if (err)
7631 goto err_setup_rx;
7632
7633 err = i40e_vsi_configure(vsi);
7634 if (err)
7635 goto err_setup_rx;
7636
7637 if (vsi->netdev) {
7638 snprintf(int_name, sizeof(int_name) - 1, "%s-%s",
7639 dev_driver_string(&pf->pdev->dev), vsi->netdev->name);
7640 err = i40e_vsi_request_irq(vsi, int_name);
7641 if (err)
7642 goto err_setup_rx;
7643
7644
7645 err = netif_set_real_num_tx_queues(vsi->netdev,
7646 vsi->num_queue_pairs);
7647 if (err)
7648 goto err_set_queues;
7649
7650 err = netif_set_real_num_rx_queues(vsi->netdev,
7651 vsi->num_queue_pairs);
7652 if (err)
7653 goto err_set_queues;
7654
7655 } else if (vsi->type == I40E_VSI_FDIR) {
7656 snprintf(int_name, sizeof(int_name) - 1, "%s-%s:fdir",
7657 dev_driver_string(&pf->pdev->dev),
7658 dev_name(&pf->pdev->dev));
7659 err = i40e_vsi_request_irq(vsi, int_name);
7660
7661 } else {
7662 err = -EINVAL;
7663 goto err_setup_rx;
7664 }
7665
7666 err = i40e_up_complete(vsi);
7667 if (err)
7668 goto err_up_complete;
7669
7670 return 0;
7671
7672err_up_complete:
7673 i40e_down(vsi);
7674err_set_queues:
7675 i40e_vsi_free_irq(vsi);
7676err_setup_rx:
7677 i40e_vsi_free_rx_resources(vsi);
7678err_setup_tx:
7679 i40e_vsi_free_tx_resources(vsi);
7680 if (vsi == pf->vsi[pf->lan_vsi])
7681 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
7682
7683 return err;
7684}
7685
7686
7687
7688
7689
7690
7691
7692
7693static void i40e_fdir_filter_exit(struct i40e_pf *pf)
7694{
7695 struct i40e_fdir_filter *filter;
7696 struct i40e_flex_pit *pit_entry, *tmp;
7697 struct hlist_node *node2;
7698
7699 hlist_for_each_entry_safe(filter, node2,
7700 &pf->fdir_filter_list, fdir_node) {
7701 hlist_del(&filter->fdir_node);
7702 kfree(filter);
7703 }
7704
7705 list_for_each_entry_safe(pit_entry, tmp, &pf->l3_flex_pit_list, list) {
7706 list_del(&pit_entry->list);
7707 kfree(pit_entry);
7708 }
7709 INIT_LIST_HEAD(&pf->l3_flex_pit_list);
7710
7711 list_for_each_entry_safe(pit_entry, tmp, &pf->l4_flex_pit_list, list) {
7712 list_del(&pit_entry->list);
7713 kfree(pit_entry);
7714 }
7715 INIT_LIST_HEAD(&pf->l4_flex_pit_list);
7716
7717 pf->fdir_pf_active_filters = 0;
7718 pf->fd_tcp4_filter_cnt = 0;
7719 pf->fd_udp4_filter_cnt = 0;
7720 pf->fd_sctp4_filter_cnt = 0;
7721 pf->fd_ip4_filter_cnt = 0;
7722
7723
7724 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
7725 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
7726 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
7727
7728
7729 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_UDP,
7730 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
7731 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
7732
7733
7734 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_SCTP,
7735 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
7736 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
7737
7738
7739 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_OTHER,
7740 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
7741
7742 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_FRAG_IPV4,
7743 I40E_L3_SRC_MASK | I40E_L3_DST_MASK);
7744}
7745
7746
7747
7748
7749
7750
7751
7752
7753static void i40e_cloud_filter_exit(struct i40e_pf *pf)
7754{
7755 struct i40e_cloud_filter *cfilter;
7756 struct hlist_node *node;
7757
7758 hlist_for_each_entry_safe(cfilter, node,
7759 &pf->cloud_filter_list, cloud_node) {
7760 hlist_del(&cfilter->cloud_node);
7761 kfree(cfilter);
7762 }
7763 pf->num_cloud_filters = 0;
7764
7765 if ((pf->flags & I40E_FLAG_FD_SB_TO_CLOUD_FILTER) &&
7766 !(pf->flags & I40E_FLAG_FD_SB_INACTIVE)) {
7767 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
7768 pf->flags &= ~I40E_FLAG_FD_SB_TO_CLOUD_FILTER;
7769 pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE;
7770 }
7771}
7772
7773
7774
7775
7776
7777
7778
7779
7780
7781
7782
7783int i40e_close(struct net_device *netdev)
7784{
7785 struct i40e_netdev_priv *np = netdev_priv(netdev);
7786 struct i40e_vsi *vsi = np->vsi;
7787
7788 i40e_vsi_close(vsi);
7789
7790 return 0;
7791}
7792
7793
7794
7795
7796
7797
7798
7799
7800
7801
7802
7803
7804void i40e_do_reset(struct i40e_pf *pf, u32 reset_flags, bool lock_acquired)
7805{
7806 u32 val;
7807
7808 WARN_ON(in_interrupt());
7809
7810
7811
7812 if (reset_flags & BIT_ULL(__I40E_GLOBAL_RESET_REQUESTED)) {
7813
7814
7815
7816
7817
7818
7819
7820
7821
7822 dev_dbg(&pf->pdev->dev, "GlobalR requested\n");
7823 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7824 val |= I40E_GLGEN_RTRIG_GLOBR_MASK;
7825 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
7826
7827 } else if (reset_flags & BIT_ULL(__I40E_CORE_RESET_REQUESTED)) {
7828
7829
7830
7831
7832
7833 dev_dbg(&pf->pdev->dev, "CoreR requested\n");
7834 val = rd32(&pf->hw, I40E_GLGEN_RTRIG);
7835 val |= I40E_GLGEN_RTRIG_CORER_MASK;
7836 wr32(&pf->hw, I40E_GLGEN_RTRIG, val);
7837 i40e_flush(&pf->hw);
7838
7839 } else if (reset_flags & I40E_PF_RESET_FLAG) {
7840
7841
7842
7843
7844
7845
7846
7847
7848
7849 dev_dbg(&pf->pdev->dev, "PFR requested\n");
7850 i40e_handle_reset_warning(pf, lock_acquired);
7851
7852 } else if (reset_flags & BIT_ULL(__I40E_REINIT_REQUESTED)) {
7853 int v;
7854
7855
7856 dev_info(&pf->pdev->dev,
7857 "VSI reinit requested\n");
7858 for (v = 0; v < pf->num_alloc_vsi; v++) {
7859 struct i40e_vsi *vsi = pf->vsi[v];
7860
7861 if (vsi != NULL &&
7862 test_and_clear_bit(__I40E_VSI_REINIT_REQUESTED,
7863 vsi->state))
7864 i40e_vsi_reinit_locked(pf->vsi[v]);
7865 }
7866 } else if (reset_flags & BIT_ULL(__I40E_DOWN_REQUESTED)) {
7867 int v;
7868
7869
7870 dev_info(&pf->pdev->dev, "VSI down requested\n");
7871 for (v = 0; v < pf->num_alloc_vsi; v++) {
7872 struct i40e_vsi *vsi = pf->vsi[v];
7873
7874 if (vsi != NULL &&
7875 test_and_clear_bit(__I40E_VSI_DOWN_REQUESTED,
7876 vsi->state)) {
7877 set_bit(__I40E_VSI_DOWN, vsi->state);
7878 i40e_down(vsi);
7879 }
7880 }
7881 } else {
7882 dev_info(&pf->pdev->dev,
7883 "bad reset request 0x%08x\n", reset_flags);
7884 }
7885}
7886
7887#ifdef CONFIG_I40E_DCB
7888
7889
7890
7891
7892
7893
7894bool i40e_dcb_need_reconfig(struct i40e_pf *pf,
7895 struct i40e_dcbx_config *old_cfg,
7896 struct i40e_dcbx_config *new_cfg)
7897{
7898 bool need_reconfig = false;
7899
7900
7901 if (memcmp(&new_cfg->etscfg,
7902 &old_cfg->etscfg,
7903 sizeof(new_cfg->etscfg))) {
7904
7905 if (memcmp(&new_cfg->etscfg.prioritytable,
7906 &old_cfg->etscfg.prioritytable,
7907 sizeof(new_cfg->etscfg.prioritytable))) {
7908 need_reconfig = true;
7909 dev_dbg(&pf->pdev->dev, "ETS UP2TC changed.\n");
7910 }
7911
7912 if (memcmp(&new_cfg->etscfg.tcbwtable,
7913 &old_cfg->etscfg.tcbwtable,
7914 sizeof(new_cfg->etscfg.tcbwtable)))
7915 dev_dbg(&pf->pdev->dev, "ETS TC BW Table changed.\n");
7916
7917 if (memcmp(&new_cfg->etscfg.tsatable,
7918 &old_cfg->etscfg.tsatable,
7919 sizeof(new_cfg->etscfg.tsatable)))
7920 dev_dbg(&pf->pdev->dev, "ETS TSA Table changed.\n");
7921 }
7922
7923
7924 if (memcmp(&new_cfg->pfc,
7925 &old_cfg->pfc,
7926 sizeof(new_cfg->pfc))) {
7927 need_reconfig = true;
7928 dev_dbg(&pf->pdev->dev, "PFC config change detected.\n");
7929 }
7930
7931
7932 if (memcmp(&new_cfg->app,
7933 &old_cfg->app,
7934 sizeof(new_cfg->app))) {
7935 need_reconfig = true;
7936 dev_dbg(&pf->pdev->dev, "APP Table change detected.\n");
7937 }
7938
7939 dev_dbg(&pf->pdev->dev, "dcb need_reconfig=%d\n", need_reconfig);
7940 return need_reconfig;
7941}
7942
7943
7944
7945
7946
7947
7948static int i40e_handle_lldp_event(struct i40e_pf *pf,
7949 struct i40e_arq_event_info *e)
7950{
7951 struct i40e_aqc_lldp_get_mib *mib =
7952 (struct i40e_aqc_lldp_get_mib *)&e->desc.params.raw;
7953 struct i40e_hw *hw = &pf->hw;
7954 struct i40e_dcbx_config tmp_dcbx_cfg;
7955 bool need_reconfig = false;
7956 int ret = 0;
7957 u8 type;
7958
7959
7960 if (!(pf->flags & I40E_FLAG_DCB_CAPABLE))
7961 return ret;
7962
7963
7964 type = ((mib->type >> I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT)
7965 & I40E_AQ_LLDP_BRIDGE_TYPE_MASK);
7966 dev_dbg(&pf->pdev->dev, "LLDP event mib bridge type 0x%x\n", type);
7967 if (type != I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE)
7968 return ret;
7969
7970
7971 type = mib->type & I40E_AQ_LLDP_MIB_TYPE_MASK;
7972 dev_dbg(&pf->pdev->dev,
7973 "LLDP event mib type %s\n", type ? "remote" : "local");
7974 if (type == I40E_AQ_LLDP_MIB_REMOTE) {
7975
7976 ret = i40e_aq_get_dcb_config(hw, I40E_AQ_LLDP_MIB_REMOTE,
7977 I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE,
7978 &hw->remote_dcbx_config);
7979 goto exit;
7980 }
7981
7982
7983 tmp_dcbx_cfg = hw->local_dcbx_config;
7984
7985
7986 memset(&hw->local_dcbx_config, 0, sizeof(hw->local_dcbx_config));
7987
7988 ret = i40e_get_dcb_config(&pf->hw);
7989 if (ret) {
7990 dev_info(&pf->pdev->dev,
7991 "Failed querying DCB configuration data from firmware, err %s aq_err %s\n",
7992 i40e_stat_str(&pf->hw, ret),
7993 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
7994 goto exit;
7995 }
7996
7997
7998 if (!memcmp(&tmp_dcbx_cfg, &hw->local_dcbx_config,
7999 sizeof(tmp_dcbx_cfg))) {
8000 dev_dbg(&pf->pdev->dev, "No change detected in DCBX configuration.\n");
8001 goto exit;
8002 }
8003
8004 need_reconfig = i40e_dcb_need_reconfig(pf, &tmp_dcbx_cfg,
8005 &hw->local_dcbx_config);
8006
8007 i40e_dcbnl_flush_apps(pf, &tmp_dcbx_cfg, &hw->local_dcbx_config);
8008
8009 if (!need_reconfig)
8010 goto exit;
8011
8012
8013 if (i40e_dcb_get_num_tc(&hw->local_dcbx_config) > 1)
8014 pf->flags |= I40E_FLAG_DCB_ENABLED;
8015 else
8016 pf->flags &= ~I40E_FLAG_DCB_ENABLED;
8017
8018 set_bit(__I40E_PORT_SUSPENDED, pf->state);
8019
8020 i40e_pf_quiesce_all_vsi(pf);
8021
8022
8023 i40e_dcb_reconfigure(pf);
8024
8025 ret = i40e_resume_port_tx(pf);
8026
8027 clear_bit(__I40E_PORT_SUSPENDED, pf->state);
8028
8029 if (ret)
8030 goto exit;
8031
8032
8033 ret = i40e_pf_wait_queues_disabled(pf);
8034 if (ret) {
8035
8036 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
8037 i40e_service_event_schedule(pf);
8038 } else {
8039 i40e_pf_unquiesce_all_vsi(pf);
8040 set_bit(__I40E_CLIENT_SERVICE_REQUESTED, pf->state);
8041 set_bit(__I40E_CLIENT_L2_CHANGE, pf->state);
8042 }
8043
8044exit:
8045 return ret;
8046}
8047#endif
8048
8049
8050
8051
8052
8053
8054
8055void i40e_do_reset_safe(struct i40e_pf *pf, u32 reset_flags)
8056{
8057 rtnl_lock();
8058 i40e_do_reset(pf, reset_flags, true);
8059 rtnl_unlock();
8060}
8061
8062
8063
8064
8065
8066
8067
8068
8069
8070static void i40e_handle_lan_overflow_event(struct i40e_pf *pf,
8071 struct i40e_arq_event_info *e)
8072{
8073 struct i40e_aqc_lan_overflow *data =
8074 (struct i40e_aqc_lan_overflow *)&e->desc.params.raw;
8075 u32 queue = le32_to_cpu(data->prtdcb_rupto);
8076 u32 qtx_ctl = le32_to_cpu(data->otx_ctl);
8077 struct i40e_hw *hw = &pf->hw;
8078 struct i40e_vf *vf;
8079 u16 vf_id;
8080
8081 dev_dbg(&pf->pdev->dev, "overflow Rx Queue Number = %d QTX_CTL=0x%08x\n",
8082 queue, qtx_ctl);
8083
8084
8085 if (((qtx_ctl & I40E_QTX_CTL_PFVF_Q_MASK)
8086 >> I40E_QTX_CTL_PFVF_Q_SHIFT) == I40E_QTX_CTL_VF_QUEUE) {
8087 vf_id = (u16)((qtx_ctl & I40E_QTX_CTL_VFVM_INDX_MASK)
8088 >> I40E_QTX_CTL_VFVM_INDX_SHIFT);
8089 vf_id -= hw->func_caps.vf_base_id;
8090 vf = &pf->vf[vf_id];
8091 i40e_vc_notify_vf_reset(vf);
8092
8093 msleep(20);
8094 i40e_reset_vf(vf, false);
8095 }
8096}
8097
8098
8099
8100
8101
8102u32 i40e_get_cur_guaranteed_fd_count(struct i40e_pf *pf)
8103{
8104 u32 val, fcnt_prog;
8105
8106 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
8107 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK);
8108 return fcnt_prog;
8109}
8110
8111
8112
8113
8114
8115u32 i40e_get_current_fd_count(struct i40e_pf *pf)
8116{
8117 u32 val, fcnt_prog;
8118
8119 val = rd32(&pf->hw, I40E_PFQF_FDSTAT);
8120 fcnt_prog = (val & I40E_PFQF_FDSTAT_GUARANT_CNT_MASK) +
8121 ((val & I40E_PFQF_FDSTAT_BEST_CNT_MASK) >>
8122 I40E_PFQF_FDSTAT_BEST_CNT_SHIFT);
8123 return fcnt_prog;
8124}
8125
8126
8127
8128
8129
8130u32 i40e_get_global_fd_count(struct i40e_pf *pf)
8131{
8132 u32 val, fcnt_prog;
8133
8134 val = rd32(&pf->hw, I40E_GLQF_FDCNT_0);
8135 fcnt_prog = (val & I40E_GLQF_FDCNT_0_GUARANT_CNT_MASK) +
8136 ((val & I40E_GLQF_FDCNT_0_BESTCNT_MASK) >>
8137 I40E_GLQF_FDCNT_0_BESTCNT_SHIFT);
8138 return fcnt_prog;
8139}
8140
8141
8142
8143
8144
8145static void i40e_reenable_fdir_sb(struct i40e_pf *pf)
8146{
8147 if (test_and_clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state))
8148 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
8149 (I40E_DEBUG_FD & pf->hw.debug_mask))
8150 dev_info(&pf->pdev->dev, "FD Sideband/ntuple is being enabled since we have space in the table now\n");
8151}
8152
8153
8154
8155
8156
8157static void i40e_reenable_fdir_atr(struct i40e_pf *pf)
8158{
8159 if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state)) {
8160
8161
8162
8163
8164
8165 i40e_write_fd_input_set(pf, I40E_FILTER_PCTYPE_NONF_IPV4_TCP,
8166 I40E_L3_SRC_MASK | I40E_L3_DST_MASK |
8167 I40E_L4_SRC_MASK | I40E_L4_DST_MASK);
8168
8169 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
8170 (I40E_DEBUG_FD & pf->hw.debug_mask))
8171 dev_info(&pf->pdev->dev, "ATR is being enabled since we have space in the table and there are no conflicting ntuple rules\n");
8172 }
8173}
8174
8175
8176
8177
8178
8179
8180static void i40e_delete_invalid_filter(struct i40e_pf *pf,
8181 struct i40e_fdir_filter *filter)
8182{
8183
8184 pf->fdir_pf_active_filters--;
8185 pf->fd_inv = 0;
8186
8187 switch (filter->flow_type) {
8188 case TCP_V4_FLOW:
8189 pf->fd_tcp4_filter_cnt--;
8190 break;
8191 case UDP_V4_FLOW:
8192 pf->fd_udp4_filter_cnt--;
8193 break;
8194 case SCTP_V4_FLOW:
8195 pf->fd_sctp4_filter_cnt--;
8196 break;
8197 case IP_USER_FLOW:
8198 switch (filter->ip4_proto) {
8199 case IPPROTO_TCP:
8200 pf->fd_tcp4_filter_cnt--;
8201 break;
8202 case IPPROTO_UDP:
8203 pf->fd_udp4_filter_cnt--;
8204 break;
8205 case IPPROTO_SCTP:
8206 pf->fd_sctp4_filter_cnt--;
8207 break;
8208 case IPPROTO_IP:
8209 pf->fd_ip4_filter_cnt--;
8210 break;
8211 }
8212 break;
8213 }
8214
8215
8216 hlist_del(&filter->fdir_node);
8217 kfree(filter);
8218}
8219
8220
8221
8222
8223
8224void i40e_fdir_check_and_reenable(struct i40e_pf *pf)
8225{
8226 struct i40e_fdir_filter *filter;
8227 u32 fcnt_prog, fcnt_avail;
8228 struct hlist_node *node;
8229
8230 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
8231 return;
8232
8233
8234 fcnt_prog = i40e_get_global_fd_count(pf);
8235 fcnt_avail = pf->fdir_pf_filter_count;
8236 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM)) ||
8237 (pf->fd_add_err == 0) ||
8238 (i40e_get_current_atr_cnt(pf) < pf->fd_atr_cnt))
8239 i40e_reenable_fdir_sb(pf);
8240
8241
8242
8243
8244
8245 if ((fcnt_prog < (fcnt_avail - I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) &&
8246 (pf->fd_tcp4_filter_cnt == 0))
8247 i40e_reenable_fdir_atr(pf);
8248
8249
8250 if (pf->fd_inv > 0) {
8251 hlist_for_each_entry_safe(filter, node,
8252 &pf->fdir_filter_list, fdir_node)
8253 if (filter->fd_id == pf->fd_inv)
8254 i40e_delete_invalid_filter(pf, filter);
8255 }
8256}
8257
8258#define I40E_MIN_FD_FLUSH_INTERVAL 10
8259#define I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE 30
8260
8261
8262
8263
8264static void i40e_fdir_flush_and_replay(struct i40e_pf *pf)
8265{
8266 unsigned long min_flush_time;
8267 int flush_wait_retry = 50;
8268 bool disable_atr = false;
8269 int fd_room;
8270 int reg;
8271
8272 if (!time_after(jiffies, pf->fd_flush_timestamp +
8273 (I40E_MIN_FD_FLUSH_INTERVAL * HZ)))
8274 return;
8275
8276
8277
8278
8279 min_flush_time = pf->fd_flush_timestamp +
8280 (I40E_MIN_FD_FLUSH_SB_ATR_UNSTABLE * HZ);
8281 fd_room = pf->fdir_pf_filter_count - pf->fdir_pf_active_filters;
8282
8283 if (!(time_after(jiffies, min_flush_time)) &&
8284 (fd_room < I40E_FDIR_BUFFER_HEAD_ROOM_FOR_ATR)) {
8285 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8286 dev_info(&pf->pdev->dev, "ATR disabled, not enough FD filter space.\n");
8287 disable_atr = true;
8288 }
8289
8290 pf->fd_flush_timestamp = jiffies;
8291 set_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
8292
8293 wr32(&pf->hw, I40E_PFQF_CTL_1,
8294 I40E_PFQF_CTL_1_CLEARFDTABLE_MASK);
8295 i40e_flush(&pf->hw);
8296 pf->fd_flush_cnt++;
8297 pf->fd_add_err = 0;
8298 do {
8299
8300 usleep_range(5000, 6000);
8301 reg = rd32(&pf->hw, I40E_PFQF_CTL_1);
8302 if (!(reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK))
8303 break;
8304 } while (flush_wait_retry--);
8305 if (reg & I40E_PFQF_CTL_1_CLEARFDTABLE_MASK) {
8306 dev_warn(&pf->pdev->dev, "FD table did not flush, needs more time\n");
8307 } else {
8308
8309 i40e_fdir_filter_restore(pf->vsi[pf->lan_vsi]);
8310 if (!disable_atr && !pf->fd_tcp4_filter_cnt)
8311 clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state);
8312 clear_bit(__I40E_FD_FLUSH_REQUESTED, pf->state);
8313 if (I40E_DEBUG_FD & pf->hw.debug_mask)
8314 dev_info(&pf->pdev->dev, "FD Filter table flushed and FD-SB replayed.\n");
8315 }
8316}
8317
8318
8319
8320
8321
8322u32 i40e_get_current_atr_cnt(struct i40e_pf *pf)
8323{
8324 return i40e_get_current_fd_count(pf) - pf->fdir_pf_active_filters;
8325}
8326
8327
8328
8329
8330
8331
8332#define I40E_MAX_FD_PROGRAM_ERROR 256
8333
8334
8335
8336
8337
8338static void i40e_fdir_reinit_subtask(struct i40e_pf *pf)
8339{
8340
8341
8342 if (test_bit(__I40E_DOWN, pf->state))
8343 return;
8344
8345 if (test_bit(__I40E_FD_FLUSH_REQUESTED, pf->state))
8346 i40e_fdir_flush_and_replay(pf);
8347
8348 i40e_fdir_check_and_reenable(pf);
8349
8350}
8351
8352
8353
8354
8355
8356
8357static void i40e_vsi_link_event(struct i40e_vsi *vsi, bool link_up)
8358{
8359 if (!vsi || test_bit(__I40E_VSI_DOWN, vsi->state))
8360 return;
8361
8362 switch (vsi->type) {
8363 case I40E_VSI_MAIN:
8364 if (!vsi->netdev || !vsi->netdev_registered)
8365 break;
8366
8367 if (link_up) {
8368 netif_carrier_on(vsi->netdev);
8369 netif_tx_wake_all_queues(vsi->netdev);
8370 } else {
8371 netif_carrier_off(vsi->netdev);
8372 netif_tx_stop_all_queues(vsi->netdev);
8373 }
8374 break;
8375
8376 case I40E_VSI_SRIOV:
8377 case I40E_VSI_VMDQ2:
8378 case I40E_VSI_CTRL:
8379 case I40E_VSI_IWARP:
8380 case I40E_VSI_MIRROR:
8381 default:
8382
8383 break;
8384 }
8385}
8386
8387
8388
8389
8390
8391
8392static void i40e_veb_link_event(struct i40e_veb *veb, bool link_up)
8393{
8394 struct i40e_pf *pf;
8395 int i;
8396
8397 if (!veb || !veb->pf)
8398 return;
8399 pf = veb->pf;
8400
8401
8402 for (i = 0; i < I40E_MAX_VEB; i++)
8403 if (pf->veb[i] && (pf->veb[i]->uplink_seid == veb->seid))
8404 i40e_veb_link_event(pf->veb[i], link_up);
8405
8406
8407 for (i = 0; i < pf->num_alloc_vsi; i++)
8408 if (pf->vsi[i] && (pf->vsi[i]->uplink_seid == veb->seid))
8409 i40e_vsi_link_event(pf->vsi[i], link_up);
8410}
8411
8412
8413
8414
8415
8416static void i40e_link_event(struct i40e_pf *pf)
8417{
8418 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8419 u8 new_link_speed, old_link_speed;
8420 i40e_status status;
8421 bool new_link, old_link;
8422
8423
8424 pf->hw.phy.link_info_old = pf->hw.phy.link_info;
8425
8426
8427 pf->hw.phy.get_link_info = true;
8428
8429 old_link = (pf->hw.phy.link_info_old.link_info & I40E_AQ_LINK_UP);
8430
8431 status = i40e_get_link_status(&pf->hw, &new_link);
8432
8433
8434 if (status == I40E_SUCCESS) {
8435 clear_bit(__I40E_TEMP_LINK_POLLING, pf->state);
8436 } else {
8437
8438
8439
8440 set_bit(__I40E_TEMP_LINK_POLLING, pf->state);
8441 dev_dbg(&pf->pdev->dev, "couldn't get link state, status: %d\n",
8442 status);
8443 return;
8444 }
8445
8446 old_link_speed = pf->hw.phy.link_info_old.link_speed;
8447 new_link_speed = pf->hw.phy.link_info.link_speed;
8448
8449 if (new_link == old_link &&
8450 new_link_speed == old_link_speed &&
8451 (test_bit(__I40E_VSI_DOWN, vsi->state) ||
8452 new_link == netif_carrier_ok(vsi->netdev)))
8453 return;
8454
8455 i40e_print_link_message(vsi, new_link);
8456
8457
8458
8459
8460 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
8461 i40e_veb_link_event(pf->veb[pf->lan_veb], new_link);
8462 else
8463 i40e_vsi_link_event(vsi, new_link);
8464
8465 if (pf->vf)
8466 i40e_vc_notify_link_state(pf);
8467
8468 if (pf->flags & I40E_FLAG_PTP)
8469 i40e_ptp_set_increment(pf);
8470}
8471
8472
8473
8474
8475
8476static void i40e_watchdog_subtask(struct i40e_pf *pf)
8477{
8478 int i;
8479
8480
8481 if (test_bit(__I40E_DOWN, pf->state) ||
8482 test_bit(__I40E_CONFIG_BUSY, pf->state))
8483 return;
8484
8485
8486 if (time_before(jiffies, (pf->service_timer_previous +
8487 pf->service_timer_period)))
8488 return;
8489 pf->service_timer_previous = jiffies;
8490
8491 if ((pf->flags & I40E_FLAG_LINK_POLLING_ENABLED) ||
8492 test_bit(__I40E_TEMP_LINK_POLLING, pf->state))
8493 i40e_link_event(pf);
8494
8495
8496
8497
8498 for (i = 0; i < pf->num_alloc_vsi; i++)
8499 if (pf->vsi[i] && pf->vsi[i]->netdev)
8500 i40e_update_stats(pf->vsi[i]);
8501
8502 if (pf->flags & I40E_FLAG_VEB_STATS_ENABLED) {
8503
8504 for (i = 0; i < I40E_MAX_VEB; i++)
8505 if (pf->veb[i])
8506 i40e_update_veb_stats(pf->veb[i]);
8507 }
8508
8509 i40e_ptp_rx_hang(pf);
8510 i40e_ptp_tx_hang(pf);
8511}
8512
8513
8514
8515
8516
8517static void i40e_reset_subtask(struct i40e_pf *pf)
8518{
8519 u32 reset_flags = 0;
8520
8521 if (test_bit(__I40E_REINIT_REQUESTED, pf->state)) {
8522 reset_flags |= BIT(__I40E_REINIT_REQUESTED);
8523 clear_bit(__I40E_REINIT_REQUESTED, pf->state);
8524 }
8525 if (test_bit(__I40E_PF_RESET_REQUESTED, pf->state)) {
8526 reset_flags |= BIT(__I40E_PF_RESET_REQUESTED);
8527 clear_bit(__I40E_PF_RESET_REQUESTED, pf->state);
8528 }
8529 if (test_bit(__I40E_CORE_RESET_REQUESTED, pf->state)) {
8530 reset_flags |= BIT(__I40E_CORE_RESET_REQUESTED);
8531 clear_bit(__I40E_CORE_RESET_REQUESTED, pf->state);
8532 }
8533 if (test_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state)) {
8534 reset_flags |= BIT(__I40E_GLOBAL_RESET_REQUESTED);
8535 clear_bit(__I40E_GLOBAL_RESET_REQUESTED, pf->state);
8536 }
8537 if (test_bit(__I40E_DOWN_REQUESTED, pf->state)) {
8538 reset_flags |= BIT(__I40E_DOWN_REQUESTED);
8539 clear_bit(__I40E_DOWN_REQUESTED, pf->state);
8540 }
8541
8542
8543
8544
8545 if (test_bit(__I40E_RESET_INTR_RECEIVED, pf->state)) {
8546 i40e_prep_for_reset(pf, false);
8547 i40e_reset(pf);
8548 i40e_rebuild(pf, false, false);
8549 }
8550
8551
8552 if (reset_flags &&
8553 !test_bit(__I40E_DOWN, pf->state) &&
8554 !test_bit(__I40E_CONFIG_BUSY, pf->state)) {
8555 i40e_do_reset(pf, reset_flags, false);
8556 }
8557}
8558
8559
8560
8561
8562
8563
8564static void i40e_handle_link_event(struct i40e_pf *pf,
8565 struct i40e_arq_event_info *e)
8566{
8567 struct i40e_aqc_get_link_status *status =
8568 (struct i40e_aqc_get_link_status *)&e->desc.params.raw;
8569
8570
8571
8572
8573
8574
8575
8576 i40e_link_event(pf);
8577
8578
8579 if (status->phy_type == I40E_PHY_TYPE_NOT_SUPPORTED_HIGH_TEMP) {
8580 dev_err(&pf->pdev->dev,
8581 "Rx/Tx is disabled on this device because the module does not meet thermal requirements.\n");
8582 dev_err(&pf->pdev->dev,
8583 "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n");
8584 } else {
8585
8586
8587
8588 if ((status->link_info & I40E_AQ_MEDIA_AVAILABLE) &&
8589 (!(status->an_info & I40E_AQ_QUALIFIED_MODULE)) &&
8590 (!(status->link_info & I40E_AQ_LINK_UP)) &&
8591 (!(pf->flags & I40E_FLAG_LINK_DOWN_ON_CLOSE_ENABLED))) {
8592 dev_err(&pf->pdev->dev,
8593 "Rx/Tx is disabled on this device because an unsupported SFP module type was detected.\n");
8594 dev_err(&pf->pdev->dev,
8595 "Refer to the Intel(R) Ethernet Adapters and Devices User Guide for a list of supported modules.\n");
8596 }
8597 }
8598}
8599
8600
8601
8602
8603
8604static void i40e_clean_adminq_subtask(struct i40e_pf *pf)
8605{
8606 struct i40e_arq_event_info event;
8607 struct i40e_hw *hw = &pf->hw;
8608 u16 pending, i = 0;
8609 i40e_status ret;
8610 u16 opcode;
8611 u32 oldval;
8612 u32 val;
8613
8614
8615 if (test_bit(__I40E_RESET_FAILED, pf->state))
8616 return;
8617
8618
8619 val = rd32(&pf->hw, pf->hw.aq.arq.len);
8620 oldval = val;
8621 if (val & I40E_PF_ARQLEN_ARQVFE_MASK) {
8622 if (hw->debug_mask & I40E_DEBUG_AQ)
8623 dev_info(&pf->pdev->dev, "ARQ VF Error detected\n");
8624 val &= ~I40E_PF_ARQLEN_ARQVFE_MASK;
8625 }
8626 if (val & I40E_PF_ARQLEN_ARQOVFL_MASK) {
8627 if (hw->debug_mask & I40E_DEBUG_AQ)
8628 dev_info(&pf->pdev->dev, "ARQ Overflow Error detected\n");
8629 val &= ~I40E_PF_ARQLEN_ARQOVFL_MASK;
8630 pf->arq_overflows++;
8631 }
8632 if (val & I40E_PF_ARQLEN_ARQCRIT_MASK) {
8633 if (hw->debug_mask & I40E_DEBUG_AQ)
8634 dev_info(&pf->pdev->dev, "ARQ Critical Error detected\n");
8635 val &= ~I40E_PF_ARQLEN_ARQCRIT_MASK;
8636 }
8637 if (oldval != val)
8638 wr32(&pf->hw, pf->hw.aq.arq.len, val);
8639
8640 val = rd32(&pf->hw, pf->hw.aq.asq.len);
8641 oldval = val;
8642 if (val & I40E_PF_ATQLEN_ATQVFE_MASK) {
8643 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
8644 dev_info(&pf->pdev->dev, "ASQ VF Error detected\n");
8645 val &= ~I40E_PF_ATQLEN_ATQVFE_MASK;
8646 }
8647 if (val & I40E_PF_ATQLEN_ATQOVFL_MASK) {
8648 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
8649 dev_info(&pf->pdev->dev, "ASQ Overflow Error detected\n");
8650 val &= ~I40E_PF_ATQLEN_ATQOVFL_MASK;
8651 }
8652 if (val & I40E_PF_ATQLEN_ATQCRIT_MASK) {
8653 if (pf->hw.debug_mask & I40E_DEBUG_AQ)
8654 dev_info(&pf->pdev->dev, "ASQ Critical Error detected\n");
8655 val &= ~I40E_PF_ATQLEN_ATQCRIT_MASK;
8656 }
8657 if (oldval != val)
8658 wr32(&pf->hw, pf->hw.aq.asq.len, val);
8659
8660 event.buf_len = I40E_MAX_AQ_BUF_SIZE;
8661 event.msg_buf = kzalloc(event.buf_len, GFP_KERNEL);
8662 if (!event.msg_buf)
8663 return;
8664
8665 do {
8666 ret = i40e_clean_arq_element(hw, &event, &pending);
8667 if (ret == I40E_ERR_ADMIN_QUEUE_NO_WORK)
8668 break;
8669 else if (ret) {
8670 dev_info(&pf->pdev->dev, "ARQ event error %d\n", ret);
8671 break;
8672 }
8673
8674 opcode = le16_to_cpu(event.desc.opcode);
8675 switch (opcode) {
8676
8677 case i40e_aqc_opc_get_link_status:
8678 i40e_handle_link_event(pf, &event);
8679 break;
8680 case i40e_aqc_opc_send_msg_to_pf:
8681 ret = i40e_vc_process_vf_msg(pf,
8682 le16_to_cpu(event.desc.retval),
8683 le32_to_cpu(event.desc.cookie_high),
8684 le32_to_cpu(event.desc.cookie_low),
8685 event.msg_buf,
8686 event.msg_len);
8687 break;
8688 case i40e_aqc_opc_lldp_update_mib:
8689 dev_dbg(&pf->pdev->dev, "ARQ: Update LLDP MIB event received\n");
8690#ifdef CONFIG_I40E_DCB
8691 rtnl_lock();
8692 ret = i40e_handle_lldp_event(pf, &event);
8693 rtnl_unlock();
8694#endif
8695 break;
8696 case i40e_aqc_opc_event_lan_overflow:
8697 dev_dbg(&pf->pdev->dev, "ARQ LAN queue overflow event received\n");
8698 i40e_handle_lan_overflow_event(pf, &event);
8699 break;
8700 case i40e_aqc_opc_send_msg_to_peer:
8701 dev_info(&pf->pdev->dev, "ARQ: Msg from other pf\n");
8702 break;
8703 case i40e_aqc_opc_nvm_erase:
8704 case i40e_aqc_opc_nvm_update:
8705 case i40e_aqc_opc_oem_post_update:
8706 i40e_debug(&pf->hw, I40E_DEBUG_NVM,
8707 "ARQ NVM operation 0x%04x completed\n",
8708 opcode);
8709 break;
8710 default:
8711 dev_info(&pf->pdev->dev,
8712 "ARQ: Unknown event 0x%04x ignored\n",
8713 opcode);
8714 break;
8715 }
8716 } while (i++ < pf->adminq_work_limit);
8717
8718 if (i < pf->adminq_work_limit)
8719 clear_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state);
8720
8721
8722 val = rd32(hw, I40E_PFINT_ICR0_ENA);
8723 val |= I40E_PFINT_ICR0_ENA_ADMINQ_MASK;
8724 wr32(hw, I40E_PFINT_ICR0_ENA, val);
8725 i40e_flush(hw);
8726
8727 kfree(event.msg_buf);
8728}
8729
8730
8731
8732
8733
8734static void i40e_verify_eeprom(struct i40e_pf *pf)
8735{
8736 int err;
8737
8738 err = i40e_diag_eeprom_test(&pf->hw);
8739 if (err) {
8740
8741 err = i40e_diag_eeprom_test(&pf->hw);
8742 if (err) {
8743 dev_info(&pf->pdev->dev, "eeprom check failed (%d), Tx/Rx traffic disabled\n",
8744 err);
8745 set_bit(__I40E_BAD_EEPROM, pf->state);
8746 }
8747 }
8748
8749 if (!err && test_bit(__I40E_BAD_EEPROM, pf->state)) {
8750 dev_info(&pf->pdev->dev, "eeprom check passed, Tx/Rx traffic enabled\n");
8751 clear_bit(__I40E_BAD_EEPROM, pf->state);
8752 }
8753}
8754
8755
8756
8757
8758
8759
8760
8761static void i40e_enable_pf_switch_lb(struct i40e_pf *pf)
8762{
8763 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8764 struct i40e_vsi_context ctxt;
8765 int ret;
8766
8767 ctxt.seid = pf->main_vsi_seid;
8768 ctxt.pf_num = pf->hw.pf_id;
8769 ctxt.vf_num = 0;
8770 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8771 if (ret) {
8772 dev_info(&pf->pdev->dev,
8773 "couldn't get PF vsi config, err %s aq_err %s\n",
8774 i40e_stat_str(&pf->hw, ret),
8775 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
8776 return;
8777 }
8778 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8779 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8780 ctxt.info.switch_id |= cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8781
8782 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
8783 if (ret) {
8784 dev_info(&pf->pdev->dev,
8785 "update vsi switch failed, err %s aq_err %s\n",
8786 i40e_stat_str(&pf->hw, ret),
8787 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
8788 }
8789}
8790
8791
8792
8793
8794
8795
8796
8797static void i40e_disable_pf_switch_lb(struct i40e_pf *pf)
8798{
8799 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
8800 struct i40e_vsi_context ctxt;
8801 int ret;
8802
8803 ctxt.seid = pf->main_vsi_seid;
8804 ctxt.pf_num = pf->hw.pf_id;
8805 ctxt.vf_num = 0;
8806 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
8807 if (ret) {
8808 dev_info(&pf->pdev->dev,
8809 "couldn't get PF vsi config, err %s aq_err %s\n",
8810 i40e_stat_str(&pf->hw, ret),
8811 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
8812 return;
8813 }
8814 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
8815 ctxt.info.valid_sections = cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
8816 ctxt.info.switch_id &= ~cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
8817
8818 ret = i40e_aq_update_vsi_params(&vsi->back->hw, &ctxt, NULL);
8819 if (ret) {
8820 dev_info(&pf->pdev->dev,
8821 "update vsi switch failed, err %s aq_err %s\n",
8822 i40e_stat_str(&pf->hw, ret),
8823 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
8824 }
8825}
8826
8827
8828
8829
8830
8831
8832
8833
8834
8835static void i40e_config_bridge_mode(struct i40e_veb *veb)
8836{
8837 struct i40e_pf *pf = veb->pf;
8838
8839 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
8840 dev_info(&pf->pdev->dev, "enabling bridge mode: %s\n",
8841 veb->bridge_mode == BRIDGE_MODE_VEPA ? "VEPA" : "VEB");
8842 if (veb->bridge_mode & BRIDGE_MODE_VEPA)
8843 i40e_disable_pf_switch_lb(pf);
8844 else
8845 i40e_enable_pf_switch_lb(pf);
8846}
8847
8848
8849
8850
8851
8852
8853
8854
8855
8856
8857static int i40e_reconstitute_veb(struct i40e_veb *veb)
8858{
8859 struct i40e_vsi *ctl_vsi = NULL;
8860 struct i40e_pf *pf = veb->pf;
8861 int v, veb_idx;
8862 int ret;
8863
8864
8865 for (v = 0; v < pf->num_alloc_vsi && !ctl_vsi; v++) {
8866 if (pf->vsi[v] &&
8867 pf->vsi[v]->veb_idx == veb->idx &&
8868 pf->vsi[v]->flags & I40E_VSI_FLAG_VEB_OWNER) {
8869 ctl_vsi = pf->vsi[v];
8870 break;
8871 }
8872 }
8873 if (!ctl_vsi) {
8874 dev_info(&pf->pdev->dev,
8875 "missing owner VSI for veb_idx %d\n", veb->idx);
8876 ret = -ENOENT;
8877 goto end_reconstitute;
8878 }
8879 if (ctl_vsi != pf->vsi[pf->lan_vsi])
8880 ctl_vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
8881 ret = i40e_add_vsi(ctl_vsi);
8882 if (ret) {
8883 dev_info(&pf->pdev->dev,
8884 "rebuild of veb_idx %d owner VSI failed: %d\n",
8885 veb->idx, ret);
8886 goto end_reconstitute;
8887 }
8888 i40e_vsi_reset_stats(ctl_vsi);
8889
8890
8891 ret = i40e_add_veb(veb, ctl_vsi);
8892 if (ret)
8893 goto end_reconstitute;
8894
8895 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
8896 veb->bridge_mode = BRIDGE_MODE_VEB;
8897 else
8898 veb->bridge_mode = BRIDGE_MODE_VEPA;
8899 i40e_config_bridge_mode(veb);
8900
8901
8902 for (v = 0; v < pf->num_alloc_vsi; v++) {
8903 if (!pf->vsi[v] || pf->vsi[v] == ctl_vsi)
8904 continue;
8905
8906 if (pf->vsi[v]->veb_idx == veb->idx) {
8907 struct i40e_vsi *vsi = pf->vsi[v];
8908
8909 vsi->uplink_seid = veb->seid;
8910 ret = i40e_add_vsi(vsi);
8911 if (ret) {
8912 dev_info(&pf->pdev->dev,
8913 "rebuild of vsi_idx %d failed: %d\n",
8914 v, ret);
8915 goto end_reconstitute;
8916 }
8917 i40e_vsi_reset_stats(vsi);
8918 }
8919 }
8920
8921
8922 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
8923 if (pf->veb[veb_idx] && pf->veb[veb_idx]->veb_idx == veb->idx) {
8924 pf->veb[veb_idx]->uplink_seid = veb->seid;
8925 ret = i40e_reconstitute_veb(pf->veb[veb_idx]);
8926 if (ret)
8927 break;
8928 }
8929 }
8930
8931end_reconstitute:
8932 return ret;
8933}
8934
8935
8936
8937
8938
8939static int i40e_get_capabilities(struct i40e_pf *pf,
8940 enum i40e_admin_queue_opc list_type)
8941{
8942 struct i40e_aqc_list_capabilities_element_resp *cap_buf;
8943 u16 data_size;
8944 int buf_len;
8945 int err;
8946
8947 buf_len = 40 * sizeof(struct i40e_aqc_list_capabilities_element_resp);
8948 do {
8949 cap_buf = kzalloc(buf_len, GFP_KERNEL);
8950 if (!cap_buf)
8951 return -ENOMEM;
8952
8953
8954 err = i40e_aq_discover_capabilities(&pf->hw, cap_buf, buf_len,
8955 &data_size, list_type,
8956 NULL);
8957
8958 kfree(cap_buf);
8959
8960 if (pf->hw.aq.asq_last_status == I40E_AQ_RC_ENOMEM) {
8961
8962 buf_len = data_size;
8963 } else if (pf->hw.aq.asq_last_status != I40E_AQ_RC_OK) {
8964 dev_info(&pf->pdev->dev,
8965 "capability discovery failed, err %s aq_err %s\n",
8966 i40e_stat_str(&pf->hw, err),
8967 i40e_aq_str(&pf->hw,
8968 pf->hw.aq.asq_last_status));
8969 return -ENODEV;
8970 }
8971 } while (err);
8972
8973 if (pf->hw.debug_mask & I40E_DEBUG_USER) {
8974 if (list_type == i40e_aqc_opc_list_func_capabilities) {
8975 dev_info(&pf->pdev->dev,
8976 "pf=%d, num_vfs=%d, msix_pf=%d, msix_vf=%d, fd_g=%d, fd_b=%d, pf_max_q=%d num_vsi=%d\n",
8977 pf->hw.pf_id, pf->hw.func_caps.num_vfs,
8978 pf->hw.func_caps.num_msix_vectors,
8979 pf->hw.func_caps.num_msix_vectors_vf,
8980 pf->hw.func_caps.fd_filters_guaranteed,
8981 pf->hw.func_caps.fd_filters_best_effort,
8982 pf->hw.func_caps.num_tx_qp,
8983 pf->hw.func_caps.num_vsis);
8984 } else if (list_type == i40e_aqc_opc_list_dev_capabilities) {
8985 dev_info(&pf->pdev->dev,
8986 "switch_mode=0x%04x, function_valid=0x%08x\n",
8987 pf->hw.dev_caps.switch_mode,
8988 pf->hw.dev_caps.valid_functions);
8989 dev_info(&pf->pdev->dev,
8990 "SR-IOV=%d, num_vfs for all function=%u\n",
8991 pf->hw.dev_caps.sr_iov_1_1,
8992 pf->hw.dev_caps.num_vfs);
8993 dev_info(&pf->pdev->dev,
8994 "num_vsis=%u, num_rx:%u, num_tx=%u\n",
8995 pf->hw.dev_caps.num_vsis,
8996 pf->hw.dev_caps.num_rx_qp,
8997 pf->hw.dev_caps.num_tx_qp);
8998 }
8999 }
9000 if (list_type == i40e_aqc_opc_list_func_capabilities) {
9001#define DEF_NUM_VSI (1 + (pf->hw.func_caps.fcoe ? 1 : 0) \
9002 + pf->hw.func_caps.num_vfs)
9003 if (pf->hw.revision_id == 0 &&
9004 pf->hw.func_caps.num_vsis < DEF_NUM_VSI) {
9005 dev_info(&pf->pdev->dev,
9006 "got num_vsis %d, setting num_vsis to %d\n",
9007 pf->hw.func_caps.num_vsis, DEF_NUM_VSI);
9008 pf->hw.func_caps.num_vsis = DEF_NUM_VSI;
9009 }
9010 }
9011 return 0;
9012}
9013
9014static int i40e_vsi_clear(struct i40e_vsi *vsi);
9015
9016
9017
9018
9019
9020static void i40e_fdir_sb_setup(struct i40e_pf *pf)
9021{
9022 struct i40e_vsi *vsi;
9023
9024
9025
9026
9027 if (!rd32(&pf->hw, I40E_GLQF_HKEY(0))) {
9028 static const u32 hkey[] = {
9029 0xe640d33f, 0xcdfe98ab, 0x73fa7161, 0x0d7a7d36,
9030 0xeacb7d61, 0xaa4f05b6, 0x9c5c89ed, 0xfc425ddb,
9031 0xa4654832, 0xfc7461d4, 0x8f827619, 0xf5c63c21,
9032 0x95b3a76d};
9033 int i;
9034
9035 for (i = 0; i <= I40E_GLQF_HKEY_MAX_INDEX; i++)
9036 wr32(&pf->hw, I40E_GLQF_HKEY(i), hkey[i]);
9037 }
9038
9039 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
9040 return;
9041
9042
9043 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
9044
9045
9046 if (!vsi) {
9047 vsi = i40e_vsi_setup(pf, I40E_VSI_FDIR,
9048 pf->vsi[pf->lan_vsi]->seid, 0);
9049 if (!vsi) {
9050 dev_info(&pf->pdev->dev, "Couldn't create FDir VSI\n");
9051 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
9052 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
9053 return;
9054 }
9055 }
9056
9057 i40e_vsi_setup_irqhandler(vsi, i40e_fdir_clean_ring);
9058}
9059
9060
9061
9062
9063
9064static void i40e_fdir_teardown(struct i40e_pf *pf)
9065{
9066 struct i40e_vsi *vsi;
9067
9068 i40e_fdir_filter_exit(pf);
9069 vsi = i40e_find_vsi_by_type(pf, I40E_VSI_FDIR);
9070 if (vsi)
9071 i40e_vsi_release(vsi);
9072}
9073
9074
9075
9076
9077
9078
9079
9080
9081
9082static int i40e_rebuild_cloud_filters(struct i40e_vsi *vsi, u16 seid)
9083{
9084 struct i40e_cloud_filter *cfilter;
9085 struct i40e_pf *pf = vsi->back;
9086 struct hlist_node *node;
9087 i40e_status ret;
9088
9089
9090 hlist_for_each_entry_safe(cfilter, node, &pf->cloud_filter_list,
9091 cloud_node) {
9092 if (cfilter->seid != seid)
9093 continue;
9094
9095 if (cfilter->dst_port)
9096 ret = i40e_add_del_cloud_filter_big_buf(vsi, cfilter,
9097 true);
9098 else
9099 ret = i40e_add_del_cloud_filter(vsi, cfilter, true);
9100
9101 if (ret) {
9102 dev_dbg(&pf->pdev->dev,
9103 "Failed to rebuild cloud filter, err %s aq_err %s\n",
9104 i40e_stat_str(&pf->hw, ret),
9105 i40e_aq_str(&pf->hw,
9106 pf->hw.aq.asq_last_status));
9107 return ret;
9108 }
9109 }
9110 return 0;
9111}
9112
9113
9114
9115
9116
9117
9118
9119static int i40e_rebuild_channels(struct i40e_vsi *vsi)
9120{
9121 struct i40e_channel *ch, *ch_tmp;
9122 i40e_status ret;
9123
9124 if (list_empty(&vsi->ch_list))
9125 return 0;
9126
9127 list_for_each_entry_safe(ch, ch_tmp, &vsi->ch_list, list) {
9128 if (!ch->initialized)
9129 break;
9130
9131 ret = i40e_add_channel(vsi->back, vsi->uplink_seid, ch);
9132 if (ret) {
9133 dev_info(&vsi->back->pdev->dev,
9134 "failed to rebuild channels using uplink_seid %u\n",
9135 vsi->uplink_seid);
9136 return ret;
9137 }
9138
9139 ret = i40e_channel_config_tx_ring(vsi->back, vsi, ch);
9140 if (ret) {
9141 dev_info(&vsi->back->pdev->dev,
9142 "failed to configure TX rings for channel %u\n",
9143 ch->seid);
9144 return ret;
9145 }
9146
9147 vsi->next_base_queue = vsi->next_base_queue +
9148 ch->num_queue_pairs;
9149 if (ch->max_tx_rate) {
9150 u64 credits = ch->max_tx_rate;
9151
9152 if (i40e_set_bw_limit(vsi, ch->seid,
9153 ch->max_tx_rate))
9154 return -EINVAL;
9155
9156 do_div(credits, I40E_BW_CREDIT_DIVISOR);
9157 dev_dbg(&vsi->back->pdev->dev,
9158 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
9159 ch->max_tx_rate,
9160 credits,
9161 ch->seid);
9162 }
9163 ret = i40e_rebuild_cloud_filters(vsi, ch->seid);
9164 if (ret) {
9165 dev_dbg(&vsi->back->pdev->dev,
9166 "Failed to rebuild cloud filters for channel VSI %u\n",
9167 ch->seid);
9168 return ret;
9169 }
9170 }
9171 return 0;
9172}
9173
9174
9175
9176
9177
9178
9179
9180
9181
9182static void i40e_prep_for_reset(struct i40e_pf *pf, bool lock_acquired)
9183{
9184 struct i40e_hw *hw = &pf->hw;
9185 i40e_status ret = 0;
9186 u32 v;
9187
9188 clear_bit(__I40E_RESET_INTR_RECEIVED, pf->state);
9189 if (test_and_set_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
9190 return;
9191 if (i40e_check_asq_alive(&pf->hw))
9192 i40e_vc_notify_reset(pf);
9193
9194 dev_dbg(&pf->pdev->dev, "Tearing down internal switch for reset\n");
9195
9196
9197
9198 if (!lock_acquired)
9199 rtnl_lock();
9200 i40e_pf_quiesce_all_vsi(pf);
9201 if (!lock_acquired)
9202 rtnl_unlock();
9203
9204 for (v = 0; v < pf->num_alloc_vsi; v++) {
9205 if (pf->vsi[v])
9206 pf->vsi[v]->seid = 0;
9207 }
9208
9209 i40e_shutdown_adminq(&pf->hw);
9210
9211
9212 if (hw->hmc.hmc_obj) {
9213 ret = i40e_shutdown_lan_hmc(hw);
9214 if (ret)
9215 dev_warn(&pf->pdev->dev,
9216 "shutdown_lan_hmc failed: %d\n", ret);
9217 }
9218}
9219
9220
9221
9222
9223
9224static void i40e_send_version(struct i40e_pf *pf)
9225{
9226 struct i40e_driver_version dv;
9227
9228 dv.major_version = DRV_VERSION_MAJOR;
9229 dv.minor_version = DRV_VERSION_MINOR;
9230 dv.build_version = DRV_VERSION_BUILD;
9231 dv.subbuild_version = 0;
9232 strlcpy(dv.driver_string, DRV_VERSION, sizeof(dv.driver_string));
9233 i40e_aq_send_driver_version(&pf->hw, &dv, NULL);
9234}
9235
9236
9237
9238
9239
9240static void i40e_get_oem_version(struct i40e_hw *hw)
9241{
9242 u16 block_offset = 0xffff;
9243 u16 block_length = 0;
9244 u16 capabilities = 0;
9245 u16 gen_snap = 0;
9246 u16 release = 0;
9247
9248#define I40E_SR_NVM_OEM_VERSION_PTR 0x1B
9249#define I40E_NVM_OEM_LENGTH_OFFSET 0x00
9250#define I40E_NVM_OEM_CAPABILITIES_OFFSET 0x01
9251#define I40E_NVM_OEM_GEN_OFFSET 0x02
9252#define I40E_NVM_OEM_RELEASE_OFFSET 0x03
9253#define I40E_NVM_OEM_CAPABILITIES_MASK 0x000F
9254#define I40E_NVM_OEM_LENGTH 3
9255
9256
9257 i40e_read_nvm_word(hw, I40E_SR_NVM_OEM_VERSION_PTR, &block_offset);
9258 if (block_offset == 0xffff)
9259 return;
9260
9261
9262 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_LENGTH_OFFSET,
9263 &block_length);
9264 if (block_length < I40E_NVM_OEM_LENGTH)
9265 return;
9266
9267
9268 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_CAPABILITIES_OFFSET,
9269 &capabilities);
9270 if ((capabilities & I40E_NVM_OEM_CAPABILITIES_MASK) != 0)
9271 return;
9272
9273 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_GEN_OFFSET,
9274 &gen_snap);
9275 i40e_read_nvm_word(hw, block_offset + I40E_NVM_OEM_RELEASE_OFFSET,
9276 &release);
9277 hw->nvm.oem_ver = (gen_snap << I40E_OEM_SNAP_SHIFT) | release;
9278 hw->nvm.eetrack = I40E_OEM_EETRACK_ID;
9279}
9280
9281
9282
9283
9284
9285static int i40e_reset(struct i40e_pf *pf)
9286{
9287 struct i40e_hw *hw = &pf->hw;
9288 i40e_status ret;
9289
9290 ret = i40e_pf_reset(hw);
9291 if (ret) {
9292 dev_info(&pf->pdev->dev, "PF reset failed, %d\n", ret);
9293 set_bit(__I40E_RESET_FAILED, pf->state);
9294 clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state);
9295 } else {
9296 pf->pfr_count++;
9297 }
9298 return ret;
9299}
9300
9301
9302
9303
9304
9305
9306
9307
9308static void i40e_rebuild(struct i40e_pf *pf, bool reinit, bool lock_acquired)
9309{
9310 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
9311 struct i40e_hw *hw = &pf->hw;
9312 u8 set_fc_aq_fail = 0;
9313 i40e_status ret;
9314 u32 val;
9315 int v;
9316
9317 if (test_bit(__I40E_DOWN, pf->state))
9318 goto clear_recovery;
9319 dev_dbg(&pf->pdev->dev, "Rebuilding internal switch\n");
9320
9321
9322 ret = i40e_init_adminq(&pf->hw);
9323 if (ret) {
9324 dev_info(&pf->pdev->dev, "Rebuild AdminQ failed, err %s aq_err %s\n",
9325 i40e_stat_str(&pf->hw, ret),
9326 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9327 goto clear_recovery;
9328 }
9329 i40e_get_oem_version(&pf->hw);
9330
9331 if (test_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state) &&
9332 ((hw->aq.fw_maj_ver == 4 && hw->aq.fw_min_ver <= 33) ||
9333 hw->aq.fw_maj_ver < 4) && hw->mac.type == I40E_MAC_XL710) {
9334
9335
9336
9337
9338
9339 mdelay(300);
9340 }
9341
9342
9343 if (test_and_clear_bit(__I40E_EMP_RESET_INTR_RECEIVED, pf->state))
9344 i40e_verify_eeprom(pf);
9345
9346 i40e_clear_pxe_mode(hw);
9347 ret = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities);
9348 if (ret)
9349 goto end_core_reset;
9350
9351 ret = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
9352 hw->func_caps.num_rx_qp, 0, 0);
9353 if (ret) {
9354 dev_info(&pf->pdev->dev, "init_lan_hmc failed: %d\n", ret);
9355 goto end_core_reset;
9356 }
9357 ret = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
9358 if (ret) {
9359 dev_info(&pf->pdev->dev, "configure_lan_hmc failed: %d\n", ret);
9360 goto end_core_reset;
9361 }
9362
9363
9364 i40e_aq_set_dcb_parameters(hw, true, NULL);
9365
9366#ifdef CONFIG_I40E_DCB
9367 ret = i40e_init_pf_dcb(pf);
9368 if (ret) {
9369 dev_info(&pf->pdev->dev, "DCB init failed %d, disabled\n", ret);
9370 pf->flags &= ~I40E_FLAG_DCB_CAPABLE;
9371
9372 }
9373#endif
9374
9375 if (!lock_acquired)
9376 rtnl_lock();
9377 ret = i40e_setup_pf_switch(pf, reinit);
9378 if (ret)
9379 goto end_unlock;
9380
9381
9382
9383
9384 ret = i40e_aq_set_phy_int_mask(&pf->hw,
9385 ~(I40E_AQ_EVENT_LINK_UPDOWN |
9386 I40E_AQ_EVENT_MEDIA_NA |
9387 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
9388 if (ret)
9389 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
9390 i40e_stat_str(&pf->hw, ret),
9391 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9392
9393
9394 ret = i40e_set_fc(&pf->hw, &set_fc_aq_fail, true);
9395 if (ret)
9396 dev_dbg(&pf->pdev->dev, "setting flow control: ret = %s last_status = %s\n",
9397 i40e_stat_str(&pf->hw, ret),
9398 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9399
9400
9401
9402
9403
9404
9405
9406
9407 if (vsi->uplink_seid != pf->mac_seid) {
9408 dev_dbg(&pf->pdev->dev, "attempting to rebuild switch\n");
9409
9410 for (v = 0; v < I40E_MAX_VEB; v++) {
9411 if (!pf->veb[v])
9412 continue;
9413
9414 if (pf->veb[v]->uplink_seid == pf->mac_seid ||
9415 pf->veb[v]->uplink_seid == 0) {
9416 ret = i40e_reconstitute_veb(pf->veb[v]);
9417
9418 if (!ret)
9419 continue;
9420
9421
9422
9423
9424
9425
9426
9427 if (pf->veb[v]->uplink_seid == pf->mac_seid) {
9428 dev_info(&pf->pdev->dev,
9429 "rebuild of switch failed: %d, will try to set up simple PF connection\n",
9430 ret);
9431 vsi->uplink_seid = pf->mac_seid;
9432 break;
9433 } else if (pf->veb[v]->uplink_seid == 0) {
9434 dev_info(&pf->pdev->dev,
9435 "rebuild of orphan VEB failed: %d\n",
9436 ret);
9437 }
9438 }
9439 }
9440 }
9441
9442 if (vsi->uplink_seid == pf->mac_seid) {
9443 dev_dbg(&pf->pdev->dev, "attempting to rebuild PF VSI\n");
9444
9445 ret = i40e_add_vsi(vsi);
9446 if (ret) {
9447 dev_info(&pf->pdev->dev,
9448 "rebuild of Main VSI failed: %d\n", ret);
9449 goto end_unlock;
9450 }
9451 }
9452
9453 if (vsi->mqprio_qopt.max_rate[0]) {
9454 u64 max_tx_rate = vsi->mqprio_qopt.max_rate[0];
9455 u64 credits = 0;
9456
9457 do_div(max_tx_rate, I40E_BW_MBPS_DIVISOR);
9458 ret = i40e_set_bw_limit(vsi, vsi->seid, max_tx_rate);
9459 if (ret)
9460 goto end_unlock;
9461
9462 credits = max_tx_rate;
9463 do_div(credits, I40E_BW_CREDIT_DIVISOR);
9464 dev_dbg(&vsi->back->pdev->dev,
9465 "Set tx rate of %llu Mbps (count of 50Mbps %llu) for vsi->seid %u\n",
9466 max_tx_rate,
9467 credits,
9468 vsi->seid);
9469 }
9470
9471 ret = i40e_rebuild_cloud_filters(vsi, vsi->seid);
9472 if (ret)
9473 goto end_unlock;
9474
9475
9476
9477
9478 ret = i40e_rebuild_channels(vsi);
9479 if (ret)
9480 goto end_unlock;
9481
9482
9483
9484
9485
9486#define I40E_REG_MSS 0x000E64DC
9487#define I40E_REG_MSS_MIN_MASK 0x3FF0000
9488#define I40E_64BYTE_MSS 0x400000
9489 val = rd32(hw, I40E_REG_MSS);
9490 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
9491 val &= ~I40E_REG_MSS_MIN_MASK;
9492 val |= I40E_64BYTE_MSS;
9493 wr32(hw, I40E_REG_MSS, val);
9494 }
9495
9496 if (pf->hw_features & I40E_HW_RESTART_AUTONEG) {
9497 msleep(75);
9498 ret = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
9499 if (ret)
9500 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
9501 i40e_stat_str(&pf->hw, ret),
9502 i40e_aq_str(&pf->hw,
9503 pf->hw.aq.asq_last_status));
9504 }
9505
9506 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9507 ret = i40e_setup_misc_vector(pf);
9508
9509
9510
9511
9512
9513
9514
9515 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
9516 pf->main_vsi_seid);
9517
9518
9519 i40e_pf_unquiesce_all_vsi(pf);
9520
9521
9522 if (!lock_acquired)
9523 rtnl_unlock();
9524
9525
9526 ret = i40e_set_promiscuous(pf, pf->cur_promisc);
9527 if (ret)
9528 dev_warn(&pf->pdev->dev,
9529 "Failed to restore promiscuous setting: %s, err %s aq_err %s\n",
9530 pf->cur_promisc ? "on" : "off",
9531 i40e_stat_str(&pf->hw, ret),
9532 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
9533
9534 i40e_reset_all_vfs(pf, true);
9535
9536
9537 i40e_send_version(pf);
9538
9539
9540 goto end_core_reset;
9541
9542end_unlock:
9543 if (!lock_acquired)
9544 rtnl_unlock();
9545end_core_reset:
9546 clear_bit(__I40E_RESET_FAILED, pf->state);
9547clear_recovery:
9548 clear_bit(__I40E_RESET_RECOVERY_PENDING, pf->state);
9549}
9550
9551
9552
9553
9554
9555
9556
9557
9558static void i40e_reset_and_rebuild(struct i40e_pf *pf, bool reinit,
9559 bool lock_acquired)
9560{
9561 int ret;
9562
9563
9564
9565
9566 ret = i40e_reset(pf);
9567 if (!ret)
9568 i40e_rebuild(pf, reinit, lock_acquired);
9569}
9570
9571
9572
9573
9574
9575
9576
9577
9578
9579
9580static void i40e_handle_reset_warning(struct i40e_pf *pf, bool lock_acquired)
9581{
9582 i40e_prep_for_reset(pf, lock_acquired);
9583 i40e_reset_and_rebuild(pf, false, lock_acquired);
9584}
9585
9586
9587
9588
9589
9590
9591
9592static void i40e_handle_mdd_event(struct i40e_pf *pf)
9593{
9594 struct i40e_hw *hw = &pf->hw;
9595 bool mdd_detected = false;
9596 bool pf_mdd_detected = false;
9597 struct i40e_vf *vf;
9598 u32 reg;
9599 int i;
9600
9601 if (!test_bit(__I40E_MDD_EVENT_PENDING, pf->state))
9602 return;
9603
9604
9605 reg = rd32(hw, I40E_GL_MDET_TX);
9606 if (reg & I40E_GL_MDET_TX_VALID_MASK) {
9607 u8 pf_num = (reg & I40E_GL_MDET_TX_PF_NUM_MASK) >>
9608 I40E_GL_MDET_TX_PF_NUM_SHIFT;
9609 u16 vf_num = (reg & I40E_GL_MDET_TX_VF_NUM_MASK) >>
9610 I40E_GL_MDET_TX_VF_NUM_SHIFT;
9611 u8 event = (reg & I40E_GL_MDET_TX_EVENT_MASK) >>
9612 I40E_GL_MDET_TX_EVENT_SHIFT;
9613 u16 queue = ((reg & I40E_GL_MDET_TX_QUEUE_MASK) >>
9614 I40E_GL_MDET_TX_QUEUE_SHIFT) -
9615 pf->hw.func_caps.base_queue;
9616 if (netif_msg_tx_err(pf))
9617 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on TX queue %d PF number 0x%02x VF number 0x%02x\n",
9618 event, queue, pf_num, vf_num);
9619 wr32(hw, I40E_GL_MDET_TX, 0xffffffff);
9620 mdd_detected = true;
9621 }
9622 reg = rd32(hw, I40E_GL_MDET_RX);
9623 if (reg & I40E_GL_MDET_RX_VALID_MASK) {
9624 u8 func = (reg & I40E_GL_MDET_RX_FUNCTION_MASK) >>
9625 I40E_GL_MDET_RX_FUNCTION_SHIFT;
9626 u8 event = (reg & I40E_GL_MDET_RX_EVENT_MASK) >>
9627 I40E_GL_MDET_RX_EVENT_SHIFT;
9628 u16 queue = ((reg & I40E_GL_MDET_RX_QUEUE_MASK) >>
9629 I40E_GL_MDET_RX_QUEUE_SHIFT) -
9630 pf->hw.func_caps.base_queue;
9631 if (netif_msg_rx_err(pf))
9632 dev_info(&pf->pdev->dev, "Malicious Driver Detection event 0x%02x on RX queue %d of function 0x%02x\n",
9633 event, queue, func);
9634 wr32(hw, I40E_GL_MDET_RX, 0xffffffff);
9635 mdd_detected = true;
9636 }
9637
9638 if (mdd_detected) {
9639 reg = rd32(hw, I40E_PF_MDET_TX);
9640 if (reg & I40E_PF_MDET_TX_VALID_MASK) {
9641 wr32(hw, I40E_PF_MDET_TX, 0xFFFF);
9642 dev_info(&pf->pdev->dev, "TX driver issue detected, PF reset issued\n");
9643 pf_mdd_detected = true;
9644 }
9645 reg = rd32(hw, I40E_PF_MDET_RX);
9646 if (reg & I40E_PF_MDET_RX_VALID_MASK) {
9647 wr32(hw, I40E_PF_MDET_RX, 0xFFFF);
9648 dev_info(&pf->pdev->dev, "RX driver issue detected, PF reset issued\n");
9649 pf_mdd_detected = true;
9650 }
9651
9652 if (pf_mdd_detected) {
9653 set_bit(__I40E_PF_RESET_REQUESTED, pf->state);
9654 i40e_service_event_schedule(pf);
9655 }
9656 }
9657
9658
9659 for (i = 0; i < pf->num_alloc_vfs && mdd_detected; i++) {
9660 vf = &(pf->vf[i]);
9661 reg = rd32(hw, I40E_VP_MDET_TX(i));
9662 if (reg & I40E_VP_MDET_TX_VALID_MASK) {
9663 wr32(hw, I40E_VP_MDET_TX(i), 0xFFFF);
9664 vf->num_mdd_events++;
9665 dev_info(&pf->pdev->dev, "TX driver issue detected on VF %d\n",
9666 i);
9667 }
9668
9669 reg = rd32(hw, I40E_VP_MDET_RX(i));
9670 if (reg & I40E_VP_MDET_RX_VALID_MASK) {
9671 wr32(hw, I40E_VP_MDET_RX(i), 0xFFFF);
9672 vf->num_mdd_events++;
9673 dev_info(&pf->pdev->dev, "RX driver issue detected on VF %d\n",
9674 i);
9675 }
9676
9677 if (vf->num_mdd_events > I40E_DEFAULT_NUM_MDD_EVENTS_ALLOWED) {
9678 dev_info(&pf->pdev->dev,
9679 "Too many MDD events on VF %d, disabled\n", i);
9680 dev_info(&pf->pdev->dev,
9681 "Use PF Control I/F to re-enable the VF\n");
9682 set_bit(I40E_VF_STATE_DISABLED, &vf->vf_states);
9683 }
9684 }
9685
9686
9687 clear_bit(__I40E_MDD_EVENT_PENDING, pf->state);
9688 reg = rd32(hw, I40E_PFINT_ICR0_ENA);
9689 reg |= I40E_PFINT_ICR0_ENA_MAL_DETECT_MASK;
9690 wr32(hw, I40E_PFINT_ICR0_ENA, reg);
9691 i40e_flush(hw);
9692}
9693
9694static const char *i40e_tunnel_name(struct i40e_udp_port_config *port)
9695{
9696 switch (port->type) {
9697 case UDP_TUNNEL_TYPE_VXLAN:
9698 return "vxlan";
9699 case UDP_TUNNEL_TYPE_GENEVE:
9700 return "geneve";
9701 default:
9702 return "unknown";
9703 }
9704}
9705
9706
9707
9708
9709
9710static void i40e_sync_udp_filters(struct i40e_pf *pf)
9711{
9712 int i;
9713
9714
9715 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
9716 if (pf->udp_ports[i].port)
9717 pf->pending_udp_bitmap |= BIT_ULL(i);
9718 }
9719
9720 set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state);
9721}
9722
9723
9724
9725
9726
9727static void i40e_sync_udp_filters_subtask(struct i40e_pf *pf)
9728{
9729 struct i40e_hw *hw = &pf->hw;
9730 i40e_status ret;
9731 u16 port;
9732 int i;
9733
9734 if (!test_and_clear_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state))
9735 return;
9736
9737 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
9738 if (pf->pending_udp_bitmap & BIT_ULL(i)) {
9739 pf->pending_udp_bitmap &= ~BIT_ULL(i);
9740 port = pf->udp_ports[i].port;
9741 if (port)
9742 ret = i40e_aq_add_udp_tunnel(hw, port,
9743 pf->udp_ports[i].type,
9744 NULL, NULL);
9745 else
9746 ret = i40e_aq_del_udp_tunnel(hw, i, NULL);
9747
9748 if (ret) {
9749 dev_info(&pf->pdev->dev,
9750 "%s %s port %d, index %d failed, err %s aq_err %s\n",
9751 i40e_tunnel_name(&pf->udp_ports[i]),
9752 port ? "add" : "delete",
9753 port, i,
9754 i40e_stat_str(&pf->hw, ret),
9755 i40e_aq_str(&pf->hw,
9756 pf->hw.aq.asq_last_status));
9757 pf->udp_ports[i].port = 0;
9758 }
9759 }
9760 }
9761}
9762
9763
9764
9765
9766
9767static void i40e_service_task(struct work_struct *work)
9768{
9769 struct i40e_pf *pf = container_of(work,
9770 struct i40e_pf,
9771 service_task);
9772 unsigned long start_time = jiffies;
9773
9774
9775 if (test_bit(__I40E_RESET_RECOVERY_PENDING, pf->state))
9776 return;
9777
9778 if (test_and_set_bit(__I40E_SERVICE_SCHED, pf->state))
9779 return;
9780
9781 i40e_detect_recover_hung(pf->vsi[pf->lan_vsi]);
9782 i40e_sync_filters_subtask(pf);
9783 i40e_reset_subtask(pf);
9784 i40e_handle_mdd_event(pf);
9785 i40e_vc_process_vflr_event(pf);
9786 i40e_watchdog_subtask(pf);
9787 i40e_fdir_reinit_subtask(pf);
9788 if (test_and_clear_bit(__I40E_CLIENT_RESET, pf->state)) {
9789
9790 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], true);
9791 } else {
9792 i40e_client_subtask(pf);
9793 if (test_and_clear_bit(__I40E_CLIENT_L2_CHANGE,
9794 pf->state))
9795 i40e_notify_client_of_l2_param_changes(
9796 pf->vsi[pf->lan_vsi]);
9797 }
9798 i40e_sync_filters_subtask(pf);
9799 i40e_sync_udp_filters_subtask(pf);
9800 i40e_clean_adminq_subtask(pf);
9801
9802
9803 smp_mb__before_atomic();
9804 clear_bit(__I40E_SERVICE_SCHED, pf->state);
9805
9806
9807
9808
9809
9810 if (time_after(jiffies, (start_time + pf->service_timer_period)) ||
9811 test_bit(__I40E_ADMINQ_EVENT_PENDING, pf->state) ||
9812 test_bit(__I40E_MDD_EVENT_PENDING, pf->state) ||
9813 test_bit(__I40E_VFLR_EVENT_PENDING, pf->state))
9814 i40e_service_event_schedule(pf);
9815}
9816
9817
9818
9819
9820
9821static void i40e_service_timer(struct timer_list *t)
9822{
9823 struct i40e_pf *pf = from_timer(pf, t, service_timer);
9824
9825 mod_timer(&pf->service_timer,
9826 round_jiffies(jiffies + pf->service_timer_period));
9827 i40e_service_event_schedule(pf);
9828}
9829
9830
9831
9832
9833
9834static int i40e_set_num_rings_in_vsi(struct i40e_vsi *vsi)
9835{
9836 struct i40e_pf *pf = vsi->back;
9837
9838 switch (vsi->type) {
9839 case I40E_VSI_MAIN:
9840 vsi->alloc_queue_pairs = pf->num_lan_qps;
9841 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
9842 I40E_REQ_DESCRIPTOR_MULTIPLE);
9843 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
9844 vsi->num_q_vectors = pf->num_lan_msix;
9845 else
9846 vsi->num_q_vectors = 1;
9847
9848 break;
9849
9850 case I40E_VSI_FDIR:
9851 vsi->alloc_queue_pairs = 1;
9852 vsi->num_desc = ALIGN(I40E_FDIR_RING_COUNT,
9853 I40E_REQ_DESCRIPTOR_MULTIPLE);
9854 vsi->num_q_vectors = pf->num_fdsb_msix;
9855 break;
9856
9857 case I40E_VSI_VMDQ2:
9858 vsi->alloc_queue_pairs = pf->num_vmdq_qps;
9859 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
9860 I40E_REQ_DESCRIPTOR_MULTIPLE);
9861 vsi->num_q_vectors = pf->num_vmdq_msix;
9862 break;
9863
9864 case I40E_VSI_SRIOV:
9865 vsi->alloc_queue_pairs = pf->num_vf_qps;
9866 vsi->num_desc = ALIGN(I40E_DEFAULT_NUM_DESCRIPTORS,
9867 I40E_REQ_DESCRIPTOR_MULTIPLE);
9868 break;
9869
9870 default:
9871 WARN_ON(1);
9872 return -ENODATA;
9873 }
9874
9875 return 0;
9876}
9877
9878
9879
9880
9881
9882
9883
9884
9885
9886static int i40e_vsi_alloc_arrays(struct i40e_vsi *vsi, bool alloc_qvectors)
9887{
9888 struct i40e_ring **next_rings;
9889 int size;
9890 int ret = 0;
9891
9892
9893 size = sizeof(struct i40e_ring *) * vsi->alloc_queue_pairs *
9894 (i40e_enabled_xdp_vsi(vsi) ? 3 : 2);
9895 vsi->tx_rings = kzalloc(size, GFP_KERNEL);
9896 if (!vsi->tx_rings)
9897 return -ENOMEM;
9898 next_rings = vsi->tx_rings + vsi->alloc_queue_pairs;
9899 if (i40e_enabled_xdp_vsi(vsi)) {
9900 vsi->xdp_rings = next_rings;
9901 next_rings += vsi->alloc_queue_pairs;
9902 }
9903 vsi->rx_rings = next_rings;
9904
9905 if (alloc_qvectors) {
9906
9907 size = sizeof(struct i40e_q_vector *) * vsi->num_q_vectors;
9908 vsi->q_vectors = kzalloc(size, GFP_KERNEL);
9909 if (!vsi->q_vectors) {
9910 ret = -ENOMEM;
9911 goto err_vectors;
9912 }
9913 }
9914 return ret;
9915
9916err_vectors:
9917 kfree(vsi->tx_rings);
9918 return ret;
9919}
9920
9921
9922
9923
9924
9925
9926
9927
9928
9929static int i40e_vsi_mem_alloc(struct i40e_pf *pf, enum i40e_vsi_type type)
9930{
9931 int ret = -ENODEV;
9932 struct i40e_vsi *vsi;
9933 int vsi_idx;
9934 int i;
9935
9936
9937 mutex_lock(&pf->switch_mutex);
9938
9939
9940
9941
9942
9943
9944
9945 i = pf->next_vsi;
9946 while (i < pf->num_alloc_vsi && pf->vsi[i])
9947 i++;
9948 if (i >= pf->num_alloc_vsi) {
9949 i = 0;
9950 while (i < pf->next_vsi && pf->vsi[i])
9951 i++;
9952 }
9953
9954 if (i < pf->num_alloc_vsi && !pf->vsi[i]) {
9955 vsi_idx = i;
9956 } else {
9957 ret = -ENODEV;
9958 goto unlock_pf;
9959 }
9960 pf->next_vsi = ++i;
9961
9962 vsi = kzalloc(sizeof(*vsi), GFP_KERNEL);
9963 if (!vsi) {
9964 ret = -ENOMEM;
9965 goto unlock_pf;
9966 }
9967 vsi->type = type;
9968 vsi->back = pf;
9969 set_bit(__I40E_VSI_DOWN, vsi->state);
9970 vsi->flags = 0;
9971 vsi->idx = vsi_idx;
9972 vsi->int_rate_limit = 0;
9973 vsi->rss_table_size = (vsi->type == I40E_VSI_MAIN) ?
9974 pf->rss_table_size : 64;
9975 vsi->netdev_registered = false;
9976 vsi->work_limit = I40E_DEFAULT_IRQ_WORK;
9977 hash_init(vsi->mac_filter_hash);
9978 vsi->irqs_ready = false;
9979
9980 ret = i40e_set_num_rings_in_vsi(vsi);
9981 if (ret)
9982 goto err_rings;
9983
9984 ret = i40e_vsi_alloc_arrays(vsi, true);
9985 if (ret)
9986 goto err_rings;
9987
9988
9989 i40e_vsi_setup_irqhandler(vsi, i40e_msix_clean_rings);
9990
9991
9992 spin_lock_init(&vsi->mac_filter_hash_lock);
9993 pf->vsi[vsi_idx] = vsi;
9994 ret = vsi_idx;
9995 goto unlock_pf;
9996
9997err_rings:
9998 pf->next_vsi = i - 1;
9999 kfree(vsi);
10000unlock_pf:
10001 mutex_unlock(&pf->switch_mutex);
10002 return ret;
10003}
10004
10005
10006
10007
10008
10009
10010
10011
10012
10013static void i40e_vsi_free_arrays(struct i40e_vsi *vsi, bool free_qvectors)
10014{
10015
10016 if (free_qvectors) {
10017 kfree(vsi->q_vectors);
10018 vsi->q_vectors = NULL;
10019 }
10020 kfree(vsi->tx_rings);
10021 vsi->tx_rings = NULL;
10022 vsi->rx_rings = NULL;
10023 vsi->xdp_rings = NULL;
10024}
10025
10026
10027
10028
10029
10030
10031static void i40e_clear_rss_config_user(struct i40e_vsi *vsi)
10032{
10033 if (!vsi)
10034 return;
10035
10036 kfree(vsi->rss_hkey_user);
10037 vsi->rss_hkey_user = NULL;
10038
10039 kfree(vsi->rss_lut_user);
10040 vsi->rss_lut_user = NULL;
10041}
10042
10043
10044
10045
10046
10047static int i40e_vsi_clear(struct i40e_vsi *vsi)
10048{
10049 struct i40e_pf *pf;
10050
10051 if (!vsi)
10052 return 0;
10053
10054 if (!vsi->back)
10055 goto free_vsi;
10056 pf = vsi->back;
10057
10058 mutex_lock(&pf->switch_mutex);
10059 if (!pf->vsi[vsi->idx]) {
10060 dev_err(&pf->pdev->dev, "pf->vsi[%d] is NULL, just free vsi[%d](type %d)\n",
10061 vsi->idx, vsi->idx, vsi->type);
10062 goto unlock_vsi;
10063 }
10064
10065 if (pf->vsi[vsi->idx] != vsi) {
10066 dev_err(&pf->pdev->dev,
10067 "pf->vsi[%d](type %d) != vsi[%d](type %d): no free!\n",
10068 pf->vsi[vsi->idx]->idx,
10069 pf->vsi[vsi->idx]->type,
10070 vsi->idx, vsi->type);
10071 goto unlock_vsi;
10072 }
10073
10074
10075 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
10076 i40e_put_lump(pf->irq_pile, vsi->base_vector, vsi->idx);
10077
10078 i40e_vsi_free_arrays(vsi, true);
10079 i40e_clear_rss_config_user(vsi);
10080
10081 pf->vsi[vsi->idx] = NULL;
10082 if (vsi->idx < pf->next_vsi)
10083 pf->next_vsi = vsi->idx;
10084
10085unlock_vsi:
10086 mutex_unlock(&pf->switch_mutex);
10087free_vsi:
10088 kfree(vsi);
10089
10090 return 0;
10091}
10092
10093
10094
10095
10096
10097static void i40e_vsi_clear_rings(struct i40e_vsi *vsi)
10098{
10099 int i;
10100
10101 if (vsi->tx_rings && vsi->tx_rings[0]) {
10102 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
10103 kfree_rcu(vsi->tx_rings[i], rcu);
10104 vsi->tx_rings[i] = NULL;
10105 vsi->rx_rings[i] = NULL;
10106 if (vsi->xdp_rings)
10107 vsi->xdp_rings[i] = NULL;
10108 }
10109 }
10110}
10111
10112
10113
10114
10115
10116static int i40e_alloc_rings(struct i40e_vsi *vsi)
10117{
10118 int i, qpv = i40e_enabled_xdp_vsi(vsi) ? 3 : 2;
10119 struct i40e_pf *pf = vsi->back;
10120 struct i40e_ring *ring;
10121
10122
10123 for (i = 0; i < vsi->alloc_queue_pairs; i++) {
10124
10125 ring = kcalloc(qpv, sizeof(struct i40e_ring), GFP_KERNEL);
10126 if (!ring)
10127 goto err_out;
10128
10129 ring->queue_index = i;
10130 ring->reg_idx = vsi->base_queue + i;
10131 ring->ring_active = false;
10132 ring->vsi = vsi;
10133 ring->netdev = vsi->netdev;
10134 ring->dev = &pf->pdev->dev;
10135 ring->count = vsi->num_desc;
10136 ring->size = 0;
10137 ring->dcb_tc = 0;
10138 if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
10139 ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
10140 ring->itr_setting = pf->tx_itr_default;
10141 vsi->tx_rings[i] = ring++;
10142
10143 if (!i40e_enabled_xdp_vsi(vsi))
10144 goto setup_rx;
10145
10146 ring->queue_index = vsi->alloc_queue_pairs + i;
10147 ring->reg_idx = vsi->base_queue + ring->queue_index;
10148 ring->ring_active = false;
10149 ring->vsi = vsi;
10150 ring->netdev = NULL;
10151 ring->dev = &pf->pdev->dev;
10152 ring->count = vsi->num_desc;
10153 ring->size = 0;
10154 ring->dcb_tc = 0;
10155 if (vsi->back->hw_features & I40E_HW_WB_ON_ITR_CAPABLE)
10156 ring->flags = I40E_TXR_FLAGS_WB_ON_ITR;
10157 set_ring_xdp(ring);
10158 ring->itr_setting = pf->tx_itr_default;
10159 vsi->xdp_rings[i] = ring++;
10160
10161setup_rx:
10162 ring->queue_index = i;
10163 ring->reg_idx = vsi->base_queue + i;
10164 ring->ring_active = false;
10165 ring->vsi = vsi;
10166 ring->netdev = vsi->netdev;
10167 ring->dev = &pf->pdev->dev;
10168 ring->count = vsi->num_desc;
10169 ring->size = 0;
10170 ring->dcb_tc = 0;
10171 ring->itr_setting = pf->rx_itr_default;
10172 vsi->rx_rings[i] = ring;
10173 }
10174
10175 return 0;
10176
10177err_out:
10178 i40e_vsi_clear_rings(vsi);
10179 return -ENOMEM;
10180}
10181
10182
10183
10184
10185
10186
10187
10188
10189static int i40e_reserve_msix_vectors(struct i40e_pf *pf, int vectors)
10190{
10191 vectors = pci_enable_msix_range(pf->pdev, pf->msix_entries,
10192 I40E_MIN_MSIX, vectors);
10193 if (vectors < 0) {
10194 dev_info(&pf->pdev->dev,
10195 "MSI-X vector reservation failed: %d\n", vectors);
10196 vectors = 0;
10197 }
10198
10199 return vectors;
10200}
10201
10202
10203
10204
10205
10206
10207
10208
10209
10210static int i40e_init_msix(struct i40e_pf *pf)
10211{
10212 struct i40e_hw *hw = &pf->hw;
10213 int cpus, extra_vectors;
10214 int vectors_left;
10215 int v_budget, i;
10216 int v_actual;
10217 int iwarp_requested = 0;
10218
10219 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
10220 return -ENODEV;
10221
10222
10223
10224
10225
10226
10227
10228
10229
10230
10231
10232
10233
10234
10235
10236
10237 vectors_left = hw->func_caps.num_msix_vectors;
10238 v_budget = 0;
10239
10240
10241 if (vectors_left) {
10242 v_budget++;
10243 vectors_left--;
10244 }
10245
10246
10247
10248
10249
10250
10251
10252
10253 cpus = num_online_cpus();
10254 pf->num_lan_msix = min_t(int, cpus, vectors_left / 2);
10255 vectors_left -= pf->num_lan_msix;
10256
10257
10258 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10259 if (vectors_left) {
10260 pf->num_fdsb_msix = 1;
10261 v_budget++;
10262 vectors_left--;
10263 } else {
10264 pf->num_fdsb_msix = 0;
10265 }
10266 }
10267
10268
10269 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
10270 iwarp_requested = pf->num_iwarp_msix;
10271
10272 if (!vectors_left)
10273 pf->num_iwarp_msix = 0;
10274 else if (vectors_left < pf->num_iwarp_msix)
10275 pf->num_iwarp_msix = 1;
10276 v_budget += pf->num_iwarp_msix;
10277 vectors_left -= pf->num_iwarp_msix;
10278 }
10279
10280
10281 if (pf->flags & I40E_FLAG_VMDQ_ENABLED) {
10282 int vmdq_vecs_wanted = pf->num_vmdq_vsis * pf->num_vmdq_qps;
10283 int vmdq_vecs = min_t(int, vectors_left, vmdq_vecs_wanted);
10284
10285 if (!vectors_left) {
10286 pf->num_vmdq_msix = 0;
10287 pf->num_vmdq_qps = 0;
10288 } else {
10289
10290
10291
10292
10293
10294
10295 if (vmdq_vecs < vmdq_vecs_wanted)
10296 pf->num_vmdq_qps = 1;
10297 pf->num_vmdq_msix = pf->num_vmdq_qps;
10298
10299 v_budget += vmdq_vecs;
10300 vectors_left -= vmdq_vecs;
10301 }
10302 }
10303
10304
10305
10306
10307
10308
10309
10310
10311
10312
10313 extra_vectors = min_t(int, cpus - pf->num_lan_msix, vectors_left);
10314 pf->num_lan_msix += extra_vectors;
10315 vectors_left -= extra_vectors;
10316
10317 WARN(vectors_left < 0,
10318 "Calculation of remaining vectors underflowed. This is an accounting bug when determining total MSI-X vectors.\n");
10319
10320 v_budget += pf->num_lan_msix;
10321 pf->msix_entries = kcalloc(v_budget, sizeof(struct msix_entry),
10322 GFP_KERNEL);
10323 if (!pf->msix_entries)
10324 return -ENOMEM;
10325
10326 for (i = 0; i < v_budget; i++)
10327 pf->msix_entries[i].entry = i;
10328 v_actual = i40e_reserve_msix_vectors(pf, v_budget);
10329
10330 if (v_actual < I40E_MIN_MSIX) {
10331 pf->flags &= ~I40E_FLAG_MSIX_ENABLED;
10332 kfree(pf->msix_entries);
10333 pf->msix_entries = NULL;
10334 pci_disable_msix(pf->pdev);
10335 return -ENODEV;
10336
10337 } else if (v_actual == I40E_MIN_MSIX) {
10338
10339 pf->num_vmdq_vsis = 0;
10340 pf->num_vmdq_qps = 0;
10341 pf->num_lan_qps = 1;
10342 pf->num_lan_msix = 1;
10343
10344 } else if (v_actual != v_budget) {
10345
10346
10347
10348
10349
10350 int vec;
10351
10352 dev_info(&pf->pdev->dev,
10353 "MSI-X vector limit reached with %d, wanted %d, attempting to redistribute vectors\n",
10354 v_actual, v_budget);
10355
10356 vec = v_actual - 1;
10357
10358
10359 pf->num_vmdq_msix = 1;
10360 pf->num_vmdq_vsis = 1;
10361 pf->num_vmdq_qps = 1;
10362
10363
10364 switch (vec) {
10365 case 2:
10366 pf->num_lan_msix = 1;
10367 break;
10368 case 3:
10369 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
10370 pf->num_lan_msix = 1;
10371 pf->num_iwarp_msix = 1;
10372 } else {
10373 pf->num_lan_msix = 2;
10374 }
10375 break;
10376 default:
10377 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
10378 pf->num_iwarp_msix = min_t(int, (vec / 3),
10379 iwarp_requested);
10380 pf->num_vmdq_vsis = min_t(int, (vec / 3),
10381 I40E_DEFAULT_NUM_VMDQ_VSI);
10382 } else {
10383 pf->num_vmdq_vsis = min_t(int, (vec / 2),
10384 I40E_DEFAULT_NUM_VMDQ_VSI);
10385 }
10386 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
10387 pf->num_fdsb_msix = 1;
10388 vec--;
10389 }
10390 pf->num_lan_msix = min_t(int,
10391 (vec - (pf->num_iwarp_msix + pf->num_vmdq_vsis)),
10392 pf->num_lan_msix);
10393 pf->num_lan_qps = pf->num_lan_msix;
10394 break;
10395 }
10396 }
10397
10398 if ((pf->flags & I40E_FLAG_FD_SB_ENABLED) &&
10399 (pf->num_fdsb_msix == 0)) {
10400 dev_info(&pf->pdev->dev, "Sideband Flowdir disabled, not enough MSI-X vectors\n");
10401 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
10402 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
10403 }
10404 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
10405 (pf->num_vmdq_msix == 0)) {
10406 dev_info(&pf->pdev->dev, "VMDq disabled, not enough MSI-X vectors\n");
10407 pf->flags &= ~I40E_FLAG_VMDQ_ENABLED;
10408 }
10409
10410 if ((pf->flags & I40E_FLAG_IWARP_ENABLED) &&
10411 (pf->num_iwarp_msix == 0)) {
10412 dev_info(&pf->pdev->dev, "IWARP disabled, not enough MSI-X vectors\n");
10413 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
10414 }
10415 i40e_debug(&pf->hw, I40E_DEBUG_INIT,
10416 "MSI-X vector distribution: PF %d, VMDq %d, FDSB %d, iWARP %d\n",
10417 pf->num_lan_msix,
10418 pf->num_vmdq_msix * pf->num_vmdq_vsis,
10419 pf->num_fdsb_msix,
10420 pf->num_iwarp_msix);
10421
10422 return v_actual;
10423}
10424
10425
10426
10427
10428
10429
10430
10431
10432
10433static int i40e_vsi_alloc_q_vector(struct i40e_vsi *vsi, int v_idx, int cpu)
10434{
10435 struct i40e_q_vector *q_vector;
10436
10437
10438 q_vector = kzalloc(sizeof(struct i40e_q_vector), GFP_KERNEL);
10439 if (!q_vector)
10440 return -ENOMEM;
10441
10442 q_vector->vsi = vsi;
10443 q_vector->v_idx = v_idx;
10444 cpumask_copy(&q_vector->affinity_mask, cpu_possible_mask);
10445
10446 if (vsi->netdev)
10447 netif_napi_add(vsi->netdev, &q_vector->napi,
10448 i40e_napi_poll, NAPI_POLL_WEIGHT);
10449
10450
10451 vsi->q_vectors[v_idx] = q_vector;
10452
10453 return 0;
10454}
10455
10456
10457
10458
10459
10460
10461
10462
10463static int i40e_vsi_alloc_q_vectors(struct i40e_vsi *vsi)
10464{
10465 struct i40e_pf *pf = vsi->back;
10466 int err, v_idx, num_q_vectors, current_cpu;
10467
10468
10469 if (pf->flags & I40E_FLAG_MSIX_ENABLED)
10470 num_q_vectors = vsi->num_q_vectors;
10471 else if (vsi == pf->vsi[pf->lan_vsi])
10472 num_q_vectors = 1;
10473 else
10474 return -EINVAL;
10475
10476 current_cpu = cpumask_first(cpu_online_mask);
10477
10478 for (v_idx = 0; v_idx < num_q_vectors; v_idx++) {
10479 err = i40e_vsi_alloc_q_vector(vsi, v_idx, current_cpu);
10480 if (err)
10481 goto err_out;
10482 current_cpu = cpumask_next(current_cpu, cpu_online_mask);
10483 if (unlikely(current_cpu >= nr_cpu_ids))
10484 current_cpu = cpumask_first(cpu_online_mask);
10485 }
10486
10487 return 0;
10488
10489err_out:
10490 while (v_idx--)
10491 i40e_free_q_vector(vsi, v_idx);
10492
10493 return err;
10494}
10495
10496
10497
10498
10499
10500static int i40e_init_interrupt_scheme(struct i40e_pf *pf)
10501{
10502 int vectors = 0;
10503 ssize_t size;
10504
10505 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
10506 vectors = i40e_init_msix(pf);
10507 if (vectors < 0) {
10508 pf->flags &= ~(I40E_FLAG_MSIX_ENABLED |
10509 I40E_FLAG_IWARP_ENABLED |
10510 I40E_FLAG_RSS_ENABLED |
10511 I40E_FLAG_DCB_CAPABLE |
10512 I40E_FLAG_DCB_ENABLED |
10513 I40E_FLAG_SRIOV_ENABLED |
10514 I40E_FLAG_FD_SB_ENABLED |
10515 I40E_FLAG_FD_ATR_ENABLED |
10516 I40E_FLAG_VMDQ_ENABLED);
10517 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
10518
10519
10520 i40e_determine_queue_usage(pf);
10521 }
10522 }
10523
10524 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) &&
10525 (pf->flags & I40E_FLAG_MSI_ENABLED)) {
10526 dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
10527 vectors = pci_enable_msi(pf->pdev);
10528 if (vectors < 0) {
10529 dev_info(&pf->pdev->dev, "MSI init failed - %d\n",
10530 vectors);
10531 pf->flags &= ~I40E_FLAG_MSI_ENABLED;
10532 }
10533 vectors = 1;
10534 }
10535
10536 if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED)))
10537 dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
10538
10539
10540 size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
10541 pf->irq_pile = kzalloc(size, GFP_KERNEL);
10542 if (!pf->irq_pile)
10543 return -ENOMEM;
10544
10545 pf->irq_pile->num_entries = vectors;
10546 pf->irq_pile->search_hint = 0;
10547
10548
10549 (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
10550
10551 return 0;
10552}
10553
10554
10555
10556
10557
10558
10559
10560
10561
10562static int i40e_restore_interrupt_scheme(struct i40e_pf *pf)
10563{
10564 int err, i;
10565
10566
10567
10568
10569
10570 pf->flags |= (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED);
10571
10572 err = i40e_init_interrupt_scheme(pf);
10573 if (err)
10574 return err;
10575
10576
10577
10578
10579 for (i = 0; i < pf->num_alloc_vsi; i++) {
10580 if (pf->vsi[i]) {
10581 err = i40e_vsi_alloc_q_vectors(pf->vsi[i]);
10582 if (err)
10583 goto err_unwind;
10584 i40e_vsi_map_rings_to_vectors(pf->vsi[i]);
10585 }
10586 }
10587
10588 err = i40e_setup_misc_vector(pf);
10589 if (err)
10590 goto err_unwind;
10591
10592 if (pf->flags & I40E_FLAG_IWARP_ENABLED)
10593 i40e_client_update_msix_info(pf);
10594
10595 return 0;
10596
10597err_unwind:
10598 while (i--) {
10599 if (pf->vsi[i])
10600 i40e_vsi_free_q_vectors(pf->vsi[i]);
10601 }
10602
10603 return err;
10604}
10605
10606
10607
10608
10609
10610
10611
10612
10613
10614static int i40e_setup_misc_vector(struct i40e_pf *pf)
10615{
10616 struct i40e_hw *hw = &pf->hw;
10617 int err = 0;
10618
10619
10620 if (!test_and_set_bit(__I40E_MISC_IRQ_REQUESTED, pf->state)) {
10621 err = request_irq(pf->msix_entries[0].vector,
10622 i40e_intr, 0, pf->int_name, pf);
10623 if (err) {
10624 clear_bit(__I40E_MISC_IRQ_REQUESTED, pf->state);
10625 dev_info(&pf->pdev->dev,
10626 "request_irq for %s failed: %d\n",
10627 pf->int_name, err);
10628 return -EFAULT;
10629 }
10630 }
10631
10632 i40e_enable_misc_int_causes(pf);
10633
10634
10635 wr32(hw, I40E_PFINT_LNKLST0, I40E_QUEUE_END_OF_LIST);
10636 wr32(hw, I40E_PFINT_ITR0(I40E_RX_ITR), I40E_ITR_8K);
10637
10638 i40e_flush(hw);
10639
10640 i40e_irq_dynamic_enable_icr0(pf);
10641
10642 return err;
10643}
10644
10645
10646
10647
10648
10649
10650
10651
10652
10653
10654static int i40e_get_rss_aq(struct i40e_vsi *vsi, const u8 *seed,
10655 u8 *lut, u16 lut_size)
10656{
10657 struct i40e_pf *pf = vsi->back;
10658 struct i40e_hw *hw = &pf->hw;
10659 int ret = 0;
10660
10661 if (seed) {
10662 ret = i40e_aq_get_rss_key(hw, vsi->id,
10663 (struct i40e_aqc_get_set_rss_key_data *)seed);
10664 if (ret) {
10665 dev_info(&pf->pdev->dev,
10666 "Cannot get RSS key, err %s aq_err %s\n",
10667 i40e_stat_str(&pf->hw, ret),
10668 i40e_aq_str(&pf->hw,
10669 pf->hw.aq.asq_last_status));
10670 return ret;
10671 }
10672 }
10673
10674 if (lut) {
10675 bool pf_lut = vsi->type == I40E_VSI_MAIN ? true : false;
10676
10677 ret = i40e_aq_get_rss_lut(hw, vsi->id, pf_lut, lut, lut_size);
10678 if (ret) {
10679 dev_info(&pf->pdev->dev,
10680 "Cannot get RSS lut, err %s aq_err %s\n",
10681 i40e_stat_str(&pf->hw, ret),
10682 i40e_aq_str(&pf->hw,
10683 pf->hw.aq.asq_last_status));
10684 return ret;
10685 }
10686 }
10687
10688 return ret;
10689}
10690
10691
10692
10693
10694
10695
10696
10697
10698
10699
10700static int i40e_config_rss_reg(struct i40e_vsi *vsi, const u8 *seed,
10701 const u8 *lut, u16 lut_size)
10702{
10703 struct i40e_pf *pf = vsi->back;
10704 struct i40e_hw *hw = &pf->hw;
10705 u16 vf_id = vsi->vf_id;
10706 u8 i;
10707
10708
10709 if (seed) {
10710 u32 *seed_dw = (u32 *)seed;
10711
10712 if (vsi->type == I40E_VSI_MAIN) {
10713 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
10714 wr32(hw, I40E_PFQF_HKEY(i), seed_dw[i]);
10715 } else if (vsi->type == I40E_VSI_SRIOV) {
10716 for (i = 0; i <= I40E_VFQF_HKEY1_MAX_INDEX; i++)
10717 wr32(hw, I40E_VFQF_HKEY1(i, vf_id), seed_dw[i]);
10718 } else {
10719 dev_err(&pf->pdev->dev, "Cannot set RSS seed - invalid VSI type\n");
10720 }
10721 }
10722
10723 if (lut) {
10724 u32 *lut_dw = (u32 *)lut;
10725
10726 if (vsi->type == I40E_VSI_MAIN) {
10727 if (lut_size != I40E_HLUT_ARRAY_SIZE)
10728 return -EINVAL;
10729 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
10730 wr32(hw, I40E_PFQF_HLUT(i), lut_dw[i]);
10731 } else if (vsi->type == I40E_VSI_SRIOV) {
10732 if (lut_size != I40E_VF_HLUT_ARRAY_SIZE)
10733 return -EINVAL;
10734 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
10735 wr32(hw, I40E_VFQF_HLUT1(i, vf_id), lut_dw[i]);
10736 } else {
10737 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
10738 }
10739 }
10740 i40e_flush(hw);
10741
10742 return 0;
10743}
10744
10745
10746
10747
10748
10749
10750
10751
10752
10753
10754static int i40e_get_rss_reg(struct i40e_vsi *vsi, u8 *seed,
10755 u8 *lut, u16 lut_size)
10756{
10757 struct i40e_pf *pf = vsi->back;
10758 struct i40e_hw *hw = &pf->hw;
10759 u16 i;
10760
10761 if (seed) {
10762 u32 *seed_dw = (u32 *)seed;
10763
10764 for (i = 0; i <= I40E_PFQF_HKEY_MAX_INDEX; i++)
10765 seed_dw[i] = i40e_read_rx_ctl(hw, I40E_PFQF_HKEY(i));
10766 }
10767 if (lut) {
10768 u32 *lut_dw = (u32 *)lut;
10769
10770 if (lut_size != I40E_HLUT_ARRAY_SIZE)
10771 return -EINVAL;
10772 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
10773 lut_dw[i] = rd32(hw, I40E_PFQF_HLUT(i));
10774 }
10775
10776 return 0;
10777}
10778
10779
10780
10781
10782
10783
10784
10785
10786
10787
10788int i40e_config_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
10789{
10790 struct i40e_pf *pf = vsi->back;
10791
10792 if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)
10793 return i40e_config_rss_aq(vsi, seed, lut, lut_size);
10794 else
10795 return i40e_config_rss_reg(vsi, seed, lut, lut_size);
10796}
10797
10798
10799
10800
10801
10802
10803
10804
10805
10806
10807int i40e_get_rss(struct i40e_vsi *vsi, u8 *seed, u8 *lut, u16 lut_size)
10808{
10809 struct i40e_pf *pf = vsi->back;
10810
10811 if (pf->hw_features & I40E_HW_RSS_AQ_CAPABLE)
10812 return i40e_get_rss_aq(vsi, seed, lut, lut_size);
10813 else
10814 return i40e_get_rss_reg(vsi, seed, lut, lut_size);
10815}
10816
10817
10818
10819
10820
10821
10822
10823
10824void i40e_fill_rss_lut(struct i40e_pf *pf, u8 *lut,
10825 u16 rss_table_size, u16 rss_size)
10826{
10827 u16 i;
10828
10829 for (i = 0; i < rss_table_size; i++)
10830 lut[i] = i % rss_size;
10831}
10832
10833
10834
10835
10836
10837static int i40e_pf_config_rss(struct i40e_pf *pf)
10838{
10839 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
10840 u8 seed[I40E_HKEY_ARRAY_SIZE];
10841 u8 *lut;
10842 struct i40e_hw *hw = &pf->hw;
10843 u32 reg_val;
10844 u64 hena;
10845 int ret;
10846
10847
10848 hena = (u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(0)) |
10849 ((u64)i40e_read_rx_ctl(hw, I40E_PFQF_HENA(1)) << 32);
10850 hena |= i40e_pf_get_default_rss_hena(pf);
10851
10852 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), (u32)hena);
10853 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), (u32)(hena >> 32));
10854
10855
10856 reg_val = i40e_read_rx_ctl(hw, I40E_PFQF_CTL_0);
10857 reg_val = (pf->rss_table_size == 512) ?
10858 (reg_val | I40E_PFQF_CTL_0_HASHLUTSIZE_512) :
10859 (reg_val & ~I40E_PFQF_CTL_0_HASHLUTSIZE_512);
10860 i40e_write_rx_ctl(hw, I40E_PFQF_CTL_0, reg_val);
10861
10862
10863 if (!vsi->rss_size) {
10864 u16 qcount;
10865
10866
10867
10868
10869
10870 qcount = vsi->num_queue_pairs /
10871 (vsi->tc_config.numtc ? vsi->tc_config.numtc : 1);
10872 vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount);
10873 }
10874 if (!vsi->rss_size)
10875 return -EINVAL;
10876
10877 lut = kzalloc(vsi->rss_table_size, GFP_KERNEL);
10878 if (!lut)
10879 return -ENOMEM;
10880
10881
10882 if (vsi->rss_lut_user)
10883 memcpy(lut, vsi->rss_lut_user, vsi->rss_table_size);
10884 else
10885 i40e_fill_rss_lut(pf, lut, vsi->rss_table_size, vsi->rss_size);
10886
10887
10888
10889
10890 if (vsi->rss_hkey_user)
10891 memcpy(seed, vsi->rss_hkey_user, I40E_HKEY_ARRAY_SIZE);
10892 else
10893 netdev_rss_key_fill((void *)seed, I40E_HKEY_ARRAY_SIZE);
10894 ret = i40e_config_rss(vsi, seed, lut, vsi->rss_table_size);
10895 kfree(lut);
10896
10897 return ret;
10898}
10899
10900
10901
10902
10903
10904
10905
10906
10907
10908
10909int i40e_reconfig_rss_queues(struct i40e_pf *pf, int queue_count)
10910{
10911 struct i40e_vsi *vsi = pf->vsi[pf->lan_vsi];
10912 int new_rss_size;
10913
10914 if (!(pf->flags & I40E_FLAG_RSS_ENABLED))
10915 return 0;
10916
10917 new_rss_size = min_t(int, queue_count, pf->rss_size_max);
10918
10919 if (queue_count != vsi->num_queue_pairs) {
10920 u16 qcount;
10921
10922 vsi->req_queue_pairs = queue_count;
10923 i40e_prep_for_reset(pf, true);
10924
10925 pf->alloc_rss_size = new_rss_size;
10926
10927 i40e_reset_and_rebuild(pf, true, true);
10928
10929
10930
10931
10932 if (queue_count < vsi->rss_size) {
10933 i40e_clear_rss_config_user(vsi);
10934 dev_dbg(&pf->pdev->dev,
10935 "discard user configured hash keys and lut\n");
10936 }
10937
10938
10939 qcount = vsi->num_queue_pairs / vsi->tc_config.numtc;
10940 vsi->rss_size = min_t(int, pf->alloc_rss_size, qcount);
10941
10942 i40e_pf_config_rss(pf);
10943 }
10944 dev_info(&pf->pdev->dev, "User requested queue count/HW max RSS count: %d/%d\n",
10945 vsi->req_queue_pairs, pf->rss_size_max);
10946 return pf->alloc_rss_size;
10947}
10948
10949
10950
10951
10952
10953i40e_status i40e_get_partition_bw_setting(struct i40e_pf *pf)
10954{
10955 i40e_status status;
10956 bool min_valid, max_valid;
10957 u32 max_bw, min_bw;
10958
10959 status = i40e_read_bw_from_alt_ram(&pf->hw, &max_bw, &min_bw,
10960 &min_valid, &max_valid);
10961
10962 if (!status) {
10963 if (min_valid)
10964 pf->min_bw = min_bw;
10965 if (max_valid)
10966 pf->max_bw = max_bw;
10967 }
10968
10969 return status;
10970}
10971
10972
10973
10974
10975
10976i40e_status i40e_set_partition_bw_setting(struct i40e_pf *pf)
10977{
10978 struct i40e_aqc_configure_partition_bw_data bw_data;
10979 i40e_status status;
10980
10981
10982 bw_data.pf_valid_bits = cpu_to_le16(BIT(pf->hw.pf_id));
10983 bw_data.max_bw[pf->hw.pf_id] = pf->max_bw & I40E_ALT_BW_VALUE_MASK;
10984 bw_data.min_bw[pf->hw.pf_id] = pf->min_bw & I40E_ALT_BW_VALUE_MASK;
10985
10986
10987 status = i40e_aq_configure_partition_bw(&pf->hw, &bw_data, NULL);
10988
10989 return status;
10990}
10991
10992
10993
10994
10995
10996i40e_status i40e_commit_partition_bw_setting(struct i40e_pf *pf)
10997{
10998
10999 enum i40e_admin_queue_err last_aq_status;
11000 i40e_status ret;
11001 u16 nvm_word;
11002
11003 if (pf->hw.partition_id != 1) {
11004 dev_info(&pf->pdev->dev,
11005 "Commit BW only works on partition 1! This is partition %d",
11006 pf->hw.partition_id);
11007 ret = I40E_NOT_SUPPORTED;
11008 goto bw_commit_out;
11009 }
11010
11011
11012 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_READ);
11013 last_aq_status = pf->hw.aq.asq_last_status;
11014 if (ret) {
11015 dev_info(&pf->pdev->dev,
11016 "Cannot acquire NVM for read access, err %s aq_err %s\n",
11017 i40e_stat_str(&pf->hw, ret),
11018 i40e_aq_str(&pf->hw, last_aq_status));
11019 goto bw_commit_out;
11020 }
11021
11022
11023 ret = i40e_aq_read_nvm(&pf->hw,
11024 I40E_SR_NVM_CONTROL_WORD,
11025 0x10, sizeof(nvm_word), &nvm_word,
11026 false, NULL);
11027
11028
11029
11030 last_aq_status = pf->hw.aq.asq_last_status;
11031 i40e_release_nvm(&pf->hw);
11032 if (ret) {
11033 dev_info(&pf->pdev->dev, "NVM read error, err %s aq_err %s\n",
11034 i40e_stat_str(&pf->hw, ret),
11035 i40e_aq_str(&pf->hw, last_aq_status));
11036 goto bw_commit_out;
11037 }
11038
11039
11040 msleep(50);
11041
11042
11043 ret = i40e_acquire_nvm(&pf->hw, I40E_RESOURCE_WRITE);
11044 last_aq_status = pf->hw.aq.asq_last_status;
11045 if (ret) {
11046 dev_info(&pf->pdev->dev,
11047 "Cannot acquire NVM for write access, err %s aq_err %s\n",
11048 i40e_stat_str(&pf->hw, ret),
11049 i40e_aq_str(&pf->hw, last_aq_status));
11050 goto bw_commit_out;
11051 }
11052
11053
11054
11055
11056 ret = i40e_aq_update_nvm(&pf->hw,
11057 I40E_SR_NVM_CONTROL_WORD,
11058 0x10, sizeof(nvm_word),
11059 &nvm_word, true, 0, NULL);
11060
11061
11062
11063 last_aq_status = pf->hw.aq.asq_last_status;
11064 i40e_release_nvm(&pf->hw);
11065 if (ret)
11066 dev_info(&pf->pdev->dev,
11067 "BW settings NOT SAVED, err %s aq_err %s\n",
11068 i40e_stat_str(&pf->hw, ret),
11069 i40e_aq_str(&pf->hw, last_aq_status));
11070bw_commit_out:
11071
11072 return ret;
11073}
11074
11075
11076
11077
11078
11079
11080
11081
11082
11083static int i40e_sw_init(struct i40e_pf *pf)
11084{
11085 int err = 0;
11086 int size;
11087
11088
11089 pf->flags = I40E_FLAG_RX_CSUM_ENABLED |
11090 I40E_FLAG_MSI_ENABLED |
11091 I40E_FLAG_MSIX_ENABLED;
11092
11093
11094 pf->rx_itr_default = I40E_ITR_RX_DEF;
11095 pf->tx_itr_default = I40E_ITR_TX_DEF;
11096
11097
11098
11099
11100 pf->rss_size_max = BIT(pf->hw.func_caps.rss_table_entry_width);
11101 pf->alloc_rss_size = 1;
11102 pf->rss_table_size = pf->hw.func_caps.rss_table_size;
11103 pf->rss_size_max = min_t(int, pf->rss_size_max,
11104 pf->hw.func_caps.num_tx_qp);
11105 if (pf->hw.func_caps.rss) {
11106 pf->flags |= I40E_FLAG_RSS_ENABLED;
11107 pf->alloc_rss_size = min_t(int, pf->rss_size_max,
11108 num_online_cpus());
11109 }
11110
11111
11112 if (pf->hw.func_caps.npar_enable || pf->hw.func_caps.flex10_enable) {
11113 pf->flags |= I40E_FLAG_MFP_ENABLED;
11114 dev_info(&pf->pdev->dev, "MFP mode Enabled\n");
11115 if (i40e_get_partition_bw_setting(pf)) {
11116 dev_warn(&pf->pdev->dev,
11117 "Could not get partition bw settings\n");
11118 } else {
11119 dev_info(&pf->pdev->dev,
11120 "Partition BW Min = %8.8x, Max = %8.8x\n",
11121 pf->min_bw, pf->max_bw);
11122
11123
11124 i40e_set_partition_bw_setting(pf);
11125 }
11126 }
11127
11128 if ((pf->hw.func_caps.fd_filters_guaranteed > 0) ||
11129 (pf->hw.func_caps.fd_filters_best_effort > 0)) {
11130 pf->flags |= I40E_FLAG_FD_ATR_ENABLED;
11131 pf->atr_sample_rate = I40E_DEFAULT_ATR_SAMPLE_RATE;
11132 if (pf->flags & I40E_FLAG_MFP_ENABLED &&
11133 pf->hw.num_partitions > 1)
11134 dev_info(&pf->pdev->dev,
11135 "Flow Director Sideband mode Disabled in MFP mode\n");
11136 else
11137 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
11138 pf->fdir_pf_filter_count =
11139 pf->hw.func_caps.fd_filters_guaranteed;
11140 pf->hw.fdir_shared_filter_count =
11141 pf->hw.func_caps.fd_filters_best_effort;
11142 }
11143
11144 if (pf->hw.mac.type == I40E_MAC_X722) {
11145 pf->hw_features |= (I40E_HW_RSS_AQ_CAPABLE |
11146 I40E_HW_128_QP_RSS_CAPABLE |
11147 I40E_HW_ATR_EVICT_CAPABLE |
11148 I40E_HW_WB_ON_ITR_CAPABLE |
11149 I40E_HW_MULTIPLE_TCP_UDP_RSS_PCTYPE |
11150 I40E_HW_NO_PCI_LINK_CHECK |
11151 I40E_HW_USE_SET_LLDP_MIB |
11152 I40E_HW_GENEVE_OFFLOAD_CAPABLE |
11153 I40E_HW_PTP_L4_CAPABLE |
11154 I40E_HW_WOL_MC_MAGIC_PKT_WAKE |
11155 I40E_HW_OUTER_UDP_CSUM_CAPABLE);
11156
11157#define I40E_FDEVICT_PCTYPE_DEFAULT 0xc03
11158 if (rd32(&pf->hw, I40E_GLQF_FDEVICTENA(1)) !=
11159 I40E_FDEVICT_PCTYPE_DEFAULT) {
11160 dev_warn(&pf->pdev->dev,
11161 "FD EVICT PCTYPES are not right, disable FD HW EVICT\n");
11162 pf->hw_features &= ~I40E_HW_ATR_EVICT_CAPABLE;
11163 }
11164 } else if ((pf->hw.aq.api_maj_ver > 1) ||
11165 ((pf->hw.aq.api_maj_ver == 1) &&
11166 (pf->hw.aq.api_min_ver > 4))) {
11167
11168 pf->hw_features |= I40E_HW_GENEVE_OFFLOAD_CAPABLE;
11169 }
11170
11171
11172 if (pf->hw_features & I40E_HW_ATR_EVICT_CAPABLE)
11173 pf->flags |= I40E_FLAG_HW_ATR_EVICT_ENABLED;
11174
11175 if ((pf->hw.mac.type == I40E_MAC_XL710) &&
11176 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 33)) ||
11177 (pf->hw.aq.fw_maj_ver < 4))) {
11178 pf->hw_features |= I40E_HW_RESTART_AUTONEG;
11179
11180 pf->hw_features |= I40E_HW_NO_DCB_SUPPORT;
11181 }
11182
11183
11184 if ((pf->hw.mac.type == I40E_MAC_XL710) &&
11185 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver < 3)) ||
11186 (pf->hw.aq.fw_maj_ver < 4)))
11187 pf->hw_features |= I40E_HW_STOP_FW_LLDP;
11188
11189
11190 if ((pf->hw.mac.type == I40E_MAC_XL710) &&
11191 (((pf->hw.aq.fw_maj_ver == 4) && (pf->hw.aq.fw_min_ver >= 40)) ||
11192 (pf->hw.aq.fw_maj_ver >= 5)))
11193 pf->hw_features |= I40E_HW_USE_SET_LLDP_MIB;
11194
11195
11196 if (pf->hw.mac.type == I40E_MAC_XL710 &&
11197 pf->hw.aq.fw_maj_ver >= 6)
11198 pf->hw_features |= I40E_HW_PTP_L4_CAPABLE;
11199
11200 if (pf->hw.func_caps.vmdq && num_online_cpus() != 1) {
11201 pf->num_vmdq_vsis = I40E_DEFAULT_NUM_VMDQ_VSI;
11202 pf->flags |= I40E_FLAG_VMDQ_ENABLED;
11203 pf->num_vmdq_qps = i40e_default_queues_per_vmdq(pf);
11204 }
11205
11206 if (pf->hw.func_caps.iwarp && num_online_cpus() != 1) {
11207 pf->flags |= I40E_FLAG_IWARP_ENABLED;
11208
11209 pf->num_iwarp_msix = (int)num_online_cpus() + 1;
11210 }
11211
11212
11213
11214
11215
11216 if (pf->hw.mac.type == I40E_MAC_XL710 &&
11217 !pf->hw.func_caps.npar_enable &&
11218 (pf->hw.aq.api_maj_ver > 1 ||
11219 (pf->hw.aq.api_maj_ver == 1 && pf->hw.aq.api_min_ver > 6)))
11220 pf->hw_features |= I40E_HW_STOPPABLE_FW_LLDP;
11221
11222#ifdef CONFIG_PCI_IOV
11223 if (pf->hw.func_caps.num_vfs && pf->hw.partition_id == 1) {
11224 pf->num_vf_qps = I40E_DEFAULT_QUEUES_PER_VF;
11225 pf->flags |= I40E_FLAG_SRIOV_ENABLED;
11226 pf->num_req_vfs = min_t(int,
11227 pf->hw.func_caps.num_vfs,
11228 I40E_MAX_VF_COUNT);
11229 }
11230#endif
11231 pf->eeprom_version = 0xDEAD;
11232 pf->lan_veb = I40E_NO_VEB;
11233 pf->lan_vsi = I40E_NO_VSI;
11234
11235
11236 pf->flags &= ~I40E_FLAG_VEB_STATS_ENABLED;
11237
11238
11239 size = sizeof(struct i40e_lump_tracking)
11240 + (sizeof(u16) * pf->hw.func_caps.num_tx_qp);
11241 pf->qp_pile = kzalloc(size, GFP_KERNEL);
11242 if (!pf->qp_pile) {
11243 err = -ENOMEM;
11244 goto sw_init_done;
11245 }
11246 pf->qp_pile->num_entries = pf->hw.func_caps.num_tx_qp;
11247 pf->qp_pile->search_hint = 0;
11248
11249 pf->tx_timeout_recovery_level = 1;
11250
11251 mutex_init(&pf->switch_mutex);
11252
11253sw_init_done:
11254 return err;
11255}
11256
11257
11258
11259
11260
11261
11262
11263
11264bool i40e_set_ntuple(struct i40e_pf *pf, netdev_features_t features)
11265{
11266 bool need_reset = false;
11267
11268
11269
11270
11271 if (features & NETIF_F_NTUPLE) {
11272
11273 if (!(pf->flags & I40E_FLAG_FD_SB_ENABLED))
11274 need_reset = true;
11275
11276
11277
11278 if (pf->num_fdsb_msix > 0 && !pf->num_cloud_filters) {
11279 pf->flags |= I40E_FLAG_FD_SB_ENABLED;
11280 pf->flags &= ~I40E_FLAG_FD_SB_INACTIVE;
11281 }
11282 } else {
11283
11284 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
11285 need_reset = true;
11286 i40e_fdir_filter_exit(pf);
11287 }
11288 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
11289 clear_bit(__I40E_FD_SB_AUTO_DISABLED, pf->state);
11290 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
11291
11292
11293 pf->fd_add_err = 0;
11294 pf->fd_atr_cnt = 0;
11295
11296 if (test_and_clear_bit(__I40E_FD_ATR_AUTO_DISABLED, pf->state))
11297 if ((pf->flags & I40E_FLAG_FD_ATR_ENABLED) &&
11298 (I40E_DEBUG_FD & pf->hw.debug_mask))
11299 dev_info(&pf->pdev->dev, "ATR re-enabled.\n");
11300 }
11301 return need_reset;
11302}
11303
11304
11305
11306
11307
11308static void i40e_clear_rss_lut(struct i40e_vsi *vsi)
11309{
11310 struct i40e_pf *pf = vsi->back;
11311 struct i40e_hw *hw = &pf->hw;
11312 u16 vf_id = vsi->vf_id;
11313 u8 i;
11314
11315 if (vsi->type == I40E_VSI_MAIN) {
11316 for (i = 0; i <= I40E_PFQF_HLUT_MAX_INDEX; i++)
11317 wr32(hw, I40E_PFQF_HLUT(i), 0);
11318 } else if (vsi->type == I40E_VSI_SRIOV) {
11319 for (i = 0; i <= I40E_VFQF_HLUT_MAX_INDEX; i++)
11320 i40e_write_rx_ctl(hw, I40E_VFQF_HLUT1(i, vf_id), 0);
11321 } else {
11322 dev_err(&pf->pdev->dev, "Cannot set RSS LUT - invalid VSI type\n");
11323 }
11324}
11325
11326
11327
11328
11329
11330
11331
11332static int i40e_set_features(struct net_device *netdev,
11333 netdev_features_t features)
11334{
11335 struct i40e_netdev_priv *np = netdev_priv(netdev);
11336 struct i40e_vsi *vsi = np->vsi;
11337 struct i40e_pf *pf = vsi->back;
11338 bool need_reset;
11339
11340 if (features & NETIF_F_RXHASH && !(netdev->features & NETIF_F_RXHASH))
11341 i40e_pf_config_rss(pf);
11342 else if (!(features & NETIF_F_RXHASH) &&
11343 netdev->features & NETIF_F_RXHASH)
11344 i40e_clear_rss_lut(vsi);
11345
11346 if (features & NETIF_F_HW_VLAN_CTAG_RX)
11347 i40e_vlan_stripping_enable(vsi);
11348 else
11349 i40e_vlan_stripping_disable(vsi);
11350
11351 if (!(features & NETIF_F_HW_TC) && pf->num_cloud_filters) {
11352 dev_err(&pf->pdev->dev,
11353 "Offloaded tc filters active, can't turn hw_tc_offload off");
11354 return -EINVAL;
11355 }
11356
11357 need_reset = i40e_set_ntuple(pf, features);
11358
11359 if (need_reset)
11360 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
11361
11362 return 0;
11363}
11364
11365
11366
11367
11368
11369
11370
11371
11372static u8 i40e_get_udp_port_idx(struct i40e_pf *pf, u16 port)
11373{
11374 u8 i;
11375
11376 for (i = 0; i < I40E_MAX_PF_UDP_OFFLOAD_PORTS; i++) {
11377 if (pf->udp_ports[i].port == port)
11378 return i;
11379 }
11380
11381 return i;
11382}
11383
11384
11385
11386
11387
11388
11389static void i40e_udp_tunnel_add(struct net_device *netdev,
11390 struct udp_tunnel_info *ti)
11391{
11392 struct i40e_netdev_priv *np = netdev_priv(netdev);
11393 struct i40e_vsi *vsi = np->vsi;
11394 struct i40e_pf *pf = vsi->back;
11395 u16 port = ntohs(ti->port);
11396 u8 next_idx;
11397 u8 idx;
11398
11399 idx = i40e_get_udp_port_idx(pf, port);
11400
11401
11402 if (idx < I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
11403 netdev_info(netdev, "port %d already offloaded\n", port);
11404 return;
11405 }
11406
11407
11408 next_idx = i40e_get_udp_port_idx(pf, 0);
11409
11410 if (next_idx == I40E_MAX_PF_UDP_OFFLOAD_PORTS) {
11411 netdev_info(netdev, "maximum number of offloaded UDP ports reached, not adding port %d\n",
11412 port);
11413 return;
11414 }
11415
11416 switch (ti->type) {
11417 case UDP_TUNNEL_TYPE_VXLAN:
11418 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_VXLAN;
11419 break;
11420 case UDP_TUNNEL_TYPE_GENEVE:
11421 if (!(pf->hw_features & I40E_HW_GENEVE_OFFLOAD_CAPABLE))
11422 return;
11423 pf->udp_ports[next_idx].type = I40E_AQC_TUNNEL_TYPE_NGE;
11424 break;
11425 default:
11426 return;
11427 }
11428
11429
11430 pf->udp_ports[next_idx].port = port;
11431 pf->pending_udp_bitmap |= BIT_ULL(next_idx);
11432 set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state);
11433}
11434
11435
11436
11437
11438
11439
11440static void i40e_udp_tunnel_del(struct net_device *netdev,
11441 struct udp_tunnel_info *ti)
11442{
11443 struct i40e_netdev_priv *np = netdev_priv(netdev);
11444 struct i40e_vsi *vsi = np->vsi;
11445 struct i40e_pf *pf = vsi->back;
11446 u16 port = ntohs(ti->port);
11447 u8 idx;
11448
11449 idx = i40e_get_udp_port_idx(pf, port);
11450
11451
11452 if (idx >= I40E_MAX_PF_UDP_OFFLOAD_PORTS)
11453 goto not_found;
11454
11455 switch (ti->type) {
11456 case UDP_TUNNEL_TYPE_VXLAN:
11457 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_VXLAN)
11458 goto not_found;
11459 break;
11460 case UDP_TUNNEL_TYPE_GENEVE:
11461 if (pf->udp_ports[idx].type != I40E_AQC_TUNNEL_TYPE_NGE)
11462 goto not_found;
11463 break;
11464 default:
11465 goto not_found;
11466 }
11467
11468
11469
11470
11471 pf->udp_ports[idx].port = 0;
11472 pf->pending_udp_bitmap |= BIT_ULL(idx);
11473 set_bit(__I40E_UDP_FILTER_SYNC_PENDING, pf->state);
11474
11475 return;
11476not_found:
11477 netdev_warn(netdev, "UDP port %d was not found, not deleting\n",
11478 port);
11479}
11480
11481static int i40e_get_phys_port_id(struct net_device *netdev,
11482 struct netdev_phys_item_id *ppid)
11483{
11484 struct i40e_netdev_priv *np = netdev_priv(netdev);
11485 struct i40e_pf *pf = np->vsi->back;
11486 struct i40e_hw *hw = &pf->hw;
11487
11488 if (!(pf->hw_features & I40E_HW_PORT_ID_VALID))
11489 return -EOPNOTSUPP;
11490
11491 ppid->id_len = min_t(int, sizeof(hw->mac.port_addr), sizeof(ppid->id));
11492 memcpy(ppid->id, hw->mac.port_addr, ppid->id_len);
11493
11494 return 0;
11495}
11496
11497
11498
11499
11500
11501
11502
11503
11504
11505static int i40e_ndo_fdb_add(struct ndmsg *ndm, struct nlattr *tb[],
11506 struct net_device *dev,
11507 const unsigned char *addr, u16 vid,
11508 u16 flags)
11509{
11510 struct i40e_netdev_priv *np = netdev_priv(dev);
11511 struct i40e_pf *pf = np->vsi->back;
11512 int err = 0;
11513
11514 if (!(pf->flags & I40E_FLAG_SRIOV_ENABLED))
11515 return -EOPNOTSUPP;
11516
11517 if (vid) {
11518 pr_info("%s: vlans aren't supported yet for dev_uc|mc_add()\n", dev->name);
11519 return -EINVAL;
11520 }
11521
11522
11523
11524
11525 if (ndm->ndm_state && !(ndm->ndm_state & NUD_PERMANENT)) {
11526 netdev_info(dev, "FDB only supports static addresses\n");
11527 return -EINVAL;
11528 }
11529
11530 if (is_unicast_ether_addr(addr) || is_link_local_ether_addr(addr))
11531 err = dev_uc_add_excl(dev, addr);
11532 else if (is_multicast_ether_addr(addr))
11533 err = dev_mc_add_excl(dev, addr);
11534 else
11535 err = -EINVAL;
11536
11537
11538 if (err == -EEXIST && !(flags & NLM_F_EXCL))
11539 err = 0;
11540
11541 return err;
11542}
11543
11544
11545
11546
11547
11548
11549
11550
11551
11552
11553
11554
11555
11556
11557
11558static int i40e_ndo_bridge_setlink(struct net_device *dev,
11559 struct nlmsghdr *nlh,
11560 u16 flags)
11561{
11562 struct i40e_netdev_priv *np = netdev_priv(dev);
11563 struct i40e_vsi *vsi = np->vsi;
11564 struct i40e_pf *pf = vsi->back;
11565 struct i40e_veb *veb = NULL;
11566 struct nlattr *attr, *br_spec;
11567 int i, rem;
11568
11569
11570 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
11571 return -EOPNOTSUPP;
11572
11573
11574 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
11575 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
11576 veb = pf->veb[i];
11577 }
11578
11579 br_spec = nlmsg_find_attr(nlh, sizeof(struct ifinfomsg), IFLA_AF_SPEC);
11580
11581 nla_for_each_nested(attr, br_spec, rem) {
11582 __u16 mode;
11583
11584 if (nla_type(attr) != IFLA_BRIDGE_MODE)
11585 continue;
11586
11587 mode = nla_get_u16(attr);
11588 if ((mode != BRIDGE_MODE_VEPA) &&
11589 (mode != BRIDGE_MODE_VEB))
11590 return -EINVAL;
11591
11592
11593 if (!veb) {
11594 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
11595 vsi->tc_config.enabled_tc);
11596 if (veb) {
11597 veb->bridge_mode = mode;
11598 i40e_config_bridge_mode(veb);
11599 } else {
11600
11601 return -ENOENT;
11602 }
11603 break;
11604 } else if (mode != veb->bridge_mode) {
11605
11606 veb->bridge_mode = mode;
11607
11608 if (mode == BRIDGE_MODE_VEB)
11609 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
11610 else
11611 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
11612 i40e_do_reset(pf, I40E_PF_RESET_FLAG, true);
11613 break;
11614 }
11615 }
11616
11617 return 0;
11618}
11619
11620
11621
11622
11623
11624
11625
11626
11627
11628
11629
11630
11631
11632static int i40e_ndo_bridge_getlink(struct sk_buff *skb, u32 pid, u32 seq,
11633 struct net_device *dev,
11634 u32 __always_unused filter_mask,
11635 int nlflags)
11636{
11637 struct i40e_netdev_priv *np = netdev_priv(dev);
11638 struct i40e_vsi *vsi = np->vsi;
11639 struct i40e_pf *pf = vsi->back;
11640 struct i40e_veb *veb = NULL;
11641 int i;
11642
11643
11644 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid)
11645 return -EOPNOTSUPP;
11646
11647
11648 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
11649 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
11650 veb = pf->veb[i];
11651 }
11652
11653 if (!veb)
11654 return 0;
11655
11656 return ndo_dflt_bridge_getlink(skb, pid, seq, dev, veb->bridge_mode,
11657 0, 0, nlflags, filter_mask, NULL);
11658}
11659
11660
11661
11662
11663
11664
11665
11666static netdev_features_t i40e_features_check(struct sk_buff *skb,
11667 struct net_device *dev,
11668 netdev_features_t features)
11669{
11670 size_t len;
11671
11672
11673
11674
11675
11676 if (skb->ip_summed != CHECKSUM_PARTIAL)
11677 return features;
11678
11679
11680
11681
11682 if (skb_is_gso(skb) && (skb_shinfo(skb)->gso_size < 64))
11683 features &= ~NETIF_F_GSO_MASK;
11684
11685
11686 len = skb_network_header(skb) - skb->data;
11687 if (len & ~(63 * 2))
11688 goto out_err;
11689
11690
11691 len = skb_transport_header(skb) - skb_network_header(skb);
11692 if (len & ~(127 * 4))
11693 goto out_err;
11694
11695 if (skb->encapsulation) {
11696
11697 len = skb_inner_network_header(skb) - skb_transport_header(skb);
11698 if (len & ~(127 * 2))
11699 goto out_err;
11700
11701
11702 len = skb_inner_transport_header(skb) -
11703 skb_inner_network_header(skb);
11704 if (len & ~(127 * 4))
11705 goto out_err;
11706 }
11707
11708
11709
11710
11711
11712
11713 return features;
11714out_err:
11715 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
11716}
11717
11718
11719
11720
11721
11722
11723static int i40e_xdp_setup(struct i40e_vsi *vsi,
11724 struct bpf_prog *prog)
11725{
11726 int frame_size = vsi->netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN;
11727 struct i40e_pf *pf = vsi->back;
11728 struct bpf_prog *old_prog;
11729 bool need_reset;
11730 int i;
11731
11732
11733 if (frame_size > vsi->rx_buf_len)
11734 return -EINVAL;
11735
11736 if (!i40e_enabled_xdp_vsi(vsi) && !prog)
11737 return 0;
11738
11739
11740 need_reset = (i40e_enabled_xdp_vsi(vsi) != !!prog);
11741
11742 if (need_reset)
11743 i40e_prep_for_reset(pf, true);
11744
11745 old_prog = xchg(&vsi->xdp_prog, prog);
11746
11747 if (need_reset)
11748 i40e_reset_and_rebuild(pf, true, true);
11749
11750 for (i = 0; i < vsi->num_queue_pairs; i++)
11751 WRITE_ONCE(vsi->rx_rings[i]->xdp_prog, vsi->xdp_prog);
11752
11753 if (old_prog)
11754 bpf_prog_put(old_prog);
11755
11756 return 0;
11757}
11758
11759
11760
11761
11762
11763
11764static int i40e_xdp(struct net_device *dev,
11765 struct netdev_bpf *xdp)
11766{
11767 struct i40e_netdev_priv *np = netdev_priv(dev);
11768 struct i40e_vsi *vsi = np->vsi;
11769
11770 if (vsi->type != I40E_VSI_MAIN)
11771 return -EINVAL;
11772
11773 switch (xdp->command) {
11774 case XDP_SETUP_PROG:
11775 return i40e_xdp_setup(vsi, xdp->prog);
11776 case XDP_QUERY_PROG:
11777 xdp->prog_attached = i40e_enabled_xdp_vsi(vsi);
11778 xdp->prog_id = vsi->xdp_prog ? vsi->xdp_prog->aux->id : 0;
11779 return 0;
11780 default:
11781 return -EINVAL;
11782 }
11783}
11784
11785static const struct net_device_ops i40e_netdev_ops = {
11786 .ndo_open = i40e_open,
11787 .ndo_stop = i40e_close,
11788 .ndo_start_xmit = i40e_lan_xmit_frame,
11789 .ndo_get_stats64 = i40e_get_netdev_stats_struct,
11790 .ndo_set_rx_mode = i40e_set_rx_mode,
11791 .ndo_validate_addr = eth_validate_addr,
11792 .ndo_set_mac_address = i40e_set_mac,
11793 .ndo_change_mtu = i40e_change_mtu,
11794 .ndo_do_ioctl = i40e_ioctl,
11795 .ndo_tx_timeout = i40e_tx_timeout,
11796 .ndo_vlan_rx_add_vid = i40e_vlan_rx_add_vid,
11797 .ndo_vlan_rx_kill_vid = i40e_vlan_rx_kill_vid,
11798#ifdef CONFIG_NET_POLL_CONTROLLER
11799 .ndo_poll_controller = i40e_netpoll,
11800#endif
11801 .ndo_setup_tc = __i40e_setup_tc,
11802 .ndo_set_features = i40e_set_features,
11803 .ndo_set_vf_mac = i40e_ndo_set_vf_mac,
11804 .ndo_set_vf_vlan = i40e_ndo_set_vf_port_vlan,
11805 .ndo_set_vf_rate = i40e_ndo_set_vf_bw,
11806 .ndo_get_vf_config = i40e_ndo_get_vf_config,
11807 .ndo_set_vf_link_state = i40e_ndo_set_vf_link_state,
11808 .ndo_set_vf_spoofchk = i40e_ndo_set_vf_spoofchk,
11809 .ndo_set_vf_trust = i40e_ndo_set_vf_trust,
11810 .ndo_udp_tunnel_add = i40e_udp_tunnel_add,
11811 .ndo_udp_tunnel_del = i40e_udp_tunnel_del,
11812 .ndo_get_phys_port_id = i40e_get_phys_port_id,
11813 .ndo_fdb_add = i40e_ndo_fdb_add,
11814 .ndo_features_check = i40e_features_check,
11815 .ndo_bridge_getlink = i40e_ndo_bridge_getlink,
11816 .ndo_bridge_setlink = i40e_ndo_bridge_setlink,
11817 .ndo_bpf = i40e_xdp,
11818 .ndo_xdp_xmit = i40e_xdp_xmit,
11819 .ndo_xdp_flush = i40e_xdp_flush,
11820};
11821
11822
11823
11824
11825
11826
11827
11828static int i40e_config_netdev(struct i40e_vsi *vsi)
11829{
11830 struct i40e_pf *pf = vsi->back;
11831 struct i40e_hw *hw = &pf->hw;
11832 struct i40e_netdev_priv *np;
11833 struct net_device *netdev;
11834 u8 broadcast[ETH_ALEN];
11835 u8 mac_addr[ETH_ALEN];
11836 int etherdev_size;
11837 netdev_features_t hw_enc_features;
11838 netdev_features_t hw_features;
11839
11840 etherdev_size = sizeof(struct i40e_netdev_priv);
11841 netdev = alloc_etherdev_mq(etherdev_size, vsi->alloc_queue_pairs);
11842 if (!netdev)
11843 return -ENOMEM;
11844
11845 vsi->netdev = netdev;
11846 np = netdev_priv(netdev);
11847 np->vsi = vsi;
11848
11849 hw_enc_features = NETIF_F_SG |
11850 NETIF_F_IP_CSUM |
11851 NETIF_F_IPV6_CSUM |
11852 NETIF_F_HIGHDMA |
11853 NETIF_F_SOFT_FEATURES |
11854 NETIF_F_TSO |
11855 NETIF_F_TSO_ECN |
11856 NETIF_F_TSO6 |
11857 NETIF_F_GSO_GRE |
11858 NETIF_F_GSO_GRE_CSUM |
11859 NETIF_F_GSO_PARTIAL |
11860 NETIF_F_GSO_UDP_TUNNEL |
11861 NETIF_F_GSO_UDP_TUNNEL_CSUM |
11862 NETIF_F_SCTP_CRC |
11863 NETIF_F_RXHASH |
11864 NETIF_F_RXCSUM |
11865 0;
11866
11867 if (!(pf->hw_features & I40E_HW_OUTER_UDP_CSUM_CAPABLE))
11868 netdev->gso_partial_features |= NETIF_F_GSO_UDP_TUNNEL_CSUM;
11869
11870 netdev->gso_partial_features |= NETIF_F_GSO_GRE_CSUM;
11871
11872 netdev->hw_enc_features |= hw_enc_features;
11873
11874
11875 netdev->vlan_features |= hw_enc_features | NETIF_F_TSO_MANGLEID;
11876
11877 if (!(pf->flags & I40E_FLAG_MFP_ENABLED))
11878 netdev->hw_features |= NETIF_F_NTUPLE | NETIF_F_HW_TC;
11879
11880 hw_features = hw_enc_features |
11881 NETIF_F_HW_VLAN_CTAG_TX |
11882 NETIF_F_HW_VLAN_CTAG_RX;
11883
11884 netdev->hw_features |= hw_features;
11885
11886 netdev->features |= hw_features | NETIF_F_HW_VLAN_CTAG_FILTER;
11887 netdev->hw_enc_features |= NETIF_F_TSO_MANGLEID;
11888
11889 if (vsi->type == I40E_VSI_MAIN) {
11890 SET_NETDEV_DEV(netdev, &pf->pdev->dev);
11891 ether_addr_copy(mac_addr, hw->mac.perm_addr);
11892
11893
11894
11895
11896
11897
11898
11899
11900
11901
11902 i40e_rm_default_mac_filter(vsi, mac_addr);
11903 spin_lock_bh(&vsi->mac_filter_hash_lock);
11904 i40e_add_mac_filter(vsi, mac_addr);
11905 spin_unlock_bh(&vsi->mac_filter_hash_lock);
11906 } else {
11907
11908
11909
11910
11911
11912 snprintf(netdev->name, IFNAMSIZ, "%.*sv%%d",
11913 IFNAMSIZ - 4,
11914 pf->vsi[pf->lan_vsi]->netdev->name);
11915 random_ether_addr(mac_addr);
11916
11917 spin_lock_bh(&vsi->mac_filter_hash_lock);
11918 i40e_add_mac_filter(vsi, mac_addr);
11919 spin_unlock_bh(&vsi->mac_filter_hash_lock);
11920 }
11921
11922
11923
11924
11925
11926
11927
11928
11929
11930
11931
11932
11933
11934
11935 eth_broadcast_addr(broadcast);
11936 spin_lock_bh(&vsi->mac_filter_hash_lock);
11937 i40e_add_mac_filter(vsi, broadcast);
11938 spin_unlock_bh(&vsi->mac_filter_hash_lock);
11939
11940 ether_addr_copy(netdev->dev_addr, mac_addr);
11941 ether_addr_copy(netdev->perm_addr, mac_addr);
11942
11943 netdev->priv_flags |= IFF_UNICAST_FLT;
11944 netdev->priv_flags |= IFF_SUPP_NOFCS;
11945
11946 i40e_vsi_config_netdev_tc(vsi, vsi->tc_config.enabled_tc);
11947
11948 netdev->netdev_ops = &i40e_netdev_ops;
11949 netdev->watchdog_timeo = 5 * HZ;
11950 i40e_set_ethtool_ops(netdev);
11951
11952
11953 netdev->min_mtu = ETH_MIN_MTU;
11954 netdev->max_mtu = I40E_MAX_RXBUFFER - I40E_PACKET_HDR_PAD;
11955
11956 return 0;
11957}
11958
11959
11960
11961
11962
11963
11964
11965static void i40e_vsi_delete(struct i40e_vsi *vsi)
11966{
11967
11968 if (vsi == vsi->back->vsi[vsi->back->lan_vsi])
11969 return;
11970
11971 i40e_aq_delete_element(&vsi->back->hw, vsi->seid, NULL);
11972}
11973
11974
11975
11976
11977
11978
11979
11980int i40e_is_vsi_uplink_mode_veb(struct i40e_vsi *vsi)
11981{
11982 struct i40e_veb *veb;
11983 struct i40e_pf *pf = vsi->back;
11984
11985
11986 if (vsi->veb_idx == I40E_NO_VEB)
11987 return 1;
11988
11989 veb = pf->veb[vsi->veb_idx];
11990 if (!veb) {
11991 dev_info(&pf->pdev->dev,
11992 "There is no veb associated with the bridge\n");
11993 return -ENOENT;
11994 }
11995
11996
11997 if (veb->bridge_mode & BRIDGE_MODE_VEPA) {
11998 return 0;
11999 } else {
12000
12001 return 1;
12002 }
12003
12004
12005 return 0;
12006}
12007
12008
12009
12010
12011
12012
12013
12014
12015static int i40e_add_vsi(struct i40e_vsi *vsi)
12016{
12017 int ret = -ENODEV;
12018 struct i40e_pf *pf = vsi->back;
12019 struct i40e_hw *hw = &pf->hw;
12020 struct i40e_vsi_context ctxt;
12021 struct i40e_mac_filter *f;
12022 struct hlist_node *h;
12023 int bkt;
12024
12025 u8 enabled_tc = 0x1;
12026 int f_count = 0;
12027
12028 memset(&ctxt, 0, sizeof(ctxt));
12029 switch (vsi->type) {
12030 case I40E_VSI_MAIN:
12031
12032
12033
12034
12035
12036 ctxt.seid = pf->main_vsi_seid;
12037 ctxt.pf_num = pf->hw.pf_id;
12038 ctxt.vf_num = 0;
12039 ret = i40e_aq_get_vsi_params(&pf->hw, &ctxt, NULL);
12040 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
12041 if (ret) {
12042 dev_info(&pf->pdev->dev,
12043 "couldn't get PF vsi config, err %s aq_err %s\n",
12044 i40e_stat_str(&pf->hw, ret),
12045 i40e_aq_str(&pf->hw,
12046 pf->hw.aq.asq_last_status));
12047 return -ENOENT;
12048 }
12049 vsi->info = ctxt.info;
12050 vsi->info.valid_sections = 0;
12051
12052 vsi->seid = ctxt.seid;
12053 vsi->id = ctxt.vsi_number;
12054
12055 enabled_tc = i40e_pf_get_tc_map(pf);
12056
12057
12058
12059
12060
12061 if (pf->flags & I40E_FLAG_SOURCE_PRUNING_DISABLED) {
12062 memset(&ctxt, 0, sizeof(ctxt));
12063 ctxt.seid = pf->main_vsi_seid;
12064 ctxt.pf_num = pf->hw.pf_id;
12065 ctxt.vf_num = 0;
12066 ctxt.info.valid_sections |=
12067 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
12068 ctxt.info.switch_id =
12069 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB);
12070 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
12071 if (ret) {
12072 dev_info(&pf->pdev->dev,
12073 "update vsi failed, err %s aq_err %s\n",
12074 i40e_stat_str(&pf->hw, ret),
12075 i40e_aq_str(&pf->hw,
12076 pf->hw.aq.asq_last_status));
12077 ret = -ENOENT;
12078 goto err;
12079 }
12080 }
12081
12082
12083 if ((pf->flags & I40E_FLAG_MFP_ENABLED) &&
12084 !(pf->hw.func_caps.iscsi)) {
12085 memset(&ctxt, 0, sizeof(ctxt));
12086 ctxt.seid = pf->main_vsi_seid;
12087 ctxt.pf_num = pf->hw.pf_id;
12088 ctxt.vf_num = 0;
12089 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, false);
12090 ret = i40e_aq_update_vsi_params(hw, &ctxt, NULL);
12091 if (ret) {
12092 dev_info(&pf->pdev->dev,
12093 "update vsi failed, err %s aq_err %s\n",
12094 i40e_stat_str(&pf->hw, ret),
12095 i40e_aq_str(&pf->hw,
12096 pf->hw.aq.asq_last_status));
12097 ret = -ENOENT;
12098 goto err;
12099 }
12100
12101 i40e_vsi_update_queue_map(vsi, &ctxt);
12102 vsi->info.valid_sections = 0;
12103 } else {
12104
12105
12106
12107
12108
12109
12110 ret = i40e_vsi_config_tc(vsi, enabled_tc);
12111 if (ret) {
12112
12113
12114
12115 dev_info(&pf->pdev->dev,
12116 "failed to configure TCs for main VSI tc_map 0x%08x, err %s aq_err %s\n",
12117 enabled_tc,
12118 i40e_stat_str(&pf->hw, ret),
12119 i40e_aq_str(&pf->hw,
12120 pf->hw.aq.asq_last_status));
12121 }
12122 }
12123 break;
12124
12125 case I40E_VSI_FDIR:
12126 ctxt.pf_num = hw->pf_id;
12127 ctxt.vf_num = 0;
12128 ctxt.uplink_seid = vsi->uplink_seid;
12129 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
12130 ctxt.flags = I40E_AQ_VSI_TYPE_PF;
12131 if ((pf->flags & I40E_FLAG_VEB_MODE_ENABLED) &&
12132 (i40e_is_vsi_uplink_mode_veb(vsi))) {
12133 ctxt.info.valid_sections |=
12134 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
12135 ctxt.info.switch_id =
12136 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
12137 }
12138 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
12139 break;
12140
12141 case I40E_VSI_VMDQ2:
12142 ctxt.pf_num = hw->pf_id;
12143 ctxt.vf_num = 0;
12144 ctxt.uplink_seid = vsi->uplink_seid;
12145 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
12146 ctxt.flags = I40E_AQ_VSI_TYPE_VMDQ2;
12147
12148
12149
12150
12151 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
12152 ctxt.info.valid_sections |=
12153 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
12154 ctxt.info.switch_id =
12155 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
12156 }
12157
12158
12159 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
12160 break;
12161
12162 case I40E_VSI_SRIOV:
12163 ctxt.pf_num = hw->pf_id;
12164 ctxt.vf_num = vsi->vf_id + hw->func_caps.vf_base_id;
12165 ctxt.uplink_seid = vsi->uplink_seid;
12166 ctxt.connection_type = I40E_AQ_VSI_CONN_TYPE_NORMAL;
12167 ctxt.flags = I40E_AQ_VSI_TYPE_VF;
12168
12169
12170
12171
12172 if (i40e_is_vsi_uplink_mode_veb(vsi)) {
12173 ctxt.info.valid_sections |=
12174 cpu_to_le16(I40E_AQ_VSI_PROP_SWITCH_VALID);
12175 ctxt.info.switch_id =
12176 cpu_to_le16(I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB);
12177 }
12178
12179 if (vsi->back->flags & I40E_FLAG_IWARP_ENABLED) {
12180 ctxt.info.valid_sections |=
12181 cpu_to_le16(I40E_AQ_VSI_PROP_QUEUE_OPT_VALID);
12182 ctxt.info.queueing_opt_flags |=
12183 (I40E_AQ_VSI_QUE_OPT_TCP_ENA |
12184 I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI);
12185 }
12186
12187 ctxt.info.valid_sections |= cpu_to_le16(I40E_AQ_VSI_PROP_VLAN_VALID);
12188 ctxt.info.port_vlan_flags |= I40E_AQ_VSI_PVLAN_MODE_ALL;
12189 if (pf->vf[vsi->vf_id].spoofchk) {
12190 ctxt.info.valid_sections |=
12191 cpu_to_le16(I40E_AQ_VSI_PROP_SECURITY_VALID);
12192 ctxt.info.sec_flags |=
12193 (I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK |
12194 I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK);
12195 }
12196
12197 i40e_vsi_setup_queue_map(vsi, &ctxt, enabled_tc, true);
12198 break;
12199
12200 case I40E_VSI_IWARP:
12201
12202 break;
12203
12204 default:
12205 return -ENODEV;
12206 }
12207
12208 if (vsi->type != I40E_VSI_MAIN) {
12209 ret = i40e_aq_add_vsi(hw, &ctxt, NULL);
12210 if (ret) {
12211 dev_info(&vsi->back->pdev->dev,
12212 "add vsi failed, err %s aq_err %s\n",
12213 i40e_stat_str(&pf->hw, ret),
12214 i40e_aq_str(&pf->hw,
12215 pf->hw.aq.asq_last_status));
12216 ret = -ENOENT;
12217 goto err;
12218 }
12219 vsi->info = ctxt.info;
12220 vsi->info.valid_sections = 0;
12221 vsi->seid = ctxt.seid;
12222 vsi->id = ctxt.vsi_number;
12223 }
12224
12225 vsi->active_filters = 0;
12226 clear_bit(__I40E_VSI_OVERFLOW_PROMISC, vsi->state);
12227 spin_lock_bh(&vsi->mac_filter_hash_lock);
12228
12229 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist) {
12230 f->state = I40E_FILTER_NEW;
12231 f_count++;
12232 }
12233 spin_unlock_bh(&vsi->mac_filter_hash_lock);
12234
12235 if (f_count) {
12236 vsi->flags |= I40E_VSI_FLAG_FILTER_CHANGED;
12237 set_bit(__I40E_MACVLAN_SYNC_PENDING, pf->state);
12238 }
12239
12240
12241 ret = i40e_vsi_get_bw_info(vsi);
12242 if (ret) {
12243 dev_info(&pf->pdev->dev,
12244 "couldn't get vsi bw info, err %s aq_err %s\n",
12245 i40e_stat_str(&pf->hw, ret),
12246 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
12247
12248 ret = 0;
12249 }
12250
12251err:
12252 return ret;
12253}
12254
12255
12256
12257
12258
12259
12260
12261int i40e_vsi_release(struct i40e_vsi *vsi)
12262{
12263 struct i40e_mac_filter *f;
12264 struct hlist_node *h;
12265 struct i40e_veb *veb = NULL;
12266 struct i40e_pf *pf;
12267 u16 uplink_seid;
12268 int i, n, bkt;
12269
12270 pf = vsi->back;
12271
12272
12273 if (vsi->flags & I40E_VSI_FLAG_VEB_OWNER) {
12274 dev_info(&pf->pdev->dev, "VSI %d has existing VEB %d\n",
12275 vsi->seid, vsi->uplink_seid);
12276 return -ENODEV;
12277 }
12278 if (vsi == pf->vsi[pf->lan_vsi] &&
12279 !test_bit(__I40E_DOWN, pf->state)) {
12280 dev_info(&pf->pdev->dev, "Can't remove PF VSI\n");
12281 return -ENODEV;
12282 }
12283
12284 uplink_seid = vsi->uplink_seid;
12285 if (vsi->type != I40E_VSI_SRIOV) {
12286 if (vsi->netdev_registered) {
12287 vsi->netdev_registered = false;
12288 if (vsi->netdev) {
12289
12290 unregister_netdev(vsi->netdev);
12291 }
12292 } else {
12293 i40e_vsi_close(vsi);
12294 }
12295 i40e_vsi_disable_irq(vsi);
12296 }
12297
12298 spin_lock_bh(&vsi->mac_filter_hash_lock);
12299
12300
12301 if (vsi->netdev) {
12302 __dev_uc_unsync(vsi->netdev, NULL);
12303 __dev_mc_unsync(vsi->netdev, NULL);
12304 }
12305
12306
12307 hash_for_each_safe(vsi->mac_filter_hash, bkt, h, f, hlist)
12308 __i40e_del_filter(vsi, f);
12309
12310 spin_unlock_bh(&vsi->mac_filter_hash_lock);
12311
12312 i40e_sync_vsi_filters(vsi);
12313
12314 i40e_vsi_delete(vsi);
12315 i40e_vsi_free_q_vectors(vsi);
12316 if (vsi->netdev) {
12317 free_netdev(vsi->netdev);
12318 vsi->netdev = NULL;
12319 }
12320 i40e_vsi_clear_rings(vsi);
12321 i40e_vsi_clear(vsi);
12322
12323
12324
12325
12326
12327
12328
12329
12330
12331 for (n = 0, i = 0; i < pf->num_alloc_vsi; i++) {
12332 if (pf->vsi[i] &&
12333 pf->vsi[i]->uplink_seid == uplink_seid &&
12334 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
12335 n++;
12336 }
12337 }
12338 for (i = 0; i < I40E_MAX_VEB; i++) {
12339 if (!pf->veb[i])
12340 continue;
12341 if (pf->veb[i]->uplink_seid == uplink_seid)
12342 n++;
12343 if (pf->veb[i]->seid == uplink_seid)
12344 veb = pf->veb[i];
12345 }
12346 if (n == 0 && veb && veb->uplink_seid != 0)
12347 i40e_veb_release(veb);
12348
12349 return 0;
12350}
12351
12352
12353
12354
12355
12356
12357
12358
12359
12360
12361
12362static int i40e_vsi_setup_vectors(struct i40e_vsi *vsi)
12363{
12364 int ret = -ENOENT;
12365 struct i40e_pf *pf = vsi->back;
12366
12367 if (vsi->q_vectors[0]) {
12368 dev_info(&pf->pdev->dev, "VSI %d has existing q_vectors\n",
12369 vsi->seid);
12370 return -EEXIST;
12371 }
12372
12373 if (vsi->base_vector) {
12374 dev_info(&pf->pdev->dev, "VSI %d has non-zero base vector %d\n",
12375 vsi->seid, vsi->base_vector);
12376 return -EEXIST;
12377 }
12378
12379 ret = i40e_vsi_alloc_q_vectors(vsi);
12380 if (ret) {
12381 dev_info(&pf->pdev->dev,
12382 "failed to allocate %d q_vector for VSI %d, ret=%d\n",
12383 vsi->num_q_vectors, vsi->seid, ret);
12384 vsi->num_q_vectors = 0;
12385 goto vector_setup_out;
12386 }
12387
12388
12389
12390
12391 if (!(pf->flags & I40E_FLAG_MSIX_ENABLED))
12392 return ret;
12393 if (vsi->num_q_vectors)
12394 vsi->base_vector = i40e_get_lump(pf, pf->irq_pile,
12395 vsi->num_q_vectors, vsi->idx);
12396 if (vsi->base_vector < 0) {
12397 dev_info(&pf->pdev->dev,
12398 "failed to get tracking for %d vectors for VSI %d, err=%d\n",
12399 vsi->num_q_vectors, vsi->seid, vsi->base_vector);
12400 i40e_vsi_free_q_vectors(vsi);
12401 ret = -ENOENT;
12402 goto vector_setup_out;
12403 }
12404
12405vector_setup_out:
12406 return ret;
12407}
12408
12409
12410
12411
12412
12413
12414
12415
12416
12417
12418static struct i40e_vsi *i40e_vsi_reinit_setup(struct i40e_vsi *vsi)
12419{
12420 u16 alloc_queue_pairs;
12421 struct i40e_pf *pf;
12422 u8 enabled_tc;
12423 int ret;
12424
12425 if (!vsi)
12426 return NULL;
12427
12428 pf = vsi->back;
12429
12430 i40e_put_lump(pf->qp_pile, vsi->base_queue, vsi->idx);
12431 i40e_vsi_clear_rings(vsi);
12432
12433 i40e_vsi_free_arrays(vsi, false);
12434 i40e_set_num_rings_in_vsi(vsi);
12435 ret = i40e_vsi_alloc_arrays(vsi, false);
12436 if (ret)
12437 goto err_vsi;
12438
12439 alloc_queue_pairs = vsi->alloc_queue_pairs *
12440 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
12441
12442 ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx);
12443 if (ret < 0) {
12444 dev_info(&pf->pdev->dev,
12445 "failed to get tracking for %d queues for VSI %d err %d\n",
12446 alloc_queue_pairs, vsi->seid, ret);
12447 goto err_vsi;
12448 }
12449 vsi->base_queue = ret;
12450
12451
12452
12453
12454 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
12455 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
12456 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
12457 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
12458 if (vsi->type == I40E_VSI_MAIN)
12459 i40e_rm_default_mac_filter(vsi, pf->hw.mac.perm_addr);
12460
12461
12462 ret = i40e_alloc_rings(vsi);
12463 if (ret)
12464 goto err_rings;
12465
12466
12467 i40e_vsi_map_rings_to_vectors(vsi);
12468 return vsi;
12469
12470err_rings:
12471 i40e_vsi_free_q_vectors(vsi);
12472 if (vsi->netdev_registered) {
12473 vsi->netdev_registered = false;
12474 unregister_netdev(vsi->netdev);
12475 free_netdev(vsi->netdev);
12476 vsi->netdev = NULL;
12477 }
12478 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
12479err_vsi:
12480 i40e_vsi_clear(vsi);
12481 return NULL;
12482}
12483
12484
12485
12486
12487
12488
12489
12490
12491
12492
12493
12494
12495
12496
12497struct i40e_vsi *i40e_vsi_setup(struct i40e_pf *pf, u8 type,
12498 u16 uplink_seid, u32 param1)
12499{
12500 struct i40e_vsi *vsi = NULL;
12501 struct i40e_veb *veb = NULL;
12502 u16 alloc_queue_pairs;
12503 int ret, i;
12504 int v_idx;
12505
12506
12507
12508
12509
12510
12511
12512
12513
12514
12515
12516
12517
12518
12519 for (i = 0; i < I40E_MAX_VEB; i++) {
12520 if (pf->veb[i] && pf->veb[i]->seid == uplink_seid) {
12521 veb = pf->veb[i];
12522 break;
12523 }
12524 }
12525
12526 if (!veb && uplink_seid != pf->mac_seid) {
12527
12528 for (i = 0; i < pf->num_alloc_vsi; i++) {
12529 if (pf->vsi[i] && pf->vsi[i]->seid == uplink_seid) {
12530 vsi = pf->vsi[i];
12531 break;
12532 }
12533 }
12534 if (!vsi) {
12535 dev_info(&pf->pdev->dev, "no such uplink_seid %d\n",
12536 uplink_seid);
12537 return NULL;
12538 }
12539
12540 if (vsi->uplink_seid == pf->mac_seid)
12541 veb = i40e_veb_setup(pf, 0, pf->mac_seid, vsi->seid,
12542 vsi->tc_config.enabled_tc);
12543 else if ((vsi->flags & I40E_VSI_FLAG_VEB_OWNER) == 0)
12544 veb = i40e_veb_setup(pf, 0, vsi->uplink_seid, vsi->seid,
12545 vsi->tc_config.enabled_tc);
12546 if (veb) {
12547 if (vsi->seid != pf->vsi[pf->lan_vsi]->seid) {
12548 dev_info(&vsi->back->pdev->dev,
12549 "New VSI creation error, uplink seid of LAN VSI expected.\n");
12550 return NULL;
12551 }
12552
12553
12554
12555
12556 if (!(pf->flags & I40E_FLAG_VEB_MODE_ENABLED)) {
12557 veb->bridge_mode = BRIDGE_MODE_VEPA;
12558 pf->flags &= ~I40E_FLAG_VEB_MODE_ENABLED;
12559 }
12560 i40e_config_bridge_mode(veb);
12561 }
12562 for (i = 0; i < I40E_MAX_VEB && !veb; i++) {
12563 if (pf->veb[i] && pf->veb[i]->seid == vsi->uplink_seid)
12564 veb = pf->veb[i];
12565 }
12566 if (!veb) {
12567 dev_info(&pf->pdev->dev, "couldn't add VEB\n");
12568 return NULL;
12569 }
12570
12571 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
12572 uplink_seid = veb->seid;
12573 }
12574
12575
12576 v_idx = i40e_vsi_mem_alloc(pf, type);
12577 if (v_idx < 0)
12578 goto err_alloc;
12579 vsi = pf->vsi[v_idx];
12580 if (!vsi)
12581 goto err_alloc;
12582 vsi->type = type;
12583 vsi->veb_idx = (veb ? veb->idx : I40E_NO_VEB);
12584
12585 if (type == I40E_VSI_MAIN)
12586 pf->lan_vsi = v_idx;
12587 else if (type == I40E_VSI_SRIOV)
12588 vsi->vf_id = param1;
12589
12590 alloc_queue_pairs = vsi->alloc_queue_pairs *
12591 (i40e_enabled_xdp_vsi(vsi) ? 2 : 1);
12592
12593 ret = i40e_get_lump(pf, pf->qp_pile, alloc_queue_pairs, vsi->idx);
12594 if (ret < 0) {
12595 dev_info(&pf->pdev->dev,
12596 "failed to get tracking for %d queues for VSI %d err=%d\n",
12597 alloc_queue_pairs, vsi->seid, ret);
12598 goto err_vsi;
12599 }
12600 vsi->base_queue = ret;
12601
12602
12603 vsi->uplink_seid = uplink_seid;
12604 ret = i40e_add_vsi(vsi);
12605 if (ret)
12606 goto err_vsi;
12607
12608 switch (vsi->type) {
12609
12610 case I40E_VSI_MAIN:
12611 case I40E_VSI_VMDQ2:
12612 ret = i40e_config_netdev(vsi);
12613 if (ret)
12614 goto err_netdev;
12615 ret = register_netdev(vsi->netdev);
12616 if (ret)
12617 goto err_netdev;
12618 vsi->netdev_registered = true;
12619 netif_carrier_off(vsi->netdev);
12620#ifdef CONFIG_I40E_DCB
12621
12622 i40e_dcbnl_setup(vsi);
12623#endif
12624
12625
12626 case I40E_VSI_FDIR:
12627
12628 ret = i40e_vsi_setup_vectors(vsi);
12629 if (ret)
12630 goto err_msix;
12631
12632 ret = i40e_alloc_rings(vsi);
12633 if (ret)
12634 goto err_rings;
12635
12636
12637 i40e_vsi_map_rings_to_vectors(vsi);
12638
12639 i40e_vsi_reset_stats(vsi);
12640 break;
12641
12642 default:
12643
12644 break;
12645 }
12646
12647 if ((pf->hw_features & I40E_HW_RSS_AQ_CAPABLE) &&
12648 (vsi->type == I40E_VSI_VMDQ2)) {
12649 ret = i40e_vsi_config_rss(vsi);
12650 }
12651 return vsi;
12652
12653err_rings:
12654 i40e_vsi_free_q_vectors(vsi);
12655err_msix:
12656 if (vsi->netdev_registered) {
12657 vsi->netdev_registered = false;
12658 unregister_netdev(vsi->netdev);
12659 free_netdev(vsi->netdev);
12660 vsi->netdev = NULL;
12661 }
12662err_netdev:
12663 i40e_aq_delete_element(&pf->hw, vsi->seid, NULL);
12664err_vsi:
12665 i40e_vsi_clear(vsi);
12666err_alloc:
12667 return NULL;
12668}
12669
12670
12671
12672
12673
12674
12675
12676static int i40e_veb_get_bw_info(struct i40e_veb *veb)
12677{
12678 struct i40e_aqc_query_switching_comp_ets_config_resp ets_data;
12679 struct i40e_aqc_query_switching_comp_bw_config_resp bw_data;
12680 struct i40e_pf *pf = veb->pf;
12681 struct i40e_hw *hw = &pf->hw;
12682 u32 tc_bw_max;
12683 int ret = 0;
12684 int i;
12685
12686 ret = i40e_aq_query_switch_comp_bw_config(hw, veb->seid,
12687 &bw_data, NULL);
12688 if (ret) {
12689 dev_info(&pf->pdev->dev,
12690 "query veb bw config failed, err %s aq_err %s\n",
12691 i40e_stat_str(&pf->hw, ret),
12692 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
12693 goto out;
12694 }
12695
12696 ret = i40e_aq_query_switch_comp_ets_config(hw, veb->seid,
12697 &ets_data, NULL);
12698 if (ret) {
12699 dev_info(&pf->pdev->dev,
12700 "query veb bw ets config failed, err %s aq_err %s\n",
12701 i40e_stat_str(&pf->hw, ret),
12702 i40e_aq_str(&pf->hw, hw->aq.asq_last_status));
12703 goto out;
12704 }
12705
12706 veb->bw_limit = le16_to_cpu(ets_data.port_bw_limit);
12707 veb->bw_max_quanta = ets_data.tc_bw_max;
12708 veb->is_abs_credits = bw_data.absolute_credits_enable;
12709 veb->enabled_tc = ets_data.tc_valid_bits;
12710 tc_bw_max = le16_to_cpu(bw_data.tc_bw_max[0]) |
12711 (le16_to_cpu(bw_data.tc_bw_max[1]) << 16);
12712 for (i = 0; i < I40E_MAX_TRAFFIC_CLASS; i++) {
12713 veb->bw_tc_share_credits[i] = bw_data.tc_bw_share_credits[i];
12714 veb->bw_tc_limit_credits[i] =
12715 le16_to_cpu(bw_data.tc_bw_limits[i]);
12716 veb->bw_tc_max_quanta[i] = ((tc_bw_max >> (i*4)) & 0x7);
12717 }
12718
12719out:
12720 return ret;
12721}
12722
12723
12724
12725
12726
12727
12728
12729
12730static int i40e_veb_mem_alloc(struct i40e_pf *pf)
12731{
12732 int ret = -ENOENT;
12733 struct i40e_veb *veb;
12734 int i;
12735
12736
12737 mutex_lock(&pf->switch_mutex);
12738
12739
12740
12741
12742
12743
12744
12745 i = 0;
12746 while ((i < I40E_MAX_VEB) && (pf->veb[i] != NULL))
12747 i++;
12748 if (i >= I40E_MAX_VEB) {
12749 ret = -ENOMEM;
12750 goto err_alloc_veb;
12751 }
12752
12753 veb = kzalloc(sizeof(*veb), GFP_KERNEL);
12754 if (!veb) {
12755 ret = -ENOMEM;
12756 goto err_alloc_veb;
12757 }
12758 veb->pf = pf;
12759 veb->idx = i;
12760 veb->enabled_tc = 1;
12761
12762 pf->veb[i] = veb;
12763 ret = i;
12764err_alloc_veb:
12765 mutex_unlock(&pf->switch_mutex);
12766 return ret;
12767}
12768
12769
12770
12771
12772
12773
12774
12775
12776static void i40e_switch_branch_release(struct i40e_veb *branch)
12777{
12778 struct i40e_pf *pf = branch->pf;
12779 u16 branch_seid = branch->seid;
12780 u16 veb_idx = branch->idx;
12781 int i;
12782
12783
12784 for (i = 0; i < I40E_MAX_VEB; i++) {
12785 if (!pf->veb[i])
12786 continue;
12787 if (pf->veb[i]->uplink_seid == branch->seid)
12788 i40e_switch_branch_release(pf->veb[i]);
12789 }
12790
12791
12792
12793
12794
12795
12796 for (i = 0; i < pf->num_alloc_vsi; i++) {
12797 if (!pf->vsi[i])
12798 continue;
12799 if (pf->vsi[i]->uplink_seid == branch_seid &&
12800 (pf->vsi[i]->flags & I40E_VSI_FLAG_VEB_OWNER) == 0) {
12801 i40e_vsi_release(pf->vsi[i]);
12802 }
12803 }
12804
12805
12806
12807
12808
12809
12810 if (pf->veb[veb_idx])
12811 i40e_veb_release(pf->veb[veb_idx]);
12812}
12813
12814
12815
12816
12817
12818static void i40e_veb_clear(struct i40e_veb *veb)
12819{
12820 if (!veb)
12821 return;
12822
12823 if (veb->pf) {
12824 struct i40e_pf *pf = veb->pf;
12825
12826 mutex_lock(&pf->switch_mutex);
12827 if (pf->veb[veb->idx] == veb)
12828 pf->veb[veb->idx] = NULL;
12829 mutex_unlock(&pf->switch_mutex);
12830 }
12831
12832 kfree(veb);
12833}
12834
12835
12836
12837
12838
12839void i40e_veb_release(struct i40e_veb *veb)
12840{
12841 struct i40e_vsi *vsi = NULL;
12842 struct i40e_pf *pf;
12843 int i, n = 0;
12844
12845 pf = veb->pf;
12846
12847
12848 for (i = 0; i < pf->num_alloc_vsi; i++) {
12849 if (pf->vsi[i] && pf->vsi[i]->uplink_seid == veb->seid) {
12850 n++;
12851 vsi = pf->vsi[i];
12852 }
12853 }
12854 if (n != 1) {
12855 dev_info(&pf->pdev->dev,
12856 "can't remove VEB %d with %d VSIs left\n",
12857 veb->seid, n);
12858 return;
12859 }
12860
12861
12862 vsi->flags &= ~I40E_VSI_FLAG_VEB_OWNER;
12863 if (veb->uplink_seid) {
12864 vsi->uplink_seid = veb->uplink_seid;
12865 if (veb->uplink_seid == pf->mac_seid)
12866 vsi->veb_idx = I40E_NO_VEB;
12867 else
12868 vsi->veb_idx = veb->veb_idx;
12869 } else {
12870
12871 vsi->uplink_seid = pf->vsi[pf->lan_vsi]->uplink_seid;
12872 vsi->veb_idx = pf->vsi[pf->lan_vsi]->veb_idx;
12873 }
12874
12875 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
12876 i40e_veb_clear(veb);
12877}
12878
12879
12880
12881
12882
12883
12884static int i40e_add_veb(struct i40e_veb *veb, struct i40e_vsi *vsi)
12885{
12886 struct i40e_pf *pf = veb->pf;
12887 bool enable_stats = !!(pf->flags & I40E_FLAG_VEB_STATS_ENABLED);
12888 int ret;
12889
12890 ret = i40e_aq_add_veb(&pf->hw, veb->uplink_seid, vsi->seid,
12891 veb->enabled_tc, false,
12892 &veb->seid, enable_stats, NULL);
12893
12894
12895 if (ret) {
12896 dev_info(&pf->pdev->dev,
12897 "couldn't add VEB, err %s aq_err %s\n",
12898 i40e_stat_str(&pf->hw, ret),
12899 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
12900 return -EPERM;
12901 }
12902
12903
12904 ret = i40e_aq_get_veb_parameters(&pf->hw, veb->seid, NULL, NULL,
12905 &veb->stats_idx, NULL, NULL, NULL);
12906 if (ret) {
12907 dev_info(&pf->pdev->dev,
12908 "couldn't get VEB statistics idx, err %s aq_err %s\n",
12909 i40e_stat_str(&pf->hw, ret),
12910 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
12911 return -EPERM;
12912 }
12913 ret = i40e_veb_get_bw_info(veb);
12914 if (ret) {
12915 dev_info(&pf->pdev->dev,
12916 "couldn't get VEB bw info, err %s aq_err %s\n",
12917 i40e_stat_str(&pf->hw, ret),
12918 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
12919 i40e_aq_delete_element(&pf->hw, veb->seid, NULL);
12920 return -ENOENT;
12921 }
12922
12923 vsi->uplink_seid = veb->seid;
12924 vsi->veb_idx = veb->idx;
12925 vsi->flags |= I40E_VSI_FLAG_VEB_OWNER;
12926
12927 return 0;
12928}
12929
12930
12931
12932
12933
12934
12935
12936
12937
12938
12939
12940
12941
12942
12943
12944
12945
12946struct i40e_veb *i40e_veb_setup(struct i40e_pf *pf, u16 flags,
12947 u16 uplink_seid, u16 vsi_seid,
12948 u8 enabled_tc)
12949{
12950 struct i40e_veb *veb, *uplink_veb = NULL;
12951 int vsi_idx, veb_idx;
12952 int ret;
12953
12954
12955 if ((uplink_seid == 0 || vsi_seid == 0) &&
12956 (uplink_seid + vsi_seid != 0)) {
12957 dev_info(&pf->pdev->dev,
12958 "one, not both seid's are 0: uplink=%d vsi=%d\n",
12959 uplink_seid, vsi_seid);
12960 return NULL;
12961 }
12962
12963
12964 for (vsi_idx = 0; vsi_idx < pf->num_alloc_vsi; vsi_idx++)
12965 if (pf->vsi[vsi_idx] && pf->vsi[vsi_idx]->seid == vsi_seid)
12966 break;
12967 if (vsi_idx >= pf->num_alloc_vsi && vsi_seid != 0) {
12968 dev_info(&pf->pdev->dev, "vsi seid %d not found\n",
12969 vsi_seid);
12970 return NULL;
12971 }
12972
12973 if (uplink_seid && uplink_seid != pf->mac_seid) {
12974 for (veb_idx = 0; veb_idx < I40E_MAX_VEB; veb_idx++) {
12975 if (pf->veb[veb_idx] &&
12976 pf->veb[veb_idx]->seid == uplink_seid) {
12977 uplink_veb = pf->veb[veb_idx];
12978 break;
12979 }
12980 }
12981 if (!uplink_veb) {
12982 dev_info(&pf->pdev->dev,
12983 "uplink seid %d not found\n", uplink_seid);
12984 return NULL;
12985 }
12986 }
12987
12988
12989 veb_idx = i40e_veb_mem_alloc(pf);
12990 if (veb_idx < 0)
12991 goto err_alloc;
12992 veb = pf->veb[veb_idx];
12993 veb->flags = flags;
12994 veb->uplink_seid = uplink_seid;
12995 veb->veb_idx = (uplink_veb ? uplink_veb->idx : I40E_NO_VEB);
12996 veb->enabled_tc = (enabled_tc ? enabled_tc : 0x1);
12997
12998
12999 ret = i40e_add_veb(veb, pf->vsi[vsi_idx]);
13000 if (ret)
13001 goto err_veb;
13002 if (vsi_idx == pf->lan_vsi)
13003 pf->lan_veb = veb->idx;
13004
13005 return veb;
13006
13007err_veb:
13008 i40e_veb_clear(veb);
13009err_alloc:
13010 return NULL;
13011}
13012
13013
13014
13015
13016
13017
13018
13019
13020
13021
13022static void i40e_setup_pf_switch_element(struct i40e_pf *pf,
13023 struct i40e_aqc_switch_config_element_resp *ele,
13024 u16 num_reported, bool printconfig)
13025{
13026 u16 downlink_seid = le16_to_cpu(ele->downlink_seid);
13027 u16 uplink_seid = le16_to_cpu(ele->uplink_seid);
13028 u8 element_type = ele->element_type;
13029 u16 seid = le16_to_cpu(ele->seid);
13030
13031 if (printconfig)
13032 dev_info(&pf->pdev->dev,
13033 "type=%d seid=%d uplink=%d downlink=%d\n",
13034 element_type, seid, uplink_seid, downlink_seid);
13035
13036 switch (element_type) {
13037 case I40E_SWITCH_ELEMENT_TYPE_MAC:
13038 pf->mac_seid = seid;
13039 break;
13040 case I40E_SWITCH_ELEMENT_TYPE_VEB:
13041
13042 if (uplink_seid != pf->mac_seid)
13043 break;
13044 if (pf->lan_veb == I40E_NO_VEB) {
13045 int v;
13046
13047
13048 for (v = 0; v < I40E_MAX_VEB; v++) {
13049 if (pf->veb[v] && (pf->veb[v]->seid == seid)) {
13050 pf->lan_veb = v;
13051 break;
13052 }
13053 }
13054 if (pf->lan_veb == I40E_NO_VEB) {
13055 v = i40e_veb_mem_alloc(pf);
13056 if (v < 0)
13057 break;
13058 pf->lan_veb = v;
13059 }
13060 }
13061
13062 pf->veb[pf->lan_veb]->seid = seid;
13063 pf->veb[pf->lan_veb]->uplink_seid = pf->mac_seid;
13064 pf->veb[pf->lan_veb]->pf = pf;
13065 pf->veb[pf->lan_veb]->veb_idx = I40E_NO_VEB;
13066 break;
13067 case I40E_SWITCH_ELEMENT_TYPE_VSI:
13068 if (num_reported != 1)
13069 break;
13070
13071
13072
13073 pf->mac_seid = uplink_seid;
13074 pf->pf_seid = downlink_seid;
13075 pf->main_vsi_seid = seid;
13076 if (printconfig)
13077 dev_info(&pf->pdev->dev,
13078 "pf_seid=%d main_vsi_seid=%d\n",
13079 pf->pf_seid, pf->main_vsi_seid);
13080 break;
13081 case I40E_SWITCH_ELEMENT_TYPE_PF:
13082 case I40E_SWITCH_ELEMENT_TYPE_VF:
13083 case I40E_SWITCH_ELEMENT_TYPE_EMP:
13084 case I40E_SWITCH_ELEMENT_TYPE_BMC:
13085 case I40E_SWITCH_ELEMENT_TYPE_PE:
13086 case I40E_SWITCH_ELEMENT_TYPE_PA:
13087
13088 break;
13089 default:
13090 dev_info(&pf->pdev->dev, "unknown element type=%d seid=%d\n",
13091 element_type, seid);
13092 break;
13093 }
13094}
13095
13096
13097
13098
13099
13100
13101
13102
13103
13104int i40e_fetch_switch_configuration(struct i40e_pf *pf, bool printconfig)
13105{
13106 struct i40e_aqc_get_switch_config_resp *sw_config;
13107 u16 next_seid = 0;
13108 int ret = 0;
13109 u8 *aq_buf;
13110 int i;
13111
13112 aq_buf = kzalloc(I40E_AQ_LARGE_BUF, GFP_KERNEL);
13113 if (!aq_buf)
13114 return -ENOMEM;
13115
13116 sw_config = (struct i40e_aqc_get_switch_config_resp *)aq_buf;
13117 do {
13118 u16 num_reported, num_total;
13119
13120 ret = i40e_aq_get_switch_config(&pf->hw, sw_config,
13121 I40E_AQ_LARGE_BUF,
13122 &next_seid, NULL);
13123 if (ret) {
13124 dev_info(&pf->pdev->dev,
13125 "get switch config failed err %s aq_err %s\n",
13126 i40e_stat_str(&pf->hw, ret),
13127 i40e_aq_str(&pf->hw,
13128 pf->hw.aq.asq_last_status));
13129 kfree(aq_buf);
13130 return -ENOENT;
13131 }
13132
13133 num_reported = le16_to_cpu(sw_config->header.num_reported);
13134 num_total = le16_to_cpu(sw_config->header.num_total);
13135
13136 if (printconfig)
13137 dev_info(&pf->pdev->dev,
13138 "header: %d reported %d total\n",
13139 num_reported, num_total);
13140
13141 for (i = 0; i < num_reported; i++) {
13142 struct i40e_aqc_switch_config_element_resp *ele =
13143 &sw_config->element[i];
13144
13145 i40e_setup_pf_switch_element(pf, ele, num_reported,
13146 printconfig);
13147 }
13148 } while (next_seid != 0);
13149
13150 kfree(aq_buf);
13151 return ret;
13152}
13153
13154
13155
13156
13157
13158
13159
13160
13161static int i40e_setup_pf_switch(struct i40e_pf *pf, bool reinit)
13162{
13163 u16 flags = 0;
13164 int ret;
13165
13166
13167 ret = i40e_fetch_switch_configuration(pf, false);
13168 if (ret) {
13169 dev_info(&pf->pdev->dev,
13170 "couldn't fetch switch config, err %s aq_err %s\n",
13171 i40e_stat_str(&pf->hw, ret),
13172 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
13173 return ret;
13174 }
13175 i40e_pf_reset_stats(pf);
13176
13177
13178
13179
13180
13181
13182
13183 if ((pf->hw.pf_id == 0) &&
13184 !(pf->flags & I40E_FLAG_TRUE_PROMISC_SUPPORT)) {
13185 flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
13186 pf->last_sw_conf_flags = flags;
13187 }
13188
13189 if (pf->hw.pf_id == 0) {
13190 u16 valid_flags;
13191
13192 valid_flags = I40E_AQ_SET_SWITCH_CFG_PROMISC;
13193 ret = i40e_aq_set_switch_config(&pf->hw, flags, valid_flags, 0,
13194 NULL);
13195 if (ret && pf->hw.aq.asq_last_status != I40E_AQ_RC_ESRCH) {
13196 dev_info(&pf->pdev->dev,
13197 "couldn't set switch config bits, err %s aq_err %s\n",
13198 i40e_stat_str(&pf->hw, ret),
13199 i40e_aq_str(&pf->hw,
13200 pf->hw.aq.asq_last_status));
13201
13202 }
13203 pf->last_sw_conf_valid_flags = valid_flags;
13204 }
13205
13206
13207 if (pf->lan_vsi == I40E_NO_VSI || reinit) {
13208 struct i40e_vsi *vsi = NULL;
13209 u16 uplink_seid;
13210
13211
13212
13213
13214 if (pf->lan_veb != I40E_NO_VEB && pf->veb[pf->lan_veb])
13215 uplink_seid = pf->veb[pf->lan_veb]->seid;
13216 else
13217 uplink_seid = pf->mac_seid;
13218 if (pf->lan_vsi == I40E_NO_VSI)
13219 vsi = i40e_vsi_setup(pf, I40E_VSI_MAIN, uplink_seid, 0);
13220 else if (reinit)
13221 vsi = i40e_vsi_reinit_setup(pf->vsi[pf->lan_vsi]);
13222 if (!vsi) {
13223 dev_info(&pf->pdev->dev, "setup of MAIN VSI failed\n");
13224 i40e_cloud_filter_exit(pf);
13225 i40e_fdir_teardown(pf);
13226 return -EAGAIN;
13227 }
13228 } else {
13229
13230 u8 enabled_tc = pf->vsi[pf->lan_vsi]->tc_config.enabled_tc;
13231
13232 pf->vsi[pf->lan_vsi]->tc_config.enabled_tc = 0;
13233 pf->vsi[pf->lan_vsi]->seid = pf->main_vsi_seid;
13234 i40e_vsi_config_tc(pf->vsi[pf->lan_vsi], enabled_tc);
13235 }
13236 i40e_vlan_stripping_disable(pf->vsi[pf->lan_vsi]);
13237
13238 i40e_fdir_sb_setup(pf);
13239
13240
13241 ret = i40e_setup_pf_filter_control(pf);
13242 if (ret) {
13243 dev_info(&pf->pdev->dev, "setup_pf_filter_control failed: %d\n",
13244 ret);
13245
13246 }
13247
13248
13249
13250
13251 if ((pf->flags & I40E_FLAG_RSS_ENABLED))
13252 i40e_pf_config_rss(pf);
13253
13254
13255 i40e_link_event(pf);
13256
13257
13258 pf->fc_autoneg_status = ((pf->hw.phy.link_info.an_info &
13259 I40E_AQ_AN_COMPLETED) ? true : false);
13260
13261 i40e_ptp_init(pf);
13262
13263
13264 i40e_sync_udp_filters(pf);
13265
13266 return ret;
13267}
13268
13269
13270
13271
13272
13273static void i40e_determine_queue_usage(struct i40e_pf *pf)
13274{
13275 int queues_left;
13276 int q_max;
13277
13278 pf->num_lan_qps = 0;
13279
13280
13281
13282
13283
13284 queues_left = pf->hw.func_caps.num_tx_qp;
13285
13286 if ((queues_left == 1) ||
13287 !(pf->flags & I40E_FLAG_MSIX_ENABLED)) {
13288
13289 queues_left = 0;
13290 pf->alloc_rss_size = pf->num_lan_qps = 1;
13291
13292
13293 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
13294 I40E_FLAG_IWARP_ENABLED |
13295 I40E_FLAG_FD_SB_ENABLED |
13296 I40E_FLAG_FD_ATR_ENABLED |
13297 I40E_FLAG_DCB_CAPABLE |
13298 I40E_FLAG_DCB_ENABLED |
13299 I40E_FLAG_SRIOV_ENABLED |
13300 I40E_FLAG_VMDQ_ENABLED);
13301 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
13302 } else if (!(pf->flags & (I40E_FLAG_RSS_ENABLED |
13303 I40E_FLAG_FD_SB_ENABLED |
13304 I40E_FLAG_FD_ATR_ENABLED |
13305 I40E_FLAG_DCB_CAPABLE))) {
13306
13307 pf->alloc_rss_size = pf->num_lan_qps = 1;
13308 queues_left -= pf->num_lan_qps;
13309
13310 pf->flags &= ~(I40E_FLAG_RSS_ENABLED |
13311 I40E_FLAG_IWARP_ENABLED |
13312 I40E_FLAG_FD_SB_ENABLED |
13313 I40E_FLAG_FD_ATR_ENABLED |
13314 I40E_FLAG_DCB_ENABLED |
13315 I40E_FLAG_VMDQ_ENABLED);
13316 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
13317 } else {
13318
13319 if ((pf->flags & I40E_FLAG_DCB_CAPABLE) &&
13320 (queues_left < I40E_MAX_TRAFFIC_CLASS)) {
13321 pf->flags &= ~(I40E_FLAG_DCB_CAPABLE |
13322 I40E_FLAG_DCB_ENABLED);
13323 dev_info(&pf->pdev->dev, "not enough queues for DCB. DCB is disabled.\n");
13324 }
13325
13326
13327 q_max = max_t(int, pf->rss_size_max, num_online_cpus());
13328 q_max = min_t(int, q_max, pf->hw.func_caps.num_tx_qp);
13329 q_max = min_t(int, q_max, pf->hw.func_caps.num_msix_vectors);
13330 pf->num_lan_qps = q_max;
13331
13332 queues_left -= pf->num_lan_qps;
13333 }
13334
13335 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
13336 if (queues_left > 1) {
13337 queues_left -= 1;
13338 } else {
13339 pf->flags &= ~I40E_FLAG_FD_SB_ENABLED;
13340 pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
13341 dev_info(&pf->pdev->dev, "not enough queues for Flow Director. Flow Director feature is disabled\n");
13342 }
13343 }
13344
13345 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
13346 pf->num_vf_qps && pf->num_req_vfs && queues_left) {
13347 pf->num_req_vfs = min_t(int, pf->num_req_vfs,
13348 (queues_left / pf->num_vf_qps));
13349 queues_left -= (pf->num_req_vfs * pf->num_vf_qps);
13350 }
13351
13352 if ((pf->flags & I40E_FLAG_VMDQ_ENABLED) &&
13353 pf->num_vmdq_vsis && pf->num_vmdq_qps && queues_left) {
13354 pf->num_vmdq_vsis = min_t(int, pf->num_vmdq_vsis,
13355 (queues_left / pf->num_vmdq_qps));
13356 queues_left -= (pf->num_vmdq_vsis * pf->num_vmdq_qps);
13357 }
13358
13359 pf->queues_left = queues_left;
13360 dev_dbg(&pf->pdev->dev,
13361 "qs_avail=%d FD SB=%d lan_qs=%d lan_tc0=%d vf=%d*%d vmdq=%d*%d, remaining=%d\n",
13362 pf->hw.func_caps.num_tx_qp,
13363 !!(pf->flags & I40E_FLAG_FD_SB_ENABLED),
13364 pf->num_lan_qps, pf->alloc_rss_size, pf->num_req_vfs,
13365 pf->num_vf_qps, pf->num_vmdq_vsis, pf->num_vmdq_qps,
13366 queues_left);
13367}
13368
13369
13370
13371
13372
13373
13374
13375
13376
13377
13378
13379
13380static int i40e_setup_pf_filter_control(struct i40e_pf *pf)
13381{
13382 struct i40e_filter_control_settings *settings = &pf->filter_settings;
13383
13384 settings->hash_lut_size = I40E_HASH_LUT_SIZE_128;
13385
13386
13387 if (pf->flags & (I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED))
13388 settings->enable_fdir = true;
13389
13390
13391 settings->enable_ethtype = true;
13392 settings->enable_macvlan = true;
13393
13394 if (i40e_set_filter_control(&pf->hw, settings))
13395 return -ENOENT;
13396
13397 return 0;
13398}
13399
13400#define INFO_STRING_LEN 255
13401#define REMAIN(__x) (INFO_STRING_LEN - (__x))
13402static void i40e_print_features(struct i40e_pf *pf)
13403{
13404 struct i40e_hw *hw = &pf->hw;
13405 char *buf;
13406 int i;
13407
13408 buf = kmalloc(INFO_STRING_LEN, GFP_KERNEL);
13409 if (!buf)
13410 return;
13411
13412 i = snprintf(buf, INFO_STRING_LEN, "Features: PF-id[%d]", hw->pf_id);
13413#ifdef CONFIG_PCI_IOV
13414 i += snprintf(&buf[i], REMAIN(i), " VFs: %d", pf->num_req_vfs);
13415#endif
13416 i += snprintf(&buf[i], REMAIN(i), " VSIs: %d QP: %d",
13417 pf->hw.func_caps.num_vsis,
13418 pf->vsi[pf->lan_vsi]->num_queue_pairs);
13419 if (pf->flags & I40E_FLAG_RSS_ENABLED)
13420 i += snprintf(&buf[i], REMAIN(i), " RSS");
13421 if (pf->flags & I40E_FLAG_FD_ATR_ENABLED)
13422 i += snprintf(&buf[i], REMAIN(i), " FD_ATR");
13423 if (pf->flags & I40E_FLAG_FD_SB_ENABLED) {
13424 i += snprintf(&buf[i], REMAIN(i), " FD_SB");
13425 i += snprintf(&buf[i], REMAIN(i), " NTUPLE");
13426 }
13427 if (pf->flags & I40E_FLAG_DCB_CAPABLE)
13428 i += snprintf(&buf[i], REMAIN(i), " DCB");
13429 i += snprintf(&buf[i], REMAIN(i), " VxLAN");
13430 i += snprintf(&buf[i], REMAIN(i), " Geneve");
13431 if (pf->flags & I40E_FLAG_PTP)
13432 i += snprintf(&buf[i], REMAIN(i), " PTP");
13433 if (pf->flags & I40E_FLAG_VEB_MODE_ENABLED)
13434 i += snprintf(&buf[i], REMAIN(i), " VEB");
13435 else
13436 i += snprintf(&buf[i], REMAIN(i), " VEPA");
13437
13438 dev_info(&pf->pdev->dev, "%s\n", buf);
13439 kfree(buf);
13440 WARN_ON(i > INFO_STRING_LEN);
13441}
13442
13443
13444
13445
13446
13447
13448
13449
13450
13451
13452
13453static void i40e_get_platform_mac_addr(struct pci_dev *pdev, struct i40e_pf *pf)
13454{
13455 if (eth_platform_get_mac_address(&pdev->dev, pf->hw.mac.addr))
13456 i40e_get_mac_addr(&pf->hw, pf->hw.mac.addr);
13457}
13458
13459
13460
13461
13462
13463
13464
13465
13466
13467
13468
13469
13470static int i40e_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
13471{
13472 struct i40e_aq_get_phy_abilities_resp abilities;
13473 struct i40e_pf *pf;
13474 struct i40e_hw *hw;
13475 static u16 pfs_found;
13476 u16 wol_nvm_bits;
13477 u16 link_status;
13478 int err;
13479 u32 val;
13480 u32 i;
13481 u8 set_fc_aq_fail;
13482
13483 err = pci_enable_device_mem(pdev);
13484 if (err)
13485 return err;
13486
13487
13488 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64));
13489 if (err) {
13490 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
13491 if (err) {
13492 dev_err(&pdev->dev,
13493 "DMA configuration failed: 0x%x\n", err);
13494 goto err_dma;
13495 }
13496 }
13497
13498
13499 err = pci_request_mem_regions(pdev, i40e_driver_name);
13500 if (err) {
13501 dev_info(&pdev->dev,
13502 "pci_request_selected_regions failed %d\n", err);
13503 goto err_pci_reg;
13504 }
13505
13506 pci_enable_pcie_error_reporting(pdev);
13507 pci_set_master(pdev);
13508
13509
13510
13511
13512
13513
13514 pf = kzalloc(sizeof(*pf), GFP_KERNEL);
13515 if (!pf) {
13516 err = -ENOMEM;
13517 goto err_pf_alloc;
13518 }
13519 pf->next_vsi = 0;
13520 pf->pdev = pdev;
13521 set_bit(__I40E_DOWN, pf->state);
13522
13523 hw = &pf->hw;
13524 hw->back = pf;
13525
13526 pf->ioremap_len = min_t(int, pci_resource_len(pdev, 0),
13527 I40E_MAX_CSR_SPACE);
13528
13529 hw->hw_addr = ioremap(pci_resource_start(pdev, 0), pf->ioremap_len);
13530 if (!hw->hw_addr) {
13531 err = -EIO;
13532 dev_info(&pdev->dev, "ioremap(0x%04x, 0x%04x) failed: 0x%x\n",
13533 (unsigned int)pci_resource_start(pdev, 0),
13534 pf->ioremap_len, err);
13535 goto err_ioremap;
13536 }
13537 hw->vendor_id = pdev->vendor;
13538 hw->device_id = pdev->device;
13539 pci_read_config_byte(pdev, PCI_REVISION_ID, &hw->revision_id);
13540 hw->subsystem_vendor_id = pdev->subsystem_vendor;
13541 hw->subsystem_device_id = pdev->subsystem_device;
13542 hw->bus.device = PCI_SLOT(pdev->devfn);
13543 hw->bus.func = PCI_FUNC(pdev->devfn);
13544 hw->bus.bus_id = pdev->bus->number;
13545 pf->instance = pfs_found;
13546
13547
13548
13549
13550 hw->switch_tag = 0xffff;
13551 hw->first_tag = ETH_P_8021AD;
13552 hw->second_tag = ETH_P_8021Q;
13553
13554 INIT_LIST_HEAD(&pf->l3_flex_pit_list);
13555 INIT_LIST_HEAD(&pf->l4_flex_pit_list);
13556
13557
13558
13559
13560 mutex_init(&hw->aq.asq_mutex);
13561 mutex_init(&hw->aq.arq_mutex);
13562
13563 pf->msg_enable = netif_msg_init(debug,
13564 NETIF_MSG_DRV |
13565 NETIF_MSG_PROBE |
13566 NETIF_MSG_LINK);
13567 if (debug < -1)
13568 pf->hw.debug_mask = debug;
13569
13570
13571 if (hw->revision_id == 0 &&
13572 (rd32(hw, I40E_GLLAN_RCTL_0) & I40E_GLLAN_RCTL_0_PXE_MODE_MASK)) {
13573 wr32(hw, I40E_GLGEN_RTRIG, I40E_GLGEN_RTRIG_CORER_MASK);
13574 i40e_flush(hw);
13575 msleep(200);
13576 pf->corer_count++;
13577
13578 i40e_clear_pxe_mode(hw);
13579 }
13580
13581
13582 i40e_clear_hw(hw);
13583 err = i40e_pf_reset(hw);
13584 if (err) {
13585 dev_info(&pdev->dev, "Initial pf_reset failed: %d\n", err);
13586 goto err_pf_reset;
13587 }
13588 pf->pfr_count++;
13589
13590 hw->aq.num_arq_entries = I40E_AQ_LEN;
13591 hw->aq.num_asq_entries = I40E_AQ_LEN;
13592 hw->aq.arq_buf_size = I40E_MAX_AQ_BUF_SIZE;
13593 hw->aq.asq_buf_size = I40E_MAX_AQ_BUF_SIZE;
13594 pf->adminq_work_limit = I40E_AQ_WORK_LIMIT;
13595
13596 snprintf(pf->int_name, sizeof(pf->int_name) - 1,
13597 "%s-%s:misc",
13598 dev_driver_string(&pf->pdev->dev), dev_name(&pdev->dev));
13599
13600 err = i40e_init_shared_code(hw);
13601 if (err) {
13602 dev_warn(&pdev->dev, "unidentified MAC or BLANK NVM: %d\n",
13603 err);
13604 goto err_pf_reset;
13605 }
13606
13607
13608 pf->hw.fc.requested_mode = I40E_FC_NONE;
13609
13610 err = i40e_init_adminq(hw);
13611 if (err) {
13612 if (err == I40E_ERR_FIRMWARE_API_VERSION)
13613 dev_info(&pdev->dev,
13614 "The driver for the device stopped because the NVM image is newer than expected. You must install the most recent version of the network driver.\n");
13615 else
13616 dev_info(&pdev->dev,
13617 "The driver for the device stopped because the device firmware failed to init. Try updating your NVM image.\n");
13618
13619 goto err_pf_reset;
13620 }
13621 i40e_get_oem_version(hw);
13622
13623
13624 dev_info(&pdev->dev, "fw %d.%d.%05d api %d.%d nvm %s\n",
13625 hw->aq.fw_maj_ver, hw->aq.fw_min_ver, hw->aq.fw_build,
13626 hw->aq.api_maj_ver, hw->aq.api_min_ver,
13627 i40e_nvm_version_str(hw));
13628
13629 if (hw->aq.api_maj_ver == I40E_FW_API_VERSION_MAJOR &&
13630 hw->aq.api_min_ver > I40E_FW_MINOR_VERSION(hw))
13631 dev_info(&pdev->dev,
13632 "The driver for the device detected a newer version of the NVM image than expected. Please install the most recent version of the network driver.\n");
13633 else if (hw->aq.api_maj_ver == 1 && hw->aq.api_min_ver < 4)
13634 dev_info(&pdev->dev,
13635 "The driver for the device detected an older version of the NVM image than expected. Please update the NVM image.\n");
13636
13637 i40e_verify_eeprom(pf);
13638
13639
13640 if (hw->revision_id < 1)
13641 dev_warn(&pdev->dev, "This device is a pre-production adapter/LOM. Please be aware there may be issues with your hardware. If you are experiencing problems please contact your Intel or hardware representative who provided you with this hardware.\n");
13642
13643 i40e_clear_pxe_mode(hw);
13644 err = i40e_get_capabilities(pf, i40e_aqc_opc_list_func_capabilities);
13645 if (err)
13646 goto err_adminq_setup;
13647
13648 err = i40e_sw_init(pf);
13649 if (err) {
13650 dev_info(&pdev->dev, "sw_init failed: %d\n", err);
13651 goto err_sw_init;
13652 }
13653
13654 err = i40e_init_lan_hmc(hw, hw->func_caps.num_tx_qp,
13655 hw->func_caps.num_rx_qp, 0, 0);
13656 if (err) {
13657 dev_info(&pdev->dev, "init_lan_hmc failed: %d\n", err);
13658 goto err_init_lan_hmc;
13659 }
13660
13661 err = i40e_configure_lan_hmc(hw, I40E_HMC_MODEL_DIRECT_ONLY);
13662 if (err) {
13663 dev_info(&pdev->dev, "configure_lan_hmc failed: %d\n", err);
13664 err = -ENOENT;
13665 goto err_configure_lan_hmc;
13666 }
13667
13668
13669
13670
13671
13672 if (pf->hw_features & I40E_HW_STOP_FW_LLDP) {
13673 dev_info(&pdev->dev, "Stopping firmware LLDP agent.\n");
13674 i40e_aq_stop_lldp(hw, true, NULL);
13675 }
13676
13677
13678 i40e_get_platform_mac_addr(pdev, pf);
13679
13680 if (!is_valid_ether_addr(hw->mac.addr)) {
13681 dev_info(&pdev->dev, "invalid MAC address %pM\n", hw->mac.addr);
13682 err = -EIO;
13683 goto err_mac_addr;
13684 }
13685 dev_info(&pdev->dev, "MAC address: %pM\n", hw->mac.addr);
13686 ether_addr_copy(hw->mac.perm_addr, hw->mac.addr);
13687 i40e_get_port_mac_addr(hw, hw->mac.port_addr);
13688 if (is_valid_ether_addr(hw->mac.port_addr))
13689 pf->hw_features |= I40E_HW_PORT_ID_VALID;
13690
13691 pci_set_drvdata(pdev, pf);
13692 pci_save_state(pdev);
13693
13694
13695 i40e_aq_set_dcb_parameters(hw, true, NULL);
13696
13697#ifdef CONFIG_I40E_DCB
13698 err = i40e_init_pf_dcb(pf);
13699 if (err) {
13700 dev_info(&pdev->dev, "DCB init failed %d, disabled\n", err);
13701 pf->flags &= ~(I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED);
13702
13703 }
13704#endif
13705
13706
13707 timer_setup(&pf->service_timer, i40e_service_timer, 0);
13708 pf->service_timer_period = HZ;
13709
13710 INIT_WORK(&pf->service_task, i40e_service_task);
13711 clear_bit(__I40E_SERVICE_SCHED, pf->state);
13712
13713
13714 i40e_read_nvm_word(hw, I40E_SR_NVM_WAKE_ON_LAN, &wol_nvm_bits);
13715 if (BIT (hw->port) & wol_nvm_bits || hw->partition_id != 1)
13716 pf->wol_en = false;
13717 else
13718 pf->wol_en = true;
13719 device_set_wakeup_enable(&pf->pdev->dev, pf->wol_en);
13720
13721
13722 i40e_determine_queue_usage(pf);
13723 err = i40e_init_interrupt_scheme(pf);
13724 if (err)
13725 goto err_switch_setup;
13726
13727
13728
13729
13730
13731
13732 if (pf->hw.func_caps.num_vsis < I40E_MIN_VSI_ALLOC)
13733 pf->num_alloc_vsi = I40E_MIN_VSI_ALLOC;
13734 else
13735 pf->num_alloc_vsi = pf->hw.func_caps.num_vsis;
13736
13737
13738 pf->vsi = kcalloc(pf->num_alloc_vsi, sizeof(struct i40e_vsi *),
13739 GFP_KERNEL);
13740 if (!pf->vsi) {
13741 err = -ENOMEM;
13742 goto err_switch_setup;
13743 }
13744
13745#ifdef CONFIG_PCI_IOV
13746
13747 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
13748 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
13749 !test_bit(__I40E_BAD_EEPROM, pf->state)) {
13750 if (pci_num_vf(pdev))
13751 pf->flags |= I40E_FLAG_VEB_MODE_ENABLED;
13752 }
13753#endif
13754 err = i40e_setup_pf_switch(pf, false);
13755 if (err) {
13756 dev_info(&pdev->dev, "setup_pf_switch failed: %d\n", err);
13757 goto err_vsis;
13758 }
13759 INIT_LIST_HEAD(&pf->vsi[pf->lan_vsi]->ch_list);
13760
13761
13762 err = i40e_set_fc(hw, &set_fc_aq_fail, true);
13763 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_GET)
13764 dev_dbg(&pf->pdev->dev,
13765 "Set fc with err %s aq_err %s on get_phy_cap\n",
13766 i40e_stat_str(hw, err),
13767 i40e_aq_str(hw, hw->aq.asq_last_status));
13768 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_SET)
13769 dev_dbg(&pf->pdev->dev,
13770 "Set fc with err %s aq_err %s on set_phy_config\n",
13771 i40e_stat_str(hw, err),
13772 i40e_aq_str(hw, hw->aq.asq_last_status));
13773 if (set_fc_aq_fail & I40E_SET_FC_AQ_FAIL_UPDATE)
13774 dev_dbg(&pf->pdev->dev,
13775 "Set fc with err %s aq_err %s on get_link_info\n",
13776 i40e_stat_str(hw, err),
13777 i40e_aq_str(hw, hw->aq.asq_last_status));
13778
13779
13780 for (i = 0; i < pf->num_alloc_vsi; i++) {
13781 if (pf->vsi[i] && pf->vsi[i]->type == I40E_VSI_FDIR) {
13782 i40e_vsi_open(pf->vsi[i]);
13783 break;
13784 }
13785 }
13786
13787
13788
13789
13790 err = i40e_aq_set_phy_int_mask(&pf->hw,
13791 ~(I40E_AQ_EVENT_LINK_UPDOWN |
13792 I40E_AQ_EVENT_MEDIA_NA |
13793 I40E_AQ_EVENT_MODULE_QUAL_FAIL), NULL);
13794 if (err)
13795 dev_info(&pf->pdev->dev, "set phy mask fail, err %s aq_err %s\n",
13796 i40e_stat_str(&pf->hw, err),
13797 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
13798
13799
13800
13801
13802
13803 val = rd32(hw, I40E_REG_MSS);
13804 if ((val & I40E_REG_MSS_MIN_MASK) > I40E_64BYTE_MSS) {
13805 val &= ~I40E_REG_MSS_MIN_MASK;
13806 val |= I40E_64BYTE_MSS;
13807 wr32(hw, I40E_REG_MSS, val);
13808 }
13809
13810 if (pf->hw_features & I40E_HW_RESTART_AUTONEG) {
13811 msleep(75);
13812 err = i40e_aq_set_link_restart_an(&pf->hw, true, NULL);
13813 if (err)
13814 dev_info(&pf->pdev->dev, "link restart failed, err %s aq_err %s\n",
13815 i40e_stat_str(&pf->hw, err),
13816 i40e_aq_str(&pf->hw,
13817 pf->hw.aq.asq_last_status));
13818 }
13819
13820
13821
13822
13823 clear_bit(__I40E_DOWN, pf->state);
13824
13825
13826
13827
13828
13829
13830 if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
13831 err = i40e_setup_misc_vector(pf);
13832 if (err) {
13833 dev_info(&pdev->dev,
13834 "setup of misc vector failed: %d\n", err);
13835 goto err_vsis;
13836 }
13837 }
13838
13839#ifdef CONFIG_PCI_IOV
13840
13841 if ((pf->flags & I40E_FLAG_SRIOV_ENABLED) &&
13842 (pf->flags & I40E_FLAG_MSIX_ENABLED) &&
13843 !test_bit(__I40E_BAD_EEPROM, pf->state)) {
13844
13845 val = rd32(hw, I40E_PFGEN_PORTMDIO_NUM);
13846 val &= ~I40E_PFGEN_PORTMDIO_NUM_VFLINK_STAT_ENA_MASK;
13847 wr32(hw, I40E_PFGEN_PORTMDIO_NUM, val);
13848 i40e_flush(hw);
13849
13850 if (pci_num_vf(pdev)) {
13851 dev_info(&pdev->dev,
13852 "Active VFs found, allocating resources.\n");
13853 err = i40e_alloc_vfs(pf, pci_num_vf(pdev));
13854 if (err)
13855 dev_info(&pdev->dev,
13856 "Error %d allocating resources for existing VFs\n",
13857 err);
13858 }
13859 }
13860#endif
13861
13862 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
13863 pf->iwarp_base_vector = i40e_get_lump(pf, pf->irq_pile,
13864 pf->num_iwarp_msix,
13865 I40E_IWARP_IRQ_PILE_ID);
13866 if (pf->iwarp_base_vector < 0) {
13867 dev_info(&pdev->dev,
13868 "failed to get tracking for %d vectors for IWARP err=%d\n",
13869 pf->num_iwarp_msix, pf->iwarp_base_vector);
13870 pf->flags &= ~I40E_FLAG_IWARP_ENABLED;
13871 }
13872 }
13873
13874 i40e_dbg_pf_init(pf);
13875
13876
13877 i40e_send_version(pf);
13878
13879
13880 mod_timer(&pf->service_timer,
13881 round_jiffies(jiffies + pf->service_timer_period));
13882
13883
13884 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
13885 err = i40e_lan_add_device(pf);
13886 if (err)
13887 dev_info(&pdev->dev, "Failed to add PF to client API service list: %d\n",
13888 err);
13889 }
13890
13891#define PCI_SPEED_SIZE 8
13892#define PCI_WIDTH_SIZE 8
13893
13894
13895
13896
13897 if (!(pf->hw_features & I40E_HW_NO_PCI_LINK_CHECK)) {
13898 char speed[PCI_SPEED_SIZE] = "Unknown";
13899 char width[PCI_WIDTH_SIZE] = "Unknown";
13900
13901
13902
13903
13904 pcie_capability_read_word(pf->pdev, PCI_EXP_LNKSTA,
13905 &link_status);
13906
13907 i40e_set_pci_config_data(hw, link_status);
13908
13909 switch (hw->bus.speed) {
13910 case i40e_bus_speed_8000:
13911 strncpy(speed, "8.0", PCI_SPEED_SIZE); break;
13912 case i40e_bus_speed_5000:
13913 strncpy(speed, "5.0", PCI_SPEED_SIZE); break;
13914 case i40e_bus_speed_2500:
13915 strncpy(speed, "2.5", PCI_SPEED_SIZE); break;
13916 default:
13917 break;
13918 }
13919 switch (hw->bus.width) {
13920 case i40e_bus_width_pcie_x8:
13921 strncpy(width, "8", PCI_WIDTH_SIZE); break;
13922 case i40e_bus_width_pcie_x4:
13923 strncpy(width, "4", PCI_WIDTH_SIZE); break;
13924 case i40e_bus_width_pcie_x2:
13925 strncpy(width, "2", PCI_WIDTH_SIZE); break;
13926 case i40e_bus_width_pcie_x1:
13927 strncpy(width, "1", PCI_WIDTH_SIZE); break;
13928 default:
13929 break;
13930 }
13931
13932 dev_info(&pdev->dev, "PCI-Express: Speed %sGT/s Width x%s\n",
13933 speed, width);
13934
13935 if (hw->bus.width < i40e_bus_width_pcie_x8 ||
13936 hw->bus.speed < i40e_bus_speed_8000) {
13937 dev_warn(&pdev->dev, "PCI-Express bandwidth available for this device may be insufficient for optimal performance.\n");
13938 dev_warn(&pdev->dev, "Please move the device to a different PCI-e link with more lanes and/or higher transfer rate.\n");
13939 }
13940 }
13941
13942
13943 err = i40e_aq_get_phy_capabilities(hw, false, false, &abilities, NULL);
13944 if (err)
13945 dev_dbg(&pf->pdev->dev, "get requested speeds ret = %s last_status = %s\n",
13946 i40e_stat_str(&pf->hw, err),
13947 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
13948 pf->hw.phy.link_info.requested_speeds = abilities.link_speed;
13949
13950
13951 err = i40e_aq_get_phy_capabilities(hw, false, true, &abilities, NULL);
13952 if (err)
13953 dev_dbg(&pf->pdev->dev, "get supported phy types ret = %s last_status = %s\n",
13954 i40e_stat_str(&pf->hw, err),
13955 i40e_aq_str(&pf->hw, pf->hw.aq.asq_last_status));
13956
13957
13958
13959
13960
13961
13962
13963 i40e_add_filter_to_drop_tx_flow_control_frames(&pf->hw,
13964 pf->main_vsi_seid);
13965
13966 if ((pf->hw.device_id == I40E_DEV_ID_10G_BASE_T) ||
13967 (pf->hw.device_id == I40E_DEV_ID_10G_BASE_T4))
13968 pf->hw_features |= I40E_HW_PHY_CONTROLS_LEDS;
13969 if (pf->hw.device_id == I40E_DEV_ID_SFP_I_X722)
13970 pf->hw_features |= I40E_HW_HAVE_CRT_RETIMER;
13971
13972 i40e_print_features(pf);
13973
13974 return 0;
13975
13976
13977err_vsis:
13978 set_bit(__I40E_DOWN, pf->state);
13979 i40e_clear_interrupt_scheme(pf);
13980 kfree(pf->vsi);
13981err_switch_setup:
13982 i40e_reset_interrupt_capability(pf);
13983 del_timer_sync(&pf->service_timer);
13984err_mac_addr:
13985err_configure_lan_hmc:
13986 (void)i40e_shutdown_lan_hmc(hw);
13987err_init_lan_hmc:
13988 kfree(pf->qp_pile);
13989err_sw_init:
13990err_adminq_setup:
13991err_pf_reset:
13992 iounmap(hw->hw_addr);
13993err_ioremap:
13994 kfree(pf);
13995err_pf_alloc:
13996 pci_disable_pcie_error_reporting(pdev);
13997 pci_release_mem_regions(pdev);
13998err_pci_reg:
13999err_dma:
14000 pci_disable_device(pdev);
14001 return err;
14002}
14003
14004
14005
14006
14007
14008
14009
14010
14011
14012
14013static void i40e_remove(struct pci_dev *pdev)
14014{
14015 struct i40e_pf *pf = pci_get_drvdata(pdev);
14016 struct i40e_hw *hw = &pf->hw;
14017 i40e_status ret_code;
14018 int i;
14019
14020 i40e_dbg_pf_exit(pf);
14021
14022 i40e_ptp_stop(pf);
14023
14024
14025 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(0), 0);
14026 i40e_write_rx_ctl(hw, I40E_PFQF_HENA(1), 0);
14027
14028
14029 set_bit(__I40E_SUSPENDED, pf->state);
14030 set_bit(__I40E_DOWN, pf->state);
14031 if (pf->service_timer.function)
14032 del_timer_sync(&pf->service_timer);
14033 if (pf->service_task.func)
14034 cancel_work_sync(&pf->service_task);
14035
14036
14037
14038
14039 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
14040
14041 if (pf->flags & I40E_FLAG_SRIOV_ENABLED) {
14042 i40e_free_vfs(pf);
14043 pf->flags &= ~I40E_FLAG_SRIOV_ENABLED;
14044 }
14045
14046 i40e_fdir_teardown(pf);
14047
14048
14049
14050
14051 for (i = 0; i < I40E_MAX_VEB; i++) {
14052 if (!pf->veb[i])
14053 continue;
14054
14055 if (pf->veb[i]->uplink_seid == pf->mac_seid ||
14056 pf->veb[i]->uplink_seid == 0)
14057 i40e_switch_branch_release(pf->veb[i]);
14058 }
14059
14060
14061
14062
14063 if (pf->vsi[pf->lan_vsi])
14064 i40e_vsi_release(pf->vsi[pf->lan_vsi]);
14065
14066 i40e_cloud_filter_exit(pf);
14067
14068
14069 if (pf->flags & I40E_FLAG_IWARP_ENABLED) {
14070 ret_code = i40e_lan_del_device(pf);
14071 if (ret_code)
14072 dev_warn(&pdev->dev, "Failed to delete client device: %d\n",
14073 ret_code);
14074 }
14075
14076
14077 if (hw->hmc.hmc_obj) {
14078 ret_code = i40e_shutdown_lan_hmc(hw);
14079 if (ret_code)
14080 dev_warn(&pdev->dev,
14081 "Failed to destroy the HMC resources: %d\n",
14082 ret_code);
14083 }
14084
14085
14086 i40e_shutdown_adminq(hw);
14087
14088
14089 mutex_destroy(&hw->aq.arq_mutex);
14090 mutex_destroy(&hw->aq.asq_mutex);
14091
14092
14093 i40e_clear_interrupt_scheme(pf);
14094 for (i = 0; i < pf->num_alloc_vsi; i++) {
14095 if (pf->vsi[i]) {
14096 i40e_vsi_clear_rings(pf->vsi[i]);
14097 i40e_vsi_clear(pf->vsi[i]);
14098 pf->vsi[i] = NULL;
14099 }
14100 }
14101
14102 for (i = 0; i < I40E_MAX_VEB; i++) {
14103 kfree(pf->veb[i]);
14104 pf->veb[i] = NULL;
14105 }
14106
14107 kfree(pf->qp_pile);
14108 kfree(pf->vsi);
14109
14110 iounmap(hw->hw_addr);
14111 kfree(pf);
14112 pci_release_mem_regions(pdev);
14113
14114 pci_disable_pcie_error_reporting(pdev);
14115 pci_disable_device(pdev);
14116}
14117
14118
14119
14120
14121
14122
14123
14124
14125
14126static pci_ers_result_t i40e_pci_error_detected(struct pci_dev *pdev,
14127 enum pci_channel_state error)
14128{
14129 struct i40e_pf *pf = pci_get_drvdata(pdev);
14130
14131 dev_info(&pdev->dev, "%s: error %d\n", __func__, error);
14132
14133 if (!pf) {
14134 dev_info(&pdev->dev,
14135 "Cannot recover - error happened during device probe\n");
14136 return PCI_ERS_RESULT_DISCONNECT;
14137 }
14138
14139
14140 if (!test_bit(__I40E_SUSPENDED, pf->state))
14141 i40e_prep_for_reset(pf, false);
14142
14143
14144 return PCI_ERS_RESULT_NEED_RESET;
14145}
14146
14147
14148
14149
14150
14151
14152
14153
14154
14155
14156static pci_ers_result_t i40e_pci_error_slot_reset(struct pci_dev *pdev)
14157{
14158 struct i40e_pf *pf = pci_get_drvdata(pdev);
14159 pci_ers_result_t result;
14160 int err;
14161 u32 reg;
14162
14163 dev_dbg(&pdev->dev, "%s\n", __func__);
14164 if (pci_enable_device_mem(pdev)) {
14165 dev_info(&pdev->dev,
14166 "Cannot re-enable PCI device after reset.\n");
14167 result = PCI_ERS_RESULT_DISCONNECT;
14168 } else {
14169 pci_set_master(pdev);
14170 pci_restore_state(pdev);
14171 pci_save_state(pdev);
14172 pci_wake_from_d3(pdev, false);
14173
14174 reg = rd32(&pf->hw, I40E_GLGEN_RTRIG);
14175 if (reg == 0)
14176 result = PCI_ERS_RESULT_RECOVERED;
14177 else
14178 result = PCI_ERS_RESULT_DISCONNECT;
14179 }
14180
14181 err = pci_cleanup_aer_uncorrect_error_status(pdev);
14182 if (err) {
14183 dev_info(&pdev->dev,
14184 "pci_cleanup_aer_uncorrect_error_status failed 0x%0x\n",
14185 err);
14186
14187 }
14188
14189 return result;
14190}
14191
14192
14193
14194
14195
14196static void i40e_pci_error_reset_prepare(struct pci_dev *pdev)
14197{
14198 struct i40e_pf *pf = pci_get_drvdata(pdev);
14199
14200 i40e_prep_for_reset(pf, false);
14201}
14202
14203
14204
14205
14206
14207static void i40e_pci_error_reset_done(struct pci_dev *pdev)
14208{
14209 struct i40e_pf *pf = pci_get_drvdata(pdev);
14210
14211 i40e_reset_and_rebuild(pf, false, false);
14212}
14213
14214
14215
14216
14217
14218
14219
14220
14221static void i40e_pci_error_resume(struct pci_dev *pdev)
14222{
14223 struct i40e_pf *pf = pci_get_drvdata(pdev);
14224
14225 dev_dbg(&pdev->dev, "%s\n", __func__);
14226 if (test_bit(__I40E_SUSPENDED, pf->state))
14227 return;
14228
14229 i40e_handle_reset_warning(pf, false);
14230}
14231
14232
14233
14234
14235
14236
14237static void i40e_enable_mc_magic_wake(struct i40e_pf *pf)
14238{
14239 struct i40e_hw *hw = &pf->hw;
14240 i40e_status ret;
14241 u8 mac_addr[6];
14242 u16 flags = 0;
14243
14244
14245 if (pf->vsi[pf->lan_vsi] && pf->vsi[pf->lan_vsi]->netdev) {
14246 ether_addr_copy(mac_addr,
14247 pf->vsi[pf->lan_vsi]->netdev->dev_addr);
14248 } else {
14249 dev_err(&pf->pdev->dev,
14250 "Failed to retrieve MAC address; using default\n");
14251 ether_addr_copy(mac_addr, hw->mac.addr);
14252 }
14253
14254
14255
14256
14257
14258 flags = I40E_AQC_WRITE_TYPE_LAA_WOL;
14259
14260 if (hw->func_caps.flex10_enable && hw->partition_id != 1)
14261 flags = I40E_AQC_WRITE_TYPE_LAA_ONLY;
14262
14263 ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL);
14264 if (ret) {
14265 dev_err(&pf->pdev->dev,
14266 "Failed to update MAC address registers; cannot enable Multicast Magic packet wake up");
14267 return;
14268 }
14269
14270 flags = I40E_AQC_MC_MAG_EN
14271 | I40E_AQC_WOL_PRESERVE_ON_PFR
14272 | I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG;
14273 ret = i40e_aq_mac_address_write(hw, flags, mac_addr, NULL);
14274 if (ret)
14275 dev_err(&pf->pdev->dev,
14276 "Failed to enable Multicast Magic Packet wake up\n");
14277}
14278
14279
14280
14281
14282
14283static void i40e_shutdown(struct pci_dev *pdev)
14284{
14285 struct i40e_pf *pf = pci_get_drvdata(pdev);
14286 struct i40e_hw *hw = &pf->hw;
14287
14288 set_bit(__I40E_SUSPENDED, pf->state);
14289 set_bit(__I40E_DOWN, pf->state);
14290 rtnl_lock();
14291 i40e_prep_for_reset(pf, true);
14292 rtnl_unlock();
14293
14294 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
14295 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
14296
14297 del_timer_sync(&pf->service_timer);
14298 cancel_work_sync(&pf->service_task);
14299 i40e_cloud_filter_exit(pf);
14300 i40e_fdir_teardown(pf);
14301
14302
14303
14304
14305 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
14306
14307 if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE))
14308 i40e_enable_mc_magic_wake(pf);
14309
14310 i40e_prep_for_reset(pf, false);
14311
14312 wr32(hw, I40E_PFPM_APM,
14313 (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
14314 wr32(hw, I40E_PFPM_WUFC,
14315 (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
14316
14317 i40e_clear_interrupt_scheme(pf);
14318
14319 if (system_state == SYSTEM_POWER_OFF) {
14320 pci_wake_from_d3(pdev, pf->wol_en);
14321 pci_set_power_state(pdev, PCI_D3hot);
14322 }
14323}
14324
14325
14326
14327
14328
14329static int __maybe_unused i40e_suspend(struct device *dev)
14330{
14331 struct pci_dev *pdev = to_pci_dev(dev);
14332 struct i40e_pf *pf = pci_get_drvdata(pdev);
14333 struct i40e_hw *hw = &pf->hw;
14334
14335
14336 if (test_and_set_bit(__I40E_SUSPENDED, pf->state))
14337 return 0;
14338
14339 set_bit(__I40E_DOWN, pf->state);
14340
14341
14342 del_timer_sync(&pf->service_timer);
14343 cancel_work_sync(&pf->service_task);
14344
14345
14346
14347
14348 i40e_notify_client_of_netdev_close(pf->vsi[pf->lan_vsi], false);
14349
14350 if (pf->wol_en && (pf->hw_features & I40E_HW_WOL_MC_MAGIC_PKT_WAKE))
14351 i40e_enable_mc_magic_wake(pf);
14352
14353
14354
14355
14356
14357 rtnl_lock();
14358
14359 i40e_prep_for_reset(pf, true);
14360
14361 wr32(hw, I40E_PFPM_APM, (pf->wol_en ? I40E_PFPM_APM_APME_MASK : 0));
14362 wr32(hw, I40E_PFPM_WUFC, (pf->wol_en ? I40E_PFPM_WUFC_MAG_MASK : 0));
14363
14364
14365
14366
14367
14368
14369 i40e_clear_interrupt_scheme(pf);
14370
14371 rtnl_unlock();
14372
14373 return 0;
14374}
14375
14376
14377
14378
14379
14380static int __maybe_unused i40e_resume(struct device *dev)
14381{
14382 struct pci_dev *pdev = to_pci_dev(dev);
14383 struct i40e_pf *pf = pci_get_drvdata(pdev);
14384 int err;
14385
14386
14387 if (!test_bit(__I40E_SUSPENDED, pf->state))
14388 return 0;
14389
14390
14391
14392
14393 rtnl_lock();
14394
14395
14396
14397
14398 err = i40e_restore_interrupt_scheme(pf);
14399 if (err) {
14400 dev_err(&pdev->dev, "Cannot restore interrupt scheme: %d\n",
14401 err);
14402 }
14403
14404 clear_bit(__I40E_DOWN, pf->state);
14405 i40e_reset_and_rebuild(pf, false, true);
14406
14407 rtnl_unlock();
14408
14409
14410 clear_bit(__I40E_SUSPENDED, pf->state);
14411
14412
14413 mod_timer(&pf->service_timer,
14414 round_jiffies(jiffies + pf->service_timer_period));
14415
14416 return 0;
14417}
14418
14419static const struct pci_error_handlers i40e_err_handler = {
14420 .error_detected = i40e_pci_error_detected,
14421 .slot_reset = i40e_pci_error_slot_reset,
14422 .reset_prepare = i40e_pci_error_reset_prepare,
14423 .reset_done = i40e_pci_error_reset_done,
14424 .resume = i40e_pci_error_resume,
14425};
14426
14427static SIMPLE_DEV_PM_OPS(i40e_pm_ops, i40e_suspend, i40e_resume);
14428
14429static struct pci_driver i40e_driver = {
14430 .name = i40e_driver_name,
14431 .id_table = i40e_pci_tbl,
14432 .probe = i40e_probe,
14433 .remove = i40e_remove,
14434 .driver = {
14435 .pm = &i40e_pm_ops,
14436 },
14437 .shutdown = i40e_shutdown,
14438 .err_handler = &i40e_err_handler,
14439 .sriov_configure = i40e_pci_sriov_configure,
14440};
14441
14442
14443
14444
14445
14446
14447
14448static int __init i40e_init_module(void)
14449{
14450 pr_info("%s: %s - version %s\n", i40e_driver_name,
14451 i40e_driver_string, i40e_driver_version_str);
14452 pr_info("%s: %s\n", i40e_driver_name, i40e_copyright);
14453
14454
14455
14456
14457
14458
14459
14460
14461 i40e_wq = alloc_workqueue("%s", WQ_MEM_RECLAIM, 0, i40e_driver_name);
14462 if (!i40e_wq) {
14463 pr_err("%s: Failed to create workqueue\n", i40e_driver_name);
14464 return -ENOMEM;
14465 }
14466
14467 i40e_dbg_init();
14468 return pci_register_driver(&i40e_driver);
14469}
14470module_init(i40e_init_module);
14471
14472
14473
14474
14475
14476
14477
14478static void __exit i40e_exit_module(void)
14479{
14480 pci_unregister_driver(&i40e_driver);
14481 destroy_workqueue(i40e_wq);
14482 i40e_dbg_exit();
14483}
14484module_exit(i40e_exit_module);
14485