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28#include "i40e.h"
29#include <linux/ptp_classify.h>
30
31
32
33
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36
37
38
39
40
41
42
43#define I40E_PTP_40GB_INCVAL 0x0199999999ULL
44#define I40E_PTP_10GB_INCVAL 0x0333333333ULL
45#define I40E_PTP_1GB_INCVAL 0x2000000000ULL
46
47#define I40E_PRTTSYN_CTL1_TSYNTYPE_V1 BIT(I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
48#define I40E_PRTTSYN_CTL1_TSYNTYPE_V2 (2 << \
49 I40E_PRTTSYN_CTL1_TSYNTYPE_SHIFT)
50
51
52
53
54
55
56
57
58
59
60static void i40e_ptp_read(struct i40e_pf *pf, struct timespec64 *ts)
61{
62 struct i40e_hw *hw = &pf->hw;
63 u32 hi, lo;
64 u64 ns;
65
66
67 lo = rd32(hw, I40E_PRTTSYN_TIME_L);
68 hi = rd32(hw, I40E_PRTTSYN_TIME_H);
69
70 ns = (((u64)hi) << 32) | lo;
71
72 *ts = ns_to_timespec64(ns);
73}
74
75
76
77
78
79
80
81
82
83
84static void i40e_ptp_write(struct i40e_pf *pf, const struct timespec64 *ts)
85{
86 struct i40e_hw *hw = &pf->hw;
87 u64 ns = timespec64_to_ns(ts);
88
89
90
91
92 wr32(hw, I40E_PRTTSYN_TIME_L, ns & 0xFFFFFFFF);
93 wr32(hw, I40E_PRTTSYN_TIME_H, ns >> 32);
94}
95
96
97
98
99
100
101
102
103
104
105static void i40e_ptp_convert_to_hwtstamp(struct skb_shared_hwtstamps *hwtstamps,
106 u64 timestamp)
107{
108 memset(hwtstamps, 0, sizeof(*hwtstamps));
109
110 hwtstamps->hwtstamp = ns_to_ktime(timestamp);
111}
112
113
114
115
116
117
118
119
120
121static int i40e_ptp_adjfreq(struct ptp_clock_info *ptp, s32 ppb)
122{
123 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
124 struct i40e_hw *hw = &pf->hw;
125 u64 adj, freq, diff;
126 int neg_adj = 0;
127
128 if (ppb < 0) {
129 neg_adj = 1;
130 ppb = -ppb;
131 }
132
133 smp_mb();
134 adj = READ_ONCE(pf->ptp_base_adj);
135
136 freq = adj;
137 freq *= ppb;
138 diff = div_u64(freq, 1000000000ULL);
139
140 if (neg_adj)
141 adj -= diff;
142 else
143 adj += diff;
144
145 wr32(hw, I40E_PRTTSYN_INC_L, adj & 0xFFFFFFFF);
146 wr32(hw, I40E_PRTTSYN_INC_H, adj >> 32);
147
148 return 0;
149}
150
151
152
153
154
155
156
157
158
159static int i40e_ptp_adjtime(struct ptp_clock_info *ptp, s64 delta)
160{
161 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
162 struct timespec64 now;
163
164 mutex_lock(&pf->tmreg_lock);
165
166 i40e_ptp_read(pf, &now);
167 timespec64_add_ns(&now, delta);
168 i40e_ptp_write(pf, (const struct timespec64 *)&now);
169
170 mutex_unlock(&pf->tmreg_lock);
171
172 return 0;
173}
174
175
176
177
178
179
180
181
182
183static int i40e_ptp_gettime(struct ptp_clock_info *ptp, struct timespec64 *ts)
184{
185 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
186
187 mutex_lock(&pf->tmreg_lock);
188 i40e_ptp_read(pf, ts);
189 mutex_unlock(&pf->tmreg_lock);
190
191 return 0;
192}
193
194
195
196
197
198
199
200
201
202static int i40e_ptp_settime(struct ptp_clock_info *ptp,
203 const struct timespec64 *ts)
204{
205 struct i40e_pf *pf = container_of(ptp, struct i40e_pf, ptp_caps);
206
207 mutex_lock(&pf->tmreg_lock);
208 i40e_ptp_write(pf, ts);
209 mutex_unlock(&pf->tmreg_lock);
210
211 return 0;
212}
213
214
215
216
217
218
219
220
221
222
223static int i40e_ptp_feature_enable(struct ptp_clock_info *ptp,
224 struct ptp_clock_request *rq, int on)
225{
226 return -EOPNOTSUPP;
227}
228
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239
240
241static u32 i40e_ptp_get_rx_events(struct i40e_pf *pf)
242{
243 struct i40e_hw *hw = &pf->hw;
244 u32 prttsyn_stat, new_latch_events;
245 int i;
246
247 prttsyn_stat = rd32(hw, I40E_PRTTSYN_STAT_1);
248 new_latch_events = prttsyn_stat & ~pf->latch_event_flags;
249
250
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253
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255
256
257
258
259 for (i = 0; i < 4; i++) {
260 if (new_latch_events & BIT(i))
261 pf->latch_events[i] = jiffies;
262 }
263
264
265 pf->latch_event_flags = prttsyn_stat;
266
267 return prttsyn_stat;
268}
269
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277
278
279
280void i40e_ptp_rx_hang(struct i40e_pf *pf)
281{
282 struct i40e_hw *hw = &pf->hw;
283 unsigned int i, cleared = 0;
284
285
286
287
288
289
290 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
291 return;
292
293 spin_lock_bh(&pf->ptp_rx_lock);
294
295
296 i40e_ptp_get_rx_events(pf);
297
298
299
300
301
302
303
304 for (i = 0; i < 4; i++) {
305 if ((pf->latch_event_flags & BIT(i)) &&
306 time_is_before_jiffies(pf->latch_events[i] + HZ)) {
307 rd32(hw, I40E_PRTTSYN_RXTIME_H(i));
308 pf->latch_event_flags &= ~BIT(i);
309 cleared++;
310 }
311 }
312
313 spin_unlock_bh(&pf->ptp_rx_lock);
314
315
316
317
318
319
320
321 if (cleared > 2)
322 dev_dbg(&pf->pdev->dev,
323 "Dropped %d missed RXTIME timestamp events\n",
324 cleared);
325
326
327 pf->rx_hwtstamp_cleared += cleared;
328}
329
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336
337
338
339void i40e_ptp_tx_hang(struct i40e_pf *pf)
340{
341 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
342 return;
343
344
345 if (!test_bit(__I40E_PTP_TX_IN_PROGRESS, pf->state))
346 return;
347
348
349
350
351
352 if (time_is_before_jiffies(pf->ptp_tx_start + HZ)) {
353 dev_kfree_skb_any(pf->ptp_tx_skb);
354 pf->ptp_tx_skb = NULL;
355 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
356 pf->tx_hwtstamp_timeouts++;
357 }
358}
359
360
361
362
363
364
365
366
367
368void i40e_ptp_tx_hwtstamp(struct i40e_pf *pf)
369{
370 struct skb_shared_hwtstamps shhwtstamps;
371 struct sk_buff *skb = pf->ptp_tx_skb;
372 struct i40e_hw *hw = &pf->hw;
373 u32 hi, lo;
374 u64 ns;
375
376 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_tx)
377 return;
378
379
380 if (!pf->ptp_tx_skb)
381 return;
382
383 lo = rd32(hw, I40E_PRTTSYN_TXTIME_L);
384 hi = rd32(hw, I40E_PRTTSYN_TXTIME_H);
385
386 ns = (((u64)hi) << 32) | lo;
387 i40e_ptp_convert_to_hwtstamp(&shhwtstamps, ns);
388
389
390
391
392
393
394 pf->ptp_tx_skb = NULL;
395 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
396
397
398 skb_tstamp_tx(skb, &shhwtstamps);
399 dev_kfree_skb_any(skb);
400}
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411
412
413
414void i40e_ptp_rx_hwtstamp(struct i40e_pf *pf, struct sk_buff *skb, u8 index)
415{
416 u32 prttsyn_stat, hi, lo;
417 struct i40e_hw *hw;
418 u64 ns;
419
420
421
422
423 if (!(pf->flags & I40E_FLAG_PTP) || !pf->ptp_rx)
424 return;
425
426 hw = &pf->hw;
427
428 spin_lock_bh(&pf->ptp_rx_lock);
429
430
431 prttsyn_stat = i40e_ptp_get_rx_events(pf);
432
433
434 if (!(prttsyn_stat & BIT(index))) {
435 spin_unlock_bh(&pf->ptp_rx_lock);
436 return;
437 }
438
439
440 pf->latch_event_flags &= ~BIT(index);
441
442 lo = rd32(hw, I40E_PRTTSYN_RXTIME_L(index));
443 hi = rd32(hw, I40E_PRTTSYN_RXTIME_H(index));
444
445 spin_unlock_bh(&pf->ptp_rx_lock);
446
447 ns = (((u64)hi) << 32) | lo;
448
449 i40e_ptp_convert_to_hwtstamp(skb_hwtstamps(skb), ns);
450}
451
452
453
454
455
456
457
458
459
460void i40e_ptp_set_increment(struct i40e_pf *pf)
461{
462 struct i40e_link_status *hw_link_info;
463 struct i40e_hw *hw = &pf->hw;
464 u64 incval;
465
466 hw_link_info = &hw->phy.link_info;
467
468 i40e_aq_get_link_info(&pf->hw, true, NULL, NULL);
469
470 switch (hw_link_info->link_speed) {
471 case I40E_LINK_SPEED_10GB:
472 incval = I40E_PTP_10GB_INCVAL;
473 break;
474 case I40E_LINK_SPEED_1GB:
475 incval = I40E_PTP_1GB_INCVAL;
476 break;
477 case I40E_LINK_SPEED_100MB:
478 {
479 static int warn_once;
480
481 if (!warn_once) {
482 dev_warn(&pf->pdev->dev,
483 "1588 functionality is not supported at 100 Mbps. Stopping the PHC.\n");
484 warn_once++;
485 }
486 incval = 0;
487 break;
488 }
489 case I40E_LINK_SPEED_40GB:
490 default:
491 incval = I40E_PTP_40GB_INCVAL;
492 break;
493 }
494
495
496
497
498
499 wr32(hw, I40E_PRTTSYN_INC_L, incval & 0xFFFFFFFF);
500 wr32(hw, I40E_PRTTSYN_INC_H, incval >> 32);
501
502
503 WRITE_ONCE(pf->ptp_base_adj, incval);
504 smp_mb();
505}
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514
515
516int i40e_ptp_get_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
517{
518 struct hwtstamp_config *config = &pf->tstamp_config;
519
520 if (!(pf->flags & I40E_FLAG_PTP))
521 return -EOPNOTSUPP;
522
523 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
524 -EFAULT : 0;
525}
526
527
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530
531
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535
536
537
538
539static int i40e_ptp_set_timestamp_mode(struct i40e_pf *pf,
540 struct hwtstamp_config *config)
541{
542 struct i40e_hw *hw = &pf->hw;
543 u32 tsyntype, regval;
544
545
546 if (config->flags)
547 return -EINVAL;
548
549 switch (config->tx_type) {
550 case HWTSTAMP_TX_OFF:
551 pf->ptp_tx = false;
552 break;
553 case HWTSTAMP_TX_ON:
554 pf->ptp_tx = true;
555 break;
556 default:
557 return -ERANGE;
558 }
559
560 switch (config->rx_filter) {
561 case HWTSTAMP_FILTER_NONE:
562 pf->ptp_rx = false;
563
564
565
566
567
568 tsyntype = I40E_PRTTSYN_CTL1_TSYNTYPE_V1;
569 break;
570 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
571 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
572 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
573 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
574 return -ERANGE;
575 pf->ptp_rx = true;
576 tsyntype = I40E_PRTTSYN_CTL1_V1MESSTYPE0_MASK |
577 I40E_PRTTSYN_CTL1_TSYNTYPE_V1 |
578 I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
579 config->rx_filter = HWTSTAMP_FILTER_PTP_V1_L4_EVENT;
580 break;
581 case HWTSTAMP_FILTER_PTP_V2_EVENT:
582 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
583 case HWTSTAMP_FILTER_PTP_V2_SYNC:
584 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
585 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
586 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
587 if (!(pf->hw_features & I40E_HW_PTP_L4_CAPABLE))
588 return -ERANGE;
589
590 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
591 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
592 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
593 pf->ptp_rx = true;
594 tsyntype = I40E_PRTTSYN_CTL1_V2MESSTYPE0_MASK |
595 I40E_PRTTSYN_CTL1_TSYNTYPE_V2;
596 if (pf->hw_features & I40E_HW_PTP_L4_CAPABLE) {
597 tsyntype |= I40E_PRTTSYN_CTL1_UDP_ENA_MASK;
598 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
599 } else {
600 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_L2_EVENT;
601 }
602 break;
603 case HWTSTAMP_FILTER_NTP_ALL:
604 case HWTSTAMP_FILTER_ALL:
605 default:
606 return -ERANGE;
607 }
608
609
610 spin_lock_bh(&pf->ptp_rx_lock);
611 rd32(hw, I40E_PRTTSYN_STAT_0);
612 rd32(hw, I40E_PRTTSYN_TXTIME_H);
613 rd32(hw, I40E_PRTTSYN_RXTIME_H(0));
614 rd32(hw, I40E_PRTTSYN_RXTIME_H(1));
615 rd32(hw, I40E_PRTTSYN_RXTIME_H(2));
616 rd32(hw, I40E_PRTTSYN_RXTIME_H(3));
617 pf->latch_event_flags = 0;
618 spin_unlock_bh(&pf->ptp_rx_lock);
619
620
621 regval = rd32(hw, I40E_PRTTSYN_CTL0);
622 if (pf->ptp_tx)
623 regval |= I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
624 else
625 regval &= ~I40E_PRTTSYN_CTL0_TXTIME_INT_ENA_MASK;
626 wr32(hw, I40E_PRTTSYN_CTL0, regval);
627
628 regval = rd32(hw, I40E_PFINT_ICR0_ENA);
629 if (pf->ptp_tx)
630 regval |= I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
631 else
632 regval &= ~I40E_PFINT_ICR0_ENA_TIMESYNC_MASK;
633 wr32(hw, I40E_PFINT_ICR0_ENA, regval);
634
635
636
637
638
639
640
641 regval = rd32(hw, I40E_PRTTSYN_CTL1);
642
643 regval &= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
644
645 regval |= tsyntype;
646 wr32(hw, I40E_PRTTSYN_CTL1, regval);
647
648 return 0;
649}
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665int i40e_ptp_set_ts_config(struct i40e_pf *pf, struct ifreq *ifr)
666{
667 struct hwtstamp_config config;
668 int err;
669
670 if (!(pf->flags & I40E_FLAG_PTP))
671 return -EOPNOTSUPP;
672
673 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
674 return -EFAULT;
675
676 err = i40e_ptp_set_timestamp_mode(pf, &config);
677 if (err)
678 return err;
679
680
681 pf->tstamp_config = config;
682
683 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
684 -EFAULT : 0;
685}
686
687
688
689
690
691
692
693
694
695
696
697static long i40e_ptp_create_clock(struct i40e_pf *pf)
698{
699
700 if (!IS_ERR_OR_NULL(pf->ptp_clock))
701 return 0;
702
703 strncpy(pf->ptp_caps.name, i40e_driver_name, sizeof(pf->ptp_caps.name));
704 pf->ptp_caps.owner = THIS_MODULE;
705 pf->ptp_caps.max_adj = 999999999;
706 pf->ptp_caps.n_ext_ts = 0;
707 pf->ptp_caps.pps = 0;
708 pf->ptp_caps.adjfreq = i40e_ptp_adjfreq;
709 pf->ptp_caps.adjtime = i40e_ptp_adjtime;
710 pf->ptp_caps.gettime64 = i40e_ptp_gettime;
711 pf->ptp_caps.settime64 = i40e_ptp_settime;
712 pf->ptp_caps.enable = i40e_ptp_feature_enable;
713
714
715 pf->ptp_clock = ptp_clock_register(&pf->ptp_caps, &pf->pdev->dev);
716 if (IS_ERR(pf->ptp_clock))
717 return PTR_ERR(pf->ptp_clock);
718
719
720
721
722
723 pf->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
724 pf->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
725
726 return 0;
727}
728
729
730
731
732
733
734
735
736
737void i40e_ptp_init(struct i40e_pf *pf)
738{
739 struct net_device *netdev = pf->vsi[pf->lan_vsi]->netdev;
740 struct i40e_hw *hw = &pf->hw;
741 u32 pf_id;
742 long err;
743
744
745
746
747 pf_id = (rd32(hw, I40E_PRTTSYN_CTL0) & I40E_PRTTSYN_CTL0_PF_ID_MASK) >>
748 I40E_PRTTSYN_CTL0_PF_ID_SHIFT;
749 if (hw->pf_id != pf_id) {
750 pf->flags &= ~I40E_FLAG_PTP;
751 dev_info(&pf->pdev->dev, "%s: PTP not supported on %s\n",
752 __func__,
753 netdev->name);
754 return;
755 }
756
757 mutex_init(&pf->tmreg_lock);
758 spin_lock_init(&pf->ptp_rx_lock);
759
760
761 err = i40e_ptp_create_clock(pf);
762 if (err) {
763 pf->ptp_clock = NULL;
764 dev_err(&pf->pdev->dev, "%s: ptp_clock_register failed\n",
765 __func__);
766 } else if (pf->ptp_clock) {
767 struct timespec64 ts;
768 u32 regval;
769
770 if (pf->hw.debug_mask & I40E_DEBUG_LAN)
771 dev_info(&pf->pdev->dev, "PHC enabled\n");
772 pf->flags |= I40E_FLAG_PTP;
773
774
775 regval = rd32(hw, I40E_PRTTSYN_CTL0);
776 regval |= I40E_PRTTSYN_CTL0_TSYNENA_MASK;
777 wr32(hw, I40E_PRTTSYN_CTL0, regval);
778 regval = rd32(hw, I40E_PRTTSYN_CTL1);
779 regval |= I40E_PRTTSYN_CTL1_TSYNENA_MASK;
780 wr32(hw, I40E_PRTTSYN_CTL1, regval);
781
782
783 i40e_ptp_set_increment(pf);
784
785
786 i40e_ptp_set_timestamp_mode(pf, &pf->tstamp_config);
787
788
789 ts = ktime_to_timespec64(ktime_get_real());
790 i40e_ptp_settime(&pf->ptp_caps, &ts);
791 }
792}
793
794
795
796
797
798
799
800
801void i40e_ptp_stop(struct i40e_pf *pf)
802{
803 pf->flags &= ~I40E_FLAG_PTP;
804 pf->ptp_tx = false;
805 pf->ptp_rx = false;
806
807 if (pf->ptp_tx_skb) {
808 dev_kfree_skb_any(pf->ptp_tx_skb);
809 pf->ptp_tx_skb = NULL;
810 clear_bit_unlock(__I40E_PTP_TX_IN_PROGRESS, pf->state);
811 }
812
813 if (pf->ptp_clock) {
814 ptp_clock_unregister(pf->ptp_clock);
815 pf->ptp_clock = NULL;
816 dev_info(&pf->pdev->dev, "%s: removed PHC on %s\n", __func__,
817 pf->vsi[pf->lan_vsi]->netdev->name);
818 }
819}
820