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19#include <linux/module.h>
20#include <linux/device.h>
21#include <linux/pci.h>
22#include <linux/ptp_classify.h>
23
24#include "igb.h"
25
26#define INCVALUE_MASK 0x7fffffff
27#define ISGN 0x80000000
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70
71#define IGB_SYSTIM_OVERFLOW_PERIOD (HZ * 60 * 9)
72#define IGB_PTP_TX_TIMEOUT (HZ * 15)
73#define INCPERIOD_82576 BIT(E1000_TIMINCA_16NS_SHIFT)
74#define INCVALUE_82576_MASK GENMASK(E1000_TIMINCA_16NS_SHIFT - 1, 0)
75#define INCVALUE_82576 (16u << IGB_82576_TSYNC_SHIFT)
76#define IGB_NBITS_82580 40
77
78static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter);
79
80
81static u64 igb_ptp_read_82576(const struct cyclecounter *cc)
82{
83 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
84 struct e1000_hw *hw = &igb->hw;
85 u64 val;
86 u32 lo, hi;
87
88 lo = rd32(E1000_SYSTIML);
89 hi = rd32(E1000_SYSTIMH);
90
91 val = ((u64) hi) << 32;
92 val |= lo;
93
94 return val;
95}
96
97
98static u64 igb_ptp_read_82580(const struct cyclecounter *cc)
99{
100 struct igb_adapter *igb = container_of(cc, struct igb_adapter, cc);
101 struct e1000_hw *hw = &igb->hw;
102 u32 lo, hi;
103 u64 val;
104
105
106
107
108
109 rd32(E1000_SYSTIMR);
110 lo = rd32(E1000_SYSTIML);
111 hi = rd32(E1000_SYSTIMH);
112
113 val = ((u64) hi) << 32;
114 val |= lo;
115
116 return val;
117}
118
119
120static void igb_ptp_read_i210(struct igb_adapter *adapter,
121 struct timespec64 *ts)
122{
123 struct e1000_hw *hw = &adapter->hw;
124 u32 sec, nsec;
125
126
127
128
129
130 rd32(E1000_SYSTIMR);
131 nsec = rd32(E1000_SYSTIML);
132 sec = rd32(E1000_SYSTIMH);
133
134 ts->tv_sec = sec;
135 ts->tv_nsec = nsec;
136}
137
138static void igb_ptp_write_i210(struct igb_adapter *adapter,
139 const struct timespec64 *ts)
140{
141 struct e1000_hw *hw = &adapter->hw;
142
143
144
145
146 wr32(E1000_SYSTIML, ts->tv_nsec);
147 wr32(E1000_SYSTIMH, (u32)ts->tv_sec);
148}
149
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164
165
166
167static void igb_ptp_systim_to_hwtstamp(struct igb_adapter *adapter,
168 struct skb_shared_hwtstamps *hwtstamps,
169 u64 systim)
170{
171 unsigned long flags;
172 u64 ns;
173
174 switch (adapter->hw.mac.type) {
175 case e1000_82576:
176 case e1000_82580:
177 case e1000_i354:
178 case e1000_i350:
179 spin_lock_irqsave(&adapter->tmreg_lock, flags);
180
181 ns = timecounter_cyc2time(&adapter->tc, systim);
182
183 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
184
185 memset(hwtstamps, 0, sizeof(*hwtstamps));
186 hwtstamps->hwtstamp = ns_to_ktime(ns);
187 break;
188 case e1000_i210:
189 case e1000_i211:
190 memset(hwtstamps, 0, sizeof(*hwtstamps));
191
192 hwtstamps->hwtstamp = ktime_set(systim >> 32,
193 systim & 0xFFFFFFFF);
194 break;
195 default:
196 break;
197 }
198}
199
200
201static int igb_ptp_adjfreq_82576(struct ptp_clock_info *ptp, s32 ppb)
202{
203 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
204 ptp_caps);
205 struct e1000_hw *hw = &igb->hw;
206 int neg_adj = 0;
207 u64 rate;
208 u32 incvalue;
209
210 if (ppb < 0) {
211 neg_adj = 1;
212 ppb = -ppb;
213 }
214 rate = ppb;
215 rate <<= 14;
216 rate = div_u64(rate, 1953125);
217
218 incvalue = 16 << IGB_82576_TSYNC_SHIFT;
219
220 if (neg_adj)
221 incvalue -= rate;
222 else
223 incvalue += rate;
224
225 wr32(E1000_TIMINCA, INCPERIOD_82576 | (incvalue & INCVALUE_82576_MASK));
226
227 return 0;
228}
229
230static int igb_ptp_adjfine_82580(struct ptp_clock_info *ptp, long scaled_ppm)
231{
232 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
233 ptp_caps);
234 struct e1000_hw *hw = &igb->hw;
235 int neg_adj = 0;
236 u64 rate;
237 u32 inca;
238
239 if (scaled_ppm < 0) {
240 neg_adj = 1;
241 scaled_ppm = -scaled_ppm;
242 }
243 rate = scaled_ppm;
244 rate <<= 13;
245 rate = div_u64(rate, 15625);
246
247 inca = rate & INCVALUE_MASK;
248 if (neg_adj)
249 inca |= ISGN;
250
251 wr32(E1000_TIMINCA, inca);
252
253 return 0;
254}
255
256static int igb_ptp_adjtime_82576(struct ptp_clock_info *ptp, s64 delta)
257{
258 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
259 ptp_caps);
260 unsigned long flags;
261
262 spin_lock_irqsave(&igb->tmreg_lock, flags);
263 timecounter_adjtime(&igb->tc, delta);
264 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
265
266 return 0;
267}
268
269static int igb_ptp_adjtime_i210(struct ptp_clock_info *ptp, s64 delta)
270{
271 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
272 ptp_caps);
273 unsigned long flags;
274 struct timespec64 now, then = ns_to_timespec64(delta);
275
276 spin_lock_irqsave(&igb->tmreg_lock, flags);
277
278 igb_ptp_read_i210(igb, &now);
279 now = timespec64_add(now, then);
280 igb_ptp_write_i210(igb, (const struct timespec64 *)&now);
281
282 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
283
284 return 0;
285}
286
287static int igb_ptp_gettime_82576(struct ptp_clock_info *ptp,
288 struct timespec64 *ts)
289{
290 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
291 ptp_caps);
292 unsigned long flags;
293 u64 ns;
294
295 spin_lock_irqsave(&igb->tmreg_lock, flags);
296
297 ns = timecounter_read(&igb->tc);
298
299 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
300
301 *ts = ns_to_timespec64(ns);
302
303 return 0;
304}
305
306static int igb_ptp_gettime_i210(struct ptp_clock_info *ptp,
307 struct timespec64 *ts)
308{
309 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
310 ptp_caps);
311 unsigned long flags;
312
313 spin_lock_irqsave(&igb->tmreg_lock, flags);
314
315 igb_ptp_read_i210(igb, ts);
316
317 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
318
319 return 0;
320}
321
322static int igb_ptp_settime_82576(struct ptp_clock_info *ptp,
323 const struct timespec64 *ts)
324{
325 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
326 ptp_caps);
327 unsigned long flags;
328 u64 ns;
329
330 ns = timespec64_to_ns(ts);
331
332 spin_lock_irqsave(&igb->tmreg_lock, flags);
333
334 timecounter_init(&igb->tc, &igb->cc, ns);
335
336 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
337
338 return 0;
339}
340
341static int igb_ptp_settime_i210(struct ptp_clock_info *ptp,
342 const struct timespec64 *ts)
343{
344 struct igb_adapter *igb = container_of(ptp, struct igb_adapter,
345 ptp_caps);
346 unsigned long flags;
347
348 spin_lock_irqsave(&igb->tmreg_lock, flags);
349
350 igb_ptp_write_i210(igb, ts);
351
352 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
353
354 return 0;
355}
356
357static void igb_pin_direction(int pin, int input, u32 *ctrl, u32 *ctrl_ext)
358{
359 u32 *ptr = pin < 2 ? ctrl : ctrl_ext;
360 static const u32 mask[IGB_N_SDP] = {
361 E1000_CTRL_SDP0_DIR,
362 E1000_CTRL_SDP1_DIR,
363 E1000_CTRL_EXT_SDP2_DIR,
364 E1000_CTRL_EXT_SDP3_DIR,
365 };
366
367 if (input)
368 *ptr &= ~mask[pin];
369 else
370 *ptr |= mask[pin];
371}
372
373static void igb_pin_extts(struct igb_adapter *igb, int chan, int pin)
374{
375 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
376 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
377 };
378 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
379 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
380 };
381 static const u32 ts_sdp_en[IGB_N_SDP] = {
382 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
383 };
384 struct e1000_hw *hw = &igb->hw;
385 u32 ctrl, ctrl_ext, tssdp = 0;
386
387 ctrl = rd32(E1000_CTRL);
388 ctrl_ext = rd32(E1000_CTRL_EXT);
389 tssdp = rd32(E1000_TSSDP);
390
391 igb_pin_direction(pin, 1, &ctrl, &ctrl_ext);
392
393
394 tssdp &= ~ts_sdp_en[pin];
395
396 if (chan == 1) {
397 tssdp &= ~AUX1_SEL_SDP3;
398 tssdp |= aux1_sel_sdp[pin] | AUX1_TS_SDP_EN;
399 } else {
400 tssdp &= ~AUX0_SEL_SDP3;
401 tssdp |= aux0_sel_sdp[pin] | AUX0_TS_SDP_EN;
402 }
403
404 wr32(E1000_TSSDP, tssdp);
405 wr32(E1000_CTRL, ctrl);
406 wr32(E1000_CTRL_EXT, ctrl_ext);
407}
408
409static void igb_pin_perout(struct igb_adapter *igb, int chan, int pin, int freq)
410{
411 static const u32 aux0_sel_sdp[IGB_N_SDP] = {
412 AUX0_SEL_SDP0, AUX0_SEL_SDP1, AUX0_SEL_SDP2, AUX0_SEL_SDP3,
413 };
414 static const u32 aux1_sel_sdp[IGB_N_SDP] = {
415 AUX1_SEL_SDP0, AUX1_SEL_SDP1, AUX1_SEL_SDP2, AUX1_SEL_SDP3,
416 };
417 static const u32 ts_sdp_en[IGB_N_SDP] = {
418 TS_SDP0_EN, TS_SDP1_EN, TS_SDP2_EN, TS_SDP3_EN,
419 };
420 static const u32 ts_sdp_sel_tt0[IGB_N_SDP] = {
421 TS_SDP0_SEL_TT0, TS_SDP1_SEL_TT0,
422 TS_SDP2_SEL_TT0, TS_SDP3_SEL_TT0,
423 };
424 static const u32 ts_sdp_sel_tt1[IGB_N_SDP] = {
425 TS_SDP0_SEL_TT1, TS_SDP1_SEL_TT1,
426 TS_SDP2_SEL_TT1, TS_SDP3_SEL_TT1,
427 };
428 static const u32 ts_sdp_sel_fc0[IGB_N_SDP] = {
429 TS_SDP0_SEL_FC0, TS_SDP1_SEL_FC0,
430 TS_SDP2_SEL_FC0, TS_SDP3_SEL_FC0,
431 };
432 static const u32 ts_sdp_sel_fc1[IGB_N_SDP] = {
433 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
434 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
435 };
436 static const u32 ts_sdp_sel_clr[IGB_N_SDP] = {
437 TS_SDP0_SEL_FC1, TS_SDP1_SEL_FC1,
438 TS_SDP2_SEL_FC1, TS_SDP3_SEL_FC1,
439 };
440 struct e1000_hw *hw = &igb->hw;
441 u32 ctrl, ctrl_ext, tssdp = 0;
442
443 ctrl = rd32(E1000_CTRL);
444 ctrl_ext = rd32(E1000_CTRL_EXT);
445 tssdp = rd32(E1000_TSSDP);
446
447 igb_pin_direction(pin, 0, &ctrl, &ctrl_ext);
448
449
450 if ((tssdp & AUX0_SEL_SDP3) == aux0_sel_sdp[pin])
451 tssdp &= ~AUX0_TS_SDP_EN;
452
453 if ((tssdp & AUX1_SEL_SDP3) == aux1_sel_sdp[pin])
454 tssdp &= ~AUX1_TS_SDP_EN;
455
456 tssdp &= ~ts_sdp_sel_clr[pin];
457 if (freq) {
458 if (chan == 1)
459 tssdp |= ts_sdp_sel_fc1[pin];
460 else
461 tssdp |= ts_sdp_sel_fc0[pin];
462 } else {
463 if (chan == 1)
464 tssdp |= ts_sdp_sel_tt1[pin];
465 else
466 tssdp |= ts_sdp_sel_tt0[pin];
467 }
468 tssdp |= ts_sdp_en[pin];
469
470 wr32(E1000_TSSDP, tssdp);
471 wr32(E1000_CTRL, ctrl);
472 wr32(E1000_CTRL_EXT, ctrl_ext);
473}
474
475static int igb_ptp_feature_enable_i210(struct ptp_clock_info *ptp,
476 struct ptp_clock_request *rq, int on)
477{
478 struct igb_adapter *igb =
479 container_of(ptp, struct igb_adapter, ptp_caps);
480 struct e1000_hw *hw = &igb->hw;
481 u32 tsauxc, tsim, tsauxc_mask, tsim_mask, trgttiml, trgttimh, freqout;
482 unsigned long flags;
483 struct timespec64 ts;
484 int use_freq = 0, pin = -1;
485 s64 ns;
486
487 switch (rq->type) {
488 case PTP_CLK_REQ_EXTTS:
489 if (on) {
490 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_EXTTS,
491 rq->extts.index);
492 if (pin < 0)
493 return -EBUSY;
494 }
495 if (rq->extts.index == 1) {
496 tsauxc_mask = TSAUXC_EN_TS1;
497 tsim_mask = TSINTR_AUTT1;
498 } else {
499 tsauxc_mask = TSAUXC_EN_TS0;
500 tsim_mask = TSINTR_AUTT0;
501 }
502 spin_lock_irqsave(&igb->tmreg_lock, flags);
503 tsauxc = rd32(E1000_TSAUXC);
504 tsim = rd32(E1000_TSIM);
505 if (on) {
506 igb_pin_extts(igb, rq->extts.index, pin);
507 tsauxc |= tsauxc_mask;
508 tsim |= tsim_mask;
509 } else {
510 tsauxc &= ~tsauxc_mask;
511 tsim &= ~tsim_mask;
512 }
513 wr32(E1000_TSAUXC, tsauxc);
514 wr32(E1000_TSIM, tsim);
515 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
516 return 0;
517
518 case PTP_CLK_REQ_PEROUT:
519 if (on) {
520 pin = ptp_find_pin(igb->ptp_clock, PTP_PF_PEROUT,
521 rq->perout.index);
522 if (pin < 0)
523 return -EBUSY;
524 }
525 ts.tv_sec = rq->perout.period.sec;
526 ts.tv_nsec = rq->perout.period.nsec;
527 ns = timespec64_to_ns(&ts);
528 ns = ns >> 1;
529 if (on && ((ns <= 70000000LL) || (ns == 125000000LL) ||
530 (ns == 250000000LL) || (ns == 500000000LL))) {
531 if (ns < 8LL)
532 return -EINVAL;
533 use_freq = 1;
534 }
535 ts = ns_to_timespec64(ns);
536 if (rq->perout.index == 1) {
537 if (use_freq) {
538 tsauxc_mask = TSAUXC_EN_CLK1 | TSAUXC_ST1;
539 tsim_mask = 0;
540 } else {
541 tsauxc_mask = TSAUXC_EN_TT1;
542 tsim_mask = TSINTR_TT1;
543 }
544 trgttiml = E1000_TRGTTIML1;
545 trgttimh = E1000_TRGTTIMH1;
546 freqout = E1000_FREQOUT1;
547 } else {
548 if (use_freq) {
549 tsauxc_mask = TSAUXC_EN_CLK0 | TSAUXC_ST0;
550 tsim_mask = 0;
551 } else {
552 tsauxc_mask = TSAUXC_EN_TT0;
553 tsim_mask = TSINTR_TT0;
554 }
555 trgttiml = E1000_TRGTTIML0;
556 trgttimh = E1000_TRGTTIMH0;
557 freqout = E1000_FREQOUT0;
558 }
559 spin_lock_irqsave(&igb->tmreg_lock, flags);
560 tsauxc = rd32(E1000_TSAUXC);
561 tsim = rd32(E1000_TSIM);
562 if (rq->perout.index == 1) {
563 tsauxc &= ~(TSAUXC_EN_TT1 | TSAUXC_EN_CLK1 | TSAUXC_ST1);
564 tsim &= ~TSINTR_TT1;
565 } else {
566 tsauxc &= ~(TSAUXC_EN_TT0 | TSAUXC_EN_CLK0 | TSAUXC_ST0);
567 tsim &= ~TSINTR_TT0;
568 }
569 if (on) {
570 int i = rq->perout.index;
571 igb_pin_perout(igb, i, pin, use_freq);
572 igb->perout[i].start.tv_sec = rq->perout.start.sec;
573 igb->perout[i].start.tv_nsec = rq->perout.start.nsec;
574 igb->perout[i].period.tv_sec = ts.tv_sec;
575 igb->perout[i].period.tv_nsec = ts.tv_nsec;
576 wr32(trgttimh, rq->perout.start.sec);
577 wr32(trgttiml, rq->perout.start.nsec);
578 if (use_freq)
579 wr32(freqout, ns);
580 tsauxc |= tsauxc_mask;
581 tsim |= tsim_mask;
582 }
583 wr32(E1000_TSAUXC, tsauxc);
584 wr32(E1000_TSIM, tsim);
585 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
586 return 0;
587
588 case PTP_CLK_REQ_PPS:
589 spin_lock_irqsave(&igb->tmreg_lock, flags);
590 tsim = rd32(E1000_TSIM);
591 if (on)
592 tsim |= TSINTR_SYS_WRAP;
593 else
594 tsim &= ~TSINTR_SYS_WRAP;
595 igb->pps_sys_wrap_on = !!on;
596 wr32(E1000_TSIM, tsim);
597 spin_unlock_irqrestore(&igb->tmreg_lock, flags);
598 return 0;
599 }
600
601 return -EOPNOTSUPP;
602}
603
604static int igb_ptp_feature_enable(struct ptp_clock_info *ptp,
605 struct ptp_clock_request *rq, int on)
606{
607 return -EOPNOTSUPP;
608}
609
610static int igb_ptp_verify_pin(struct ptp_clock_info *ptp, unsigned int pin,
611 enum ptp_pin_function func, unsigned int chan)
612{
613 switch (func) {
614 case PTP_PF_NONE:
615 case PTP_PF_EXTTS:
616 case PTP_PF_PEROUT:
617 break;
618 case PTP_PF_PHYSYNC:
619 return -1;
620 }
621 return 0;
622}
623
624
625
626
627
628
629
630
631static void igb_ptp_tx_work(struct work_struct *work)
632{
633 struct igb_adapter *adapter = container_of(work, struct igb_adapter,
634 ptp_tx_work);
635 struct e1000_hw *hw = &adapter->hw;
636 u32 tsynctxctl;
637
638 if (!adapter->ptp_tx_skb)
639 return;
640
641 if (time_is_before_jiffies(adapter->ptp_tx_start +
642 IGB_PTP_TX_TIMEOUT)) {
643 dev_kfree_skb_any(adapter->ptp_tx_skb);
644 adapter->ptp_tx_skb = NULL;
645 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
646 adapter->tx_hwtstamp_timeouts++;
647
648
649
650 rd32(E1000_TXSTMPH);
651 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
652 return;
653 }
654
655 tsynctxctl = rd32(E1000_TSYNCTXCTL);
656 if (tsynctxctl & E1000_TSYNCTXCTL_VALID)
657 igb_ptp_tx_hwtstamp(adapter);
658 else
659
660 schedule_work(&adapter->ptp_tx_work);
661}
662
663static void igb_ptp_overflow_check(struct work_struct *work)
664{
665 struct igb_adapter *igb =
666 container_of(work, struct igb_adapter, ptp_overflow_work.work);
667 struct timespec64 ts;
668
669 igb->ptp_caps.gettime64(&igb->ptp_caps, &ts);
670
671 pr_debug("igb overflow check at %lld.%09lu\n",
672 (long long) ts.tv_sec, ts.tv_nsec);
673
674 schedule_delayed_work(&igb->ptp_overflow_work,
675 IGB_SYSTIM_OVERFLOW_PERIOD);
676}
677
678
679
680
681
682
683
684
685
686
687void igb_ptp_rx_hang(struct igb_adapter *adapter)
688{
689 struct e1000_hw *hw = &adapter->hw;
690 u32 tsyncrxctl = rd32(E1000_TSYNCRXCTL);
691 unsigned long rx_event;
692
693
694 if (hw->mac.type != e1000_82576)
695 return;
696
697
698
699
700 if (!(tsyncrxctl & E1000_TSYNCRXCTL_VALID)) {
701 adapter->last_rx_ptp_check = jiffies;
702 return;
703 }
704
705
706 rx_event = adapter->last_rx_ptp_check;
707 if (time_after(adapter->last_rx_timestamp, rx_event))
708 rx_event = adapter->last_rx_timestamp;
709
710
711 if (time_is_before_jiffies(rx_event + 5 * HZ)) {
712 rd32(E1000_RXSTMPH);
713 adapter->last_rx_ptp_check = jiffies;
714 adapter->rx_hwtstamp_cleared++;
715 dev_warn(&adapter->pdev->dev, "clearing Rx timestamp hang\n");
716 }
717}
718
719
720
721
722
723void igb_ptp_tx_hang(struct igb_adapter *adapter)
724{
725 struct e1000_hw *hw = &adapter->hw;
726 bool timeout = time_is_before_jiffies(adapter->ptp_tx_start +
727 IGB_PTP_TX_TIMEOUT);
728
729 if (!adapter->ptp_tx_skb)
730 return;
731
732 if (!test_bit(__IGB_PTP_TX_IN_PROGRESS, &adapter->state))
733 return;
734
735
736
737
738
739 if (timeout) {
740 cancel_work_sync(&adapter->ptp_tx_work);
741 dev_kfree_skb_any(adapter->ptp_tx_skb);
742 adapter->ptp_tx_skb = NULL;
743 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
744 adapter->tx_hwtstamp_timeouts++;
745
746
747
748 rd32(E1000_TXSTMPH);
749 dev_warn(&adapter->pdev->dev, "clearing Tx timestamp hang\n");
750 }
751}
752
753
754
755
756
757
758
759
760
761static void igb_ptp_tx_hwtstamp(struct igb_adapter *adapter)
762{
763 struct sk_buff *skb = adapter->ptp_tx_skb;
764 struct e1000_hw *hw = &adapter->hw;
765 struct skb_shared_hwtstamps shhwtstamps;
766 u64 regval;
767 int adjust = 0;
768
769 regval = rd32(E1000_TXSTMPL);
770 regval |= (u64)rd32(E1000_TXSTMPH) << 32;
771
772 igb_ptp_systim_to_hwtstamp(adapter, &shhwtstamps, regval);
773
774 if (adapter->hw.mac.type == e1000_i210) {
775 switch (adapter->link_speed) {
776 case SPEED_10:
777 adjust = IGB_I210_TX_LATENCY_10;
778 break;
779 case SPEED_100:
780 adjust = IGB_I210_TX_LATENCY_100;
781 break;
782 case SPEED_1000:
783 adjust = IGB_I210_TX_LATENCY_1000;
784 break;
785 }
786 }
787
788 shhwtstamps.hwtstamp =
789 ktime_add_ns(shhwtstamps.hwtstamp, adjust);
790
791
792
793
794
795
796 adapter->ptp_tx_skb = NULL;
797 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
798
799
800 skb_tstamp_tx(skb, &shhwtstamps);
801 dev_kfree_skb_any(skb);
802}
803
804
805
806
807
808
809
810
811
812
813
814void igb_ptp_rx_pktstamp(struct igb_q_vector *q_vector, void *va,
815 struct sk_buff *skb)
816{
817 __le64 *regval = (__le64 *)va;
818 struct igb_adapter *adapter = q_vector->adapter;
819 int adjust = 0;
820
821
822
823
824
825 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb),
826 le64_to_cpu(regval[1]));
827
828
829 if (adapter->hw.mac.type == e1000_i210) {
830 switch (adapter->link_speed) {
831 case SPEED_10:
832 adjust = IGB_I210_RX_LATENCY_10;
833 break;
834 case SPEED_100:
835 adjust = IGB_I210_RX_LATENCY_100;
836 break;
837 case SPEED_1000:
838 adjust = IGB_I210_RX_LATENCY_1000;
839 break;
840 }
841 }
842 skb_hwtstamps(skb)->hwtstamp =
843 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
844}
845
846
847
848
849
850
851
852
853
854void igb_ptp_rx_rgtstamp(struct igb_q_vector *q_vector,
855 struct sk_buff *skb)
856{
857 struct igb_adapter *adapter = q_vector->adapter;
858 struct e1000_hw *hw = &adapter->hw;
859 u64 regval;
860 int adjust = 0;
861
862
863
864
865
866
867
868
869
870
871
872 if (!(rd32(E1000_TSYNCRXCTL) & E1000_TSYNCRXCTL_VALID))
873 return;
874
875 regval = rd32(E1000_RXSTMPL);
876 regval |= (u64)rd32(E1000_RXSTMPH) << 32;
877
878 igb_ptp_systim_to_hwtstamp(adapter, skb_hwtstamps(skb), regval);
879
880
881 if (adapter->hw.mac.type == e1000_i210) {
882 switch (adapter->link_speed) {
883 case SPEED_10:
884 adjust = IGB_I210_RX_LATENCY_10;
885 break;
886 case SPEED_100:
887 adjust = IGB_I210_RX_LATENCY_100;
888 break;
889 case SPEED_1000:
890 adjust = IGB_I210_RX_LATENCY_1000;
891 break;
892 }
893 }
894 skb_hwtstamps(skb)->hwtstamp =
895 ktime_sub_ns(skb_hwtstamps(skb)->hwtstamp, adjust);
896
897
898
899
900 adapter->last_rx_timestamp = jiffies;
901}
902
903
904
905
906
907
908
909
910
911
912int igb_ptp_get_ts_config(struct net_device *netdev, struct ifreq *ifr)
913{
914 struct igb_adapter *adapter = netdev_priv(netdev);
915 struct hwtstamp_config *config = &adapter->tstamp_config;
916
917 return copy_to_user(ifr->ifr_data, config, sizeof(*config)) ?
918 -EFAULT : 0;
919}
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938static int igb_ptp_set_timestamp_mode(struct igb_adapter *adapter,
939 struct hwtstamp_config *config)
940{
941 struct e1000_hw *hw = &adapter->hw;
942 u32 tsync_tx_ctl = E1000_TSYNCTXCTL_ENABLED;
943 u32 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
944 u32 tsync_rx_cfg = 0;
945 bool is_l4 = false;
946 bool is_l2 = false;
947 u32 regval;
948
949
950 if (config->flags)
951 return -EINVAL;
952
953 switch (config->tx_type) {
954 case HWTSTAMP_TX_OFF:
955 tsync_tx_ctl = 0;
956 case HWTSTAMP_TX_ON:
957 break;
958 default:
959 return -ERANGE;
960 }
961
962 switch (config->rx_filter) {
963 case HWTSTAMP_FILTER_NONE:
964 tsync_rx_ctl = 0;
965 break;
966 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
967 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
968 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_SYNC_MESSAGE;
969 is_l4 = true;
970 break;
971 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
972 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_L4_V1;
973 tsync_rx_cfg = E1000_TSYNCRXCFG_PTP_V1_DELAY_REQ_MESSAGE;
974 is_l4 = true;
975 break;
976 case HWTSTAMP_FILTER_PTP_V2_EVENT:
977 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
978 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
979 case HWTSTAMP_FILTER_PTP_V2_SYNC:
980 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
981 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
982 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
983 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
984 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
985 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_EVENT_V2;
986 config->rx_filter = HWTSTAMP_FILTER_PTP_V2_EVENT;
987 is_l2 = true;
988 is_l4 = true;
989 break;
990 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
991 case HWTSTAMP_FILTER_NTP_ALL:
992 case HWTSTAMP_FILTER_ALL:
993
994
995
996 if (hw->mac.type != e1000_82576) {
997 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
998 config->rx_filter = HWTSTAMP_FILTER_ALL;
999 break;
1000 }
1001
1002 default:
1003 config->rx_filter = HWTSTAMP_FILTER_NONE;
1004 return -ERANGE;
1005 }
1006
1007 if (hw->mac.type == e1000_82575) {
1008 if (tsync_rx_ctl | tsync_tx_ctl)
1009 return -EINVAL;
1010 return 0;
1011 }
1012
1013
1014
1015
1016
1017 if ((hw->mac.type >= e1000_82580) && tsync_rx_ctl) {
1018 tsync_rx_ctl = E1000_TSYNCRXCTL_ENABLED;
1019 tsync_rx_ctl |= E1000_TSYNCRXCTL_TYPE_ALL;
1020 config->rx_filter = HWTSTAMP_FILTER_ALL;
1021 is_l2 = true;
1022 is_l4 = true;
1023
1024 if ((hw->mac.type == e1000_i210) ||
1025 (hw->mac.type == e1000_i211)) {
1026 regval = rd32(E1000_RXPBS);
1027 regval |= E1000_RXPBS_CFG_TS_EN;
1028 wr32(E1000_RXPBS, regval);
1029 }
1030 }
1031
1032
1033 regval = rd32(E1000_TSYNCTXCTL);
1034 regval &= ~E1000_TSYNCTXCTL_ENABLED;
1035 regval |= tsync_tx_ctl;
1036 wr32(E1000_TSYNCTXCTL, regval);
1037
1038
1039 regval = rd32(E1000_TSYNCRXCTL);
1040 regval &= ~(E1000_TSYNCRXCTL_ENABLED | E1000_TSYNCRXCTL_TYPE_MASK);
1041 regval |= tsync_rx_ctl;
1042 wr32(E1000_TSYNCRXCTL, regval);
1043
1044
1045 wr32(E1000_TSYNCRXCFG, tsync_rx_cfg);
1046
1047
1048 if (is_l2)
1049 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588),
1050 (E1000_ETQF_FILTER_ENABLE |
1051 E1000_ETQF_1588 |
1052 ETH_P_1588));
1053 else
1054 wr32(E1000_ETQF(IGB_ETQF_FILTER_1588), 0);
1055
1056
1057 if (is_l4) {
1058 u32 ftqf = (IPPROTO_UDP
1059 | E1000_FTQF_VF_BP
1060 | E1000_FTQF_1588_TIME_STAMP
1061 | E1000_FTQF_MASK);
1062 ftqf &= ~E1000_FTQF_MASK_PROTO_BP;
1063
1064 wr32(E1000_IMIR(3), htons(PTP_EV_PORT));
1065 wr32(E1000_IMIREXT(3),
1066 (E1000_IMIREXT_SIZE_BP | E1000_IMIREXT_CTRL_BP));
1067 if (hw->mac.type == e1000_82576) {
1068
1069 wr32(E1000_SPQF(3), htons(PTP_EV_PORT));
1070 ftqf &= ~E1000_FTQF_MASK_SOURCE_PORT_BP;
1071 }
1072 wr32(E1000_FTQF(3), ftqf);
1073 } else {
1074 wr32(E1000_FTQF(3), E1000_FTQF_MASK);
1075 }
1076 wrfl();
1077
1078
1079 regval = rd32(E1000_TXSTMPL);
1080 regval = rd32(E1000_TXSTMPH);
1081 regval = rd32(E1000_RXSTMPL);
1082 regval = rd32(E1000_RXSTMPH);
1083
1084 return 0;
1085}
1086
1087
1088
1089
1090
1091
1092
1093int igb_ptp_set_ts_config(struct net_device *netdev, struct ifreq *ifr)
1094{
1095 struct igb_adapter *adapter = netdev_priv(netdev);
1096 struct hwtstamp_config config;
1097 int err;
1098
1099 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
1100 return -EFAULT;
1101
1102 err = igb_ptp_set_timestamp_mode(adapter, &config);
1103 if (err)
1104 return err;
1105
1106
1107 memcpy(&adapter->tstamp_config, &config,
1108 sizeof(adapter->tstamp_config));
1109
1110 return copy_to_user(ifr->ifr_data, &config, sizeof(config)) ?
1111 -EFAULT : 0;
1112}
1113
1114
1115
1116
1117
1118
1119
1120
1121void igb_ptp_init(struct igb_adapter *adapter)
1122{
1123 struct e1000_hw *hw = &adapter->hw;
1124 struct net_device *netdev = adapter->netdev;
1125 int i;
1126
1127 switch (hw->mac.type) {
1128 case e1000_82576:
1129 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1130 adapter->ptp_caps.owner = THIS_MODULE;
1131 adapter->ptp_caps.max_adj = 999999881;
1132 adapter->ptp_caps.n_ext_ts = 0;
1133 adapter->ptp_caps.pps = 0;
1134 adapter->ptp_caps.adjfreq = igb_ptp_adjfreq_82576;
1135 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1136 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1137 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1138 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1139 adapter->cc.read = igb_ptp_read_82576;
1140 adapter->cc.mask = CYCLECOUNTER_MASK(64);
1141 adapter->cc.mult = 1;
1142 adapter->cc.shift = IGB_82576_TSYNC_SHIFT;
1143 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1144 break;
1145 case e1000_82580:
1146 case e1000_i354:
1147 case e1000_i350:
1148 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1149 adapter->ptp_caps.owner = THIS_MODULE;
1150 adapter->ptp_caps.max_adj = 62499999;
1151 adapter->ptp_caps.n_ext_ts = 0;
1152 adapter->ptp_caps.pps = 0;
1153 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1154 adapter->ptp_caps.adjtime = igb_ptp_adjtime_82576;
1155 adapter->ptp_caps.gettime64 = igb_ptp_gettime_82576;
1156 adapter->ptp_caps.settime64 = igb_ptp_settime_82576;
1157 adapter->ptp_caps.enable = igb_ptp_feature_enable;
1158 adapter->cc.read = igb_ptp_read_82580;
1159 adapter->cc.mask = CYCLECOUNTER_MASK(IGB_NBITS_82580);
1160 adapter->cc.mult = 1;
1161 adapter->cc.shift = 0;
1162 adapter->ptp_flags |= IGB_PTP_OVERFLOW_CHECK;
1163 break;
1164 case e1000_i210:
1165 case e1000_i211:
1166 for (i = 0; i < IGB_N_SDP; i++) {
1167 struct ptp_pin_desc *ppd = &adapter->sdp_config[i];
1168
1169 snprintf(ppd->name, sizeof(ppd->name), "SDP%d", i);
1170 ppd->index = i;
1171 ppd->func = PTP_PF_NONE;
1172 }
1173 snprintf(adapter->ptp_caps.name, 16, "%pm", netdev->dev_addr);
1174 adapter->ptp_caps.owner = THIS_MODULE;
1175 adapter->ptp_caps.max_adj = 62499999;
1176 adapter->ptp_caps.n_ext_ts = IGB_N_EXTTS;
1177 adapter->ptp_caps.n_per_out = IGB_N_PEROUT;
1178 adapter->ptp_caps.n_pins = IGB_N_SDP;
1179 adapter->ptp_caps.pps = 1;
1180 adapter->ptp_caps.pin_config = adapter->sdp_config;
1181 adapter->ptp_caps.adjfine = igb_ptp_adjfine_82580;
1182 adapter->ptp_caps.adjtime = igb_ptp_adjtime_i210;
1183 adapter->ptp_caps.gettime64 = igb_ptp_gettime_i210;
1184 adapter->ptp_caps.settime64 = igb_ptp_settime_i210;
1185 adapter->ptp_caps.enable = igb_ptp_feature_enable_i210;
1186 adapter->ptp_caps.verify = igb_ptp_verify_pin;
1187 break;
1188 default:
1189 adapter->ptp_clock = NULL;
1190 return;
1191 }
1192
1193 spin_lock_init(&adapter->tmreg_lock);
1194 INIT_WORK(&adapter->ptp_tx_work, igb_ptp_tx_work);
1195
1196 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1197 INIT_DELAYED_WORK(&adapter->ptp_overflow_work,
1198 igb_ptp_overflow_check);
1199
1200 adapter->tstamp_config.rx_filter = HWTSTAMP_FILTER_NONE;
1201 adapter->tstamp_config.tx_type = HWTSTAMP_TX_OFF;
1202
1203 igb_ptp_reset(adapter);
1204
1205 adapter->ptp_clock = ptp_clock_register(&adapter->ptp_caps,
1206 &adapter->pdev->dev);
1207 if (IS_ERR(adapter->ptp_clock)) {
1208 adapter->ptp_clock = NULL;
1209 dev_err(&adapter->pdev->dev, "ptp_clock_register failed\n");
1210 } else if (adapter->ptp_clock) {
1211 dev_info(&adapter->pdev->dev, "added PHC on %s\n",
1212 adapter->netdev->name);
1213 adapter->ptp_flags |= IGB_PTP_ENABLED;
1214 }
1215}
1216
1217
1218
1219
1220
1221
1222
1223
1224void igb_ptp_suspend(struct igb_adapter *adapter)
1225{
1226 if (!(adapter->ptp_flags & IGB_PTP_ENABLED))
1227 return;
1228
1229 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1230 cancel_delayed_work_sync(&adapter->ptp_overflow_work);
1231
1232 cancel_work_sync(&adapter->ptp_tx_work);
1233 if (adapter->ptp_tx_skb) {
1234 dev_kfree_skb_any(adapter->ptp_tx_skb);
1235 adapter->ptp_tx_skb = NULL;
1236 clear_bit_unlock(__IGB_PTP_TX_IN_PROGRESS, &adapter->state);
1237 }
1238}
1239
1240
1241
1242
1243
1244
1245
1246void igb_ptp_stop(struct igb_adapter *adapter)
1247{
1248 igb_ptp_suspend(adapter);
1249
1250 if (adapter->ptp_clock) {
1251 ptp_clock_unregister(adapter->ptp_clock);
1252 dev_info(&adapter->pdev->dev, "removed PHC on %s\n",
1253 adapter->netdev->name);
1254 adapter->ptp_flags &= ~IGB_PTP_ENABLED;
1255 }
1256}
1257
1258
1259
1260
1261
1262
1263
1264void igb_ptp_reset(struct igb_adapter *adapter)
1265{
1266 struct e1000_hw *hw = &adapter->hw;
1267 unsigned long flags;
1268
1269
1270 igb_ptp_set_timestamp_mode(adapter, &adapter->tstamp_config);
1271
1272 spin_lock_irqsave(&adapter->tmreg_lock, flags);
1273
1274 switch (adapter->hw.mac.type) {
1275 case e1000_82576:
1276
1277 wr32(E1000_TIMINCA, INCPERIOD_82576 | INCVALUE_82576);
1278 break;
1279 case e1000_82580:
1280 case e1000_i354:
1281 case e1000_i350:
1282 case e1000_i210:
1283 case e1000_i211:
1284 wr32(E1000_TSAUXC, 0x0);
1285 wr32(E1000_TSSDP, 0x0);
1286 wr32(E1000_TSIM,
1287 TSYNC_INTERRUPTS |
1288 (adapter->pps_sys_wrap_on ? TSINTR_SYS_WRAP : 0));
1289 wr32(E1000_IMS, E1000_IMS_TS);
1290 break;
1291 default:
1292
1293 goto out;
1294 }
1295
1296
1297 if ((hw->mac.type == e1000_i210) || (hw->mac.type == e1000_i211)) {
1298 struct timespec64 ts = ktime_to_timespec64(ktime_get_real());
1299
1300 igb_ptp_write_i210(adapter, &ts);
1301 } else {
1302 timecounter_init(&adapter->tc, &adapter->cc,
1303 ktime_to_ns(ktime_get_real()));
1304 }
1305out:
1306 spin_unlock_irqrestore(&adapter->tmreg_lock, flags);
1307
1308 wrfl();
1309
1310 if (adapter->ptp_flags & IGB_PTP_OVERFLOW_CHECK)
1311 schedule_delayed_work(&adapter->ptp_overflow_work,
1312 IGB_SYSTIM_OVERFLOW_PERIOD);
1313}
1314