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36#include <linux/module.h>
37#include <linux/kernel.h>
38#include <linux/init.h>
39#include <linux/errno.h>
40#include <linux/pci.h>
41#include <linux/dma-mapping.h>
42#include <linux/slab.h>
43#include <linux/io-mapping.h>
44#include <linux/delay.h>
45#include <linux/kmod.h>
46#include <linux/etherdevice.h>
47#include <net/devlink.h>
48
49#include <uapi/rdma/mlx4-abi.h>
50#include <linux/mlx4/device.h>
51#include <linux/mlx4/doorbell.h>
52
53#include "mlx4.h"
54#include "fw.h"
55#include "icm.h"
56
57MODULE_AUTHOR("Roland Dreier");
58MODULE_DESCRIPTION("Mellanox ConnectX HCA low-level driver");
59MODULE_LICENSE("Dual BSD/GPL");
60MODULE_VERSION(DRV_VERSION);
61
62struct workqueue_struct *mlx4_wq;
63
64#ifdef CONFIG_MLX4_DEBUG
65
66int mlx4_debug_level = 0;
67module_param_named(debug_level, mlx4_debug_level, int, 0644);
68MODULE_PARM_DESC(debug_level, "Enable debug tracing if > 0");
69
70#endif
71
72#ifdef CONFIG_PCI_MSI
73
74static int msi_x = 1;
75module_param(msi_x, int, 0444);
76MODULE_PARM_DESC(msi_x, "attempt to use MSI-X if nonzero");
77
78#else
79
80#define msi_x (0)
81
82#endif
83
84static uint8_t num_vfs[3] = {0, 0, 0};
85static int num_vfs_argc;
86module_param_array(num_vfs, byte , &num_vfs_argc, 0444);
87MODULE_PARM_DESC(num_vfs, "enable #num_vfs functions if num_vfs > 0\n"
88 "num_vfs=port1,port2,port1+2");
89
90static uint8_t probe_vf[3] = {0, 0, 0};
91static int probe_vfs_argc;
92module_param_array(probe_vf, byte, &probe_vfs_argc, 0444);
93MODULE_PARM_DESC(probe_vf, "number of vfs to probe by pf driver (num_vfs > 0)\n"
94 "probe_vf=port1,port2,port1+2");
95
96static int mlx4_log_num_mgm_entry_size = MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
97module_param_named(log_num_mgm_entry_size,
98 mlx4_log_num_mgm_entry_size, int, 0444);
99MODULE_PARM_DESC(log_num_mgm_entry_size, "log mgm size, that defines the num"
100 " of qp per mcg, for example:"
101 " 10 gives 248.range: 7 <="
102 " log_num_mgm_entry_size <= 12."
103 " To activate device managed"
104 " flow steering when available, set to -1");
105
106static bool enable_64b_cqe_eqe = true;
107module_param(enable_64b_cqe_eqe, bool, 0444);
108MODULE_PARM_DESC(enable_64b_cqe_eqe,
109 "Enable 64 byte CQEs/EQEs when the FW supports this (default: True)");
110
111static bool enable_4k_uar;
112module_param(enable_4k_uar, bool, 0444);
113MODULE_PARM_DESC(enable_4k_uar,
114 "Enable using 4K UAR. Should not be enabled if have VFs which do not support 4K UARs (default: false)");
115
116#define PF_CONTEXT_BEHAVIOUR_MASK (MLX4_FUNC_CAP_64B_EQE_CQE | \
117 MLX4_FUNC_CAP_EQE_CQE_STRIDE | \
118 MLX4_FUNC_CAP_DMFS_A0_STATIC)
119
120#define RESET_PERSIST_MASK_FLAGS (MLX4_FLAG_SRIOV)
121
122static char mlx4_version[] =
123 DRV_NAME ": Mellanox ConnectX core driver v"
124 DRV_VERSION "\n";
125
126static const struct mlx4_profile default_profile = {
127 .num_qp = 1 << 18,
128 .num_srq = 1 << 16,
129 .rdmarc_per_qp = 1 << 4,
130 .num_cq = 1 << 16,
131 .num_mcg = 1 << 13,
132 .num_mpt = 1 << 19,
133 .num_mtt = 1 << 20,
134};
135
136static const struct mlx4_profile low_mem_profile = {
137 .num_qp = 1 << 17,
138 .num_srq = 1 << 6,
139 .rdmarc_per_qp = 1 << 4,
140 .num_cq = 1 << 8,
141 .num_mcg = 1 << 8,
142 .num_mpt = 1 << 9,
143 .num_mtt = 1 << 7,
144};
145
146static int log_num_mac = 7;
147module_param_named(log_num_mac, log_num_mac, int, 0444);
148MODULE_PARM_DESC(log_num_mac, "Log2 max number of MACs per ETH port (1-7)");
149
150static int log_num_vlan;
151module_param_named(log_num_vlan, log_num_vlan, int, 0444);
152MODULE_PARM_DESC(log_num_vlan, "Log2 max number of VLANs per ETH port (0-7)");
153
154#define MLX4_LOG_NUM_VLANS 7
155#define MLX4_MIN_LOG_NUM_VLANS 0
156#define MLX4_MIN_LOG_NUM_MAC 1
157
158static bool use_prio;
159module_param_named(use_prio, use_prio, bool, 0444);
160MODULE_PARM_DESC(use_prio, "Enable steering by VLAN priority on ETH ports (deprecated)");
161
162int log_mtts_per_seg = ilog2(MLX4_MTT_ENTRY_PER_SEG);
163module_param_named(log_mtts_per_seg, log_mtts_per_seg, int, 0444);
164MODULE_PARM_DESC(log_mtts_per_seg, "Log2 number of MTT entries per segment (1-7)");
165
166static int port_type_array[2] = {MLX4_PORT_TYPE_NONE, MLX4_PORT_TYPE_NONE};
167static int arr_argc = 2;
168module_param_array(port_type_array, int, &arr_argc, 0444);
169MODULE_PARM_DESC(port_type_array, "Array of port types: HW_DEFAULT (0) is default "
170 "1 for IB, 2 for Ethernet");
171
172struct mlx4_port_config {
173 struct list_head list;
174 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1];
175 struct pci_dev *pdev;
176};
177
178static atomic_t pf_loading = ATOMIC_INIT(0);
179
180static inline void mlx4_set_num_reserved_uars(struct mlx4_dev *dev,
181 struct mlx4_dev_cap *dev_cap)
182{
183
184
185
186
187 dev->caps.reserved_uars =
188 max_t(int,
189 mlx4_get_num_reserved_uar(dev),
190 dev_cap->reserved_uars /
191 (1 << (PAGE_SHIFT - dev->uar_page_shift)));
192}
193
194int mlx4_check_port_params(struct mlx4_dev *dev,
195 enum mlx4_port_type *port_type)
196{
197 int i;
198
199 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP)) {
200 for (i = 0; i < dev->caps.num_ports - 1; i++) {
201 if (port_type[i] != port_type[i + 1]) {
202 mlx4_err(dev, "Only same port types supported on this HCA, aborting\n");
203 return -EINVAL;
204 }
205 }
206 }
207
208 for (i = 0; i < dev->caps.num_ports; i++) {
209 if (!(port_type[i] & dev->caps.supported_type[i+1])) {
210 mlx4_err(dev, "Requested port type for port %d is not supported on this HCA\n",
211 i + 1);
212 return -EINVAL;
213 }
214 }
215 return 0;
216}
217
218static void mlx4_set_port_mask(struct mlx4_dev *dev)
219{
220 int i;
221
222 for (i = 1; i <= dev->caps.num_ports; ++i)
223 dev->caps.port_mask[i] = dev->caps.port_type[i];
224}
225
226enum {
227 MLX4_QUERY_FUNC_NUM_SYS_EQS = 1 << 0,
228};
229
230static int mlx4_query_func(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
231{
232 int err = 0;
233 struct mlx4_func func;
234
235 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
236 err = mlx4_QUERY_FUNC(dev, &func, 0);
237 if (err) {
238 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
239 return err;
240 }
241 dev_cap->max_eqs = func.max_eq;
242 dev_cap->reserved_eqs = func.rsvd_eqs;
243 dev_cap->reserved_uars = func.rsvd_uars;
244 err |= MLX4_QUERY_FUNC_NUM_SYS_EQS;
245 }
246 return err;
247}
248
249static void mlx4_enable_cqe_eqe_stride(struct mlx4_dev *dev)
250{
251 struct mlx4_caps *dev_cap = &dev->caps;
252
253
254 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) ||
255 !(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE))
256 return;
257
258
259
260
261 if (!(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_EQE) ||
262 !(dev_cap->flags & MLX4_DEV_CAP_FLAG_64B_CQE)) {
263 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
264 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
265 return;
266 }
267
268 if (cache_line_size() == 128 || cache_line_size() == 256) {
269 mlx4_dbg(dev, "Enabling CQE stride cacheLine supported\n");
270
271 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
272 dev_cap->flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
273
274 if (mlx4_is_master(dev))
275 dev_cap->function_caps |= MLX4_FUNC_CAP_EQE_CQE_STRIDE;
276 } else {
277 if (cache_line_size() != 32 && cache_line_size() != 64)
278 mlx4_dbg(dev, "Disabling CQE stride, cacheLine size unsupported\n");
279 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
280 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
281 }
282}
283
284static int _mlx4_dev_port(struct mlx4_dev *dev, int port,
285 struct mlx4_port_cap *port_cap)
286{
287 dev->caps.vl_cap[port] = port_cap->max_vl;
288 dev->caps.ib_mtu_cap[port] = port_cap->ib_mtu;
289 dev->phys_caps.gid_phys_table_len[port] = port_cap->max_gids;
290 dev->phys_caps.pkey_phys_table_len[port] = port_cap->max_pkeys;
291
292
293
294 dev->caps.gid_table_len[port] = port_cap->max_gids;
295 dev->caps.pkey_table_len[port] = port_cap->max_pkeys;
296 dev->caps.port_width_cap[port] = port_cap->max_port_width;
297 dev->caps.eth_mtu_cap[port] = port_cap->eth_mtu;
298 dev->caps.max_tc_eth = port_cap->max_tc_eth;
299 dev->caps.def_mac[port] = port_cap->def_mac;
300 dev->caps.supported_type[port] = port_cap->supported_port_types;
301 dev->caps.suggested_type[port] = port_cap->suggested_type;
302 dev->caps.default_sense[port] = port_cap->default_sense;
303 dev->caps.trans_type[port] = port_cap->trans_type;
304 dev->caps.vendor_oui[port] = port_cap->vendor_oui;
305 dev->caps.wavelength[port] = port_cap->wavelength;
306 dev->caps.trans_code[port] = port_cap->trans_code;
307
308 return 0;
309}
310
311static int mlx4_dev_port(struct mlx4_dev *dev, int port,
312 struct mlx4_port_cap *port_cap)
313{
314 int err = 0;
315
316 err = mlx4_QUERY_PORT(dev, port, port_cap);
317
318 if (err)
319 mlx4_err(dev, "QUERY_PORT command failed.\n");
320
321 return err;
322}
323
324static inline void mlx4_enable_ignore_fcs(struct mlx4_dev *dev)
325{
326 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_IGNORE_FCS))
327 return;
328
329 if (mlx4_is_mfunc(dev)) {
330 mlx4_dbg(dev, "SRIOV mode - Disabling Ignore FCS");
331 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
332 return;
333 }
334
335 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_FCS_KEEP)) {
336 mlx4_dbg(dev,
337 "Keep FCS is not supported - Disabling Ignore FCS");
338 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_IGNORE_FCS;
339 return;
340 }
341}
342
343#define MLX4_A0_STEERING_TABLE_SIZE 256
344static int mlx4_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap)
345{
346 int err;
347 int i;
348
349 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
350 if (err) {
351 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
352 return err;
353 }
354 mlx4_dev_cap_dump(dev, dev_cap);
355
356 if (dev_cap->min_page_sz > PAGE_SIZE) {
357 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
358 dev_cap->min_page_sz, PAGE_SIZE);
359 return -ENODEV;
360 }
361 if (dev_cap->num_ports > MLX4_MAX_PORTS) {
362 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
363 dev_cap->num_ports, MLX4_MAX_PORTS);
364 return -ENODEV;
365 }
366
367 if (dev_cap->uar_size > pci_resource_len(dev->persist->pdev, 2)) {
368 mlx4_err(dev, "HCA reported UAR size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
369 dev_cap->uar_size,
370 (unsigned long long)
371 pci_resource_len(dev->persist->pdev, 2));
372 return -ENODEV;
373 }
374
375 dev->caps.num_ports = dev_cap->num_ports;
376 dev->caps.num_sys_eqs = dev_cap->num_sys_eqs;
377 dev->phys_caps.num_phys_eqs = dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS ?
378 dev->caps.num_sys_eqs :
379 MLX4_MAX_EQ_NUM;
380 for (i = 1; i <= dev->caps.num_ports; ++i) {
381 err = _mlx4_dev_port(dev, i, dev_cap->port_cap + i);
382 if (err) {
383 mlx4_err(dev, "QUERY_PORT command failed, aborting\n");
384 return err;
385 }
386 }
387
388 dev->caps.uar_page_size = PAGE_SIZE;
389 dev->caps.num_uars = dev_cap->uar_size / PAGE_SIZE;
390 dev->caps.local_ca_ack_delay = dev_cap->local_ca_ack_delay;
391 dev->caps.bf_reg_size = dev_cap->bf_reg_size;
392 dev->caps.bf_regs_per_page = dev_cap->bf_regs_per_page;
393 dev->caps.max_sq_sg = dev_cap->max_sq_sg;
394 dev->caps.max_rq_sg = dev_cap->max_rq_sg;
395 dev->caps.max_wqes = dev_cap->max_qp_sz;
396 dev->caps.max_qp_init_rdma = dev_cap->max_requester_per_qp;
397 dev->caps.max_srq_wqes = dev_cap->max_srq_sz;
398 dev->caps.max_srq_sge = dev_cap->max_rq_sg - 1;
399 dev->caps.reserved_srqs = dev_cap->reserved_srqs;
400 dev->caps.max_sq_desc_sz = dev_cap->max_sq_desc_sz;
401 dev->caps.max_rq_desc_sz = dev_cap->max_rq_desc_sz;
402
403
404
405
406
407 dev->caps.max_cqes = dev_cap->max_cq_sz - 1;
408 dev->caps.reserved_cqs = dev_cap->reserved_cqs;
409 dev->caps.reserved_eqs = dev_cap->reserved_eqs;
410 dev->caps.reserved_mtts = dev_cap->reserved_mtts;
411 dev->caps.reserved_mrws = dev_cap->reserved_mrws;
412
413 dev->caps.reserved_pds = dev_cap->reserved_pds;
414 dev->caps.reserved_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
415 dev_cap->reserved_xrcds : 0;
416 dev->caps.max_xrcds = (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) ?
417 dev_cap->max_xrcds : 0;
418 dev->caps.mtt_entry_sz = dev_cap->mtt_entry_sz;
419
420 dev->caps.max_msg_sz = dev_cap->max_msg_sz;
421 dev->caps.page_size_cap = ~(u32) (dev_cap->min_page_sz - 1);
422 dev->caps.flags = dev_cap->flags;
423 dev->caps.flags2 = dev_cap->flags2;
424 dev->caps.bmme_flags = dev_cap->bmme_flags;
425 dev->caps.reserved_lkey = dev_cap->reserved_lkey;
426 dev->caps.stat_rate_support = dev_cap->stat_rate_support;
427 dev->caps.max_gso_sz = dev_cap->max_gso_sz;
428 dev->caps.max_rss_tbl_sz = dev_cap->max_rss_tbl_sz;
429 dev->caps.wol_port[1] = dev_cap->wol_port[1];
430 dev->caps.wol_port[2] = dev_cap->wol_port[2];
431
432
433 if (!mlx4_is_slave(dev)) {
434
435
436
437 if (enable_4k_uar || !dev->persist->num_vfs)
438 dev->uar_page_shift = DEFAULT_UAR_PAGE_SHIFT;
439 else
440 dev->uar_page_shift = PAGE_SHIFT;
441
442 mlx4_set_num_reserved_uars(dev, dev_cap);
443 }
444
445 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN) {
446 struct mlx4_init_hca_param hca_param;
447
448 memset(&hca_param, 0, sizeof(hca_param));
449 err = mlx4_QUERY_HCA(dev, &hca_param);
450
451
452
453
454
455
456 if (err || hca_param.phv_check_en)
457 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_PHV_EN;
458 }
459
460
461 if (mlx4_priv(dev)->pci_dev_data & MLX4_PCI_DEV_FORCE_SENSE_PORT)
462 dev->caps.flags |= MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
463
464 if (mlx4_is_mfunc(dev))
465 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_SENSE_SUPPORT;
466
467 if (mlx4_low_memory_profile()) {
468 dev->caps.log_num_macs = MLX4_MIN_LOG_NUM_MAC;
469 dev->caps.log_num_vlans = MLX4_MIN_LOG_NUM_VLANS;
470 } else {
471 dev->caps.log_num_macs = log_num_mac;
472 dev->caps.log_num_vlans = MLX4_LOG_NUM_VLANS;
473 }
474
475 for (i = 1; i <= dev->caps.num_ports; ++i) {
476 dev->caps.port_type[i] = MLX4_PORT_TYPE_NONE;
477 if (dev->caps.supported_type[i]) {
478
479 if (dev->caps.supported_type[i] == MLX4_PORT_TYPE_ETH)
480 dev->caps.port_type[i] = MLX4_PORT_TYPE_ETH;
481
482 else if (dev->caps.supported_type[i] ==
483 MLX4_PORT_TYPE_IB)
484 dev->caps.port_type[i] = MLX4_PORT_TYPE_IB;
485 else {
486
487
488
489 if (port_type_array[i - 1] == MLX4_PORT_TYPE_NONE)
490 dev->caps.port_type[i] = dev->caps.suggested_type[i] ?
491 MLX4_PORT_TYPE_ETH : MLX4_PORT_TYPE_IB;
492 else
493 dev->caps.port_type[i] = port_type_array[i - 1];
494 }
495 }
496
497
498
499
500
501
502 mlx4_priv(dev)->sense.sense_allowed[i] =
503 ((dev->caps.supported_type[i] == MLX4_PORT_TYPE_AUTO) &&
504 (dev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
505 (dev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT));
506
507
508
509
510
511
512 if (mlx4_priv(dev)->sense.sense_allowed[i] && dev->caps.default_sense[i]) {
513 enum mlx4_port_type sensed_port = MLX4_PORT_TYPE_NONE;
514 dev->caps.possible_type[i] = MLX4_PORT_TYPE_AUTO;
515 mlx4_SENSE_PORT(dev, i, &sensed_port);
516 if (sensed_port != MLX4_PORT_TYPE_NONE)
517 dev->caps.port_type[i] = sensed_port;
518 } else {
519 dev->caps.possible_type[i] = dev->caps.port_type[i];
520 }
521
522 if (dev->caps.log_num_macs > dev_cap->port_cap[i].log_max_macs) {
523 dev->caps.log_num_macs = dev_cap->port_cap[i].log_max_macs;
524 mlx4_warn(dev, "Requested number of MACs is too much for port %d, reducing to %d\n",
525 i, 1 << dev->caps.log_num_macs);
526 }
527 if (dev->caps.log_num_vlans > dev_cap->port_cap[i].log_max_vlans) {
528 dev->caps.log_num_vlans = dev_cap->port_cap[i].log_max_vlans;
529 mlx4_warn(dev, "Requested number of VLANs is too much for port %d, reducing to %d\n",
530 i, 1 << dev->caps.log_num_vlans);
531 }
532 }
533
534 if (mlx4_is_master(dev) && (dev->caps.num_ports == 2) &&
535 (port_type_array[0] == MLX4_PORT_TYPE_IB) &&
536 (port_type_array[1] == MLX4_PORT_TYPE_ETH)) {
537 mlx4_warn(dev,
538 "Granular QoS per VF not supported with IB/Eth configuration\n");
539 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_QOS_VPP;
540 }
541
542 dev->caps.max_counters = dev_cap->max_counters;
543
544 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] = dev_cap->reserved_qps;
545 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] =
546 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] =
547 (1 << dev->caps.log_num_macs) *
548 (1 << dev->caps.log_num_vlans) *
549 dev->caps.num_ports;
550 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH] = MLX4_NUM_FEXCH;
551
552 if (dev_cap->dmfs_high_rate_qpn_base > 0 &&
553 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN)
554 dev->caps.dmfs_high_rate_qpn_base = dev_cap->dmfs_high_rate_qpn_base;
555 else
556 dev->caps.dmfs_high_rate_qpn_base =
557 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
558
559 if (dev_cap->dmfs_high_rate_qpn_range > 0 &&
560 dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN) {
561 dev->caps.dmfs_high_rate_qpn_range = dev_cap->dmfs_high_rate_qpn_range;
562 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DEFAULT;
563 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_FS_A0;
564 } else {
565 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_NOT_SUPPORTED;
566 dev->caps.dmfs_high_rate_qpn_base =
567 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
568 dev->caps.dmfs_high_rate_qpn_range = MLX4_A0_STEERING_TABLE_SIZE;
569 }
570
571 dev->caps.rl_caps = dev_cap->rl_caps;
572
573 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_RSS_RAW_ETH] =
574 dev->caps.dmfs_high_rate_qpn_range;
575
576 dev->caps.reserved_qps = dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW] +
577 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_ETH_ADDR] +
578 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_ADDR] +
579 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FC_EXCH];
580
581 dev->caps.sqp_demux = (mlx4_is_master(dev)) ? MLX4_MAX_NUM_SLAVES : 0;
582
583 if (!enable_64b_cqe_eqe && !mlx4_is_slave(dev)) {
584 if (dev_cap->flags &
585 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) {
586 mlx4_warn(dev, "64B EQEs/CQEs supported by the device but not enabled\n");
587 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_CQE;
588 dev->caps.flags &= ~MLX4_DEV_CAP_FLAG_64B_EQE;
589 }
590
591 if (dev_cap->flags2 &
592 (MLX4_DEV_CAP_FLAG2_CQE_STRIDE |
593 MLX4_DEV_CAP_FLAG2_EQE_STRIDE)) {
594 mlx4_warn(dev, "Disabling EQE/CQE stride per user request\n");
595 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_CQE_STRIDE;
596 dev_cap->flags2 &= ~MLX4_DEV_CAP_FLAG2_EQE_STRIDE;
597 }
598 }
599
600 if ((dev->caps.flags &
601 (MLX4_DEV_CAP_FLAG_64B_CQE | MLX4_DEV_CAP_FLAG_64B_EQE)) &&
602 mlx4_is_master(dev))
603 dev->caps.function_caps |= MLX4_FUNC_CAP_64B_EQE_CQE;
604
605 if (!mlx4_is_slave(dev)) {
606 mlx4_enable_cqe_eqe_stride(dev);
607 dev->caps.alloc_res_qp_mask =
608 (dev->caps.bf_reg_size ? MLX4_RESERVE_ETH_BF_QP : 0) |
609 MLX4_RESERVE_A0_QP;
610
611 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG) &&
612 dev->caps.flags & MLX4_DEV_CAP_FLAG_SET_ETH_SCHED) {
613 mlx4_warn(dev, "Old device ETS support detected\n");
614 mlx4_warn(dev, "Consider upgrading device FW.\n");
615 dev->caps.flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG;
616 }
617
618 } else {
619 dev->caps.alloc_res_qp_mask = 0;
620 }
621
622 mlx4_enable_ignore_fcs(dev);
623
624 return 0;
625}
626
627
628static int mlx4_how_many_lives_vf(struct mlx4_dev *dev)
629{
630 struct mlx4_priv *priv = mlx4_priv(dev);
631 struct mlx4_slave_state *s_state;
632 int i;
633 int ret = 0;
634
635 for (i = 1; i < dev->num_slaves; ++i) {
636 s_state = &priv->mfunc.master.slave_state[i];
637 if (s_state->active && s_state->last_cmd !=
638 MLX4_COMM_CMD_RESET) {
639 mlx4_warn(dev, "%s: slave: %d is still active\n",
640 __func__, i);
641 ret++;
642 }
643 }
644 return ret;
645}
646
647int mlx4_get_parav_qkey(struct mlx4_dev *dev, u32 qpn, u32 *qkey)
648{
649 u32 qk = MLX4_RESERVED_QKEY_BASE;
650
651 if (qpn >= dev->phys_caps.base_tunnel_sqpn + 8 * MLX4_MFUNC_MAX ||
652 qpn < dev->phys_caps.base_proxy_sqpn)
653 return -EINVAL;
654
655 if (qpn >= dev->phys_caps.base_tunnel_sqpn)
656
657 qk += qpn - dev->phys_caps.base_tunnel_sqpn;
658 else
659 qk += qpn - dev->phys_caps.base_proxy_sqpn;
660 *qkey = qk;
661 return 0;
662}
663EXPORT_SYMBOL(mlx4_get_parav_qkey);
664
665void mlx4_sync_pkey_table(struct mlx4_dev *dev, int slave, int port, int i, int val)
666{
667 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
668
669 if (!mlx4_is_master(dev))
670 return;
671
672 priv->virt2phys_pkey[slave][port - 1][i] = val;
673}
674EXPORT_SYMBOL(mlx4_sync_pkey_table);
675
676void mlx4_put_slave_node_guid(struct mlx4_dev *dev, int slave, __be64 guid)
677{
678 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
679
680 if (!mlx4_is_master(dev))
681 return;
682
683 priv->slave_node_guids[slave] = guid;
684}
685EXPORT_SYMBOL(mlx4_put_slave_node_guid);
686
687__be64 mlx4_get_slave_node_guid(struct mlx4_dev *dev, int slave)
688{
689 struct mlx4_priv *priv = container_of(dev, struct mlx4_priv, dev);
690
691 if (!mlx4_is_master(dev))
692 return 0;
693
694 return priv->slave_node_guids[slave];
695}
696EXPORT_SYMBOL(mlx4_get_slave_node_guid);
697
698int mlx4_is_slave_active(struct mlx4_dev *dev, int slave)
699{
700 struct mlx4_priv *priv = mlx4_priv(dev);
701 struct mlx4_slave_state *s_slave;
702
703 if (!mlx4_is_master(dev))
704 return 0;
705
706 s_slave = &priv->mfunc.master.slave_state[slave];
707 return !!s_slave->active;
708}
709EXPORT_SYMBOL(mlx4_is_slave_active);
710
711void mlx4_handle_eth_header_mcast_prio(struct mlx4_net_trans_rule_hw_ctrl *ctrl,
712 struct _rule_hw *eth_header)
713{
714 if (is_multicast_ether_addr(eth_header->eth.dst_mac) ||
715 is_broadcast_ether_addr(eth_header->eth.dst_mac)) {
716 struct mlx4_net_trans_rule_hw_eth *eth =
717 (struct mlx4_net_trans_rule_hw_eth *)eth_header;
718 struct _rule_hw *next_rule = (struct _rule_hw *)(eth + 1);
719 bool last_rule = next_rule->size == 0 && next_rule->id == 0 &&
720 next_rule->rsvd == 0;
721
722 if (last_rule)
723 ctrl->prio = cpu_to_be16(MLX4_DOMAIN_NIC);
724 }
725}
726EXPORT_SYMBOL(mlx4_handle_eth_header_mcast_prio);
727
728static void slave_adjust_steering_mode(struct mlx4_dev *dev,
729 struct mlx4_dev_cap *dev_cap,
730 struct mlx4_init_hca_param *hca_param)
731{
732 dev->caps.steering_mode = hca_param->steering_mode;
733 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) {
734 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
735 dev->caps.fs_log_max_ucast_qp_range_size =
736 dev_cap->fs_log_max_ucast_qp_range_size;
737 } else
738 dev->caps.num_qp_per_mgm =
739 4 * ((1 << hca_param->log_mc_entry_sz)/16 - 2);
740
741 mlx4_dbg(dev, "Steering mode is: %s\n",
742 mlx4_steering_mode_str(dev->caps.steering_mode));
743}
744
745static void mlx4_slave_destroy_special_qp_cap(struct mlx4_dev *dev)
746{
747 kfree(dev->caps.spec_qps);
748 dev->caps.spec_qps = NULL;
749}
750
751static int mlx4_slave_special_qp_cap(struct mlx4_dev *dev)
752{
753 struct mlx4_func_cap *func_cap = NULL;
754 struct mlx4_caps *caps = &dev->caps;
755 int i, err = 0;
756
757 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
758 caps->spec_qps = kcalloc(caps->num_ports, sizeof(*caps->spec_qps), GFP_KERNEL);
759
760 if (!func_cap || !caps->spec_qps) {
761 mlx4_err(dev, "Failed to allocate memory for special qps cap\n");
762 err = -ENOMEM;
763 goto err_mem;
764 }
765
766 for (i = 1; i <= caps->num_ports; ++i) {
767 err = mlx4_QUERY_FUNC_CAP(dev, i, func_cap);
768 if (err) {
769 mlx4_err(dev, "QUERY_FUNC_CAP port command failed for port %d, aborting (%d)\n",
770 i, err);
771 goto err_mem;
772 }
773 caps->spec_qps[i - 1] = func_cap->spec_qps;
774 caps->port_mask[i] = caps->port_type[i];
775 caps->phys_port_id[i] = func_cap->phys_port_id;
776 err = mlx4_get_slave_pkey_gid_tbl_len(dev, i,
777 &caps->gid_table_len[i],
778 &caps->pkey_table_len[i]);
779 if (err) {
780 mlx4_err(dev, "QUERY_PORT command failed for port %d, aborting (%d)\n",
781 i, err);
782 goto err_mem;
783 }
784 }
785
786err_mem:
787 if (err)
788 mlx4_slave_destroy_special_qp_cap(dev);
789 kfree(func_cap);
790 return err;
791}
792
793static int mlx4_slave_cap(struct mlx4_dev *dev)
794{
795 int err;
796 u32 page_size;
797 struct mlx4_dev_cap *dev_cap = NULL;
798 struct mlx4_func_cap *func_cap = NULL;
799 struct mlx4_init_hca_param *hca_param = NULL;
800
801 hca_param = kzalloc(sizeof(*hca_param), GFP_KERNEL);
802 func_cap = kzalloc(sizeof(*func_cap), GFP_KERNEL);
803 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
804 if (!hca_param || !func_cap || !dev_cap) {
805 mlx4_err(dev, "Failed to allocate memory for slave_cap\n");
806 err = -ENOMEM;
807 goto free_mem;
808 }
809
810 err = mlx4_QUERY_HCA(dev, hca_param);
811 if (err) {
812 mlx4_err(dev, "QUERY_HCA command failed, aborting\n");
813 goto free_mem;
814 }
815
816
817
818
819 if (hca_param->global_caps) {
820 mlx4_err(dev, "Unknown hca global capabilities\n");
821 err = -EINVAL;
822 goto free_mem;
823 }
824
825 dev->caps.hca_core_clock = hca_param->hca_core_clock;
826
827 dev->caps.max_qp_dest_rdma = 1 << hca_param->log_rd_per_qp;
828 err = mlx4_dev_cap(dev, dev_cap);
829 if (err) {
830 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
831 goto free_mem;
832 }
833
834 err = mlx4_QUERY_FW(dev);
835 if (err)
836 mlx4_err(dev, "QUERY_FW command failed: could not get FW version\n");
837
838 page_size = ~dev->caps.page_size_cap + 1;
839 mlx4_warn(dev, "HCA minimum page size:%d\n", page_size);
840 if (page_size > PAGE_SIZE) {
841 mlx4_err(dev, "HCA minimum page size of %d bigger than kernel PAGE_SIZE of %ld, aborting\n",
842 page_size, PAGE_SIZE);
843 err = -ENODEV;
844 goto free_mem;
845 }
846
847
848 dev->uar_page_shift = hca_param->uar_page_sz + 12;
849
850
851 if (dev->uar_page_shift > PAGE_SHIFT) {
852 mlx4_err(dev,
853 "Invalid configuration: uar page size is larger than system page size\n");
854 err = -ENODEV;
855 goto free_mem;
856 }
857
858
859 mlx4_set_num_reserved_uars(dev, dev_cap);
860
861
862
863
864
865 dev->caps.uar_page_size = PAGE_SIZE;
866
867 err = mlx4_QUERY_FUNC_CAP(dev, 0, func_cap);
868 if (err) {
869 mlx4_err(dev, "QUERY_FUNC_CAP general command failed, aborting (%d)\n",
870 err);
871 goto free_mem;
872 }
873
874 if ((func_cap->pf_context_behaviour | PF_CONTEXT_BEHAVIOUR_MASK) !=
875 PF_CONTEXT_BEHAVIOUR_MASK) {
876 mlx4_err(dev, "Unknown pf context behaviour %x known flags %x\n",
877 func_cap->pf_context_behaviour,
878 PF_CONTEXT_BEHAVIOUR_MASK);
879 err = -EINVAL;
880 goto free_mem;
881 }
882
883 dev->caps.num_ports = func_cap->num_ports;
884 dev->quotas.qp = func_cap->qp_quota;
885 dev->quotas.srq = func_cap->srq_quota;
886 dev->quotas.cq = func_cap->cq_quota;
887 dev->quotas.mpt = func_cap->mpt_quota;
888 dev->quotas.mtt = func_cap->mtt_quota;
889 dev->caps.num_qps = 1 << hca_param->log_num_qps;
890 dev->caps.num_srqs = 1 << hca_param->log_num_srqs;
891 dev->caps.num_cqs = 1 << hca_param->log_num_cqs;
892 dev->caps.num_mpts = 1 << hca_param->log_mpt_sz;
893 dev->caps.num_eqs = func_cap->max_eq;
894 dev->caps.reserved_eqs = func_cap->reserved_eq;
895 dev->caps.reserved_lkey = func_cap->reserved_lkey;
896 dev->caps.num_pds = MLX4_NUM_PDS;
897 dev->caps.num_mgms = 0;
898 dev->caps.num_amgms = 0;
899
900 if (dev->caps.num_ports > MLX4_MAX_PORTS) {
901 mlx4_err(dev, "HCA has %d ports, but we only support %d, aborting\n",
902 dev->caps.num_ports, MLX4_MAX_PORTS);
903 err = -ENODEV;
904 goto free_mem;
905 }
906
907 mlx4_replace_zero_macs(dev);
908
909 err = mlx4_slave_special_qp_cap(dev);
910 if (err) {
911 mlx4_err(dev, "Set special QP caps failed. aborting\n");
912 goto free_mem;
913 }
914
915 if (dev->caps.uar_page_size * (dev->caps.num_uars -
916 dev->caps.reserved_uars) >
917 pci_resource_len(dev->persist->pdev,
918 2)) {
919 mlx4_err(dev, "HCA reported UAR region size of 0x%x bigger than PCI resource 2 size of 0x%llx, aborting\n",
920 dev->caps.uar_page_size * dev->caps.num_uars,
921 (unsigned long long)
922 pci_resource_len(dev->persist->pdev, 2));
923 err = -ENOMEM;
924 goto err_mem;
925 }
926
927 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_EQE_ENABLED) {
928 dev->caps.eqe_size = 64;
929 dev->caps.eqe_factor = 1;
930 } else {
931 dev->caps.eqe_size = 32;
932 dev->caps.eqe_factor = 0;
933 }
934
935 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_64B_CQE_ENABLED) {
936 dev->caps.cqe_size = 64;
937 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
938 } else {
939 dev->caps.cqe_size = 32;
940 }
941
942 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_EQE_STRIDE_ENABLED) {
943 dev->caps.eqe_size = hca_param->eqe_size;
944 dev->caps.eqe_factor = 0;
945 }
946
947 if (hca_param->dev_cap_enabled & MLX4_DEV_CAP_CQE_STRIDE_ENABLED) {
948 dev->caps.cqe_size = hca_param->cqe_size;
949
950 dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE;
951 }
952
953 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
954 mlx4_warn(dev, "Timestamping is not supported in slave mode\n");
955
956 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_USER_MAC_EN;
957 mlx4_dbg(dev, "User MAC FW update is not supported in slave mode\n");
958
959 slave_adjust_steering_mode(dev, dev_cap, hca_param);
960 mlx4_dbg(dev, "RSS support for IP fragments is %s\n",
961 hca_param->rss_ip_frags ? "on" : "off");
962
963 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_BF_RES_QP &&
964 dev->caps.bf_reg_size)
965 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_ETH_BF_QP;
966
967 if (func_cap->extra_flags & MLX4_QUERY_FUNC_FLAGS_A0_RES_QP)
968 dev->caps.alloc_res_qp_mask |= MLX4_RESERVE_A0_QP;
969
970err_mem:
971 if (err)
972 mlx4_slave_destroy_special_qp_cap(dev);
973free_mem:
974 kfree(hca_param);
975 kfree(func_cap);
976 kfree(dev_cap);
977 return err;
978}
979
980static void mlx4_request_modules(struct mlx4_dev *dev)
981{
982 int port;
983 int has_ib_port = false;
984 int has_eth_port = false;
985#define EN_DRV_NAME "mlx4_en"
986#define IB_DRV_NAME "mlx4_ib"
987
988 for (port = 1; port <= dev->caps.num_ports; port++) {
989 if (dev->caps.port_type[port] == MLX4_PORT_TYPE_IB)
990 has_ib_port = true;
991 else if (dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH)
992 has_eth_port = true;
993 }
994
995 if (has_eth_port)
996 request_module_nowait(EN_DRV_NAME);
997 if (has_ib_port || (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE))
998 request_module_nowait(IB_DRV_NAME);
999}
1000
1001
1002
1003
1004
1005int mlx4_change_port_types(struct mlx4_dev *dev,
1006 enum mlx4_port_type *port_types)
1007{
1008 int err = 0;
1009 int change = 0;
1010 int port;
1011
1012 for (port = 0; port < dev->caps.num_ports; port++) {
1013
1014
1015 if (port_types[port] != dev->caps.port_type[port + 1])
1016 change = 1;
1017 }
1018 if (change) {
1019 mlx4_unregister_device(dev);
1020 for (port = 1; port <= dev->caps.num_ports; port++) {
1021 mlx4_CLOSE_PORT(dev, port);
1022 dev->caps.port_type[port] = port_types[port - 1];
1023 err = mlx4_SET_PORT(dev, port, -1);
1024 if (err) {
1025 mlx4_err(dev, "Failed to set port %d, aborting\n",
1026 port);
1027 goto out;
1028 }
1029 }
1030 mlx4_set_port_mask(dev);
1031 err = mlx4_register_device(dev);
1032 if (err) {
1033 mlx4_err(dev, "Failed to register device\n");
1034 goto out;
1035 }
1036 mlx4_request_modules(dev);
1037 }
1038
1039out:
1040 return err;
1041}
1042
1043static ssize_t show_port_type(struct device *dev,
1044 struct device_attribute *attr,
1045 char *buf)
1046{
1047 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1048 port_attr);
1049 struct mlx4_dev *mdev = info->dev;
1050 char type[8];
1051
1052 sprintf(type, "%s",
1053 (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_IB) ?
1054 "ib" : "eth");
1055 if (mdev->caps.possible_type[info->port] == MLX4_PORT_TYPE_AUTO)
1056 sprintf(buf, "auto (%s)\n", type);
1057 else
1058 sprintf(buf, "%s\n", type);
1059
1060 return strlen(buf);
1061}
1062
1063static int __set_port_type(struct mlx4_port_info *info,
1064 enum mlx4_port_type port_type)
1065{
1066 struct mlx4_dev *mdev = info->dev;
1067 struct mlx4_priv *priv = mlx4_priv(mdev);
1068 enum mlx4_port_type types[MLX4_MAX_PORTS];
1069 enum mlx4_port_type new_types[MLX4_MAX_PORTS];
1070 int i;
1071 int err = 0;
1072
1073 if ((port_type & mdev->caps.supported_type[info->port]) != port_type) {
1074 mlx4_err(mdev,
1075 "Requested port type for port %d is not supported on this HCA\n",
1076 info->port);
1077 err = -EINVAL;
1078 goto err_sup;
1079 }
1080
1081 mlx4_stop_sense(mdev);
1082 mutex_lock(&priv->port_mutex);
1083 info->tmp_type = port_type;
1084
1085
1086 mdev->caps.possible_type[info->port] = info->tmp_type;
1087
1088 for (i = 0; i < mdev->caps.num_ports; i++) {
1089 types[i] = priv->port[i+1].tmp_type ? priv->port[i+1].tmp_type :
1090 mdev->caps.possible_type[i+1];
1091 if (types[i] == MLX4_PORT_TYPE_AUTO)
1092 types[i] = mdev->caps.port_type[i+1];
1093 }
1094
1095 if (!(mdev->caps.flags & MLX4_DEV_CAP_FLAG_DPDP) &&
1096 !(mdev->caps.flags & MLX4_DEV_CAP_FLAG_SENSE_SUPPORT)) {
1097 for (i = 1; i <= mdev->caps.num_ports; i++) {
1098 if (mdev->caps.possible_type[i] == MLX4_PORT_TYPE_AUTO) {
1099 mdev->caps.possible_type[i] = mdev->caps.port_type[i];
1100 err = -EINVAL;
1101 }
1102 }
1103 }
1104 if (err) {
1105 mlx4_err(mdev, "Auto sensing is not supported on this HCA. Set only 'eth' or 'ib' for both ports (should be the same)\n");
1106 goto out;
1107 }
1108
1109 mlx4_do_sense_ports(mdev, new_types, types);
1110
1111 err = mlx4_check_port_params(mdev, new_types);
1112 if (err)
1113 goto out;
1114
1115
1116
1117
1118 for (i = 0; i < mdev->caps.num_ports; i++)
1119 priv->port[i + 1].tmp_type = 0;
1120
1121 err = mlx4_change_port_types(mdev, new_types);
1122
1123out:
1124 mlx4_start_sense(mdev);
1125 mutex_unlock(&priv->port_mutex);
1126err_sup:
1127 return err;
1128}
1129
1130static ssize_t set_port_type(struct device *dev,
1131 struct device_attribute *attr,
1132 const char *buf, size_t count)
1133{
1134 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1135 port_attr);
1136 struct mlx4_dev *mdev = info->dev;
1137 enum mlx4_port_type port_type;
1138 static DEFINE_MUTEX(set_port_type_mutex);
1139 int err;
1140
1141 mutex_lock(&set_port_type_mutex);
1142
1143 if (!strcmp(buf, "ib\n")) {
1144 port_type = MLX4_PORT_TYPE_IB;
1145 } else if (!strcmp(buf, "eth\n")) {
1146 port_type = MLX4_PORT_TYPE_ETH;
1147 } else if (!strcmp(buf, "auto\n")) {
1148 port_type = MLX4_PORT_TYPE_AUTO;
1149 } else {
1150 mlx4_err(mdev, "%s is not supported port type\n", buf);
1151 err = -EINVAL;
1152 goto err_out;
1153 }
1154
1155 err = __set_port_type(info, port_type);
1156
1157err_out:
1158 mutex_unlock(&set_port_type_mutex);
1159
1160 return err ? err : count;
1161}
1162
1163enum ibta_mtu {
1164 IB_MTU_256 = 1,
1165 IB_MTU_512 = 2,
1166 IB_MTU_1024 = 3,
1167 IB_MTU_2048 = 4,
1168 IB_MTU_4096 = 5
1169};
1170
1171static inline int int_to_ibta_mtu(int mtu)
1172{
1173 switch (mtu) {
1174 case 256: return IB_MTU_256;
1175 case 512: return IB_MTU_512;
1176 case 1024: return IB_MTU_1024;
1177 case 2048: return IB_MTU_2048;
1178 case 4096: return IB_MTU_4096;
1179 default: return -1;
1180 }
1181}
1182
1183static inline int ibta_mtu_to_int(enum ibta_mtu mtu)
1184{
1185 switch (mtu) {
1186 case IB_MTU_256: return 256;
1187 case IB_MTU_512: return 512;
1188 case IB_MTU_1024: return 1024;
1189 case IB_MTU_2048: return 2048;
1190 case IB_MTU_4096: return 4096;
1191 default: return -1;
1192 }
1193}
1194
1195static ssize_t show_port_ib_mtu(struct device *dev,
1196 struct device_attribute *attr,
1197 char *buf)
1198{
1199 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1200 port_mtu_attr);
1201 struct mlx4_dev *mdev = info->dev;
1202
1203 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH)
1204 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1205
1206 sprintf(buf, "%d\n",
1207 ibta_mtu_to_int(mdev->caps.port_ib_mtu[info->port]));
1208 return strlen(buf);
1209}
1210
1211static ssize_t set_port_ib_mtu(struct device *dev,
1212 struct device_attribute *attr,
1213 const char *buf, size_t count)
1214{
1215 struct mlx4_port_info *info = container_of(attr, struct mlx4_port_info,
1216 port_mtu_attr);
1217 struct mlx4_dev *mdev = info->dev;
1218 struct mlx4_priv *priv = mlx4_priv(mdev);
1219 int err, port, mtu, ibta_mtu = -1;
1220
1221 if (mdev->caps.port_type[info->port] == MLX4_PORT_TYPE_ETH) {
1222 mlx4_warn(mdev, "port level mtu is only used for IB ports\n");
1223 return -EINVAL;
1224 }
1225
1226 err = kstrtoint(buf, 0, &mtu);
1227 if (!err)
1228 ibta_mtu = int_to_ibta_mtu(mtu);
1229
1230 if (err || ibta_mtu < 0) {
1231 mlx4_err(mdev, "%s is invalid IBTA mtu\n", buf);
1232 return -EINVAL;
1233 }
1234
1235 mdev->caps.port_ib_mtu[info->port] = ibta_mtu;
1236
1237 mlx4_stop_sense(mdev);
1238 mutex_lock(&priv->port_mutex);
1239 mlx4_unregister_device(mdev);
1240 for (port = 1; port <= mdev->caps.num_ports; port++) {
1241 mlx4_CLOSE_PORT(mdev, port);
1242 err = mlx4_SET_PORT(mdev, port, -1);
1243 if (err) {
1244 mlx4_err(mdev, "Failed to set port %d, aborting\n",
1245 port);
1246 goto err_set_port;
1247 }
1248 }
1249 err = mlx4_register_device(mdev);
1250err_set_port:
1251 mutex_unlock(&priv->port_mutex);
1252 mlx4_start_sense(mdev);
1253 return err ? err : count;
1254}
1255
1256
1257#define MAX_MF_BOND_ALLOWED_SLAVES 63
1258static int mlx4_mf_bond(struct mlx4_dev *dev)
1259{
1260 int err = 0;
1261 int nvfs;
1262 struct mlx4_slaves_pport slaves_port1;
1263 struct mlx4_slaves_pport slaves_port2;
1264 DECLARE_BITMAP(slaves_port_1_2, MLX4_MFUNC_MAX);
1265
1266 slaves_port1 = mlx4_phys_to_slaves_pport(dev, 1);
1267 slaves_port2 = mlx4_phys_to_slaves_pport(dev, 2);
1268 bitmap_and(slaves_port_1_2,
1269 slaves_port1.slaves, slaves_port2.slaves,
1270 dev->persist->num_vfs + 1);
1271
1272
1273 if (bitmap_weight(slaves_port_1_2, dev->persist->num_vfs + 1) > 1) {
1274 mlx4_warn(dev, "HA mode unsupported for dual ported VFs\n");
1275 return -EINVAL;
1276 }
1277
1278
1279
1280
1281 nvfs = bitmap_weight(slaves_port1.slaves, dev->persist->num_vfs + 1) +
1282 bitmap_weight(slaves_port2.slaves, dev->persist->num_vfs + 1) - 2;
1283
1284
1285 if (nvfs > MAX_MF_BOND_ALLOWED_SLAVES) {
1286 mlx4_warn(dev, "HA mode is not supported for %d VFs (max %d are allowed)\n",
1287 nvfs, MAX_MF_BOND_ALLOWED_SLAVES);
1288 return -EINVAL;
1289 }
1290
1291 if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) {
1292 mlx4_warn(dev, "HA mode unsupported for NON DMFS steering\n");
1293 return -EINVAL;
1294 }
1295
1296 err = mlx4_bond_mac_table(dev);
1297 if (err)
1298 return err;
1299 err = mlx4_bond_vlan_table(dev);
1300 if (err)
1301 goto err1;
1302 err = mlx4_bond_fs_rules(dev);
1303 if (err)
1304 goto err2;
1305
1306 return 0;
1307err2:
1308 (void)mlx4_unbond_vlan_table(dev);
1309err1:
1310 (void)mlx4_unbond_mac_table(dev);
1311 return err;
1312}
1313
1314static int mlx4_mf_unbond(struct mlx4_dev *dev)
1315{
1316 int ret, ret1;
1317
1318 ret = mlx4_unbond_fs_rules(dev);
1319 if (ret)
1320 mlx4_warn(dev, "multifunction unbond for flow rules failed (%d)\n", ret);
1321 ret1 = mlx4_unbond_mac_table(dev);
1322 if (ret1) {
1323 mlx4_warn(dev, "multifunction unbond for MAC table failed (%d)\n", ret1);
1324 ret = ret1;
1325 }
1326 ret1 = mlx4_unbond_vlan_table(dev);
1327 if (ret1) {
1328 mlx4_warn(dev, "multifunction unbond for VLAN table failed (%d)\n", ret1);
1329 ret = ret1;
1330 }
1331 return ret;
1332}
1333
1334int mlx4_bond(struct mlx4_dev *dev)
1335{
1336 int ret = 0;
1337 struct mlx4_priv *priv = mlx4_priv(dev);
1338
1339 mutex_lock(&priv->bond_mutex);
1340
1341 if (!mlx4_is_bonded(dev)) {
1342 ret = mlx4_do_bond(dev, true);
1343 if (ret)
1344 mlx4_err(dev, "Failed to bond device: %d\n", ret);
1345 if (!ret && mlx4_is_master(dev)) {
1346 ret = mlx4_mf_bond(dev);
1347 if (ret) {
1348 mlx4_err(dev, "bond for multifunction failed\n");
1349 mlx4_do_bond(dev, false);
1350 }
1351 }
1352 }
1353
1354 mutex_unlock(&priv->bond_mutex);
1355 if (!ret)
1356 mlx4_dbg(dev, "Device is bonded\n");
1357
1358 return ret;
1359}
1360EXPORT_SYMBOL_GPL(mlx4_bond);
1361
1362int mlx4_unbond(struct mlx4_dev *dev)
1363{
1364 int ret = 0;
1365 struct mlx4_priv *priv = mlx4_priv(dev);
1366
1367 mutex_lock(&priv->bond_mutex);
1368
1369 if (mlx4_is_bonded(dev)) {
1370 int ret2 = 0;
1371
1372 ret = mlx4_do_bond(dev, false);
1373 if (ret)
1374 mlx4_err(dev, "Failed to unbond device: %d\n", ret);
1375 if (mlx4_is_master(dev))
1376 ret2 = mlx4_mf_unbond(dev);
1377 if (ret2) {
1378 mlx4_warn(dev, "Failed to unbond device for multifunction (%d)\n", ret2);
1379 ret = ret2;
1380 }
1381 }
1382
1383 mutex_unlock(&priv->bond_mutex);
1384 if (!ret)
1385 mlx4_dbg(dev, "Device is unbonded\n");
1386
1387 return ret;
1388}
1389EXPORT_SYMBOL_GPL(mlx4_unbond);
1390
1391
1392int mlx4_port_map_set(struct mlx4_dev *dev, struct mlx4_port_map *v2p)
1393{
1394 u8 port1 = v2p->port1;
1395 u8 port2 = v2p->port2;
1396 struct mlx4_priv *priv = mlx4_priv(dev);
1397 int err;
1398
1399 if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PORT_REMAP))
1400 return -EOPNOTSUPP;
1401
1402 mutex_lock(&priv->bond_mutex);
1403
1404
1405 if (port1 == 0)
1406 port1 = priv->v2p.port1;
1407 if (port2 == 0)
1408 port2 = priv->v2p.port2;
1409
1410 if ((port1 < 1) || (port1 > MLX4_MAX_PORTS) ||
1411 (port2 < 1) || (port2 > MLX4_MAX_PORTS) ||
1412 (port1 == 2 && port2 == 1)) {
1413
1414
1415 err = -EINVAL;
1416 } else if ((port1 == priv->v2p.port1) &&
1417 (port2 == priv->v2p.port2)) {
1418 err = 0;
1419 } else {
1420 err = mlx4_virt2phy_port_map(dev, port1, port2);
1421 if (!err) {
1422 mlx4_dbg(dev, "port map changed: [%d][%d]\n",
1423 port1, port2);
1424 priv->v2p.port1 = port1;
1425 priv->v2p.port2 = port2;
1426 } else {
1427 mlx4_err(dev, "Failed to change port mape: %d\n", err);
1428 }
1429 }
1430
1431 mutex_unlock(&priv->bond_mutex);
1432 return err;
1433}
1434EXPORT_SYMBOL_GPL(mlx4_port_map_set);
1435
1436static int mlx4_load_fw(struct mlx4_dev *dev)
1437{
1438 struct mlx4_priv *priv = mlx4_priv(dev);
1439 int err;
1440
1441 priv->fw.fw_icm = mlx4_alloc_icm(dev, priv->fw.fw_pages,
1442 GFP_HIGHUSER | __GFP_NOWARN, 0);
1443 if (!priv->fw.fw_icm) {
1444 mlx4_err(dev, "Couldn't allocate FW area, aborting\n");
1445 return -ENOMEM;
1446 }
1447
1448 err = mlx4_MAP_FA(dev, priv->fw.fw_icm);
1449 if (err) {
1450 mlx4_err(dev, "MAP_FA command failed, aborting\n");
1451 goto err_free;
1452 }
1453
1454 err = mlx4_RUN_FW(dev);
1455 if (err) {
1456 mlx4_err(dev, "RUN_FW command failed, aborting\n");
1457 goto err_unmap_fa;
1458 }
1459
1460 return 0;
1461
1462err_unmap_fa:
1463 mlx4_UNMAP_FA(dev);
1464
1465err_free:
1466 mlx4_free_icm(dev, priv->fw.fw_icm, 0);
1467 return err;
1468}
1469
1470static int mlx4_init_cmpt_table(struct mlx4_dev *dev, u64 cmpt_base,
1471 int cmpt_entry_sz)
1472{
1473 struct mlx4_priv *priv = mlx4_priv(dev);
1474 int err;
1475 int num_eqs;
1476
1477 err = mlx4_init_icm_table(dev, &priv->qp_table.cmpt_table,
1478 cmpt_base +
1479 ((u64) (MLX4_CMPT_TYPE_QP *
1480 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1481 cmpt_entry_sz, dev->caps.num_qps,
1482 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1483 0, 0);
1484 if (err)
1485 goto err;
1486
1487 err = mlx4_init_icm_table(dev, &priv->srq_table.cmpt_table,
1488 cmpt_base +
1489 ((u64) (MLX4_CMPT_TYPE_SRQ *
1490 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1491 cmpt_entry_sz, dev->caps.num_srqs,
1492 dev->caps.reserved_srqs, 0, 0);
1493 if (err)
1494 goto err_qp;
1495
1496 err = mlx4_init_icm_table(dev, &priv->cq_table.cmpt_table,
1497 cmpt_base +
1498 ((u64) (MLX4_CMPT_TYPE_CQ *
1499 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1500 cmpt_entry_sz, dev->caps.num_cqs,
1501 dev->caps.reserved_cqs, 0, 0);
1502 if (err)
1503 goto err_srq;
1504
1505 num_eqs = dev->phys_caps.num_phys_eqs;
1506 err = mlx4_init_icm_table(dev, &priv->eq_table.cmpt_table,
1507 cmpt_base +
1508 ((u64) (MLX4_CMPT_TYPE_EQ *
1509 cmpt_entry_sz) << MLX4_CMPT_SHIFT),
1510 cmpt_entry_sz, num_eqs, num_eqs, 0, 0);
1511 if (err)
1512 goto err_cq;
1513
1514 return 0;
1515
1516err_cq:
1517 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1518
1519err_srq:
1520 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1521
1522err_qp:
1523 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1524
1525err:
1526 return err;
1527}
1528
1529static int mlx4_init_icm(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
1530 struct mlx4_init_hca_param *init_hca, u64 icm_size)
1531{
1532 struct mlx4_priv *priv = mlx4_priv(dev);
1533 u64 aux_pages;
1534 int num_eqs;
1535 int err;
1536
1537 err = mlx4_SET_ICM_SIZE(dev, icm_size, &aux_pages);
1538 if (err) {
1539 mlx4_err(dev, "SET_ICM_SIZE command failed, aborting\n");
1540 return err;
1541 }
1542
1543 mlx4_dbg(dev, "%lld KB of HCA context requires %lld KB aux memory\n",
1544 (unsigned long long) icm_size >> 10,
1545 (unsigned long long) aux_pages << 2);
1546
1547 priv->fw.aux_icm = mlx4_alloc_icm(dev, aux_pages,
1548 GFP_HIGHUSER | __GFP_NOWARN, 0);
1549 if (!priv->fw.aux_icm) {
1550 mlx4_err(dev, "Couldn't allocate aux memory, aborting\n");
1551 return -ENOMEM;
1552 }
1553
1554 err = mlx4_MAP_ICM_AUX(dev, priv->fw.aux_icm);
1555 if (err) {
1556 mlx4_err(dev, "MAP_ICM_AUX command failed, aborting\n");
1557 goto err_free_aux;
1558 }
1559
1560 err = mlx4_init_cmpt_table(dev, init_hca->cmpt_base, dev_cap->cmpt_entry_sz);
1561 if (err) {
1562 mlx4_err(dev, "Failed to map cMPT context memory, aborting\n");
1563 goto err_unmap_aux;
1564 }
1565
1566
1567 num_eqs = dev->phys_caps.num_phys_eqs;
1568 err = mlx4_init_icm_table(dev, &priv->eq_table.table,
1569 init_hca->eqc_base, dev_cap->eqc_entry_sz,
1570 num_eqs, num_eqs, 0, 0);
1571 if (err) {
1572 mlx4_err(dev, "Failed to map EQ context memory, aborting\n");
1573 goto err_unmap_cmpt;
1574 }
1575
1576
1577
1578
1579
1580
1581
1582
1583 dev->caps.reserved_mtts =
1584 ALIGN(dev->caps.reserved_mtts * dev->caps.mtt_entry_sz,
1585 dma_get_cache_alignment()) / dev->caps.mtt_entry_sz;
1586
1587 err = mlx4_init_icm_table(dev, &priv->mr_table.mtt_table,
1588 init_hca->mtt_base,
1589 dev->caps.mtt_entry_sz,
1590 dev->caps.num_mtts,
1591 dev->caps.reserved_mtts, 1, 0);
1592 if (err) {
1593 mlx4_err(dev, "Failed to map MTT context memory, aborting\n");
1594 goto err_unmap_eq;
1595 }
1596
1597 err = mlx4_init_icm_table(dev, &priv->mr_table.dmpt_table,
1598 init_hca->dmpt_base,
1599 dev_cap->dmpt_entry_sz,
1600 dev->caps.num_mpts,
1601 dev->caps.reserved_mrws, 1, 1);
1602 if (err) {
1603 mlx4_err(dev, "Failed to map dMPT context memory, aborting\n");
1604 goto err_unmap_mtt;
1605 }
1606
1607 err = mlx4_init_icm_table(dev, &priv->qp_table.qp_table,
1608 init_hca->qpc_base,
1609 dev_cap->qpc_entry_sz,
1610 dev->caps.num_qps,
1611 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1612 0, 0);
1613 if (err) {
1614 mlx4_err(dev, "Failed to map QP context memory, aborting\n");
1615 goto err_unmap_dmpt;
1616 }
1617
1618 err = mlx4_init_icm_table(dev, &priv->qp_table.auxc_table,
1619 init_hca->auxc_base,
1620 dev_cap->aux_entry_sz,
1621 dev->caps.num_qps,
1622 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1623 0, 0);
1624 if (err) {
1625 mlx4_err(dev, "Failed to map AUXC context memory, aborting\n");
1626 goto err_unmap_qp;
1627 }
1628
1629 err = mlx4_init_icm_table(dev, &priv->qp_table.altc_table,
1630 init_hca->altc_base,
1631 dev_cap->altc_entry_sz,
1632 dev->caps.num_qps,
1633 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1634 0, 0);
1635 if (err) {
1636 mlx4_err(dev, "Failed to map ALTC context memory, aborting\n");
1637 goto err_unmap_auxc;
1638 }
1639
1640 err = mlx4_init_icm_table(dev, &priv->qp_table.rdmarc_table,
1641 init_hca->rdmarc_base,
1642 dev_cap->rdmarc_entry_sz << priv->qp_table.rdmarc_shift,
1643 dev->caps.num_qps,
1644 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW],
1645 0, 0);
1646 if (err) {
1647 mlx4_err(dev, "Failed to map RDMARC context memory, aborting\n");
1648 goto err_unmap_altc;
1649 }
1650
1651 err = mlx4_init_icm_table(dev, &priv->cq_table.table,
1652 init_hca->cqc_base,
1653 dev_cap->cqc_entry_sz,
1654 dev->caps.num_cqs,
1655 dev->caps.reserved_cqs, 0, 0);
1656 if (err) {
1657 mlx4_err(dev, "Failed to map CQ context memory, aborting\n");
1658 goto err_unmap_rdmarc;
1659 }
1660
1661 err = mlx4_init_icm_table(dev, &priv->srq_table.table,
1662 init_hca->srqc_base,
1663 dev_cap->srq_entry_sz,
1664 dev->caps.num_srqs,
1665 dev->caps.reserved_srqs, 0, 0);
1666 if (err) {
1667 mlx4_err(dev, "Failed to map SRQ context memory, aborting\n");
1668 goto err_unmap_cq;
1669 }
1670
1671
1672
1673
1674
1675
1676
1677
1678 err = mlx4_init_icm_table(dev, &priv->mcg_table.table,
1679 init_hca->mc_base,
1680 mlx4_get_mgm_entry_size(dev),
1681 dev->caps.num_mgms + dev->caps.num_amgms,
1682 dev->caps.num_mgms + dev->caps.num_amgms,
1683 0, 0);
1684 if (err) {
1685 mlx4_err(dev, "Failed to map MCG context memory, aborting\n");
1686 goto err_unmap_srq;
1687 }
1688
1689 return 0;
1690
1691err_unmap_srq:
1692 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1693
1694err_unmap_cq:
1695 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1696
1697err_unmap_rdmarc:
1698 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1699
1700err_unmap_altc:
1701 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1702
1703err_unmap_auxc:
1704 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1705
1706err_unmap_qp:
1707 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1708
1709err_unmap_dmpt:
1710 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1711
1712err_unmap_mtt:
1713 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1714
1715err_unmap_eq:
1716 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1717
1718err_unmap_cmpt:
1719 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1720 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1721 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1722 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1723
1724err_unmap_aux:
1725 mlx4_UNMAP_ICM_AUX(dev);
1726
1727err_free_aux:
1728 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1729
1730 return err;
1731}
1732
1733static void mlx4_free_icms(struct mlx4_dev *dev)
1734{
1735 struct mlx4_priv *priv = mlx4_priv(dev);
1736
1737 mlx4_cleanup_icm_table(dev, &priv->mcg_table.table);
1738 mlx4_cleanup_icm_table(dev, &priv->srq_table.table);
1739 mlx4_cleanup_icm_table(dev, &priv->cq_table.table);
1740 mlx4_cleanup_icm_table(dev, &priv->qp_table.rdmarc_table);
1741 mlx4_cleanup_icm_table(dev, &priv->qp_table.altc_table);
1742 mlx4_cleanup_icm_table(dev, &priv->qp_table.auxc_table);
1743 mlx4_cleanup_icm_table(dev, &priv->qp_table.qp_table);
1744 mlx4_cleanup_icm_table(dev, &priv->mr_table.dmpt_table);
1745 mlx4_cleanup_icm_table(dev, &priv->mr_table.mtt_table);
1746 mlx4_cleanup_icm_table(dev, &priv->eq_table.table);
1747 mlx4_cleanup_icm_table(dev, &priv->eq_table.cmpt_table);
1748 mlx4_cleanup_icm_table(dev, &priv->cq_table.cmpt_table);
1749 mlx4_cleanup_icm_table(dev, &priv->srq_table.cmpt_table);
1750 mlx4_cleanup_icm_table(dev, &priv->qp_table.cmpt_table);
1751
1752 mlx4_UNMAP_ICM_AUX(dev);
1753 mlx4_free_icm(dev, priv->fw.aux_icm, 0);
1754}
1755
1756static void mlx4_slave_exit(struct mlx4_dev *dev)
1757{
1758 struct mlx4_priv *priv = mlx4_priv(dev);
1759
1760 mutex_lock(&priv->cmd.slave_cmd_mutex);
1761 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP,
1762 MLX4_COMM_TIME))
1763 mlx4_warn(dev, "Failed to close slave function\n");
1764 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1765}
1766
1767static int map_bf_area(struct mlx4_dev *dev)
1768{
1769 struct mlx4_priv *priv = mlx4_priv(dev);
1770 resource_size_t bf_start;
1771 resource_size_t bf_len;
1772 int err = 0;
1773
1774 if (!dev->caps.bf_reg_size)
1775 return -ENXIO;
1776
1777 bf_start = pci_resource_start(dev->persist->pdev, 2) +
1778 (dev->caps.num_uars << PAGE_SHIFT);
1779 bf_len = pci_resource_len(dev->persist->pdev, 2) -
1780 (dev->caps.num_uars << PAGE_SHIFT);
1781 priv->bf_mapping = io_mapping_create_wc(bf_start, bf_len);
1782 if (!priv->bf_mapping)
1783 err = -ENOMEM;
1784
1785 return err;
1786}
1787
1788static void unmap_bf_area(struct mlx4_dev *dev)
1789{
1790 if (mlx4_priv(dev)->bf_mapping)
1791 io_mapping_free(mlx4_priv(dev)->bf_mapping);
1792}
1793
1794u64 mlx4_read_clock(struct mlx4_dev *dev)
1795{
1796 u32 clockhi, clocklo, clockhi1;
1797 u64 cycles;
1798 int i;
1799 struct mlx4_priv *priv = mlx4_priv(dev);
1800
1801 for (i = 0; i < 10; i++) {
1802 clockhi = swab32(readl(priv->clock_mapping));
1803 clocklo = swab32(readl(priv->clock_mapping + 4));
1804 clockhi1 = swab32(readl(priv->clock_mapping));
1805 if (clockhi == clockhi1)
1806 break;
1807 }
1808
1809 cycles = (u64) clockhi << 32 | (u64) clocklo;
1810
1811 return cycles;
1812}
1813EXPORT_SYMBOL_GPL(mlx4_read_clock);
1814
1815
1816static int map_internal_clock(struct mlx4_dev *dev)
1817{
1818 struct mlx4_priv *priv = mlx4_priv(dev);
1819
1820 priv->clock_mapping =
1821 ioremap(pci_resource_start(dev->persist->pdev,
1822 priv->fw.clock_bar) +
1823 priv->fw.clock_offset, MLX4_CLOCK_SIZE);
1824
1825 if (!priv->clock_mapping)
1826 return -ENOMEM;
1827
1828 return 0;
1829}
1830
1831int mlx4_get_internal_clock_params(struct mlx4_dev *dev,
1832 struct mlx4_clock_params *params)
1833{
1834 struct mlx4_priv *priv = mlx4_priv(dev);
1835
1836 if (mlx4_is_slave(dev))
1837 return -EOPNOTSUPP;
1838
1839 if (!params)
1840 return -EINVAL;
1841
1842 params->bar = priv->fw.clock_bar;
1843 params->offset = priv->fw.clock_offset;
1844 params->size = MLX4_CLOCK_SIZE;
1845
1846 return 0;
1847}
1848EXPORT_SYMBOL_GPL(mlx4_get_internal_clock_params);
1849
1850static void unmap_internal_clock(struct mlx4_dev *dev)
1851{
1852 struct mlx4_priv *priv = mlx4_priv(dev);
1853
1854 if (priv->clock_mapping)
1855 iounmap(priv->clock_mapping);
1856}
1857
1858static void mlx4_close_hca(struct mlx4_dev *dev)
1859{
1860 unmap_internal_clock(dev);
1861 unmap_bf_area(dev);
1862 if (mlx4_is_slave(dev))
1863 mlx4_slave_exit(dev);
1864 else {
1865 mlx4_CLOSE_HCA(dev, 0);
1866 mlx4_free_icms(dev);
1867 }
1868}
1869
1870static void mlx4_close_fw(struct mlx4_dev *dev)
1871{
1872 if (!mlx4_is_slave(dev)) {
1873 mlx4_UNMAP_FA(dev);
1874 mlx4_free_icm(dev, mlx4_priv(dev)->fw.fw_icm, 0);
1875 }
1876}
1877
1878static int mlx4_comm_check_offline(struct mlx4_dev *dev)
1879{
1880#define COMM_CHAN_OFFLINE_OFFSET 0x09
1881
1882 u32 comm_flags;
1883 u32 offline_bit;
1884 unsigned long end;
1885 struct mlx4_priv *priv = mlx4_priv(dev);
1886
1887 end = msecs_to_jiffies(MLX4_COMM_OFFLINE_TIME_OUT) + jiffies;
1888 while (time_before(jiffies, end)) {
1889 comm_flags = swab32(readl((__iomem char *)priv->mfunc.comm +
1890 MLX4_COMM_CHAN_FLAGS));
1891 offline_bit = (comm_flags &
1892 (u32)(1 << COMM_CHAN_OFFLINE_OFFSET));
1893 if (!offline_bit)
1894 return 0;
1895
1896
1897
1898
1899 if (dev->persist->interface_state &
1900 MLX4_INTERFACE_STATE_NOWAIT)
1901 break;
1902
1903
1904
1905
1906
1907
1908 msleep(100);
1909 }
1910 mlx4_err(dev, "Communication channel is offline.\n");
1911 return -EIO;
1912}
1913
1914static void mlx4_reset_vf_support(struct mlx4_dev *dev)
1915{
1916#define COMM_CHAN_RST_OFFSET 0x1e
1917
1918 struct mlx4_priv *priv = mlx4_priv(dev);
1919 u32 comm_rst;
1920 u32 comm_caps;
1921
1922 comm_caps = swab32(readl((__iomem char *)priv->mfunc.comm +
1923 MLX4_COMM_CHAN_CAPS));
1924 comm_rst = (comm_caps & (u32)(1 << COMM_CHAN_RST_OFFSET));
1925
1926 if (comm_rst)
1927 dev->caps.vf_caps |= MLX4_VF_CAP_FLAG_RESET;
1928}
1929
1930static int mlx4_init_slave(struct mlx4_dev *dev)
1931{
1932 struct mlx4_priv *priv = mlx4_priv(dev);
1933 u64 dma = (u64) priv->mfunc.vhcr_dma;
1934 int ret_from_reset = 0;
1935 u32 slave_read;
1936 u32 cmd_channel_ver;
1937
1938 if (atomic_read(&pf_loading)) {
1939 mlx4_warn(dev, "PF is not ready - Deferring probe\n");
1940 return -EPROBE_DEFER;
1941 }
1942
1943 mutex_lock(&priv->cmd.slave_cmd_mutex);
1944 priv->cmd.max_cmds = 1;
1945 if (mlx4_comm_check_offline(dev)) {
1946 mlx4_err(dev, "PF is not responsive, skipping initialization\n");
1947 goto err_offline;
1948 }
1949
1950 mlx4_reset_vf_support(dev);
1951 mlx4_warn(dev, "Sending reset\n");
1952 ret_from_reset = mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0,
1953 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME);
1954
1955
1956 if (ret_from_reset) {
1957 if (MLX4_DELAY_RESET_SLAVE == ret_from_reset) {
1958 mlx4_warn(dev, "slave is currently in the middle of FLR - Deferring probe\n");
1959 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1960 return -EPROBE_DEFER;
1961 } else
1962 goto err;
1963 }
1964
1965
1966
1967 slave_read = swab32(readl(&priv->mfunc.comm->slave_read));
1968 cmd_channel_ver = mlx4_comm_get_version();
1969
1970 if (MLX4_COMM_GET_IF_REV(cmd_channel_ver) !=
1971 MLX4_COMM_GET_IF_REV(slave_read)) {
1972 mlx4_err(dev, "slave driver version is not supported by the master\n");
1973 goto err;
1974 }
1975
1976 mlx4_warn(dev, "Sending vhcr0\n");
1977 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR0, dma >> 48,
1978 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1979 goto err;
1980 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR1, dma >> 32,
1981 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1982 goto err;
1983 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR2, dma >> 16,
1984 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1985 goto err;
1986 if (mlx4_comm_cmd(dev, MLX4_COMM_CMD_VHCR_EN, dma,
1987 MLX4_COMM_CMD_NA_OP, MLX4_COMM_TIME))
1988 goto err;
1989
1990 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1991 return 0;
1992
1993err:
1994 mlx4_comm_cmd(dev, MLX4_COMM_CMD_RESET, 0, MLX4_COMM_CMD_NA_OP, 0);
1995err_offline:
1996 mutex_unlock(&priv->cmd.slave_cmd_mutex);
1997 return -EIO;
1998}
1999
2000static void mlx4_parav_master_pf_caps(struct mlx4_dev *dev)
2001{
2002 int i;
2003
2004 for (i = 1; i <= dev->caps.num_ports; i++) {
2005 if (dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH)
2006 dev->caps.gid_table_len[i] =
2007 mlx4_get_slave_num_gids(dev, 0, i);
2008 else
2009 dev->caps.gid_table_len[i] = 1;
2010 dev->caps.pkey_table_len[i] =
2011 dev->phys_caps.pkey_phys_table_len[i] - 1;
2012 }
2013}
2014
2015static int choose_log_fs_mgm_entry_size(int qp_per_entry)
2016{
2017 int i = MLX4_MIN_MGM_LOG_ENTRY_SIZE;
2018
2019 for (i = MLX4_MIN_MGM_LOG_ENTRY_SIZE; i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE;
2020 i++) {
2021 if (qp_per_entry <= 4 * ((1 << i) / 16 - 2))
2022 break;
2023 }
2024
2025 return (i <= MLX4_MAX_MGM_LOG_ENTRY_SIZE) ? i : -1;
2026}
2027
2028static const char *dmfs_high_rate_steering_mode_str(int dmfs_high_steer_mode)
2029{
2030 switch (dmfs_high_steer_mode) {
2031 case MLX4_STEERING_DMFS_A0_DEFAULT:
2032 return "default performance";
2033
2034 case MLX4_STEERING_DMFS_A0_DYNAMIC:
2035 return "dynamic hybrid mode";
2036
2037 case MLX4_STEERING_DMFS_A0_STATIC:
2038 return "performance optimized for limited rule configuration (static)";
2039
2040 case MLX4_STEERING_DMFS_A0_DISABLE:
2041 return "disabled performance optimized steering";
2042
2043 case MLX4_STEERING_DMFS_A0_NOT_SUPPORTED:
2044 return "performance optimized steering not supported";
2045
2046 default:
2047 return "Unrecognized mode";
2048 }
2049}
2050
2051#define MLX4_DMFS_A0_STEERING (1UL << 2)
2052
2053static void choose_steering_mode(struct mlx4_dev *dev,
2054 struct mlx4_dev_cap *dev_cap)
2055{
2056 if (mlx4_log_num_mgm_entry_size <= 0) {
2057 if ((-mlx4_log_num_mgm_entry_size) & MLX4_DMFS_A0_STEERING) {
2058 if (dev->caps.dmfs_high_steer_mode ==
2059 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2060 mlx4_err(dev, "DMFS high rate mode not supported\n");
2061 else
2062 dev->caps.dmfs_high_steer_mode =
2063 MLX4_STEERING_DMFS_A0_STATIC;
2064 }
2065 }
2066
2067 if (mlx4_log_num_mgm_entry_size <= 0 &&
2068 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_FS_EN &&
2069 (!mlx4_is_mfunc(dev) ||
2070 (dev_cap->fs_max_num_qp_per_entry >=
2071 (dev->persist->num_vfs + 1))) &&
2072 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry) >=
2073 MLX4_MIN_MGM_LOG_ENTRY_SIZE) {
2074 dev->oper_log_mgm_entry_size =
2075 choose_log_fs_mgm_entry_size(dev_cap->fs_max_num_qp_per_entry);
2076 dev->caps.steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED;
2077 dev->caps.num_qp_per_mgm = dev_cap->fs_max_num_qp_per_entry;
2078 dev->caps.fs_log_max_ucast_qp_range_size =
2079 dev_cap->fs_log_max_ucast_qp_range_size;
2080 } else {
2081 if (dev->caps.dmfs_high_steer_mode !=
2082 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2083 dev->caps.dmfs_high_steer_mode = MLX4_STEERING_DMFS_A0_DISABLE;
2084 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER &&
2085 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2086 dev->caps.steering_mode = MLX4_STEERING_MODE_B0;
2087 else {
2088 dev->caps.steering_mode = MLX4_STEERING_MODE_A0;
2089
2090 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_UC_STEER ||
2091 dev->caps.flags & MLX4_DEV_CAP_FLAG_VEP_MC_STEER)
2092 mlx4_warn(dev, "Must have both UC_STEER and MC_STEER flags set to use B0 steering - falling back to A0 steering mode\n");
2093 }
2094 dev->oper_log_mgm_entry_size =
2095 mlx4_log_num_mgm_entry_size > 0 ?
2096 mlx4_log_num_mgm_entry_size :
2097 MLX4_DEFAULT_MGM_LOG_ENTRY_SIZE;
2098 dev->caps.num_qp_per_mgm = mlx4_get_qp_per_mgm(dev);
2099 }
2100 mlx4_dbg(dev, "Steering mode is: %s, oper_log_mgm_entry_size = %d, modparam log_num_mgm_entry_size = %d\n",
2101 mlx4_steering_mode_str(dev->caps.steering_mode),
2102 dev->oper_log_mgm_entry_size,
2103 mlx4_log_num_mgm_entry_size);
2104}
2105
2106static void choose_tunnel_offload_mode(struct mlx4_dev *dev,
2107 struct mlx4_dev_cap *dev_cap)
2108{
2109 if (dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED &&
2110 dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS)
2111 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_VXLAN;
2112 else
2113 dev->caps.tunnel_offload_mode = MLX4_TUNNEL_OFFLOAD_MODE_NONE;
2114
2115 mlx4_dbg(dev, "Tunneling offload mode is: %s\n", (dev->caps.tunnel_offload_mode
2116 == MLX4_TUNNEL_OFFLOAD_MODE_VXLAN) ? "vxlan" : "none");
2117}
2118
2119static int mlx4_validate_optimized_steering(struct mlx4_dev *dev)
2120{
2121 int i;
2122 struct mlx4_port_cap port_cap;
2123
2124 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_NOT_SUPPORTED)
2125 return -EINVAL;
2126
2127 for (i = 1; i <= dev->caps.num_ports; i++) {
2128 if (mlx4_dev_port(dev, i, &port_cap)) {
2129 mlx4_err(dev,
2130 "QUERY_DEV_CAP command failed, can't veify DMFS high rate steering.\n");
2131 } else if ((dev->caps.dmfs_high_steer_mode !=
2132 MLX4_STEERING_DMFS_A0_DEFAULT) &&
2133 (port_cap.dmfs_optimized_state ==
2134 !!(dev->caps.dmfs_high_steer_mode ==
2135 MLX4_STEERING_DMFS_A0_DISABLE))) {
2136 mlx4_err(dev,
2137 "DMFS high rate steer mode differ, driver requested %s but %s in FW.\n",
2138 dmfs_high_rate_steering_mode_str(
2139 dev->caps.dmfs_high_steer_mode),
2140 (port_cap.dmfs_optimized_state ?
2141 "enabled" : "disabled"));
2142 }
2143 }
2144
2145 return 0;
2146}
2147
2148static int mlx4_init_fw(struct mlx4_dev *dev)
2149{
2150 struct mlx4_mod_stat_cfg mlx4_cfg;
2151 int err = 0;
2152
2153 if (!mlx4_is_slave(dev)) {
2154 err = mlx4_QUERY_FW(dev);
2155 if (err) {
2156 if (err == -EACCES)
2157 mlx4_info(dev, "non-primary physical function, skipping\n");
2158 else
2159 mlx4_err(dev, "QUERY_FW command failed, aborting\n");
2160 return err;
2161 }
2162
2163 err = mlx4_load_fw(dev);
2164 if (err) {
2165 mlx4_err(dev, "Failed to start FW, aborting\n");
2166 return err;
2167 }
2168
2169 mlx4_cfg.log_pg_sz_m = 1;
2170 mlx4_cfg.log_pg_sz = 0;
2171 err = mlx4_MOD_STAT_CFG(dev, &mlx4_cfg);
2172 if (err)
2173 mlx4_warn(dev, "Failed to override log_pg_sz parameter\n");
2174 }
2175
2176 return err;
2177}
2178
2179static int mlx4_init_hca(struct mlx4_dev *dev)
2180{
2181 struct mlx4_priv *priv = mlx4_priv(dev);
2182 struct mlx4_adapter adapter;
2183 struct mlx4_dev_cap dev_cap;
2184 struct mlx4_profile profile;
2185 struct mlx4_init_hca_param init_hca;
2186 u64 icm_size;
2187 struct mlx4_config_dev_params params;
2188 int err;
2189
2190 if (!mlx4_is_slave(dev)) {
2191 err = mlx4_dev_cap(dev, &dev_cap);
2192 if (err) {
2193 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting\n");
2194 return err;
2195 }
2196
2197 choose_steering_mode(dev, &dev_cap);
2198 choose_tunnel_offload_mode(dev, &dev_cap);
2199
2200 if (dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC &&
2201 mlx4_is_master(dev))
2202 dev->caps.function_caps |= MLX4_FUNC_CAP_DMFS_A0_STATIC;
2203
2204 err = mlx4_get_phys_port_id(dev);
2205 if (err)
2206 mlx4_err(dev, "Fail to get physical port id\n");
2207
2208 if (mlx4_is_master(dev))
2209 mlx4_parav_master_pf_caps(dev);
2210
2211 if (mlx4_low_memory_profile()) {
2212 mlx4_info(dev, "Running from within kdump kernel. Using low memory profile\n");
2213 profile = low_mem_profile;
2214 } else {
2215 profile = default_profile;
2216 }
2217 if (dev->caps.steering_mode ==
2218 MLX4_STEERING_MODE_DEVICE_MANAGED)
2219 profile.num_mcg = MLX4_FS_NUM_MCG;
2220
2221 icm_size = mlx4_make_profile(dev, &profile, &dev_cap,
2222 &init_hca);
2223 if ((long long) icm_size < 0) {
2224 err = icm_size;
2225 return err;
2226 }
2227
2228 dev->caps.max_fmr_maps = (1 << (32 - ilog2(dev->caps.num_mpts))) - 1;
2229
2230 if (enable_4k_uar || !dev->persist->num_vfs) {
2231 init_hca.log_uar_sz = ilog2(dev->caps.num_uars) +
2232 PAGE_SHIFT - DEFAULT_UAR_PAGE_SHIFT;
2233 init_hca.uar_page_sz = DEFAULT_UAR_PAGE_SHIFT - 12;
2234 } else {
2235 init_hca.log_uar_sz = ilog2(dev->caps.num_uars);
2236 init_hca.uar_page_sz = PAGE_SHIFT - 12;
2237 }
2238
2239 init_hca.mw_enabled = 0;
2240 if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
2241 dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN)
2242 init_hca.mw_enabled = INIT_HCA_TPT_MW_ENABLE;
2243
2244 err = mlx4_init_icm(dev, &dev_cap, &init_hca, icm_size);
2245 if (err)
2246 return err;
2247
2248 err = mlx4_INIT_HCA(dev, &init_hca);
2249 if (err) {
2250 mlx4_err(dev, "INIT_HCA command failed, aborting\n");
2251 goto err_free_icm;
2252 }
2253
2254 if (dev_cap.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) {
2255 err = mlx4_query_func(dev, &dev_cap);
2256 if (err < 0) {
2257 mlx4_err(dev, "QUERY_FUNC command failed, aborting.\n");
2258 goto err_close;
2259 } else if (err & MLX4_QUERY_FUNC_NUM_SYS_EQS) {
2260 dev->caps.num_eqs = dev_cap.max_eqs;
2261 dev->caps.reserved_eqs = dev_cap.reserved_eqs;
2262 dev->caps.reserved_uars = dev_cap.reserved_uars;
2263 }
2264 }
2265
2266
2267
2268
2269
2270 if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_TS) {
2271 memset(&init_hca, 0, sizeof(init_hca));
2272 err = mlx4_QUERY_HCA(dev, &init_hca);
2273 if (err) {
2274 mlx4_err(dev, "QUERY_HCA command failed, disable timestamp\n");
2275 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2276 } else {
2277 dev->caps.hca_core_clock =
2278 init_hca.hca_core_clock;
2279 }
2280
2281
2282
2283
2284 if (!dev->caps.hca_core_clock) {
2285 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2286 mlx4_err(dev,
2287 "HCA frequency is 0 - timestamping is not supported\n");
2288 } else if (map_internal_clock(dev)) {
2289
2290
2291
2292
2293 dev->caps.flags2 &= ~MLX4_DEV_CAP_FLAG2_TS;
2294 mlx4_err(dev, "Failed to map internal clock. Timestamping is not supported\n");
2295 }
2296 }
2297
2298 if (dev->caps.dmfs_high_steer_mode !=
2299 MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) {
2300 if (mlx4_validate_optimized_steering(dev))
2301 mlx4_warn(dev, "Optimized steering validation failed\n");
2302
2303 if (dev->caps.dmfs_high_steer_mode ==
2304 MLX4_STEERING_DMFS_A0_DISABLE) {
2305 dev->caps.dmfs_high_rate_qpn_base =
2306 dev->caps.reserved_qps_cnt[MLX4_QP_REGION_FW];
2307 dev->caps.dmfs_high_rate_qpn_range =
2308 MLX4_A0_STEERING_TABLE_SIZE;
2309 }
2310
2311 mlx4_info(dev, "DMFS high rate steer mode is: %s\n",
2312 dmfs_high_rate_steering_mode_str(
2313 dev->caps.dmfs_high_steer_mode));
2314 }
2315 } else {
2316 err = mlx4_init_slave(dev);
2317 if (err) {
2318 if (err != -EPROBE_DEFER)
2319 mlx4_err(dev, "Failed to initialize slave\n");
2320 return err;
2321 }
2322
2323 err = mlx4_slave_cap(dev);
2324 if (err) {
2325 mlx4_err(dev, "Failed to obtain slave caps\n");
2326 goto err_close;
2327 }
2328 }
2329
2330 if (map_bf_area(dev))
2331 mlx4_dbg(dev, "Failed to map blue flame area\n");
2332
2333
2334 if (!mlx4_is_slave(dev))
2335 mlx4_set_port_mask(dev);
2336
2337 err = mlx4_QUERY_ADAPTER(dev, &adapter);
2338 if (err) {
2339 mlx4_err(dev, "QUERY_ADAPTER command failed, aborting\n");
2340 goto unmap_bf;
2341 }
2342
2343
2344 err = mlx4_config_dev_retrieval(dev, ¶ms);
2345 if (err && err != -EOPNOTSUPP) {
2346 mlx4_err(dev, "Failed to query CONFIG_DEV parameters\n");
2347 } else if (!err) {
2348 dev->caps.rx_checksum_flags_port[1] = params.rx_csum_flags_port_1;
2349 dev->caps.rx_checksum_flags_port[2] = params.rx_csum_flags_port_2;
2350 }
2351 priv->eq_table.inta_pin = adapter.inta_pin;
2352 memcpy(dev->board_id, adapter.board_id, sizeof(dev->board_id));
2353
2354 return 0;
2355
2356unmap_bf:
2357 unmap_internal_clock(dev);
2358 unmap_bf_area(dev);
2359
2360 if (mlx4_is_slave(dev))
2361 mlx4_slave_destroy_special_qp_cap(dev);
2362
2363err_close:
2364 if (mlx4_is_slave(dev))
2365 mlx4_slave_exit(dev);
2366 else
2367 mlx4_CLOSE_HCA(dev, 0);
2368
2369err_free_icm:
2370 if (!mlx4_is_slave(dev))
2371 mlx4_free_icms(dev);
2372
2373 return err;
2374}
2375
2376static int mlx4_init_counters_table(struct mlx4_dev *dev)
2377{
2378 struct mlx4_priv *priv = mlx4_priv(dev);
2379 int nent_pow2;
2380
2381 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2382 return -ENOENT;
2383
2384 if (!dev->caps.max_counters)
2385 return -ENOSPC;
2386
2387 nent_pow2 = roundup_pow_of_two(dev->caps.max_counters);
2388
2389 return mlx4_bitmap_init(&priv->counters_bitmap, nent_pow2,
2390 nent_pow2 - 1, 0,
2391 nent_pow2 - dev->caps.max_counters + 1);
2392}
2393
2394static void mlx4_cleanup_counters_table(struct mlx4_dev *dev)
2395{
2396 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2397 return;
2398
2399 if (!dev->caps.max_counters)
2400 return;
2401
2402 mlx4_bitmap_cleanup(&mlx4_priv(dev)->counters_bitmap);
2403}
2404
2405static void mlx4_cleanup_default_counters(struct mlx4_dev *dev)
2406{
2407 struct mlx4_priv *priv = mlx4_priv(dev);
2408 int port;
2409
2410 for (port = 0; port < dev->caps.num_ports; port++)
2411 if (priv->def_counter[port] != -1)
2412 mlx4_counter_free(dev, priv->def_counter[port]);
2413}
2414
2415static int mlx4_allocate_default_counters(struct mlx4_dev *dev)
2416{
2417 struct mlx4_priv *priv = mlx4_priv(dev);
2418 int port, err = 0;
2419 u32 idx;
2420
2421 for (port = 0; port < dev->caps.num_ports; port++)
2422 priv->def_counter[port] = -1;
2423
2424 for (port = 0; port < dev->caps.num_ports; port++) {
2425 err = mlx4_counter_alloc(dev, &idx, MLX4_RES_USAGE_DRIVER);
2426
2427 if (!err || err == -ENOSPC) {
2428 priv->def_counter[port] = idx;
2429 } else if (err == -ENOENT) {
2430 err = 0;
2431 continue;
2432 } else if (mlx4_is_slave(dev) && err == -EINVAL) {
2433 priv->def_counter[port] = MLX4_SINK_COUNTER_INDEX(dev);
2434 mlx4_warn(dev, "can't allocate counter from old PF driver, using index %d\n",
2435 MLX4_SINK_COUNTER_INDEX(dev));
2436 err = 0;
2437 } else {
2438 mlx4_err(dev, "%s: failed to allocate default counter port %d err %d\n",
2439 __func__, port + 1, err);
2440 mlx4_cleanup_default_counters(dev);
2441 return err;
2442 }
2443
2444 mlx4_dbg(dev, "%s: default counter index %d for port %d\n",
2445 __func__, priv->def_counter[port], port + 1);
2446 }
2447
2448 return err;
2449}
2450
2451int __mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx)
2452{
2453 struct mlx4_priv *priv = mlx4_priv(dev);
2454
2455 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2456 return -ENOENT;
2457
2458 *idx = mlx4_bitmap_alloc(&priv->counters_bitmap);
2459 if (*idx == -1) {
2460 *idx = MLX4_SINK_COUNTER_INDEX(dev);
2461 return -ENOSPC;
2462 }
2463
2464 return 0;
2465}
2466
2467int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx, u8 usage)
2468{
2469 u32 in_modifier = RES_COUNTER | (((u32)usage & 3) << 30);
2470 u64 out_param;
2471 int err;
2472
2473 if (mlx4_is_mfunc(dev)) {
2474 err = mlx4_cmd_imm(dev, 0, &out_param, in_modifier,
2475 RES_OP_RESERVE, MLX4_CMD_ALLOC_RES,
2476 MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED);
2477 if (!err)
2478 *idx = get_param_l(&out_param);
2479
2480 return err;
2481 }
2482 return __mlx4_counter_alloc(dev, idx);
2483}
2484EXPORT_SYMBOL_GPL(mlx4_counter_alloc);
2485
2486static int __mlx4_clear_if_stat(struct mlx4_dev *dev,
2487 u8 counter_index)
2488{
2489 struct mlx4_cmd_mailbox *if_stat_mailbox;
2490 int err;
2491 u32 if_stat_in_mod = (counter_index & 0xff) | MLX4_QUERY_IF_STAT_RESET;
2492
2493 if_stat_mailbox = mlx4_alloc_cmd_mailbox(dev);
2494 if (IS_ERR(if_stat_mailbox))
2495 return PTR_ERR(if_stat_mailbox);
2496
2497 err = mlx4_cmd_box(dev, 0, if_stat_mailbox->dma, if_stat_in_mod, 0,
2498 MLX4_CMD_QUERY_IF_STAT, MLX4_CMD_TIME_CLASS_C,
2499 MLX4_CMD_NATIVE);
2500
2501 mlx4_free_cmd_mailbox(dev, if_stat_mailbox);
2502 return err;
2503}
2504
2505void __mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2506{
2507 if (!(dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS))
2508 return;
2509
2510 if (idx == MLX4_SINK_COUNTER_INDEX(dev))
2511 return;
2512
2513 __mlx4_clear_if_stat(dev, idx);
2514
2515 mlx4_bitmap_free(&mlx4_priv(dev)->counters_bitmap, idx, MLX4_USE_RR);
2516 return;
2517}
2518
2519void mlx4_counter_free(struct mlx4_dev *dev, u32 idx)
2520{
2521 u64 in_param = 0;
2522
2523 if (mlx4_is_mfunc(dev)) {
2524 set_param_l(&in_param, idx);
2525 mlx4_cmd(dev, in_param, RES_COUNTER, RES_OP_RESERVE,
2526 MLX4_CMD_FREE_RES, MLX4_CMD_TIME_CLASS_A,
2527 MLX4_CMD_WRAPPED);
2528 return;
2529 }
2530 __mlx4_counter_free(dev, idx);
2531}
2532EXPORT_SYMBOL_GPL(mlx4_counter_free);
2533
2534int mlx4_get_default_counter_index(struct mlx4_dev *dev, int port)
2535{
2536 struct mlx4_priv *priv = mlx4_priv(dev);
2537
2538 return priv->def_counter[port - 1];
2539}
2540EXPORT_SYMBOL_GPL(mlx4_get_default_counter_index);
2541
2542void mlx4_set_admin_guid(struct mlx4_dev *dev, __be64 guid, int entry, int port)
2543{
2544 struct mlx4_priv *priv = mlx4_priv(dev);
2545
2546 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2547}
2548EXPORT_SYMBOL_GPL(mlx4_set_admin_guid);
2549
2550__be64 mlx4_get_admin_guid(struct mlx4_dev *dev, int entry, int port)
2551{
2552 struct mlx4_priv *priv = mlx4_priv(dev);
2553
2554 return priv->mfunc.master.vf_admin[entry].vport[port].guid;
2555}
2556EXPORT_SYMBOL_GPL(mlx4_get_admin_guid);
2557
2558void mlx4_set_random_admin_guid(struct mlx4_dev *dev, int entry, int port)
2559{
2560 struct mlx4_priv *priv = mlx4_priv(dev);
2561 __be64 guid;
2562
2563
2564 if (entry == 0)
2565 return;
2566
2567 get_random_bytes((char *)&guid, sizeof(guid));
2568 guid &= ~(cpu_to_be64(1ULL << 56));
2569 guid |= cpu_to_be64(1ULL << 57);
2570 priv->mfunc.master.vf_admin[entry].vport[port].guid = guid;
2571}
2572
2573static int mlx4_setup_hca(struct mlx4_dev *dev)
2574{
2575 struct mlx4_priv *priv = mlx4_priv(dev);
2576 int err;
2577 int port;
2578 __be32 ib_port_default_caps;
2579
2580 err = mlx4_init_uar_table(dev);
2581 if (err) {
2582 mlx4_err(dev, "Failed to initialize user access region table, aborting\n");
2583 return err;
2584 }
2585
2586 err = mlx4_uar_alloc(dev, &priv->driver_uar);
2587 if (err) {
2588 mlx4_err(dev, "Failed to allocate driver access region, aborting\n");
2589 goto err_uar_table_free;
2590 }
2591
2592 priv->kar = ioremap((phys_addr_t) priv->driver_uar.pfn << PAGE_SHIFT, PAGE_SIZE);
2593 if (!priv->kar) {
2594 mlx4_err(dev, "Couldn't map kernel access region, aborting\n");
2595 err = -ENOMEM;
2596 goto err_uar_free;
2597 }
2598
2599 err = mlx4_init_pd_table(dev);
2600 if (err) {
2601 mlx4_err(dev, "Failed to initialize protection domain table, aborting\n");
2602 goto err_kar_unmap;
2603 }
2604
2605 err = mlx4_init_xrcd_table(dev);
2606 if (err) {
2607 mlx4_err(dev, "Failed to initialize reliable connection domain table, aborting\n");
2608 goto err_pd_table_free;
2609 }
2610
2611 err = mlx4_init_mr_table(dev);
2612 if (err) {
2613 mlx4_err(dev, "Failed to initialize memory region table, aborting\n");
2614 goto err_xrcd_table_free;
2615 }
2616
2617 if (!mlx4_is_slave(dev)) {
2618 err = mlx4_init_mcg_table(dev);
2619 if (err) {
2620 mlx4_err(dev, "Failed to initialize multicast group table, aborting\n");
2621 goto err_mr_table_free;
2622 }
2623 err = mlx4_config_mad_demux(dev);
2624 if (err) {
2625 mlx4_err(dev, "Failed in config_mad_demux, aborting\n");
2626 goto err_mcg_table_free;
2627 }
2628 }
2629
2630 err = mlx4_init_eq_table(dev);
2631 if (err) {
2632 mlx4_err(dev, "Failed to initialize event queue table, aborting\n");
2633 goto err_mcg_table_free;
2634 }
2635
2636 err = mlx4_cmd_use_events(dev);
2637 if (err) {
2638 mlx4_err(dev, "Failed to switch to event-driven firmware commands, aborting\n");
2639 goto err_eq_table_free;
2640 }
2641
2642 err = mlx4_NOP(dev);
2643 if (err) {
2644 if (dev->flags & MLX4_FLAG_MSI_X) {
2645 mlx4_warn(dev, "NOP command failed to generate MSI-X interrupt IRQ %d)\n",
2646 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2647 mlx4_warn(dev, "Trying again without MSI-X\n");
2648 } else {
2649 mlx4_err(dev, "NOP command failed to generate interrupt (IRQ %d), aborting\n",
2650 priv->eq_table.eq[MLX4_EQ_ASYNC].irq);
2651 mlx4_err(dev, "BIOS or ACPI interrupt routing problem?\n");
2652 }
2653
2654 goto err_cmd_poll;
2655 }
2656
2657 mlx4_dbg(dev, "NOP command IRQ test passed\n");
2658
2659 err = mlx4_init_cq_table(dev);
2660 if (err) {
2661 mlx4_err(dev, "Failed to initialize completion queue table, aborting\n");
2662 goto err_cmd_poll;
2663 }
2664
2665 err = mlx4_init_srq_table(dev);
2666 if (err) {
2667 mlx4_err(dev, "Failed to initialize shared receive queue table, aborting\n");
2668 goto err_cq_table_free;
2669 }
2670
2671 err = mlx4_init_qp_table(dev);
2672 if (err) {
2673 mlx4_err(dev, "Failed to initialize queue pair table, aborting\n");
2674 goto err_srq_table_free;
2675 }
2676
2677 if (!mlx4_is_slave(dev)) {
2678 err = mlx4_init_counters_table(dev);
2679 if (err && err != -ENOENT) {
2680 mlx4_err(dev, "Failed to initialize counters table, aborting\n");
2681 goto err_qp_table_free;
2682 }
2683 }
2684
2685 err = mlx4_allocate_default_counters(dev);
2686 if (err) {
2687 mlx4_err(dev, "Failed to allocate default counters, aborting\n");
2688 goto err_counters_table_free;
2689 }
2690
2691 if (!mlx4_is_slave(dev)) {
2692 for (port = 1; port <= dev->caps.num_ports; port++) {
2693 ib_port_default_caps = 0;
2694 err = mlx4_get_port_ib_caps(dev, port,
2695 &ib_port_default_caps);
2696 if (err)
2697 mlx4_warn(dev, "failed to get port %d default ib capabilities (%d). Continuing with caps = 0\n",
2698 port, err);
2699 dev->caps.ib_port_def_cap[port] = ib_port_default_caps;
2700
2701
2702 if (mlx4_is_master(dev)) {
2703 int i;
2704 for (i = 0; i < dev->num_slaves; i++) {
2705 if (i == mlx4_master_func_num(dev))
2706 continue;
2707 priv->mfunc.master.slave_state[i].ib_cap_mask[port] =
2708 ib_port_default_caps;
2709 }
2710 }
2711
2712 if (mlx4_is_mfunc(dev))
2713 dev->caps.port_ib_mtu[port] = IB_MTU_2048;
2714 else
2715 dev->caps.port_ib_mtu[port] = IB_MTU_4096;
2716
2717 err = mlx4_SET_PORT(dev, port, mlx4_is_master(dev) ?
2718 dev->caps.pkey_table_len[port] : -1);
2719 if (err) {
2720 mlx4_err(dev, "Failed to set port %d, aborting\n",
2721 port);
2722 goto err_default_countes_free;
2723 }
2724 }
2725 }
2726
2727 return 0;
2728
2729err_default_countes_free:
2730 mlx4_cleanup_default_counters(dev);
2731
2732err_counters_table_free:
2733 if (!mlx4_is_slave(dev))
2734 mlx4_cleanup_counters_table(dev);
2735
2736err_qp_table_free:
2737 mlx4_cleanup_qp_table(dev);
2738
2739err_srq_table_free:
2740 mlx4_cleanup_srq_table(dev);
2741
2742err_cq_table_free:
2743 mlx4_cleanup_cq_table(dev);
2744
2745err_cmd_poll:
2746 mlx4_cmd_use_polling(dev);
2747
2748err_eq_table_free:
2749 mlx4_cleanup_eq_table(dev);
2750
2751err_mcg_table_free:
2752 if (!mlx4_is_slave(dev))
2753 mlx4_cleanup_mcg_table(dev);
2754
2755err_mr_table_free:
2756 mlx4_cleanup_mr_table(dev);
2757
2758err_xrcd_table_free:
2759 mlx4_cleanup_xrcd_table(dev);
2760
2761err_pd_table_free:
2762 mlx4_cleanup_pd_table(dev);
2763
2764err_kar_unmap:
2765 iounmap(priv->kar);
2766
2767err_uar_free:
2768 mlx4_uar_free(dev, &priv->driver_uar);
2769
2770err_uar_table_free:
2771 mlx4_cleanup_uar_table(dev);
2772 return err;
2773}
2774
2775static int mlx4_init_affinity_hint(struct mlx4_dev *dev, int port, int eqn)
2776{
2777 int requested_cpu = 0;
2778 struct mlx4_priv *priv = mlx4_priv(dev);
2779 struct mlx4_eq *eq;
2780 int off = 0;
2781 int i;
2782
2783 if (eqn > dev->caps.num_comp_vectors)
2784 return -EINVAL;
2785
2786 for (i = 1; i < port; i++)
2787 off += mlx4_get_eqs_per_port(dev, i);
2788
2789 requested_cpu = eqn - off - !!(eqn > MLX4_EQ_ASYNC);
2790
2791
2792 if (requested_cpu < 0)
2793 return 0;
2794
2795 eq = &priv->eq_table.eq[eqn];
2796
2797 if (!zalloc_cpumask_var(&eq->affinity_mask, GFP_KERNEL))
2798 return -ENOMEM;
2799
2800 cpumask_set_cpu(requested_cpu, eq->affinity_mask);
2801
2802 return 0;
2803}
2804
2805static void mlx4_enable_msi_x(struct mlx4_dev *dev)
2806{
2807 struct mlx4_priv *priv = mlx4_priv(dev);
2808 struct msix_entry *entries;
2809 int i;
2810 int port = 0;
2811
2812 if (msi_x) {
2813 int nreq = min3(dev->caps.num_ports *
2814 (int)num_online_cpus() + 1,
2815 dev->caps.num_eqs - dev->caps.reserved_eqs,
2816 MAX_MSIX);
2817
2818 entries = kcalloc(nreq, sizeof(*entries), GFP_KERNEL);
2819 if (!entries)
2820 goto no_msi;
2821
2822 for (i = 0; i < nreq; ++i)
2823 entries[i].entry = i;
2824
2825 nreq = pci_enable_msix_range(dev->persist->pdev, entries, 2,
2826 nreq);
2827
2828 if (nreq < 0 || nreq < MLX4_EQ_ASYNC) {
2829 kfree(entries);
2830 goto no_msi;
2831 }
2832
2833 dev->caps.num_comp_vectors = nreq - 1;
2834
2835 priv->eq_table.eq[MLX4_EQ_ASYNC].irq = entries[0].vector;
2836 bitmap_zero(priv->eq_table.eq[MLX4_EQ_ASYNC].actv_ports.ports,
2837 dev->caps.num_ports);
2838
2839 for (i = 0; i < dev->caps.num_comp_vectors + 1; i++) {
2840 if (i == MLX4_EQ_ASYNC)
2841 continue;
2842
2843 priv->eq_table.eq[i].irq =
2844 entries[i + 1 - !!(i > MLX4_EQ_ASYNC)].vector;
2845
2846 if (MLX4_IS_LEGACY_EQ_MODE(dev->caps)) {
2847 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2848 dev->caps.num_ports);
2849
2850
2851
2852 } else {
2853 set_bit(port,
2854 priv->eq_table.eq[i].actv_ports.ports);
2855 if (mlx4_init_affinity_hint(dev, port + 1, i))
2856 mlx4_warn(dev, "Couldn't init hint cpumask for EQ %d\n",
2857 i);
2858 }
2859
2860
2861
2862
2863
2864
2865
2866
2867
2868 if ((dev->caps.num_comp_vectors > dev->caps.num_ports) &&
2869 ((i + 1) %
2870 (dev->caps.num_comp_vectors / dev->caps.num_ports)) ==
2871 !!((i + 1) > MLX4_EQ_ASYNC))
2872
2873
2874
2875 port++;
2876 }
2877
2878 dev->flags |= MLX4_FLAG_MSI_X;
2879
2880 kfree(entries);
2881 return;
2882 }
2883
2884no_msi:
2885 dev->caps.num_comp_vectors = 1;
2886
2887 BUG_ON(MLX4_EQ_ASYNC >= 2);
2888 for (i = 0; i < 2; ++i) {
2889 priv->eq_table.eq[i].irq = dev->persist->pdev->irq;
2890 if (i != MLX4_EQ_ASYNC) {
2891 bitmap_fill(priv->eq_table.eq[i].actv_ports.ports,
2892 dev->caps.num_ports);
2893 }
2894 }
2895}
2896
2897static int mlx4_init_port_info(struct mlx4_dev *dev, int port)
2898{
2899 struct devlink *devlink = priv_to_devlink(mlx4_priv(dev));
2900 struct mlx4_port_info *info = &mlx4_priv(dev)->port[port];
2901 int err;
2902
2903 err = devlink_port_register(devlink, &info->devlink_port, port);
2904 if (err)
2905 return err;
2906
2907 info->dev = dev;
2908 info->port = port;
2909 if (!mlx4_is_slave(dev)) {
2910 mlx4_init_mac_table(dev, &info->mac_table);
2911 mlx4_init_vlan_table(dev, &info->vlan_table);
2912 mlx4_init_roce_gid_table(dev, &info->gid_table);
2913 info->base_qpn = mlx4_get_base_qpn(dev, port);
2914 }
2915
2916 sprintf(info->dev_name, "mlx4_port%d", port);
2917 info->port_attr.attr.name = info->dev_name;
2918 if (mlx4_is_mfunc(dev)) {
2919 info->port_attr.attr.mode = 0444;
2920 } else {
2921 info->port_attr.attr.mode = 0644;
2922 info->port_attr.store = set_port_type;
2923 }
2924 info->port_attr.show = show_port_type;
2925 sysfs_attr_init(&info->port_attr.attr);
2926
2927 err = device_create_file(&dev->persist->pdev->dev, &info->port_attr);
2928 if (err) {
2929 mlx4_err(dev, "Failed to create file for port %d\n", port);
2930 devlink_port_unregister(&info->devlink_port);
2931 info->port = -1;
2932 return err;
2933 }
2934
2935 sprintf(info->dev_mtu_name, "mlx4_port%d_mtu", port);
2936 info->port_mtu_attr.attr.name = info->dev_mtu_name;
2937 if (mlx4_is_mfunc(dev)) {
2938 info->port_mtu_attr.attr.mode = 0444;
2939 } else {
2940 info->port_mtu_attr.attr.mode = 0644;
2941 info->port_mtu_attr.store = set_port_ib_mtu;
2942 }
2943 info->port_mtu_attr.show = show_port_ib_mtu;
2944 sysfs_attr_init(&info->port_mtu_attr.attr);
2945
2946 err = device_create_file(&dev->persist->pdev->dev,
2947 &info->port_mtu_attr);
2948 if (err) {
2949 mlx4_err(dev, "Failed to create mtu file for port %d\n", port);
2950 device_remove_file(&info->dev->persist->pdev->dev,
2951 &info->port_attr);
2952 devlink_port_unregister(&info->devlink_port);
2953 info->port = -1;
2954 return err;
2955 }
2956
2957 return 0;
2958}
2959
2960static void mlx4_cleanup_port_info(struct mlx4_port_info *info)
2961{
2962 if (info->port < 0)
2963 return;
2964
2965 device_remove_file(&info->dev->persist->pdev->dev, &info->port_attr);
2966 device_remove_file(&info->dev->persist->pdev->dev,
2967 &info->port_mtu_attr);
2968 devlink_port_unregister(&info->devlink_port);
2969
2970#ifdef CONFIG_RFS_ACCEL
2971 free_irq_cpu_rmap(info->rmap);
2972 info->rmap = NULL;
2973#endif
2974}
2975
2976static int mlx4_init_steering(struct mlx4_dev *dev)
2977{
2978 struct mlx4_priv *priv = mlx4_priv(dev);
2979 int num_entries = dev->caps.num_ports;
2980 int i, j;
2981
2982 priv->steer = kzalloc(sizeof(struct mlx4_steer) * num_entries, GFP_KERNEL);
2983 if (!priv->steer)
2984 return -ENOMEM;
2985
2986 for (i = 0; i < num_entries; i++)
2987 for (j = 0; j < MLX4_NUM_STEERS; j++) {
2988 INIT_LIST_HEAD(&priv->steer[i].promisc_qps[j]);
2989 INIT_LIST_HEAD(&priv->steer[i].steer_entries[j]);
2990 }
2991 return 0;
2992}
2993
2994static void mlx4_clear_steering(struct mlx4_dev *dev)
2995{
2996 struct mlx4_priv *priv = mlx4_priv(dev);
2997 struct mlx4_steer_index *entry, *tmp_entry;
2998 struct mlx4_promisc_qp *pqp, *tmp_pqp;
2999 int num_entries = dev->caps.num_ports;
3000 int i, j;
3001
3002 for (i = 0; i < num_entries; i++) {
3003 for (j = 0; j < MLX4_NUM_STEERS; j++) {
3004 list_for_each_entry_safe(pqp, tmp_pqp,
3005 &priv->steer[i].promisc_qps[j],
3006 list) {
3007 list_del(&pqp->list);
3008 kfree(pqp);
3009 }
3010 list_for_each_entry_safe(entry, tmp_entry,
3011 &priv->steer[i].steer_entries[j],
3012 list) {
3013 list_del(&entry->list);
3014 list_for_each_entry_safe(pqp, tmp_pqp,
3015 &entry->duplicates,
3016 list) {
3017 list_del(&pqp->list);
3018 kfree(pqp);
3019 }
3020 kfree(entry);
3021 }
3022 }
3023 }
3024 kfree(priv->steer);
3025}
3026
3027static int extended_func_num(struct pci_dev *pdev)
3028{
3029 return PCI_SLOT(pdev->devfn) * 8 + PCI_FUNC(pdev->devfn);
3030}
3031
3032#define MLX4_OWNER_BASE 0x8069c
3033#define MLX4_OWNER_SIZE 4
3034
3035static int mlx4_get_ownership(struct mlx4_dev *dev)
3036{
3037 void __iomem *owner;
3038 u32 ret;
3039
3040 if (pci_channel_offline(dev->persist->pdev))
3041 return -EIO;
3042
3043 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3044 MLX4_OWNER_BASE,
3045 MLX4_OWNER_SIZE);
3046 if (!owner) {
3047 mlx4_err(dev, "Failed to obtain ownership bit\n");
3048 return -ENOMEM;
3049 }
3050
3051 ret = readl(owner);
3052 iounmap(owner);
3053 return (int) !!ret;
3054}
3055
3056static void mlx4_free_ownership(struct mlx4_dev *dev)
3057{
3058 void __iomem *owner;
3059
3060 if (pci_channel_offline(dev->persist->pdev))
3061 return;
3062
3063 owner = ioremap(pci_resource_start(dev->persist->pdev, 0) +
3064 MLX4_OWNER_BASE,
3065 MLX4_OWNER_SIZE);
3066 if (!owner) {
3067 mlx4_err(dev, "Failed to obtain ownership bit\n");
3068 return;
3069 }
3070 writel(0, owner);
3071 msleep(1000);
3072 iounmap(owner);
3073}
3074
3075#define SRIOV_VALID_STATE(flags) (!!((flags) & MLX4_FLAG_SRIOV) ==\
3076 !!((flags) & MLX4_FLAG_MASTER))
3077
3078static u64 mlx4_enable_sriov(struct mlx4_dev *dev, struct pci_dev *pdev,
3079 u8 total_vfs, int existing_vfs, int reset_flow)
3080{
3081 u64 dev_flags = dev->flags;
3082 int err = 0;
3083 int fw_enabled_sriov_vfs = min(pci_sriov_get_totalvfs(pdev),
3084 MLX4_MAX_NUM_VF);
3085
3086 if (reset_flow) {
3087 dev->dev_vfs = kcalloc(total_vfs, sizeof(*dev->dev_vfs),
3088 GFP_KERNEL);
3089 if (!dev->dev_vfs)
3090 goto free_mem;
3091 return dev_flags;
3092 }
3093
3094 atomic_inc(&pf_loading);
3095 if (dev->flags & MLX4_FLAG_SRIOV) {
3096 if (existing_vfs != total_vfs) {
3097 mlx4_err(dev, "SR-IOV was already enabled, but with num_vfs (%d) different than requested (%d)\n",
3098 existing_vfs, total_vfs);
3099 total_vfs = existing_vfs;
3100 }
3101 }
3102
3103 dev->dev_vfs = kzalloc(total_vfs * sizeof(*dev->dev_vfs), GFP_KERNEL);
3104 if (NULL == dev->dev_vfs) {
3105 mlx4_err(dev, "Failed to allocate memory for VFs\n");
3106 goto disable_sriov;
3107 }
3108
3109 if (!(dev->flags & MLX4_FLAG_SRIOV)) {
3110 if (total_vfs > fw_enabled_sriov_vfs) {
3111 mlx4_err(dev, "requested vfs (%d) > available vfs (%d). Continuing without SR_IOV\n",
3112 total_vfs, fw_enabled_sriov_vfs);
3113 err = -ENOMEM;
3114 goto disable_sriov;
3115 }
3116 mlx4_warn(dev, "Enabling SR-IOV with %d VFs\n", total_vfs);
3117 err = pci_enable_sriov(pdev, total_vfs);
3118 }
3119 if (err) {
3120 mlx4_err(dev, "Failed to enable SR-IOV, continuing without SR-IOV (err = %d)\n",
3121 err);
3122 goto disable_sriov;
3123 } else {
3124 mlx4_warn(dev, "Running in master mode\n");
3125 dev_flags |= MLX4_FLAG_SRIOV |
3126 MLX4_FLAG_MASTER;
3127 dev_flags &= ~MLX4_FLAG_SLAVE;
3128 dev->persist->num_vfs = total_vfs;
3129 }
3130 return dev_flags;
3131
3132disable_sriov:
3133 atomic_dec(&pf_loading);
3134free_mem:
3135 dev->persist->num_vfs = 0;
3136 kfree(dev->dev_vfs);
3137 dev->dev_vfs = NULL;
3138 return dev_flags & ~MLX4_FLAG_MASTER;
3139}
3140
3141enum {
3142 MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64 = -1,
3143};
3144
3145static int mlx4_check_dev_cap(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap,
3146 int *nvfs)
3147{
3148 int requested_vfs = nvfs[0] + nvfs[1] + nvfs[2];
3149
3150 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_80_VFS) &&
3151 requested_vfs >= 64) {
3152 mlx4_err(dev, "Requested %d VFs, but FW does not support more than 64\n",
3153 requested_vfs);
3154 return MLX4_DEV_CAP_CHECK_NUM_VFS_ABOVE_64;
3155 }
3156 return 0;
3157}
3158
3159static int mlx4_pci_enable_device(struct mlx4_dev *dev)
3160{
3161 struct pci_dev *pdev = dev->persist->pdev;
3162 int err = 0;
3163
3164 mutex_lock(&dev->persist->pci_status_mutex);
3165 if (dev->persist->pci_status == MLX4_PCI_STATUS_DISABLED) {
3166 err = pci_enable_device(pdev);
3167 if (!err)
3168 dev->persist->pci_status = MLX4_PCI_STATUS_ENABLED;
3169 }
3170 mutex_unlock(&dev->persist->pci_status_mutex);
3171
3172 return err;
3173}
3174
3175static void mlx4_pci_disable_device(struct mlx4_dev *dev)
3176{
3177 struct pci_dev *pdev = dev->persist->pdev;
3178
3179 mutex_lock(&dev->persist->pci_status_mutex);
3180 if (dev->persist->pci_status == MLX4_PCI_STATUS_ENABLED) {
3181 pci_disable_device(pdev);
3182 dev->persist->pci_status = MLX4_PCI_STATUS_DISABLED;
3183 }
3184 mutex_unlock(&dev->persist->pci_status_mutex);
3185}
3186
3187static int mlx4_load_one(struct pci_dev *pdev, int pci_dev_data,
3188 int total_vfs, int *nvfs, struct mlx4_priv *priv,
3189 int reset_flow)
3190{
3191 struct mlx4_dev *dev;
3192 unsigned sum = 0;
3193 int err;
3194 int port;
3195 int i;
3196 struct mlx4_dev_cap *dev_cap = NULL;
3197 int existing_vfs = 0;
3198
3199 dev = &priv->dev;
3200
3201 INIT_LIST_HEAD(&priv->ctx_list);
3202 spin_lock_init(&priv->ctx_lock);
3203
3204 mutex_init(&priv->port_mutex);
3205 mutex_init(&priv->bond_mutex);
3206
3207 INIT_LIST_HEAD(&priv->pgdir_list);
3208 mutex_init(&priv->pgdir_mutex);
3209 spin_lock_init(&priv->cmd.context_lock);
3210
3211 INIT_LIST_HEAD(&priv->bf_list);
3212 mutex_init(&priv->bf_mutex);
3213
3214 dev->rev_id = pdev->revision;
3215 dev->numa_node = dev_to_node(&pdev->dev);
3216
3217
3218 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3219 mlx4_warn(dev, "Detected virtual function - running in slave mode\n");
3220 dev->flags |= MLX4_FLAG_SLAVE;
3221 } else {
3222
3223
3224
3225 err = mlx4_get_ownership(dev);
3226 if (err) {
3227 if (err < 0)
3228 return err;
3229 else {
3230 mlx4_warn(dev, "Multiple PFs not yet supported - Skipping PF\n");
3231 return -EINVAL;
3232 }
3233 }
3234
3235 atomic_set(&priv->opreq_count, 0);
3236 INIT_WORK(&priv->opreq_task, mlx4_opreq_action);
3237
3238
3239
3240
3241
3242
3243 err = mlx4_reset(dev);
3244 if (err) {
3245 mlx4_err(dev, "Failed to reset HCA, aborting\n");
3246 goto err_sriov;
3247 }
3248
3249 if (total_vfs) {
3250 dev->flags = MLX4_FLAG_MASTER;
3251 existing_vfs = pci_num_vf(pdev);
3252 if (existing_vfs)
3253 dev->flags |= MLX4_FLAG_SRIOV;
3254 dev->persist->num_vfs = total_vfs;
3255 }
3256 }
3257
3258
3259
3260
3261 dev->persist->state = MLX4_DEVICE_STATE_UP;
3262
3263slave_start:
3264 err = mlx4_cmd_init(dev);
3265 if (err) {
3266 mlx4_err(dev, "Failed to init command interface, aborting\n");
3267 goto err_sriov;
3268 }
3269
3270
3271
3272
3273 if (mlx4_is_mfunc(dev)) {
3274 if (mlx4_is_master(dev)) {
3275 dev->num_slaves = MLX4_MAX_NUM_SLAVES;
3276
3277 } else {
3278 dev->num_slaves = 0;
3279 err = mlx4_multi_func_init(dev);
3280 if (err) {
3281 mlx4_err(dev, "Failed to init slave mfunc interface, aborting\n");
3282 goto err_cmd;
3283 }
3284 }
3285 }
3286
3287 err = mlx4_init_fw(dev);
3288 if (err) {
3289 mlx4_err(dev, "Failed to init fw, aborting.\n");
3290 goto err_mfunc;
3291 }
3292
3293 if (mlx4_is_master(dev)) {
3294
3295 if (!dev_cap) {
3296 dev_cap = kzalloc(sizeof(*dev_cap), GFP_KERNEL);
3297
3298 if (!dev_cap) {
3299 err = -ENOMEM;
3300 goto err_fw;
3301 }
3302
3303 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3304 if (err) {
3305 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3306 goto err_fw;
3307 }
3308
3309 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3310 goto err_fw;
3311
3312 if (!(dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3313 u64 dev_flags = mlx4_enable_sriov(dev, pdev,
3314 total_vfs,
3315 existing_vfs,
3316 reset_flow);
3317
3318 mlx4_close_fw(dev);
3319 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3320 dev->flags = dev_flags;
3321 if (!SRIOV_VALID_STATE(dev->flags)) {
3322 mlx4_err(dev, "Invalid SRIOV state\n");
3323 goto err_sriov;
3324 }
3325 err = mlx4_reset(dev);
3326 if (err) {
3327 mlx4_err(dev, "Failed to reset HCA, aborting.\n");
3328 goto err_sriov;
3329 }
3330 goto slave_start;
3331 }
3332 } else {
3333
3334
3335
3336
3337 memset(dev_cap, 0, sizeof(*dev_cap));
3338 err = mlx4_QUERY_DEV_CAP(dev, dev_cap);
3339 if (err) {
3340 mlx4_err(dev, "QUERY_DEV_CAP command failed, aborting.\n");
3341 goto err_fw;
3342 }
3343
3344 if (mlx4_check_dev_cap(dev, dev_cap, nvfs))
3345 goto err_fw;
3346 }
3347 }
3348
3349 err = mlx4_init_hca(dev);
3350 if (err) {
3351 if (err == -EACCES) {
3352
3353
3354 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3355
3356 if (dev->flags & MLX4_FLAG_SRIOV) {
3357 if (!existing_vfs)
3358 pci_disable_sriov(pdev);
3359 if (mlx4_is_master(dev) && !reset_flow)
3360 atomic_dec(&pf_loading);
3361 dev->flags &= ~MLX4_FLAG_SRIOV;
3362 }
3363 if (!mlx4_is_slave(dev))
3364 mlx4_free_ownership(dev);
3365 dev->flags |= MLX4_FLAG_SLAVE;
3366 dev->flags &= ~MLX4_FLAG_MASTER;
3367 goto slave_start;
3368 } else
3369 goto err_fw;
3370 }
3371
3372 if (mlx4_is_master(dev) && (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS)) {
3373 u64 dev_flags = mlx4_enable_sriov(dev, pdev, total_vfs,
3374 existing_vfs, reset_flow);
3375
3376 if ((dev->flags ^ dev_flags) & (MLX4_FLAG_MASTER | MLX4_FLAG_SLAVE)) {
3377 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_VHCR);
3378 dev->flags = dev_flags;
3379 err = mlx4_cmd_init(dev);
3380 if (err) {
3381
3382
3383
3384 mlx4_err(dev, "Failed to init VHCR command interface, aborting\n");
3385 goto err_close;
3386 }
3387 } else {
3388 dev->flags = dev_flags;
3389 }
3390
3391 if (!SRIOV_VALID_STATE(dev->flags)) {
3392 mlx4_err(dev, "Invalid SRIOV state\n");
3393 goto err_close;
3394 }
3395 }
3396
3397
3398
3399
3400
3401 if (!mlx4_is_slave(dev))
3402 pcie_print_link_status(dev->persist->pdev);
3403
3404
3405
3406 if (mlx4_is_master(dev)) {
3407 if (dev->caps.num_ports < 2 &&
3408 num_vfs_argc > 1) {
3409 err = -EINVAL;
3410 mlx4_err(dev,
3411 "Error: Trying to configure VFs on port 2, but HCA has only %d physical ports\n",
3412 dev->caps.num_ports);
3413 goto err_close;
3414 }
3415 memcpy(dev->persist->nvfs, nvfs, sizeof(dev->persist->nvfs));
3416
3417 for (i = 0;
3418 i < sizeof(dev->persist->nvfs)/
3419 sizeof(dev->persist->nvfs[0]); i++) {
3420 unsigned j;
3421
3422 for (j = 0; j < dev->persist->nvfs[i]; ++sum, ++j) {
3423 dev->dev_vfs[sum].min_port = i < 2 ? i + 1 : 1;
3424 dev->dev_vfs[sum].n_ports = i < 2 ? 1 :
3425 dev->caps.num_ports;
3426 }
3427 }
3428
3429
3430
3431
3432 err = mlx4_multi_func_init(dev);
3433 if (err) {
3434 mlx4_err(dev, "Failed to init master mfunc interface, aborting.\n");
3435 goto err_close;
3436 }
3437 }
3438
3439 err = mlx4_alloc_eq_table(dev);
3440 if (err)
3441 goto err_master_mfunc;
3442
3443 bitmap_zero(priv->msix_ctl.pool_bm, MAX_MSIX);
3444 mutex_init(&priv->msix_ctl.pool_lock);
3445
3446 mlx4_enable_msi_x(dev);
3447 if ((mlx4_is_mfunc(dev)) &&
3448 !(dev->flags & MLX4_FLAG_MSI_X)) {
3449 err = -EOPNOTSUPP;
3450 mlx4_err(dev, "INTx is not supported in multi-function mode, aborting\n");
3451 goto err_free_eq;
3452 }
3453
3454 if (!mlx4_is_slave(dev)) {
3455 err = mlx4_init_steering(dev);
3456 if (err)
3457 goto err_disable_msix;
3458 }
3459
3460 mlx4_init_quotas(dev);
3461
3462 err = mlx4_setup_hca(dev);
3463 if (err == -EBUSY && (dev->flags & MLX4_FLAG_MSI_X) &&
3464 !mlx4_is_mfunc(dev)) {
3465 dev->flags &= ~MLX4_FLAG_MSI_X;
3466 dev->caps.num_comp_vectors = 1;
3467 pci_disable_msix(pdev);
3468 err = mlx4_setup_hca(dev);
3469 }
3470
3471 if (err)
3472 goto err_steer;
3473
3474
3475
3476
3477 if (mlx4_is_master(dev)) {
3478 err = mlx4_ARM_COMM_CHANNEL(dev);
3479 if (err) {
3480 mlx4_err(dev, " Failed to arm comm channel eq: %x\n",
3481 err);
3482 goto err_steer;
3483 }
3484 }
3485
3486 for (port = 1; port <= dev->caps.num_ports; port++) {
3487 err = mlx4_init_port_info(dev, port);
3488 if (err)
3489 goto err_port;
3490 }
3491
3492 priv->v2p.port1 = 1;
3493 priv->v2p.port2 = 2;
3494
3495 err = mlx4_register_device(dev);
3496 if (err)
3497 goto err_port;
3498
3499 mlx4_request_modules(dev);
3500
3501 mlx4_sense_init(dev);
3502 mlx4_start_sense(dev);
3503
3504 priv->removed = 0;
3505
3506 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3507 atomic_dec(&pf_loading);
3508
3509 kfree(dev_cap);
3510 return 0;
3511
3512err_port:
3513 for (--port; port >= 1; --port)
3514 mlx4_cleanup_port_info(&priv->port[port]);
3515
3516 mlx4_cleanup_default_counters(dev);
3517 if (!mlx4_is_slave(dev))
3518 mlx4_cleanup_counters_table(dev);
3519 mlx4_cleanup_qp_table(dev);
3520 mlx4_cleanup_srq_table(dev);
3521 mlx4_cleanup_cq_table(dev);
3522 mlx4_cmd_use_polling(dev);
3523 mlx4_cleanup_eq_table(dev);
3524 mlx4_cleanup_mcg_table(dev);
3525 mlx4_cleanup_mr_table(dev);
3526 mlx4_cleanup_xrcd_table(dev);
3527 mlx4_cleanup_pd_table(dev);
3528 mlx4_cleanup_uar_table(dev);
3529
3530err_steer:
3531 if (!mlx4_is_slave(dev))
3532 mlx4_clear_steering(dev);
3533
3534err_disable_msix:
3535 if (dev->flags & MLX4_FLAG_MSI_X)
3536 pci_disable_msix(pdev);
3537
3538err_free_eq:
3539 mlx4_free_eq_table(dev);
3540
3541err_master_mfunc:
3542 if (mlx4_is_master(dev)) {
3543 mlx4_free_resource_tracker(dev, RES_TR_FREE_STRUCTS_ONLY);
3544 mlx4_multi_func_cleanup(dev);
3545 }
3546
3547 if (mlx4_is_slave(dev))
3548 mlx4_slave_destroy_special_qp_cap(dev);
3549
3550err_close:
3551 mlx4_close_hca(dev);
3552
3553err_fw:
3554 mlx4_close_fw(dev);
3555
3556err_mfunc:
3557 if (mlx4_is_slave(dev))
3558 mlx4_multi_func_cleanup(dev);
3559
3560err_cmd:
3561 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3562
3563err_sriov:
3564 if (dev->flags & MLX4_FLAG_SRIOV && !existing_vfs) {
3565 pci_disable_sriov(pdev);
3566 dev->flags &= ~MLX4_FLAG_SRIOV;
3567 }
3568
3569 if (mlx4_is_master(dev) && dev->persist->num_vfs && !reset_flow)
3570 atomic_dec(&pf_loading);
3571
3572 kfree(priv->dev.dev_vfs);
3573
3574 if (!mlx4_is_slave(dev))
3575 mlx4_free_ownership(dev);
3576
3577 kfree(dev_cap);
3578 return err;
3579}
3580
3581static int __mlx4_init_one(struct pci_dev *pdev, int pci_dev_data,
3582 struct mlx4_priv *priv)
3583{
3584 int err;
3585 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3586 int prb_vf[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3587 const int param_map[MLX4_MAX_PORTS + 1][MLX4_MAX_PORTS + 1] = {
3588 {2, 0, 0}, {0, 1, 2}, {0, 1, 2} };
3589 unsigned total_vfs = 0;
3590 unsigned int i;
3591
3592 pr_info(DRV_NAME ": Initializing %s\n", pci_name(pdev));
3593
3594 err = mlx4_pci_enable_device(&priv->dev);
3595 if (err) {
3596 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
3597 return err;
3598 }
3599
3600
3601
3602
3603
3604 for (i = 0; i < ARRAY_SIZE(nvfs) && i < num_vfs_argc;
3605 total_vfs += nvfs[param_map[num_vfs_argc - 1][i]], i++) {
3606 nvfs[param_map[num_vfs_argc - 1][i]] = num_vfs[i];
3607 if (nvfs[i] < 0) {
3608 dev_err(&pdev->dev, "num_vfs module parameter cannot be negative\n");
3609 err = -EINVAL;
3610 goto err_disable_pdev;
3611 }
3612 }
3613 for (i = 0; i < ARRAY_SIZE(prb_vf) && i < probe_vfs_argc;
3614 i++) {
3615 prb_vf[param_map[probe_vfs_argc - 1][i]] = probe_vf[i];
3616 if (prb_vf[i] < 0 || prb_vf[i] > nvfs[i]) {
3617 dev_err(&pdev->dev, "probe_vf module parameter cannot be negative or greater than num_vfs\n");
3618 err = -EINVAL;
3619 goto err_disable_pdev;
3620 }
3621 }
3622 if (total_vfs > MLX4_MAX_NUM_VF) {
3623 dev_err(&pdev->dev,
3624 "Requested more VF's (%d) than allowed by hw (%d)\n",
3625 total_vfs, MLX4_MAX_NUM_VF);
3626 err = -EINVAL;
3627 goto err_disable_pdev;
3628 }
3629
3630 for (i = 0; i < MLX4_MAX_PORTS; i++) {
3631 if (nvfs[i] + nvfs[2] > MLX4_MAX_NUM_VF_P_PORT) {
3632 dev_err(&pdev->dev,
3633 "Requested more VF's (%d) for port (%d) than allowed by driver (%d)\n",
3634 nvfs[i] + nvfs[2], i + 1,
3635 MLX4_MAX_NUM_VF_P_PORT);
3636 err = -EINVAL;
3637 goto err_disable_pdev;
3638 }
3639 }
3640
3641
3642 if (!(pci_dev_data & MLX4_PCI_DEV_IS_VF) &&
3643 !(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
3644 dev_err(&pdev->dev, "Missing DCS, aborting (driver_data: 0x%x, pci_resource_flags(pdev, 0):0x%lx)\n",
3645 pci_dev_data, pci_resource_flags(pdev, 0));
3646 err = -ENODEV;
3647 goto err_disable_pdev;
3648 }
3649 if (!(pci_resource_flags(pdev, 2) & IORESOURCE_MEM)) {
3650 dev_err(&pdev->dev, "Missing UAR, aborting\n");
3651 err = -ENODEV;
3652 goto err_disable_pdev;
3653 }
3654
3655 err = pci_request_regions(pdev, DRV_NAME);
3656 if (err) {
3657 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
3658 goto err_disable_pdev;
3659 }
3660
3661 pci_set_master(pdev);
3662
3663 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
3664 if (err) {
3665 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
3666 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
3667 if (err) {
3668 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
3669 goto err_release_regions;
3670 }
3671 }
3672 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
3673 if (err) {
3674 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
3675 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
3676 if (err) {
3677 dev_err(&pdev->dev, "Can't set consistent PCI DMA mask, aborting\n");
3678 goto err_release_regions;
3679 }
3680 }
3681
3682
3683 dma_set_max_seg_size(&pdev->dev, 1024 * 1024 * 1024);
3684
3685 if (pci_dev_data & MLX4_PCI_DEV_IS_VF) {
3686
3687
3688
3689 if (total_vfs) {
3690 unsigned vfs_offset = 0;
3691
3692 for (i = 0; i < ARRAY_SIZE(nvfs) &&
3693 vfs_offset + nvfs[i] < extended_func_num(pdev);
3694 vfs_offset += nvfs[i], i++)
3695 ;
3696 if (i == ARRAY_SIZE(nvfs)) {
3697 err = -ENODEV;
3698 goto err_release_regions;
3699 }
3700 if ((extended_func_num(pdev) - vfs_offset)
3701 > prb_vf[i]) {
3702 dev_warn(&pdev->dev, "Skipping virtual function:%d\n",
3703 extended_func_num(pdev));
3704 err = -ENODEV;
3705 goto err_release_regions;
3706 }
3707 }
3708 }
3709
3710 err = mlx4_catas_init(&priv->dev);
3711 if (err)
3712 goto err_release_regions;
3713
3714 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 0);
3715 if (err)
3716 goto err_catas;
3717
3718 return 0;
3719
3720err_catas:
3721 mlx4_catas_end(&priv->dev);
3722
3723err_release_regions:
3724 pci_release_regions(pdev);
3725
3726err_disable_pdev:
3727 mlx4_pci_disable_device(&priv->dev);
3728 return err;
3729}
3730
3731static int mlx4_devlink_port_type_set(struct devlink_port *devlink_port,
3732 enum devlink_port_type port_type)
3733{
3734 struct mlx4_port_info *info = container_of(devlink_port,
3735 struct mlx4_port_info,
3736 devlink_port);
3737 enum mlx4_port_type mlx4_port_type;
3738
3739 switch (port_type) {
3740 case DEVLINK_PORT_TYPE_AUTO:
3741 mlx4_port_type = MLX4_PORT_TYPE_AUTO;
3742 break;
3743 case DEVLINK_PORT_TYPE_ETH:
3744 mlx4_port_type = MLX4_PORT_TYPE_ETH;
3745 break;
3746 case DEVLINK_PORT_TYPE_IB:
3747 mlx4_port_type = MLX4_PORT_TYPE_IB;
3748 break;
3749 default:
3750 return -EOPNOTSUPP;
3751 }
3752
3753 return __set_port_type(info, mlx4_port_type);
3754}
3755
3756static const struct devlink_ops mlx4_devlink_ops = {
3757 .port_type_set = mlx4_devlink_port_type_set,
3758};
3759
3760static int mlx4_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
3761{
3762 struct devlink *devlink;
3763 struct mlx4_priv *priv;
3764 struct mlx4_dev *dev;
3765 int ret;
3766
3767 printk_once(KERN_INFO "%s", mlx4_version);
3768
3769 devlink = devlink_alloc(&mlx4_devlink_ops, sizeof(*priv));
3770 if (!devlink)
3771 return -ENOMEM;
3772 priv = devlink_priv(devlink);
3773
3774 dev = &priv->dev;
3775 dev->persist = kzalloc(sizeof(*dev->persist), GFP_KERNEL);
3776 if (!dev->persist) {
3777 ret = -ENOMEM;
3778 goto err_devlink_free;
3779 }
3780 dev->persist->pdev = pdev;
3781 dev->persist->dev = dev;
3782 pci_set_drvdata(pdev, dev->persist);
3783 priv->pci_dev_data = id->driver_data;
3784 mutex_init(&dev->persist->device_state_mutex);
3785 mutex_init(&dev->persist->interface_state_mutex);
3786 mutex_init(&dev->persist->pci_status_mutex);
3787
3788 ret = devlink_register(devlink, &pdev->dev);
3789 if (ret)
3790 goto err_persist_free;
3791
3792 ret = __mlx4_init_one(pdev, id->driver_data, priv);
3793 if (ret)
3794 goto err_devlink_unregister;
3795
3796 pci_save_state(pdev);
3797 return 0;
3798
3799err_devlink_unregister:
3800 devlink_unregister(devlink);
3801err_persist_free:
3802 kfree(dev->persist);
3803err_devlink_free:
3804 devlink_free(devlink);
3805 return ret;
3806}
3807
3808static void mlx4_clean_dev(struct mlx4_dev *dev)
3809{
3810 struct mlx4_dev_persistent *persist = dev->persist;
3811 struct mlx4_priv *priv = mlx4_priv(dev);
3812 unsigned long flags = (dev->flags & RESET_PERSIST_MASK_FLAGS);
3813
3814 memset(priv, 0, sizeof(*priv));
3815 priv->dev.persist = persist;
3816 priv->dev.flags = flags;
3817}
3818
3819static void mlx4_unload_one(struct pci_dev *pdev)
3820{
3821 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3822 struct mlx4_dev *dev = persist->dev;
3823 struct mlx4_priv *priv = mlx4_priv(dev);
3824 int pci_dev_data;
3825 int p, i;
3826
3827 if (priv->removed)
3828 return;
3829
3830
3831 for (i = 0; i < dev->caps.num_ports; i++) {
3832 dev->persist->curr_port_type[i] = dev->caps.port_type[i + 1];
3833 dev->persist->curr_port_poss_type[i] = dev->caps.
3834 possible_type[i + 1];
3835 }
3836
3837 pci_dev_data = priv->pci_dev_data;
3838
3839 mlx4_stop_sense(dev);
3840 mlx4_unregister_device(dev);
3841
3842 for (p = 1; p <= dev->caps.num_ports; p++) {
3843 mlx4_cleanup_port_info(&priv->port[p]);
3844 mlx4_CLOSE_PORT(dev, p);
3845 }
3846
3847 if (mlx4_is_master(dev))
3848 mlx4_free_resource_tracker(dev,
3849 RES_TR_FREE_SLAVES_ONLY);
3850
3851 mlx4_cleanup_default_counters(dev);
3852 if (!mlx4_is_slave(dev))
3853 mlx4_cleanup_counters_table(dev);
3854 mlx4_cleanup_qp_table(dev);
3855 mlx4_cleanup_srq_table(dev);
3856 mlx4_cleanup_cq_table(dev);
3857 mlx4_cmd_use_polling(dev);
3858 mlx4_cleanup_eq_table(dev);
3859 mlx4_cleanup_mcg_table(dev);
3860 mlx4_cleanup_mr_table(dev);
3861 mlx4_cleanup_xrcd_table(dev);
3862 mlx4_cleanup_pd_table(dev);
3863
3864 if (mlx4_is_master(dev))
3865 mlx4_free_resource_tracker(dev,
3866 RES_TR_FREE_STRUCTS_ONLY);
3867
3868 iounmap(priv->kar);
3869 mlx4_uar_free(dev, &priv->driver_uar);
3870 mlx4_cleanup_uar_table(dev);
3871 if (!mlx4_is_slave(dev))
3872 mlx4_clear_steering(dev);
3873 mlx4_free_eq_table(dev);
3874 if (mlx4_is_master(dev))
3875 mlx4_multi_func_cleanup(dev);
3876 mlx4_close_hca(dev);
3877 mlx4_close_fw(dev);
3878 if (mlx4_is_slave(dev))
3879 mlx4_multi_func_cleanup(dev);
3880 mlx4_cmd_cleanup(dev, MLX4_CMD_CLEANUP_ALL);
3881
3882 if (dev->flags & MLX4_FLAG_MSI_X)
3883 pci_disable_msix(pdev);
3884
3885 if (!mlx4_is_slave(dev))
3886 mlx4_free_ownership(dev);
3887
3888 mlx4_slave_destroy_special_qp_cap(dev);
3889 kfree(dev->dev_vfs);
3890
3891 mlx4_clean_dev(dev);
3892 priv->pci_dev_data = pci_dev_data;
3893 priv->removed = 1;
3894}
3895
3896static void mlx4_remove_one(struct pci_dev *pdev)
3897{
3898 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3899 struct mlx4_dev *dev = persist->dev;
3900 struct mlx4_priv *priv = mlx4_priv(dev);
3901 struct devlink *devlink = priv_to_devlink(priv);
3902 int active_vfs = 0;
3903
3904 if (mlx4_is_slave(dev))
3905 persist->interface_state |= MLX4_INTERFACE_STATE_NOWAIT;
3906
3907 mutex_lock(&persist->interface_state_mutex);
3908 persist->interface_state |= MLX4_INTERFACE_STATE_DELETION;
3909 mutex_unlock(&persist->interface_state_mutex);
3910
3911
3912 if (mlx4_is_master(dev) && dev->flags & MLX4_FLAG_SRIOV) {
3913 active_vfs = mlx4_how_many_lives_vf(dev);
3914 if (active_vfs) {
3915 pr_warn("Removing PF when there are active VF's !!\n");
3916 pr_warn("Will not disable SR-IOV.\n");
3917 }
3918 }
3919
3920
3921
3922
3923 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
3924 mlx4_unload_one(pdev);
3925 else
3926 mlx4_info(dev, "%s: interface is down\n", __func__);
3927 mlx4_catas_end(dev);
3928 if (dev->flags & MLX4_FLAG_SRIOV && !active_vfs) {
3929 mlx4_warn(dev, "Disabling SR-IOV\n");
3930 pci_disable_sriov(pdev);
3931 }
3932
3933 pci_release_regions(pdev);
3934 mlx4_pci_disable_device(dev);
3935 devlink_unregister(devlink);
3936 kfree(dev->persist);
3937 devlink_free(devlink);
3938}
3939
3940static int restore_current_port_types(struct mlx4_dev *dev,
3941 enum mlx4_port_type *types,
3942 enum mlx4_port_type *poss_types)
3943{
3944 struct mlx4_priv *priv = mlx4_priv(dev);
3945 int err, i;
3946
3947 mlx4_stop_sense(dev);
3948
3949 mutex_lock(&priv->port_mutex);
3950 for (i = 0; i < dev->caps.num_ports; i++)
3951 dev->caps.possible_type[i + 1] = poss_types[i];
3952 err = mlx4_change_port_types(dev, types);
3953 mlx4_start_sense(dev);
3954 mutex_unlock(&priv->port_mutex);
3955
3956 return err;
3957}
3958
3959int mlx4_restart_one(struct pci_dev *pdev)
3960{
3961 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
3962 struct mlx4_dev *dev = persist->dev;
3963 struct mlx4_priv *priv = mlx4_priv(dev);
3964 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
3965 int pci_dev_data, err, total_vfs;
3966
3967 pci_dev_data = priv->pci_dev_data;
3968 total_vfs = dev->persist->num_vfs;
3969 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
3970
3971 mlx4_unload_one(pdev);
3972 err = mlx4_load_one(pdev, pci_dev_data, total_vfs, nvfs, priv, 1);
3973 if (err) {
3974 mlx4_err(dev, "%s: ERROR: mlx4_load_one failed, pci_name=%s, err=%d\n",
3975 __func__, pci_name(pdev), err);
3976 return err;
3977 }
3978
3979 err = restore_current_port_types(dev, dev->persist->curr_port_type,
3980 dev->persist->curr_port_poss_type);
3981 if (err)
3982 mlx4_err(dev, "could not restore original port types (%d)\n",
3983 err);
3984
3985 return err;
3986}
3987
3988#define MLX_SP(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_FORCE_SENSE_PORT }
3989#define MLX_VF(id) { PCI_VDEVICE(MELLANOX, id), MLX4_PCI_DEV_IS_VF }
3990#define MLX_GN(id) { PCI_VDEVICE(MELLANOX, id), 0 }
3991
3992static const struct pci_device_id mlx4_pci_table[] = {
3993#ifdef CONFIG_MLX4_CORE_GEN2
3994
3995 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_SDR),
3996 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR),
3997 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR),
3998 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2),
3999 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2),
4000 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN),
4001 MLX_SP(PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2),
4002
4003 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN),
4004 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2),
4005
4006 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2),
4007
4008 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2),
4009
4010 MLX_SP(PCI_DEVICE_ID_MELLANOX_CONNECTX2),
4011
4012 MLX_VF(0x1002),
4013#endif
4014
4015 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3),
4016 MLX_VF(0x1004),
4017 MLX_GN(0x1005),
4018 MLX_GN(0x1006),
4019 MLX_GN(PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO),
4020 MLX_GN(0x1008),
4021 MLX_GN(0x1009),
4022 MLX_GN(0x100a),
4023 MLX_GN(0x100b),
4024 MLX_GN(0x100c),
4025 MLX_GN(0x100d),
4026 MLX_GN(0x100e),
4027 MLX_GN(0x100f),
4028 MLX_GN(0x1010),
4029
4030
4031
4032
4033
4034
4035 { 0, }
4036};
4037
4038MODULE_DEVICE_TABLE(pci, mlx4_pci_table);
4039
4040static pci_ers_result_t mlx4_pci_err_detected(struct pci_dev *pdev,
4041 pci_channel_state_t state)
4042{
4043 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4044
4045 mlx4_err(persist->dev, "mlx4_pci_err_detected was called\n");
4046 mlx4_enter_error_state(persist);
4047
4048 mutex_lock(&persist->interface_state_mutex);
4049 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4050 mlx4_unload_one(pdev);
4051
4052 mutex_unlock(&persist->interface_state_mutex);
4053 if (state == pci_channel_io_perm_failure)
4054 return PCI_ERS_RESULT_DISCONNECT;
4055
4056 mlx4_pci_disable_device(persist->dev);
4057 return PCI_ERS_RESULT_NEED_RESET;
4058}
4059
4060static pci_ers_result_t mlx4_pci_slot_reset(struct pci_dev *pdev)
4061{
4062 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4063 struct mlx4_dev *dev = persist->dev;
4064 int err;
4065
4066 mlx4_err(dev, "mlx4_pci_slot_reset was called\n");
4067 err = mlx4_pci_enable_device(dev);
4068 if (err) {
4069 mlx4_err(dev, "Can not re-enable device, err=%d\n", err);
4070 return PCI_ERS_RESULT_DISCONNECT;
4071 }
4072
4073 pci_set_master(pdev);
4074 pci_restore_state(pdev);
4075 pci_save_state(pdev);
4076 return PCI_ERS_RESULT_RECOVERED;
4077}
4078
4079static void mlx4_pci_resume(struct pci_dev *pdev)
4080{
4081 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4082 struct mlx4_dev *dev = persist->dev;
4083 struct mlx4_priv *priv = mlx4_priv(dev);
4084 int nvfs[MLX4_MAX_PORTS + 1] = {0, 0, 0};
4085 int total_vfs;
4086 int err;
4087
4088 mlx4_err(dev, "%s was called\n", __func__);
4089 total_vfs = dev->persist->num_vfs;
4090 memcpy(nvfs, dev->persist->nvfs, sizeof(dev->persist->nvfs));
4091
4092 mutex_lock(&persist->interface_state_mutex);
4093 if (!(persist->interface_state & MLX4_INTERFACE_STATE_UP)) {
4094 err = mlx4_load_one(pdev, priv->pci_dev_data, total_vfs, nvfs,
4095 priv, 1);
4096 if (err) {
4097 mlx4_err(dev, "%s: mlx4_load_one failed, err=%d\n",
4098 __func__, err);
4099 goto end;
4100 }
4101
4102 err = restore_current_port_types(dev, dev->persist->
4103 curr_port_type, dev->persist->
4104 curr_port_poss_type);
4105 if (err)
4106 mlx4_err(dev, "could not restore original port types (%d)\n", err);
4107 }
4108end:
4109 mutex_unlock(&persist->interface_state_mutex);
4110
4111}
4112
4113static void mlx4_shutdown(struct pci_dev *pdev)
4114{
4115 struct mlx4_dev_persistent *persist = pci_get_drvdata(pdev);
4116
4117 mlx4_info(persist->dev, "mlx4_shutdown was called\n");
4118 mutex_lock(&persist->interface_state_mutex);
4119 if (persist->interface_state & MLX4_INTERFACE_STATE_UP)
4120 mlx4_unload_one(pdev);
4121 mutex_unlock(&persist->interface_state_mutex);
4122}
4123
4124static const struct pci_error_handlers mlx4_err_handler = {
4125 .error_detected = mlx4_pci_err_detected,
4126 .slot_reset = mlx4_pci_slot_reset,
4127 .resume = mlx4_pci_resume,
4128};
4129
4130static struct pci_driver mlx4_driver = {
4131 .name = DRV_NAME,
4132 .id_table = mlx4_pci_table,
4133 .probe = mlx4_init_one,
4134 .shutdown = mlx4_shutdown,
4135 .remove = mlx4_remove_one,
4136 .err_handler = &mlx4_err_handler,
4137};
4138
4139static int __init mlx4_verify_params(void)
4140{
4141 if ((log_num_mac < 0) || (log_num_mac > 7)) {
4142 pr_warn("mlx4_core: bad num_mac: %d\n", log_num_mac);
4143 return -1;
4144 }
4145
4146 if (log_num_vlan != 0)
4147 pr_warn("mlx4_core: log_num_vlan - obsolete module param, using %d\n",
4148 MLX4_LOG_NUM_VLANS);
4149
4150 if (use_prio != 0)
4151 pr_warn("mlx4_core: use_prio - obsolete module param, ignored\n");
4152
4153 if ((log_mtts_per_seg < 1) || (log_mtts_per_seg > 7)) {
4154 pr_warn("mlx4_core: bad log_mtts_per_seg: %d\n",
4155 log_mtts_per_seg);
4156 return -1;
4157 }
4158
4159
4160 if (port_type_array[0] == false && port_type_array[1] == true) {
4161 pr_warn("Module parameter configuration ETH/IB is not supported. Switching to default configuration IB/IB\n");
4162 port_type_array[0] = true;
4163 }
4164
4165 if (mlx4_log_num_mgm_entry_size < -7 ||
4166 (mlx4_log_num_mgm_entry_size > 0 &&
4167 (mlx4_log_num_mgm_entry_size < MLX4_MIN_MGM_LOG_ENTRY_SIZE ||
4168 mlx4_log_num_mgm_entry_size > MLX4_MAX_MGM_LOG_ENTRY_SIZE))) {
4169 pr_warn("mlx4_core: mlx4_log_num_mgm_entry_size (%d) not in legal range (-7..0 or %d..%d)\n",
4170 mlx4_log_num_mgm_entry_size,
4171 MLX4_MIN_MGM_LOG_ENTRY_SIZE,
4172 MLX4_MAX_MGM_LOG_ENTRY_SIZE);
4173 return -1;
4174 }
4175
4176 return 0;
4177}
4178
4179static int __init mlx4_init(void)
4180{
4181 int ret;
4182
4183 if (mlx4_verify_params())
4184 return -EINVAL;
4185
4186
4187 mlx4_wq = create_singlethread_workqueue("mlx4");
4188 if (!mlx4_wq)
4189 return -ENOMEM;
4190
4191 ret = pci_register_driver(&mlx4_driver);
4192 if (ret < 0)
4193 destroy_workqueue(mlx4_wq);
4194 return ret < 0 ? ret : 0;
4195}
4196
4197static void __exit mlx4_cleanup(void)
4198{
4199 pci_unregister_driver(&mlx4_driver);
4200 destroy_workqueue(mlx4_wq);
4201}
4202
4203module_init(mlx4_init);
4204module_exit(mlx4_cleanup);
4205