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33#include <net/tc_act/tc_gact.h>
34#include <net/pkt_cls.h>
35#include <linux/mlx5/fs.h>
36#include <net/vxlan.h>
37#include <linux/bpf.h>
38#include "eswitch.h"
39#include "en.h"
40#include "en_tc.h"
41#include "en_rep.h"
42#include "en_accel/ipsec.h"
43#include "en_accel/ipsec_rxtx.h"
44#include "accel/ipsec.h"
45#include "vxlan.h"
46
47struct mlx5e_rq_param {
48 u32 rqc[MLX5_ST_SZ_DW(rqc)];
49 struct mlx5_wq_param wq;
50};
51
52struct mlx5e_sq_param {
53 u32 sqc[MLX5_ST_SZ_DW(sqc)];
54 struct mlx5_wq_param wq;
55};
56
57struct mlx5e_cq_param {
58 u32 cqc[MLX5_ST_SZ_DW(cqc)];
59 struct mlx5_wq_param wq;
60 u16 eq_ix;
61 u8 cq_period_mode;
62};
63
64struct mlx5e_channel_param {
65 struct mlx5e_rq_param rq;
66 struct mlx5e_sq_param sq;
67 struct mlx5e_sq_param xdp_sq;
68 struct mlx5e_sq_param icosq;
69 struct mlx5e_cq_param rx_cq;
70 struct mlx5e_cq_param tx_cq;
71 struct mlx5e_cq_param icosq_cq;
72};
73
74bool mlx5e_check_fragmented_striding_rq_cap(struct mlx5_core_dev *mdev)
75{
76 bool striding_rq_umr = MLX5_CAP_GEN(mdev, striding_rq) &&
77 MLX5_CAP_GEN(mdev, umr_ptr_rlky) &&
78 MLX5_CAP_ETH(mdev, reg_umr_sq);
79 u16 max_wqe_sz_cap = MLX5_CAP_GEN(mdev, max_wqe_sz_sq);
80 bool inline_umr = MLX5E_UMR_WQE_INLINE_SZ <= max_wqe_sz_cap;
81
82 if (!striding_rq_umr)
83 return false;
84 if (!inline_umr) {
85 mlx5_core_warn(mdev, "Cannot support Striding RQ: UMR WQE size (%d) exceeds maximum supported (%d).\n",
86 (int)MLX5E_UMR_WQE_INLINE_SZ, max_wqe_sz_cap);
87 return false;
88 }
89 return true;
90}
91
92static u32 mlx5e_mpwqe_get_linear_frag_sz(struct mlx5e_params *params)
93{
94 if (!params->xdp_prog) {
95 u16 hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
96 u16 rq_headroom = MLX5_RX_HEADROOM + NET_IP_ALIGN;
97
98 return MLX5_SKB_FRAG_SZ(rq_headroom + hw_mtu);
99 }
100
101 return PAGE_SIZE;
102}
103
104static u8 mlx5e_mpwqe_log_pkts_per_wqe(struct mlx5e_params *params)
105{
106 u32 linear_frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
107
108 return MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(linear_frag_sz);
109}
110
111static bool mlx5e_rx_mpwqe_is_linear_skb(struct mlx5_core_dev *mdev,
112 struct mlx5e_params *params)
113{
114 u32 frag_sz = mlx5e_mpwqe_get_linear_frag_sz(params);
115 s8 signed_log_num_strides_param;
116 u8 log_num_strides;
117
118 if (params->lro_en || frag_sz > PAGE_SIZE)
119 return false;
120
121 if (MLX5_CAP_GEN(mdev, ext_stride_num_range))
122 return true;
123
124 log_num_strides = MLX5_MPWRQ_LOG_WQE_SZ - order_base_2(frag_sz);
125 signed_log_num_strides_param =
126 (s8)log_num_strides - MLX5_MPWQE_LOG_NUM_STRIDES_BASE;
127
128 return signed_log_num_strides_param >= 0;
129}
130
131static u8 mlx5e_mpwqe_get_log_rq_size(struct mlx5e_params *params)
132{
133 if (params->log_rq_mtu_frames <
134 mlx5e_mpwqe_log_pkts_per_wqe(params) + MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW)
135 return MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE_MPW;
136
137 return params->log_rq_mtu_frames - mlx5e_mpwqe_log_pkts_per_wqe(params);
138}
139
140static u8 mlx5e_mpwqe_get_log_stride_size(struct mlx5_core_dev *mdev,
141 struct mlx5e_params *params)
142{
143 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
144 return order_base_2(mlx5e_mpwqe_get_linear_frag_sz(params));
145
146 return MLX5E_MPWQE_STRIDE_SZ(mdev,
147 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
148}
149
150static u8 mlx5e_mpwqe_get_log_num_strides(struct mlx5_core_dev *mdev,
151 struct mlx5e_params *params)
152{
153 return MLX5_MPWRQ_LOG_WQE_SZ -
154 mlx5e_mpwqe_get_log_stride_size(mdev, params);
155}
156
157static u16 mlx5e_get_rq_headroom(struct mlx5_core_dev *mdev,
158 struct mlx5e_params *params)
159{
160 u16 linear_rq_headroom = params->xdp_prog ?
161 XDP_PACKET_HEADROOM : MLX5_RX_HEADROOM;
162
163 linear_rq_headroom += NET_IP_ALIGN;
164
165 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST)
166 return linear_rq_headroom;
167
168 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
169 return linear_rq_headroom;
170
171 return 0;
172}
173
174void mlx5e_init_rq_type_params(struct mlx5_core_dev *mdev,
175 struct mlx5e_params *params)
176{
177 params->lro_wqe_sz = MLX5E_PARAMS_DEFAULT_LRO_WQE_SZ;
178 params->log_rq_mtu_frames = is_kdump_kernel() ?
179 MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE :
180 MLX5E_PARAMS_DEFAULT_LOG_RQ_SIZE;
181 switch (params->rq_wq_type) {
182 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
183 break;
184 default:
185
186 params->lro_wqe_sz -= mlx5e_get_rq_headroom(mdev, params) +
187 SKB_DATA_ALIGN(sizeof(struct skb_shared_info));
188 }
189
190 mlx5_core_info(mdev, "MLX5E: StrdRq(%d) RqSz(%ld) StrdSz(%ld) RxCqeCmprss(%d)\n",
191 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ,
192 params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ ?
193 BIT(mlx5e_mpwqe_get_log_rq_size(params)) :
194 BIT(params->log_rq_mtu_frames),
195 BIT(mlx5e_mpwqe_get_log_stride_size(mdev, params)),
196 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS));
197}
198
199bool mlx5e_striding_rq_possible(struct mlx5_core_dev *mdev,
200 struct mlx5e_params *params)
201{
202 return mlx5e_check_fragmented_striding_rq_cap(mdev) &&
203 !MLX5_IPSEC_DEV(mdev) &&
204 !(params->xdp_prog && !mlx5e_rx_mpwqe_is_linear_skb(mdev, params));
205}
206
207void mlx5e_set_rq_type(struct mlx5_core_dev *mdev, struct mlx5e_params *params)
208{
209 params->rq_wq_type = mlx5e_striding_rq_possible(mdev, params) &&
210 MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ) ?
211 MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ :
212 MLX5_WQ_TYPE_LINKED_LIST;
213}
214
215static void mlx5e_update_carrier(struct mlx5e_priv *priv)
216{
217 struct mlx5_core_dev *mdev = priv->mdev;
218 u8 port_state;
219
220 port_state = mlx5_query_vport_state(mdev,
221 MLX5_QUERY_VPORT_STATE_IN_OP_MOD_VNIC_VPORT,
222 0);
223
224 if (port_state == VPORT_STATE_UP) {
225 netdev_info(priv->netdev, "Link up\n");
226 netif_carrier_on(priv->netdev);
227 } else {
228 netdev_info(priv->netdev, "Link down\n");
229 netif_carrier_off(priv->netdev);
230 }
231}
232
233static void mlx5e_update_carrier_work(struct work_struct *work)
234{
235 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
236 update_carrier_work);
237
238 mutex_lock(&priv->state_lock);
239 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
240 if (priv->profile->update_carrier)
241 priv->profile->update_carrier(priv);
242 mutex_unlock(&priv->state_lock);
243}
244
245void mlx5e_update_stats(struct mlx5e_priv *priv)
246{
247 int i;
248
249 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
250 if (mlx5e_stats_grps[i].update_stats)
251 mlx5e_stats_grps[i].update_stats(priv);
252}
253
254static void mlx5e_update_ndo_stats(struct mlx5e_priv *priv)
255{
256 int i;
257
258 for (i = mlx5e_num_stats_grps - 1; i >= 0; i--)
259 if (mlx5e_stats_grps[i].update_stats_mask &
260 MLX5E_NDO_UPDATE_STATS)
261 mlx5e_stats_grps[i].update_stats(priv);
262}
263
264void mlx5e_update_stats_work(struct work_struct *work)
265{
266 struct delayed_work *dwork = to_delayed_work(work);
267 struct mlx5e_priv *priv = container_of(dwork, struct mlx5e_priv,
268 update_stats_work);
269 mutex_lock(&priv->state_lock);
270 if (test_bit(MLX5E_STATE_OPENED, &priv->state)) {
271 priv->profile->update_stats(priv);
272 queue_delayed_work(priv->wq, dwork,
273 msecs_to_jiffies(MLX5E_UPDATE_STATS_INTERVAL));
274 }
275 mutex_unlock(&priv->state_lock);
276}
277
278static void mlx5e_async_event(struct mlx5_core_dev *mdev, void *vpriv,
279 enum mlx5_dev_event event, unsigned long param)
280{
281 struct mlx5e_priv *priv = vpriv;
282
283 if (!test_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state))
284 return;
285
286 switch (event) {
287 case MLX5_DEV_EVENT_PORT_UP:
288 case MLX5_DEV_EVENT_PORT_DOWN:
289 queue_work(priv->wq, &priv->update_carrier_work);
290 break;
291 default:
292 break;
293 }
294}
295
296static void mlx5e_enable_async_events(struct mlx5e_priv *priv)
297{
298 set_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
299}
300
301static void mlx5e_disable_async_events(struct mlx5e_priv *priv)
302{
303 clear_bit(MLX5E_STATE_ASYNC_EVENTS_ENABLED, &priv->state);
304 synchronize_irq(pci_irq_vector(priv->mdev->pdev, MLX5_EQ_VEC_ASYNC));
305}
306
307static inline void mlx5e_build_umr_wqe(struct mlx5e_rq *rq,
308 struct mlx5e_icosq *sq,
309 struct mlx5e_umr_wqe *wqe)
310{
311 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
312 struct mlx5_wqe_umr_ctrl_seg *ucseg = &wqe->uctrl;
313 u8 ds_cnt = DIV_ROUND_UP(MLX5E_UMR_WQE_INLINE_SZ, MLX5_SEND_WQE_DS);
314
315 cseg->qpn_ds = cpu_to_be32((sq->sqn << MLX5_WQE_CTRL_QPN_SHIFT) |
316 ds_cnt);
317 cseg->fm_ce_se = MLX5_WQE_CTRL_CQ_UPDATE;
318 cseg->imm = rq->mkey_be;
319
320 ucseg->flags = MLX5_UMR_TRANSLATION_OFFSET_EN | MLX5_UMR_INLINE;
321 ucseg->xlt_octowords =
322 cpu_to_be16(MLX5_MTT_OCTW(MLX5_MPWRQ_PAGES_PER_WQE));
323 ucseg->mkey_mask = cpu_to_be64(MLX5_MKEY_MASK_FREE);
324}
325
326static int mlx5e_rq_alloc_mpwqe_info(struct mlx5e_rq *rq,
327 struct mlx5e_channel *c)
328{
329 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
330
331 rq->mpwqe.info = kzalloc_node(wq_sz * sizeof(*rq->mpwqe.info),
332 GFP_KERNEL, cpu_to_node(c->cpu));
333 if (!rq->mpwqe.info)
334 return -ENOMEM;
335
336 mlx5e_build_umr_wqe(rq, &c->icosq, &rq->mpwqe.umr_wqe);
337
338 return 0;
339}
340
341static int mlx5e_create_umr_mkey(struct mlx5_core_dev *mdev,
342 u64 npages, u8 page_shift,
343 struct mlx5_core_mkey *umr_mkey)
344{
345 int inlen = MLX5_ST_SZ_BYTES(create_mkey_in);
346 void *mkc;
347 u32 *in;
348 int err;
349
350 in = kvzalloc(inlen, GFP_KERNEL);
351 if (!in)
352 return -ENOMEM;
353
354 mkc = MLX5_ADDR_OF(create_mkey_in, in, memory_key_mkey_entry);
355
356 MLX5_SET(mkc, mkc, free, 1);
357 MLX5_SET(mkc, mkc, umr_en, 1);
358 MLX5_SET(mkc, mkc, lw, 1);
359 MLX5_SET(mkc, mkc, lr, 1);
360 MLX5_SET(mkc, mkc, access_mode_1_0, MLX5_MKC_ACCESS_MODE_MTT);
361
362 MLX5_SET(mkc, mkc, qpn, 0xffffff);
363 MLX5_SET(mkc, mkc, pd, mdev->mlx5e_res.pdn);
364 MLX5_SET64(mkc, mkc, len, npages << page_shift);
365 MLX5_SET(mkc, mkc, translations_octword_size,
366 MLX5_MTT_OCTW(npages));
367 MLX5_SET(mkc, mkc, log_page_size, page_shift);
368
369 err = mlx5_core_create_mkey(mdev, umr_mkey, in, inlen);
370
371 kvfree(in);
372 return err;
373}
374
375static int mlx5e_create_rq_umr_mkey(struct mlx5_core_dev *mdev, struct mlx5e_rq *rq)
376{
377 u64 num_mtts = MLX5E_REQUIRED_MTTS(mlx5_wq_ll_get_size(&rq->wq));
378
379 return mlx5e_create_umr_mkey(mdev, num_mtts, PAGE_SHIFT, &rq->umr_mkey);
380}
381
382static inline u64 mlx5e_get_mpwqe_offset(struct mlx5e_rq *rq, u16 wqe_ix)
383{
384 return (wqe_ix << MLX5E_LOG_ALIGNED_MPWQE_PPW) << PAGE_SHIFT;
385}
386
387static int mlx5e_alloc_rq(struct mlx5e_channel *c,
388 struct mlx5e_params *params,
389 struct mlx5e_rq_param *rqp,
390 struct mlx5e_rq *rq)
391{
392 struct mlx5_core_dev *mdev = c->mdev;
393 void *rqc = rqp->rqc;
394 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
395 u32 byte_count;
396 int npages;
397 int wq_sz;
398 int err;
399 int i;
400
401 rqp->wq.db_numa_node = cpu_to_node(c->cpu);
402
403 err = mlx5_wq_ll_create(mdev, &rqp->wq, rqc_wq, &rq->wq,
404 &rq->wq_ctrl);
405 if (err)
406 return err;
407
408 rq->wq.db = &rq->wq.db[MLX5_RCV_DBR];
409
410 wq_sz = mlx5_wq_ll_get_size(&rq->wq);
411
412 rq->wq_type = params->rq_wq_type;
413 rq->pdev = c->pdev;
414 rq->netdev = c->netdev;
415 rq->tstamp = c->tstamp;
416 rq->clock = &mdev->clock;
417 rq->channel = c;
418 rq->ix = c->ix;
419 rq->mdev = mdev;
420 rq->hw_mtu = MLX5E_SW2HW_MTU(params, params->sw_mtu);
421
422 rq->xdp_prog = params->xdp_prog ? bpf_prog_inc(params->xdp_prog) : NULL;
423 if (IS_ERR(rq->xdp_prog)) {
424 err = PTR_ERR(rq->xdp_prog);
425 rq->xdp_prog = NULL;
426 goto err_rq_wq_destroy;
427 }
428
429 err = xdp_rxq_info_reg(&rq->xdp_rxq, rq->netdev, rq->ix);
430 if (err < 0)
431 goto err_rq_wq_destroy;
432
433 rq->buff.map_dir = rq->xdp_prog ? DMA_BIDIRECTIONAL : DMA_FROM_DEVICE;
434 rq->buff.headroom = mlx5e_get_rq_headroom(mdev, params);
435
436 switch (rq->wq_type) {
437 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
438 rq->post_wqes = mlx5e_post_rx_mpwqes;
439 rq->dealloc_wqe = mlx5e_dealloc_rx_mpwqe;
440
441 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe_mpwqe;
442#ifdef CONFIG_MLX5_EN_IPSEC
443 if (MLX5_IPSEC_DEV(mdev)) {
444 err = -EINVAL;
445 netdev_err(c->netdev, "MPWQE RQ with IPSec offload not supported\n");
446 goto err_rq_wq_destroy;
447 }
448#endif
449 if (!rq->handle_rx_cqe) {
450 err = -EINVAL;
451 netdev_err(c->netdev, "RX handler of MPWQE RQ is not set, err %d\n", err);
452 goto err_rq_wq_destroy;
453 }
454
455 rq->mpwqe.skb_from_cqe_mpwrq =
456 mlx5e_rx_mpwqe_is_linear_skb(mdev, params) ?
457 mlx5e_skb_from_cqe_mpwrq_linear :
458 mlx5e_skb_from_cqe_mpwrq_nonlinear;
459 rq->mpwqe.log_stride_sz = mlx5e_mpwqe_get_log_stride_size(mdev, params);
460 rq->mpwqe.num_strides = BIT(mlx5e_mpwqe_get_log_num_strides(mdev, params));
461
462 byte_count = rq->mpwqe.num_strides << rq->mpwqe.log_stride_sz;
463
464 err = mlx5e_create_rq_umr_mkey(mdev, rq);
465 if (err)
466 goto err_rq_wq_destroy;
467 rq->mkey_be = cpu_to_be32(rq->umr_mkey.key);
468
469 err = mlx5e_rq_alloc_mpwqe_info(rq, c);
470 if (err)
471 goto err_destroy_umr_mkey;
472 break;
473 default:
474 rq->wqe.frag_info =
475 kzalloc_node(wq_sz * sizeof(*rq->wqe.frag_info),
476 GFP_KERNEL, cpu_to_node(c->cpu));
477 if (!rq->wqe.frag_info) {
478 err = -ENOMEM;
479 goto err_rq_wq_destroy;
480 }
481 rq->post_wqes = mlx5e_post_rx_wqes;
482 rq->dealloc_wqe = mlx5e_dealloc_rx_wqe;
483
484#ifdef CONFIG_MLX5_EN_IPSEC
485 if (c->priv->ipsec)
486 rq->handle_rx_cqe = mlx5e_ipsec_handle_rx_cqe;
487 else
488#endif
489 rq->handle_rx_cqe = c->priv->profile->rx_handlers.handle_rx_cqe;
490 if (!rq->handle_rx_cqe) {
491 kfree(rq->wqe.frag_info);
492 err = -EINVAL;
493 netdev_err(c->netdev, "RX handler of RQ is not set, err %d\n", err);
494 goto err_rq_wq_destroy;
495 }
496
497 byte_count = params->lro_en ?
498 params->lro_wqe_sz :
499 MLX5E_SW2HW_MTU(params, params->sw_mtu);
500#ifdef CONFIG_MLX5_EN_IPSEC
501 if (MLX5_IPSEC_DEV(mdev))
502 byte_count += MLX5E_METADATA_ETHER_LEN;
503#endif
504 rq->wqe.page_reuse = !params->xdp_prog && !params->lro_en;
505
506
507 rq->wqe.frag_sz = MLX5_SKB_FRAG_SZ(rq->buff.headroom + byte_count);
508 npages = DIV_ROUND_UP(rq->wqe.frag_sz, PAGE_SIZE);
509 rq->buff.page_order = order_base_2(npages);
510
511 byte_count |= MLX5_HW_START_PADDING;
512 rq->mkey_be = c->mkey_be;
513 }
514
515 for (i = 0; i < wq_sz; i++) {
516 struct mlx5e_rx_wqe *wqe = mlx5_wq_ll_get_wqe(&rq->wq, i);
517
518 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ) {
519 u64 dma_offset = mlx5e_get_mpwqe_offset(rq, i);
520
521 wqe->data.addr = cpu_to_be64(dma_offset + rq->buff.headroom);
522 }
523
524 wqe->data.byte_count = cpu_to_be32(byte_count);
525 wqe->data.lkey = rq->mkey_be;
526 }
527
528 INIT_WORK(&rq->dim.work, mlx5e_rx_dim_work);
529
530 switch (params->rx_cq_moderation.cq_period_mode) {
531 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
532 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE;
533 break;
534 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
535 default:
536 rq->dim.mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
537 }
538
539 rq->page_cache.head = 0;
540 rq->page_cache.tail = 0;
541
542 return 0;
543
544err_destroy_umr_mkey:
545 mlx5_core_destroy_mkey(mdev, &rq->umr_mkey);
546
547err_rq_wq_destroy:
548 if (rq->xdp_prog)
549 bpf_prog_put(rq->xdp_prog);
550 xdp_rxq_info_unreg(&rq->xdp_rxq);
551 mlx5_wq_destroy(&rq->wq_ctrl);
552
553 return err;
554}
555
556static void mlx5e_free_rq(struct mlx5e_rq *rq)
557{
558 int i;
559
560 if (rq->xdp_prog)
561 bpf_prog_put(rq->xdp_prog);
562
563 xdp_rxq_info_unreg(&rq->xdp_rxq);
564
565 switch (rq->wq_type) {
566 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
567 kfree(rq->mpwqe.info);
568 mlx5_core_destroy_mkey(rq->mdev, &rq->umr_mkey);
569 break;
570 default:
571 kfree(rq->wqe.frag_info);
572 }
573
574 for (i = rq->page_cache.head; i != rq->page_cache.tail;
575 i = (i + 1) & (MLX5E_CACHE_SIZE - 1)) {
576 struct mlx5e_dma_info *dma_info = &rq->page_cache.page_cache[i];
577
578 mlx5e_page_release(rq, dma_info, false);
579 }
580 mlx5_wq_destroy(&rq->wq_ctrl);
581}
582
583static int mlx5e_create_rq(struct mlx5e_rq *rq,
584 struct mlx5e_rq_param *param)
585{
586 struct mlx5_core_dev *mdev = rq->mdev;
587
588 void *in;
589 void *rqc;
590 void *wq;
591 int inlen;
592 int err;
593
594 inlen = MLX5_ST_SZ_BYTES(create_rq_in) +
595 sizeof(u64) * rq->wq_ctrl.buf.npages;
596 in = kvzalloc(inlen, GFP_KERNEL);
597 if (!in)
598 return -ENOMEM;
599
600 rqc = MLX5_ADDR_OF(create_rq_in, in, ctx);
601 wq = MLX5_ADDR_OF(rqc, rqc, wq);
602
603 memcpy(rqc, param->rqc, sizeof(param->rqc));
604
605 MLX5_SET(rqc, rqc, cqn, rq->cq.mcq.cqn);
606 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RST);
607 MLX5_SET(wq, wq, log_wq_pg_sz, rq->wq_ctrl.buf.page_shift -
608 MLX5_ADAPTER_PAGE_SHIFT);
609 MLX5_SET64(wq, wq, dbr_addr, rq->wq_ctrl.db.dma);
610
611 mlx5_fill_page_array(&rq->wq_ctrl.buf,
612 (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
613
614 err = mlx5_core_create_rq(mdev, in, inlen, &rq->rqn);
615
616 kvfree(in);
617
618 return err;
619}
620
621static int mlx5e_modify_rq_state(struct mlx5e_rq *rq, int curr_state,
622 int next_state)
623{
624 struct mlx5_core_dev *mdev = rq->mdev;
625
626 void *in;
627 void *rqc;
628 int inlen;
629 int err;
630
631 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
632 in = kvzalloc(inlen, GFP_KERNEL);
633 if (!in)
634 return -ENOMEM;
635
636 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
637
638 MLX5_SET(modify_rq_in, in, rq_state, curr_state);
639 MLX5_SET(rqc, rqc, state, next_state);
640
641 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
642
643 kvfree(in);
644
645 return err;
646}
647
648static int mlx5e_modify_rq_scatter_fcs(struct mlx5e_rq *rq, bool enable)
649{
650 struct mlx5e_channel *c = rq->channel;
651 struct mlx5e_priv *priv = c->priv;
652 struct mlx5_core_dev *mdev = priv->mdev;
653
654 void *in;
655 void *rqc;
656 int inlen;
657 int err;
658
659 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
660 in = kvzalloc(inlen, GFP_KERNEL);
661 if (!in)
662 return -ENOMEM;
663
664 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
665
666 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
667 MLX5_SET64(modify_rq_in, in, modify_bitmask,
668 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_SCATTER_FCS);
669 MLX5_SET(rqc, rqc, scatter_fcs, enable);
670 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
671
672 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
673
674 kvfree(in);
675
676 return err;
677}
678
679static int mlx5e_modify_rq_vsd(struct mlx5e_rq *rq, bool vsd)
680{
681 struct mlx5e_channel *c = rq->channel;
682 struct mlx5_core_dev *mdev = c->mdev;
683 void *in;
684 void *rqc;
685 int inlen;
686 int err;
687
688 inlen = MLX5_ST_SZ_BYTES(modify_rq_in);
689 in = kvzalloc(inlen, GFP_KERNEL);
690 if (!in)
691 return -ENOMEM;
692
693 rqc = MLX5_ADDR_OF(modify_rq_in, in, ctx);
694
695 MLX5_SET(modify_rq_in, in, rq_state, MLX5_RQC_STATE_RDY);
696 MLX5_SET64(modify_rq_in, in, modify_bitmask,
697 MLX5_MODIFY_RQ_IN_MODIFY_BITMASK_VSD);
698 MLX5_SET(rqc, rqc, vsd, vsd);
699 MLX5_SET(rqc, rqc, state, MLX5_RQC_STATE_RDY);
700
701 err = mlx5_core_modify_rq(mdev, rq->rqn, in, inlen);
702
703 kvfree(in);
704
705 return err;
706}
707
708static void mlx5e_destroy_rq(struct mlx5e_rq *rq)
709{
710 mlx5_core_destroy_rq(rq->mdev, rq->rqn);
711}
712
713static int mlx5e_wait_for_min_rx_wqes(struct mlx5e_rq *rq)
714{
715 unsigned long exp_time = jiffies + msecs_to_jiffies(20000);
716 struct mlx5e_channel *c = rq->channel;
717
718 struct mlx5_wq_ll *wq = &rq->wq;
719 u16 min_wqes = mlx5_min_rx_wqes(rq->wq_type, mlx5_wq_ll_get_size(wq));
720
721 while (time_before(jiffies, exp_time)) {
722 if (wq->cur_sz >= min_wqes)
723 return 0;
724
725 msleep(20);
726 }
727
728 netdev_warn(c->netdev, "Failed to get min RX wqes on RQN[0x%x] wq cur_sz(%d) min_rx_wqes(%d)\n",
729 rq->rqn, wq->cur_sz, min_wqes);
730 return -ETIMEDOUT;
731}
732
733static void mlx5e_free_rx_descs(struct mlx5e_rq *rq)
734{
735 struct mlx5_wq_ll *wq = &rq->wq;
736 struct mlx5e_rx_wqe *wqe;
737 __be16 wqe_ix_be;
738 u16 wqe_ix;
739
740
741 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ &&
742 rq->mpwqe.umr_in_progress)
743 mlx5e_free_rx_mpwqe(rq, &rq->mpwqe.info[wq->head]);
744
745 while (!mlx5_wq_ll_is_empty(wq)) {
746 wqe_ix_be = *wq->tail_next;
747 wqe_ix = be16_to_cpu(wqe_ix_be);
748 wqe = mlx5_wq_ll_get_wqe(&rq->wq, wqe_ix);
749 rq->dealloc_wqe(rq, wqe_ix);
750 mlx5_wq_ll_pop(&rq->wq, wqe_ix_be,
751 &wqe->next.next_wqe_index);
752 }
753
754 if (rq->wq_type == MLX5_WQ_TYPE_LINKED_LIST && rq->wqe.page_reuse) {
755
756
757
758 int wq_sz = mlx5_wq_ll_get_size(&rq->wq);
759
760 for (wqe_ix = 0; wqe_ix < wq_sz; wqe_ix++)
761 rq->dealloc_wqe(rq, wqe_ix);
762 }
763}
764
765static int mlx5e_open_rq(struct mlx5e_channel *c,
766 struct mlx5e_params *params,
767 struct mlx5e_rq_param *param,
768 struct mlx5e_rq *rq)
769{
770 int err;
771
772 err = mlx5e_alloc_rq(c, params, param, rq);
773 if (err)
774 return err;
775
776 err = mlx5e_create_rq(rq, param);
777 if (err)
778 goto err_free_rq;
779
780 err = mlx5e_modify_rq_state(rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
781 if (err)
782 goto err_destroy_rq;
783
784 if (params->rx_dim_enabled)
785 c->rq.state |= BIT(MLX5E_RQ_STATE_AM);
786
787 return 0;
788
789err_destroy_rq:
790 mlx5e_destroy_rq(rq);
791err_free_rq:
792 mlx5e_free_rq(rq);
793
794 return err;
795}
796
797static void mlx5e_activate_rq(struct mlx5e_rq *rq)
798{
799 struct mlx5e_icosq *sq = &rq->channel->icosq;
800 u16 pi = sq->pc & sq->wq.sz_m1;
801 struct mlx5e_tx_wqe *nopwqe;
802
803 set_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
804 sq->db.ico_wqe[pi].opcode = MLX5_OPCODE_NOP;
805 nopwqe = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
806 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nopwqe->ctrl);
807}
808
809static void mlx5e_deactivate_rq(struct mlx5e_rq *rq)
810{
811 clear_bit(MLX5E_RQ_STATE_ENABLED, &rq->state);
812 napi_synchronize(&rq->channel->napi);
813}
814
815static void mlx5e_close_rq(struct mlx5e_rq *rq)
816{
817 cancel_work_sync(&rq->dim.work);
818 mlx5e_destroy_rq(rq);
819 mlx5e_free_rx_descs(rq);
820 mlx5e_free_rq(rq);
821}
822
823static void mlx5e_free_xdpsq_db(struct mlx5e_xdpsq *sq)
824{
825 kfree(sq->db.di);
826}
827
828static int mlx5e_alloc_xdpsq_db(struct mlx5e_xdpsq *sq, int numa)
829{
830 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
831
832 sq->db.di = kzalloc_node(sizeof(*sq->db.di) * wq_sz,
833 GFP_KERNEL, numa);
834 if (!sq->db.di) {
835 mlx5e_free_xdpsq_db(sq);
836 return -ENOMEM;
837 }
838
839 return 0;
840}
841
842static int mlx5e_alloc_xdpsq(struct mlx5e_channel *c,
843 struct mlx5e_params *params,
844 struct mlx5e_sq_param *param,
845 struct mlx5e_xdpsq *sq)
846{
847 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
848 struct mlx5_core_dev *mdev = c->mdev;
849 int err;
850
851 sq->pdev = c->pdev;
852 sq->mkey_be = c->mkey_be;
853 sq->channel = c;
854 sq->uar_map = mdev->mlx5e_res.bfreg.map;
855 sq->min_inline_mode = params->tx_min_inline_mode;
856
857 param->wq.db_numa_node = cpu_to_node(c->cpu);
858 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
859 if (err)
860 return err;
861 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
862
863 err = mlx5e_alloc_xdpsq_db(sq, cpu_to_node(c->cpu));
864 if (err)
865 goto err_sq_wq_destroy;
866
867 return 0;
868
869err_sq_wq_destroy:
870 mlx5_wq_destroy(&sq->wq_ctrl);
871
872 return err;
873}
874
875static void mlx5e_free_xdpsq(struct mlx5e_xdpsq *sq)
876{
877 mlx5e_free_xdpsq_db(sq);
878 mlx5_wq_destroy(&sq->wq_ctrl);
879}
880
881static void mlx5e_free_icosq_db(struct mlx5e_icosq *sq)
882{
883 kfree(sq->db.ico_wqe);
884}
885
886static int mlx5e_alloc_icosq_db(struct mlx5e_icosq *sq, int numa)
887{
888 u8 wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
889
890 sq->db.ico_wqe = kzalloc_node(sizeof(*sq->db.ico_wqe) * wq_sz,
891 GFP_KERNEL, numa);
892 if (!sq->db.ico_wqe)
893 return -ENOMEM;
894
895 return 0;
896}
897
898static int mlx5e_alloc_icosq(struct mlx5e_channel *c,
899 struct mlx5e_sq_param *param,
900 struct mlx5e_icosq *sq)
901{
902 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
903 struct mlx5_core_dev *mdev = c->mdev;
904 int err;
905
906 sq->channel = c;
907 sq->uar_map = mdev->mlx5e_res.bfreg.map;
908
909 param->wq.db_numa_node = cpu_to_node(c->cpu);
910 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
911 if (err)
912 return err;
913 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
914
915 err = mlx5e_alloc_icosq_db(sq, cpu_to_node(c->cpu));
916 if (err)
917 goto err_sq_wq_destroy;
918
919 sq->edge = (sq->wq.sz_m1 + 1) - MLX5E_ICOSQ_MAX_WQEBBS;
920
921 return 0;
922
923err_sq_wq_destroy:
924 mlx5_wq_destroy(&sq->wq_ctrl);
925
926 return err;
927}
928
929static void mlx5e_free_icosq(struct mlx5e_icosq *sq)
930{
931 mlx5e_free_icosq_db(sq);
932 mlx5_wq_destroy(&sq->wq_ctrl);
933}
934
935static void mlx5e_free_txqsq_db(struct mlx5e_txqsq *sq)
936{
937 kfree(sq->db.wqe_info);
938 kfree(sq->db.dma_fifo);
939}
940
941static int mlx5e_alloc_txqsq_db(struct mlx5e_txqsq *sq, int numa)
942{
943 int wq_sz = mlx5_wq_cyc_get_size(&sq->wq);
944 int df_sz = wq_sz * MLX5_SEND_WQEBB_NUM_DS;
945
946 sq->db.dma_fifo = kzalloc_node(df_sz * sizeof(*sq->db.dma_fifo),
947 GFP_KERNEL, numa);
948 sq->db.wqe_info = kzalloc_node(wq_sz * sizeof(*sq->db.wqe_info),
949 GFP_KERNEL, numa);
950 if (!sq->db.dma_fifo || !sq->db.wqe_info) {
951 mlx5e_free_txqsq_db(sq);
952 return -ENOMEM;
953 }
954
955 sq->dma_fifo_mask = df_sz - 1;
956
957 return 0;
958}
959
960static void mlx5e_sq_recover(struct work_struct *work);
961static int mlx5e_alloc_txqsq(struct mlx5e_channel *c,
962 int txq_ix,
963 struct mlx5e_params *params,
964 struct mlx5e_sq_param *param,
965 struct mlx5e_txqsq *sq)
966{
967 void *sqc_wq = MLX5_ADDR_OF(sqc, param->sqc, wq);
968 struct mlx5_core_dev *mdev = c->mdev;
969 int err;
970
971 sq->pdev = c->pdev;
972 sq->tstamp = c->tstamp;
973 sq->clock = &mdev->clock;
974 sq->mkey_be = c->mkey_be;
975 sq->channel = c;
976 sq->txq_ix = txq_ix;
977 sq->uar_map = mdev->mlx5e_res.bfreg.map;
978 sq->min_inline_mode = params->tx_min_inline_mode;
979 INIT_WORK(&sq->recover.recover_work, mlx5e_sq_recover);
980 if (MLX5_IPSEC_DEV(c->priv->mdev))
981 set_bit(MLX5E_SQ_STATE_IPSEC, &sq->state);
982
983 param->wq.db_numa_node = cpu_to_node(c->cpu);
984 err = mlx5_wq_cyc_create(mdev, ¶m->wq, sqc_wq, &sq->wq, &sq->wq_ctrl);
985 if (err)
986 return err;
987 sq->wq.db = &sq->wq.db[MLX5_SND_DBR];
988
989 err = mlx5e_alloc_txqsq_db(sq, cpu_to_node(c->cpu));
990 if (err)
991 goto err_sq_wq_destroy;
992
993 sq->edge = (sq->wq.sz_m1 + 1) - MLX5_SEND_WQE_MAX_WQEBBS;
994
995 return 0;
996
997err_sq_wq_destroy:
998 mlx5_wq_destroy(&sq->wq_ctrl);
999
1000 return err;
1001}
1002
1003static void mlx5e_free_txqsq(struct mlx5e_txqsq *sq)
1004{
1005 mlx5e_free_txqsq_db(sq);
1006 mlx5_wq_destroy(&sq->wq_ctrl);
1007}
1008
1009struct mlx5e_create_sq_param {
1010 struct mlx5_wq_ctrl *wq_ctrl;
1011 u32 cqn;
1012 u32 tisn;
1013 u8 tis_lst_sz;
1014 u8 min_inline_mode;
1015};
1016
1017static int mlx5e_create_sq(struct mlx5_core_dev *mdev,
1018 struct mlx5e_sq_param *param,
1019 struct mlx5e_create_sq_param *csp,
1020 u32 *sqn)
1021{
1022 void *in;
1023 void *sqc;
1024 void *wq;
1025 int inlen;
1026 int err;
1027
1028 inlen = MLX5_ST_SZ_BYTES(create_sq_in) +
1029 sizeof(u64) * csp->wq_ctrl->buf.npages;
1030 in = kvzalloc(inlen, GFP_KERNEL);
1031 if (!in)
1032 return -ENOMEM;
1033
1034 sqc = MLX5_ADDR_OF(create_sq_in, in, ctx);
1035 wq = MLX5_ADDR_OF(sqc, sqc, wq);
1036
1037 memcpy(sqc, param->sqc, sizeof(param->sqc));
1038 MLX5_SET(sqc, sqc, tis_lst_sz, csp->tis_lst_sz);
1039 MLX5_SET(sqc, sqc, tis_num_0, csp->tisn);
1040 MLX5_SET(sqc, sqc, cqn, csp->cqn);
1041
1042 if (MLX5_CAP_ETH(mdev, wqe_inline_mode) == MLX5_CAP_INLINE_MODE_VPORT_CONTEXT)
1043 MLX5_SET(sqc, sqc, min_wqe_inline_mode, csp->min_inline_mode);
1044
1045 MLX5_SET(sqc, sqc, state, MLX5_SQC_STATE_RST);
1046 MLX5_SET(sqc, sqc, flush_in_error_en, 1);
1047
1048 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_CYCLIC);
1049 MLX5_SET(wq, wq, uar_page, mdev->mlx5e_res.bfreg.index);
1050 MLX5_SET(wq, wq, log_wq_pg_sz, csp->wq_ctrl->buf.page_shift -
1051 MLX5_ADAPTER_PAGE_SHIFT);
1052 MLX5_SET64(wq, wq, dbr_addr, csp->wq_ctrl->db.dma);
1053
1054 mlx5_fill_page_array(&csp->wq_ctrl->buf, (__be64 *)MLX5_ADDR_OF(wq, wq, pas));
1055
1056 err = mlx5_core_create_sq(mdev, in, inlen, sqn);
1057
1058 kvfree(in);
1059
1060 return err;
1061}
1062
1063struct mlx5e_modify_sq_param {
1064 int curr_state;
1065 int next_state;
1066 bool rl_update;
1067 int rl_index;
1068};
1069
1070static int mlx5e_modify_sq(struct mlx5_core_dev *mdev, u32 sqn,
1071 struct mlx5e_modify_sq_param *p)
1072{
1073 void *in;
1074 void *sqc;
1075 int inlen;
1076 int err;
1077
1078 inlen = MLX5_ST_SZ_BYTES(modify_sq_in);
1079 in = kvzalloc(inlen, GFP_KERNEL);
1080 if (!in)
1081 return -ENOMEM;
1082
1083 sqc = MLX5_ADDR_OF(modify_sq_in, in, ctx);
1084
1085 MLX5_SET(modify_sq_in, in, sq_state, p->curr_state);
1086 MLX5_SET(sqc, sqc, state, p->next_state);
1087 if (p->rl_update && p->next_state == MLX5_SQC_STATE_RDY) {
1088 MLX5_SET64(modify_sq_in, in, modify_bitmask, 1);
1089 MLX5_SET(sqc, sqc, packet_pacing_rate_limit_index, p->rl_index);
1090 }
1091
1092 err = mlx5_core_modify_sq(mdev, sqn, in, inlen);
1093
1094 kvfree(in);
1095
1096 return err;
1097}
1098
1099static void mlx5e_destroy_sq(struct mlx5_core_dev *mdev, u32 sqn)
1100{
1101 mlx5_core_destroy_sq(mdev, sqn);
1102}
1103
1104static int mlx5e_create_sq_rdy(struct mlx5_core_dev *mdev,
1105 struct mlx5e_sq_param *param,
1106 struct mlx5e_create_sq_param *csp,
1107 u32 *sqn)
1108{
1109 struct mlx5e_modify_sq_param msp = {0};
1110 int err;
1111
1112 err = mlx5e_create_sq(mdev, param, csp, sqn);
1113 if (err)
1114 return err;
1115
1116 msp.curr_state = MLX5_SQC_STATE_RST;
1117 msp.next_state = MLX5_SQC_STATE_RDY;
1118 err = mlx5e_modify_sq(mdev, *sqn, &msp);
1119 if (err)
1120 mlx5e_destroy_sq(mdev, *sqn);
1121
1122 return err;
1123}
1124
1125static int mlx5e_set_sq_maxrate(struct net_device *dev,
1126 struct mlx5e_txqsq *sq, u32 rate);
1127
1128static int mlx5e_open_txqsq(struct mlx5e_channel *c,
1129 u32 tisn,
1130 int txq_ix,
1131 struct mlx5e_params *params,
1132 struct mlx5e_sq_param *param,
1133 struct mlx5e_txqsq *sq)
1134{
1135 struct mlx5e_create_sq_param csp = {};
1136 u32 tx_rate;
1137 int err;
1138
1139 err = mlx5e_alloc_txqsq(c, txq_ix, params, param, sq);
1140 if (err)
1141 return err;
1142
1143 csp.tisn = tisn;
1144 csp.tis_lst_sz = 1;
1145 csp.cqn = sq->cq.mcq.cqn;
1146 csp.wq_ctrl = &sq->wq_ctrl;
1147 csp.min_inline_mode = sq->min_inline_mode;
1148 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1149 if (err)
1150 goto err_free_txqsq;
1151
1152 tx_rate = c->priv->tx_rates[sq->txq_ix];
1153 if (tx_rate)
1154 mlx5e_set_sq_maxrate(c->netdev, sq, tx_rate);
1155
1156 return 0;
1157
1158err_free_txqsq:
1159 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1160 mlx5e_free_txqsq(sq);
1161
1162 return err;
1163}
1164
1165static void mlx5e_reset_txqsq_cc_pc(struct mlx5e_txqsq *sq)
1166{
1167 WARN_ONCE(sq->cc != sq->pc,
1168 "SQ 0x%x: cc (0x%x) != pc (0x%x)\n",
1169 sq->sqn, sq->cc, sq->pc);
1170 sq->cc = 0;
1171 sq->dma_fifo_cc = 0;
1172 sq->pc = 0;
1173}
1174
1175static void mlx5e_activate_txqsq(struct mlx5e_txqsq *sq)
1176{
1177 sq->txq = netdev_get_tx_queue(sq->channel->netdev, sq->txq_ix);
1178 clear_bit(MLX5E_SQ_STATE_RECOVERING, &sq->state);
1179 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1180 netdev_tx_reset_queue(sq->txq);
1181 netif_tx_start_queue(sq->txq);
1182}
1183
1184static inline void netif_tx_disable_queue(struct netdev_queue *txq)
1185{
1186 __netif_tx_lock_bh(txq);
1187 netif_tx_stop_queue(txq);
1188 __netif_tx_unlock_bh(txq);
1189}
1190
1191static void mlx5e_deactivate_txqsq(struct mlx5e_txqsq *sq)
1192{
1193 struct mlx5e_channel *c = sq->channel;
1194
1195 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1196
1197 napi_synchronize(&c->napi);
1198
1199 netif_tx_disable_queue(sq->txq);
1200
1201
1202 if (mlx5e_wqc_has_room_for(&sq->wq, sq->cc, sq->pc, 1)) {
1203 struct mlx5e_tx_wqe *nop;
1204
1205 sq->db.wqe_info[(sq->pc & sq->wq.sz_m1)].skb = NULL;
1206 nop = mlx5e_post_nop(&sq->wq, sq->sqn, &sq->pc);
1207 mlx5e_notify_hw(&sq->wq, sq->pc, sq->uar_map, &nop->ctrl);
1208 }
1209}
1210
1211static void mlx5e_close_txqsq(struct mlx5e_txqsq *sq)
1212{
1213 struct mlx5e_channel *c = sq->channel;
1214 struct mlx5_core_dev *mdev = c->mdev;
1215 struct mlx5_rate_limit rl = {0};
1216
1217 mlx5e_destroy_sq(mdev, sq->sqn);
1218 if (sq->rate_limit) {
1219 rl.rate = sq->rate_limit;
1220 mlx5_rl_remove_rate(mdev, &rl);
1221 }
1222 mlx5e_free_txqsq_descs(sq);
1223 mlx5e_free_txqsq(sq);
1224}
1225
1226static int mlx5e_wait_for_sq_flush(struct mlx5e_txqsq *sq)
1227{
1228 unsigned long exp_time = jiffies + msecs_to_jiffies(2000);
1229
1230 while (time_before(jiffies, exp_time)) {
1231 if (sq->cc == sq->pc)
1232 return 0;
1233
1234 msleep(20);
1235 }
1236
1237 netdev_err(sq->channel->netdev,
1238 "Wait for SQ 0x%x flush timeout (sq cc = 0x%x, sq pc = 0x%x)\n",
1239 sq->sqn, sq->cc, sq->pc);
1240
1241 return -ETIMEDOUT;
1242}
1243
1244static int mlx5e_sq_to_ready(struct mlx5e_txqsq *sq, int curr_state)
1245{
1246 struct mlx5_core_dev *mdev = sq->channel->mdev;
1247 struct net_device *dev = sq->channel->netdev;
1248 struct mlx5e_modify_sq_param msp = {0};
1249 int err;
1250
1251 msp.curr_state = curr_state;
1252 msp.next_state = MLX5_SQC_STATE_RST;
1253
1254 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1255 if (err) {
1256 netdev_err(dev, "Failed to move sq 0x%x to reset\n", sq->sqn);
1257 return err;
1258 }
1259
1260 memset(&msp, 0, sizeof(msp));
1261 msp.curr_state = MLX5_SQC_STATE_RST;
1262 msp.next_state = MLX5_SQC_STATE_RDY;
1263
1264 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1265 if (err) {
1266 netdev_err(dev, "Failed to move sq 0x%x to ready\n", sq->sqn);
1267 return err;
1268 }
1269
1270 return 0;
1271}
1272
1273static void mlx5e_sq_recover(struct work_struct *work)
1274{
1275 struct mlx5e_txqsq_recover *recover =
1276 container_of(work, struct mlx5e_txqsq_recover,
1277 recover_work);
1278 struct mlx5e_txqsq *sq = container_of(recover, struct mlx5e_txqsq,
1279 recover);
1280 struct mlx5_core_dev *mdev = sq->channel->mdev;
1281 struct net_device *dev = sq->channel->netdev;
1282 u8 state;
1283 int err;
1284
1285 err = mlx5_core_query_sq_state(mdev, sq->sqn, &state);
1286 if (err) {
1287 netdev_err(dev, "Failed to query SQ 0x%x state. err = %d\n",
1288 sq->sqn, err);
1289 return;
1290 }
1291
1292 if (state != MLX5_RQC_STATE_ERR) {
1293 netdev_err(dev, "SQ 0x%x not in ERROR state\n", sq->sqn);
1294 return;
1295 }
1296
1297 netif_tx_disable_queue(sq->txq);
1298
1299 if (mlx5e_wait_for_sq_flush(sq))
1300 return;
1301
1302
1303
1304
1305
1306
1307 if (jiffies_to_msecs(jiffies - recover->last_recover) <
1308 MLX5E_SQ_RECOVER_MIN_INTERVAL) {
1309 netdev_err(dev, "Recover SQ 0x%x canceled, too many error CQEs\n",
1310 sq->sqn);
1311 return;
1312 }
1313
1314
1315
1316
1317
1318 if (mlx5e_sq_to_ready(sq, state))
1319 return;
1320
1321 mlx5e_reset_txqsq_cc_pc(sq);
1322 sq->stats.recover++;
1323 recover->last_recover = jiffies;
1324 mlx5e_activate_txqsq(sq);
1325}
1326
1327static int mlx5e_open_icosq(struct mlx5e_channel *c,
1328 struct mlx5e_params *params,
1329 struct mlx5e_sq_param *param,
1330 struct mlx5e_icosq *sq)
1331{
1332 struct mlx5e_create_sq_param csp = {};
1333 int err;
1334
1335 err = mlx5e_alloc_icosq(c, param, sq);
1336 if (err)
1337 return err;
1338
1339 csp.cqn = sq->cq.mcq.cqn;
1340 csp.wq_ctrl = &sq->wq_ctrl;
1341 csp.min_inline_mode = params->tx_min_inline_mode;
1342 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1343 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1344 if (err)
1345 goto err_free_icosq;
1346
1347 return 0;
1348
1349err_free_icosq:
1350 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1351 mlx5e_free_icosq(sq);
1352
1353 return err;
1354}
1355
1356static void mlx5e_close_icosq(struct mlx5e_icosq *sq)
1357{
1358 struct mlx5e_channel *c = sq->channel;
1359
1360 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1361 napi_synchronize(&c->napi);
1362
1363 mlx5e_destroy_sq(c->mdev, sq->sqn);
1364 mlx5e_free_icosq(sq);
1365}
1366
1367static int mlx5e_open_xdpsq(struct mlx5e_channel *c,
1368 struct mlx5e_params *params,
1369 struct mlx5e_sq_param *param,
1370 struct mlx5e_xdpsq *sq)
1371{
1372 unsigned int ds_cnt = MLX5E_XDP_TX_DS_COUNT;
1373 struct mlx5e_create_sq_param csp = {};
1374 unsigned int inline_hdr_sz = 0;
1375 int err;
1376 int i;
1377
1378 err = mlx5e_alloc_xdpsq(c, params, param, sq);
1379 if (err)
1380 return err;
1381
1382 csp.tis_lst_sz = 1;
1383 csp.tisn = c->priv->tisn[0];
1384 csp.cqn = sq->cq.mcq.cqn;
1385 csp.wq_ctrl = &sq->wq_ctrl;
1386 csp.min_inline_mode = sq->min_inline_mode;
1387 set_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1388 err = mlx5e_create_sq_rdy(c->mdev, param, &csp, &sq->sqn);
1389 if (err)
1390 goto err_free_xdpsq;
1391
1392 if (sq->min_inline_mode != MLX5_INLINE_MODE_NONE) {
1393 inline_hdr_sz = MLX5E_XDP_MIN_INLINE;
1394 ds_cnt++;
1395 }
1396
1397
1398 for (i = 0; i < mlx5_wq_cyc_get_size(&sq->wq); i++) {
1399 struct mlx5e_tx_wqe *wqe = mlx5_wq_cyc_get_wqe(&sq->wq, i);
1400 struct mlx5_wqe_ctrl_seg *cseg = &wqe->ctrl;
1401 struct mlx5_wqe_eth_seg *eseg = &wqe->eth;
1402 struct mlx5_wqe_data_seg *dseg;
1403
1404 cseg->qpn_ds = cpu_to_be32((sq->sqn << 8) | ds_cnt);
1405 eseg->inline_hdr.sz = cpu_to_be16(inline_hdr_sz);
1406
1407 dseg = (struct mlx5_wqe_data_seg *)cseg + (ds_cnt - 1);
1408 dseg->lkey = sq->mkey_be;
1409 }
1410
1411 return 0;
1412
1413err_free_xdpsq:
1414 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1415 mlx5e_free_xdpsq(sq);
1416
1417 return err;
1418}
1419
1420static void mlx5e_close_xdpsq(struct mlx5e_xdpsq *sq)
1421{
1422 struct mlx5e_channel *c = sq->channel;
1423
1424 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
1425 napi_synchronize(&c->napi);
1426
1427 mlx5e_destroy_sq(c->mdev, sq->sqn);
1428 mlx5e_free_xdpsq_descs(sq);
1429 mlx5e_free_xdpsq(sq);
1430}
1431
1432static int mlx5e_alloc_cq_common(struct mlx5_core_dev *mdev,
1433 struct mlx5e_cq_param *param,
1434 struct mlx5e_cq *cq)
1435{
1436 struct mlx5_core_cq *mcq = &cq->mcq;
1437 int eqn_not_used;
1438 unsigned int irqn;
1439 int err;
1440 u32 i;
1441
1442 err = mlx5_cqwq_create(mdev, ¶m->wq, param->cqc, &cq->wq,
1443 &cq->wq_ctrl);
1444 if (err)
1445 return err;
1446
1447 mlx5_vector2eqn(mdev, param->eq_ix, &eqn_not_used, &irqn);
1448
1449 mcq->cqe_sz = 64;
1450 mcq->set_ci_db = cq->wq_ctrl.db.db;
1451 mcq->arm_db = cq->wq_ctrl.db.db + 1;
1452 *mcq->set_ci_db = 0;
1453 *mcq->arm_db = 0;
1454 mcq->vector = param->eq_ix;
1455 mcq->comp = mlx5e_completion_event;
1456 mcq->event = mlx5e_cq_error_event;
1457 mcq->irqn = irqn;
1458
1459 for (i = 0; i < mlx5_cqwq_get_size(&cq->wq); i++) {
1460 struct mlx5_cqe64 *cqe = mlx5_cqwq_get_wqe(&cq->wq, i);
1461
1462 cqe->op_own = 0xf1;
1463 }
1464
1465 cq->mdev = mdev;
1466
1467 return 0;
1468}
1469
1470static int mlx5e_alloc_cq(struct mlx5e_channel *c,
1471 struct mlx5e_cq_param *param,
1472 struct mlx5e_cq *cq)
1473{
1474 struct mlx5_core_dev *mdev = c->priv->mdev;
1475 int err;
1476
1477 param->wq.buf_numa_node = cpu_to_node(c->cpu);
1478 param->wq.db_numa_node = cpu_to_node(c->cpu);
1479 param->eq_ix = c->ix;
1480
1481 err = mlx5e_alloc_cq_common(mdev, param, cq);
1482
1483 cq->napi = &c->napi;
1484 cq->channel = c;
1485
1486 return err;
1487}
1488
1489static void mlx5e_free_cq(struct mlx5e_cq *cq)
1490{
1491 mlx5_cqwq_destroy(&cq->wq_ctrl);
1492}
1493
1494static int mlx5e_create_cq(struct mlx5e_cq *cq, struct mlx5e_cq_param *param)
1495{
1496 struct mlx5_core_dev *mdev = cq->mdev;
1497 struct mlx5_core_cq *mcq = &cq->mcq;
1498
1499 void *in;
1500 void *cqc;
1501 int inlen;
1502 unsigned int irqn_not_used;
1503 int eqn;
1504 int err;
1505
1506 inlen = MLX5_ST_SZ_BYTES(create_cq_in) +
1507 sizeof(u64) * cq->wq_ctrl.frag_buf.npages;
1508 in = kvzalloc(inlen, GFP_KERNEL);
1509 if (!in)
1510 return -ENOMEM;
1511
1512 cqc = MLX5_ADDR_OF(create_cq_in, in, cq_context);
1513
1514 memcpy(cqc, param->cqc, sizeof(param->cqc));
1515
1516 mlx5_fill_page_frag_array(&cq->wq_ctrl.frag_buf,
1517 (__be64 *)MLX5_ADDR_OF(create_cq_in, in, pas));
1518
1519 mlx5_vector2eqn(mdev, param->eq_ix, &eqn, &irqn_not_used);
1520
1521 MLX5_SET(cqc, cqc, cq_period_mode, param->cq_period_mode);
1522 MLX5_SET(cqc, cqc, c_eqn, eqn);
1523 MLX5_SET(cqc, cqc, uar_page, mdev->priv.uar->index);
1524 MLX5_SET(cqc, cqc, log_page_size, cq->wq_ctrl.frag_buf.page_shift -
1525 MLX5_ADAPTER_PAGE_SHIFT);
1526 MLX5_SET64(cqc, cqc, dbr_addr, cq->wq_ctrl.db.dma);
1527
1528 err = mlx5_core_create_cq(mdev, mcq, in, inlen);
1529
1530 kvfree(in);
1531
1532 if (err)
1533 return err;
1534
1535 mlx5e_cq_arm(cq);
1536
1537 return 0;
1538}
1539
1540static void mlx5e_destroy_cq(struct mlx5e_cq *cq)
1541{
1542 mlx5_core_destroy_cq(cq->mdev, &cq->mcq);
1543}
1544
1545static int mlx5e_open_cq(struct mlx5e_channel *c,
1546 struct net_dim_cq_moder moder,
1547 struct mlx5e_cq_param *param,
1548 struct mlx5e_cq *cq)
1549{
1550 struct mlx5_core_dev *mdev = c->mdev;
1551 int err;
1552
1553 err = mlx5e_alloc_cq(c, param, cq);
1554 if (err)
1555 return err;
1556
1557 err = mlx5e_create_cq(cq, param);
1558 if (err)
1559 goto err_free_cq;
1560
1561 if (MLX5_CAP_GEN(mdev, cq_moderation))
1562 mlx5_core_modify_cq_moderation(mdev, &cq->mcq, moder.usec, moder.pkts);
1563 return 0;
1564
1565err_free_cq:
1566 mlx5e_free_cq(cq);
1567
1568 return err;
1569}
1570
1571static void mlx5e_close_cq(struct mlx5e_cq *cq)
1572{
1573 mlx5e_destroy_cq(cq);
1574 mlx5e_free_cq(cq);
1575}
1576
1577static int mlx5e_get_cpu(struct mlx5e_priv *priv, int ix)
1578{
1579 return cpumask_first(priv->mdev->priv.irq_info[ix].mask);
1580}
1581
1582static int mlx5e_open_tx_cqs(struct mlx5e_channel *c,
1583 struct mlx5e_params *params,
1584 struct mlx5e_channel_param *cparam)
1585{
1586 int err;
1587 int tc;
1588
1589 for (tc = 0; tc < c->num_tc; tc++) {
1590 err = mlx5e_open_cq(c, params->tx_cq_moderation,
1591 &cparam->tx_cq, &c->sq[tc].cq);
1592 if (err)
1593 goto err_close_tx_cqs;
1594 }
1595
1596 return 0;
1597
1598err_close_tx_cqs:
1599 for (tc--; tc >= 0; tc--)
1600 mlx5e_close_cq(&c->sq[tc].cq);
1601
1602 return err;
1603}
1604
1605static void mlx5e_close_tx_cqs(struct mlx5e_channel *c)
1606{
1607 int tc;
1608
1609 for (tc = 0; tc < c->num_tc; tc++)
1610 mlx5e_close_cq(&c->sq[tc].cq);
1611}
1612
1613static int mlx5e_open_sqs(struct mlx5e_channel *c,
1614 struct mlx5e_params *params,
1615 struct mlx5e_channel_param *cparam)
1616{
1617 int err;
1618 int tc;
1619
1620 for (tc = 0; tc < params->num_tc; tc++) {
1621 int txq_ix = c->ix + tc * params->num_channels;
1622
1623 err = mlx5e_open_txqsq(c, c->priv->tisn[tc], txq_ix,
1624 params, &cparam->sq, &c->sq[tc]);
1625 if (err)
1626 goto err_close_sqs;
1627 }
1628
1629 return 0;
1630
1631err_close_sqs:
1632 for (tc--; tc >= 0; tc--)
1633 mlx5e_close_txqsq(&c->sq[tc]);
1634
1635 return err;
1636}
1637
1638static void mlx5e_close_sqs(struct mlx5e_channel *c)
1639{
1640 int tc;
1641
1642 for (tc = 0; tc < c->num_tc; tc++)
1643 mlx5e_close_txqsq(&c->sq[tc]);
1644}
1645
1646static int mlx5e_set_sq_maxrate(struct net_device *dev,
1647 struct mlx5e_txqsq *sq, u32 rate)
1648{
1649 struct mlx5e_priv *priv = netdev_priv(dev);
1650 struct mlx5_core_dev *mdev = priv->mdev;
1651 struct mlx5e_modify_sq_param msp = {0};
1652 struct mlx5_rate_limit rl = {0};
1653 u16 rl_index = 0;
1654 int err;
1655
1656 if (rate == sq->rate_limit)
1657
1658 return 0;
1659
1660 if (sq->rate_limit) {
1661 rl.rate = sq->rate_limit;
1662
1663 mlx5_rl_remove_rate(mdev, &rl);
1664 }
1665
1666 sq->rate_limit = 0;
1667
1668 if (rate) {
1669 rl.rate = rate;
1670 err = mlx5_rl_add_rate(mdev, &rl_index, &rl);
1671 if (err) {
1672 netdev_err(dev, "Failed configuring rate %u: %d\n",
1673 rate, err);
1674 return err;
1675 }
1676 }
1677
1678 msp.curr_state = MLX5_SQC_STATE_RDY;
1679 msp.next_state = MLX5_SQC_STATE_RDY;
1680 msp.rl_index = rl_index;
1681 msp.rl_update = true;
1682 err = mlx5e_modify_sq(mdev, sq->sqn, &msp);
1683 if (err) {
1684 netdev_err(dev, "Failed configuring rate %u: %d\n",
1685 rate, err);
1686
1687 if (rate)
1688 mlx5_rl_remove_rate(mdev, &rl);
1689 return err;
1690 }
1691
1692 sq->rate_limit = rate;
1693 return 0;
1694}
1695
1696static int mlx5e_set_tx_maxrate(struct net_device *dev, int index, u32 rate)
1697{
1698 struct mlx5e_priv *priv = netdev_priv(dev);
1699 struct mlx5_core_dev *mdev = priv->mdev;
1700 struct mlx5e_txqsq *sq = priv->txq2sq[index];
1701 int err = 0;
1702
1703 if (!mlx5_rl_is_supported(mdev)) {
1704 netdev_err(dev, "Rate limiting is not supported on this device\n");
1705 return -EINVAL;
1706 }
1707
1708
1709 rate = rate << 10;
1710
1711
1712 if (rate && !mlx5_rl_is_in_range(mdev, rate)) {
1713 netdev_err(dev, "TX rate %u, is not in range\n", rate);
1714 return -ERANGE;
1715 }
1716
1717 mutex_lock(&priv->state_lock);
1718 if (test_bit(MLX5E_STATE_OPENED, &priv->state))
1719 err = mlx5e_set_sq_maxrate(dev, sq, rate);
1720 if (!err)
1721 priv->tx_rates[index] = rate;
1722 mutex_unlock(&priv->state_lock);
1723
1724 return err;
1725}
1726
1727static int mlx5e_open_channel(struct mlx5e_priv *priv, int ix,
1728 struct mlx5e_params *params,
1729 struct mlx5e_channel_param *cparam,
1730 struct mlx5e_channel **cp)
1731{
1732 struct net_dim_cq_moder icocq_moder = {0, 0};
1733 struct net_device *netdev = priv->netdev;
1734 int cpu = mlx5e_get_cpu(priv, ix);
1735 struct mlx5e_channel *c;
1736 unsigned int irq;
1737 int err;
1738 int eqn;
1739
1740 c = kzalloc_node(sizeof(*c), GFP_KERNEL, cpu_to_node(cpu));
1741 if (!c)
1742 return -ENOMEM;
1743
1744 c->priv = priv;
1745 c->mdev = priv->mdev;
1746 c->tstamp = &priv->tstamp;
1747 c->ix = ix;
1748 c->cpu = cpu;
1749 c->pdev = &priv->mdev->pdev->dev;
1750 c->netdev = priv->netdev;
1751 c->mkey_be = cpu_to_be32(priv->mdev->mlx5e_res.mkey.key);
1752 c->num_tc = params->num_tc;
1753 c->xdp = !!params->xdp_prog;
1754
1755 mlx5_vector2eqn(priv->mdev, ix, &eqn, &irq);
1756 c->irq_desc = irq_to_desc(irq);
1757
1758 netif_napi_add(netdev, &c->napi, mlx5e_napi_poll, 64);
1759
1760 err = mlx5e_open_cq(c, icocq_moder, &cparam->icosq_cq, &c->icosq.cq);
1761 if (err)
1762 goto err_napi_del;
1763
1764 err = mlx5e_open_tx_cqs(c, params, cparam);
1765 if (err)
1766 goto err_close_icosq_cq;
1767
1768 err = mlx5e_open_cq(c, params->rx_cq_moderation, &cparam->rx_cq, &c->rq.cq);
1769 if (err)
1770 goto err_close_tx_cqs;
1771
1772
1773 err = c->xdp ? mlx5e_open_cq(c, params->tx_cq_moderation,
1774 &cparam->tx_cq, &c->rq.xdpsq.cq) : 0;
1775 if (err)
1776 goto err_close_rx_cq;
1777
1778 napi_enable(&c->napi);
1779
1780 err = mlx5e_open_icosq(c, params, &cparam->icosq, &c->icosq);
1781 if (err)
1782 goto err_disable_napi;
1783
1784 err = mlx5e_open_sqs(c, params, cparam);
1785 if (err)
1786 goto err_close_icosq;
1787
1788 err = c->xdp ? mlx5e_open_xdpsq(c, params, &cparam->xdp_sq, &c->rq.xdpsq) : 0;
1789 if (err)
1790 goto err_close_sqs;
1791
1792 err = mlx5e_open_rq(c, params, &cparam->rq, &c->rq);
1793 if (err)
1794 goto err_close_xdp_sq;
1795
1796 *cp = c;
1797
1798 return 0;
1799err_close_xdp_sq:
1800 if (c->xdp)
1801 mlx5e_close_xdpsq(&c->rq.xdpsq);
1802
1803err_close_sqs:
1804 mlx5e_close_sqs(c);
1805
1806err_close_icosq:
1807 mlx5e_close_icosq(&c->icosq);
1808
1809err_disable_napi:
1810 napi_disable(&c->napi);
1811 if (c->xdp)
1812 mlx5e_close_cq(&c->rq.xdpsq.cq);
1813
1814err_close_rx_cq:
1815 mlx5e_close_cq(&c->rq.cq);
1816
1817err_close_tx_cqs:
1818 mlx5e_close_tx_cqs(c);
1819
1820err_close_icosq_cq:
1821 mlx5e_close_cq(&c->icosq.cq);
1822
1823err_napi_del:
1824 netif_napi_del(&c->napi);
1825 kfree(c);
1826
1827 return err;
1828}
1829
1830static void mlx5e_activate_channel(struct mlx5e_channel *c)
1831{
1832 int tc;
1833
1834 for (tc = 0; tc < c->num_tc; tc++)
1835 mlx5e_activate_txqsq(&c->sq[tc]);
1836 mlx5e_activate_rq(&c->rq);
1837 netif_set_xps_queue(c->netdev, get_cpu_mask(c->cpu), c->ix);
1838}
1839
1840static void mlx5e_deactivate_channel(struct mlx5e_channel *c)
1841{
1842 int tc;
1843
1844 mlx5e_deactivate_rq(&c->rq);
1845 for (tc = 0; tc < c->num_tc; tc++)
1846 mlx5e_deactivate_txqsq(&c->sq[tc]);
1847}
1848
1849static void mlx5e_close_channel(struct mlx5e_channel *c)
1850{
1851 mlx5e_close_rq(&c->rq);
1852 if (c->xdp)
1853 mlx5e_close_xdpsq(&c->rq.xdpsq);
1854 mlx5e_close_sqs(c);
1855 mlx5e_close_icosq(&c->icosq);
1856 napi_disable(&c->napi);
1857 if (c->xdp)
1858 mlx5e_close_cq(&c->rq.xdpsq.cq);
1859 mlx5e_close_cq(&c->rq.cq);
1860 mlx5e_close_tx_cqs(c);
1861 mlx5e_close_cq(&c->icosq.cq);
1862 netif_napi_del(&c->napi);
1863
1864 kfree(c);
1865}
1866
1867static void mlx5e_build_rq_param(struct mlx5e_priv *priv,
1868 struct mlx5e_params *params,
1869 struct mlx5e_rq_param *param)
1870{
1871 struct mlx5_core_dev *mdev = priv->mdev;
1872 void *rqc = param->rqc;
1873 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1874
1875 switch (params->rq_wq_type) {
1876 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1877 MLX5_SET(wq, wq, log_wqe_num_of_strides,
1878 mlx5e_mpwqe_get_log_num_strides(mdev, params) -
1879 MLX5_MPWQE_LOG_NUM_STRIDES_BASE);
1880 MLX5_SET(wq, wq, log_wqe_stride_size,
1881 mlx5e_mpwqe_get_log_stride_size(mdev, params) -
1882 MLX5_MPWQE_LOG_STRIDE_SZ_BASE);
1883 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ);
1884 MLX5_SET(wq, wq, log_wq_sz, mlx5e_mpwqe_get_log_rq_size(params));
1885 break;
1886 default:
1887 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1888 MLX5_SET(wq, wq, log_wq_sz, params->log_rq_mtu_frames);
1889 }
1890
1891 MLX5_SET(wq, wq, end_padding_mode, MLX5_WQ_END_PAD_MODE_ALIGN);
1892 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1893 MLX5_SET(wq, wq, pd, mdev->mlx5e_res.pdn);
1894 MLX5_SET(rqc, rqc, counter_set_id, priv->q_counter);
1895 MLX5_SET(rqc, rqc, vsd, params->vlan_strip_disable);
1896 MLX5_SET(rqc, rqc, scatter_fcs, params->scatter_fcs_en);
1897
1898 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1899 param->wq.linear = 1;
1900}
1901
1902static void mlx5e_build_drop_rq_param(struct mlx5e_priv *priv,
1903 struct mlx5e_rq_param *param)
1904{
1905 struct mlx5_core_dev *mdev = priv->mdev;
1906 void *rqc = param->rqc;
1907 void *wq = MLX5_ADDR_OF(rqc, rqc, wq);
1908
1909 MLX5_SET(wq, wq, wq_type, MLX5_WQ_TYPE_LINKED_LIST);
1910 MLX5_SET(wq, wq, log_wq_stride, ilog2(sizeof(struct mlx5e_rx_wqe)));
1911 MLX5_SET(rqc, rqc, counter_set_id, priv->drop_rq_q_counter);
1912
1913 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
1914}
1915
1916static void mlx5e_build_sq_param_common(struct mlx5e_priv *priv,
1917 struct mlx5e_sq_param *param)
1918{
1919 void *sqc = param->sqc;
1920 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1921
1922 MLX5_SET(wq, wq, log_wq_stride, ilog2(MLX5_SEND_WQE_BB));
1923 MLX5_SET(wq, wq, pd, priv->mdev->mlx5e_res.pdn);
1924
1925 param->wq.buf_numa_node = dev_to_node(&priv->mdev->pdev->dev);
1926}
1927
1928static void mlx5e_build_sq_param(struct mlx5e_priv *priv,
1929 struct mlx5e_params *params,
1930 struct mlx5e_sq_param *param)
1931{
1932 void *sqc = param->sqc;
1933 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
1934
1935 mlx5e_build_sq_param_common(priv, param);
1936 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
1937 MLX5_SET(sqc, sqc, allow_swp, !!MLX5_IPSEC_DEV(priv->mdev));
1938}
1939
1940static void mlx5e_build_common_cq_param(struct mlx5e_priv *priv,
1941 struct mlx5e_cq_param *param)
1942{
1943 void *cqc = param->cqc;
1944
1945 MLX5_SET(cqc, cqc, uar_page, priv->mdev->priv.uar->index);
1946}
1947
1948static void mlx5e_build_rx_cq_param(struct mlx5e_priv *priv,
1949 struct mlx5e_params *params,
1950 struct mlx5e_cq_param *param)
1951{
1952 struct mlx5_core_dev *mdev = priv->mdev;
1953 void *cqc = param->cqc;
1954 u8 log_cq_size;
1955
1956 switch (params->rq_wq_type) {
1957 case MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ:
1958 log_cq_size = mlx5e_mpwqe_get_log_rq_size(params) +
1959 mlx5e_mpwqe_get_log_num_strides(mdev, params);
1960 break;
1961 default:
1962 log_cq_size = params->log_rq_mtu_frames;
1963 }
1964
1965 MLX5_SET(cqc, cqc, log_cq_size, log_cq_size);
1966 if (MLX5E_GET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS)) {
1967 MLX5_SET(cqc, cqc, mini_cqe_res_format, MLX5_CQE_FORMAT_CSUM);
1968 MLX5_SET(cqc, cqc, cqe_comp_en, 1);
1969 }
1970
1971 mlx5e_build_common_cq_param(priv, param);
1972 param->cq_period_mode = params->rx_cq_moderation.cq_period_mode;
1973}
1974
1975static void mlx5e_build_tx_cq_param(struct mlx5e_priv *priv,
1976 struct mlx5e_params *params,
1977 struct mlx5e_cq_param *param)
1978{
1979 void *cqc = param->cqc;
1980
1981 MLX5_SET(cqc, cqc, log_cq_size, params->log_sq_size);
1982
1983 mlx5e_build_common_cq_param(priv, param);
1984 param->cq_period_mode = params->tx_cq_moderation.cq_period_mode;
1985}
1986
1987static void mlx5e_build_ico_cq_param(struct mlx5e_priv *priv,
1988 u8 log_wq_size,
1989 struct mlx5e_cq_param *param)
1990{
1991 void *cqc = param->cqc;
1992
1993 MLX5_SET(cqc, cqc, log_cq_size, log_wq_size);
1994
1995 mlx5e_build_common_cq_param(priv, param);
1996
1997 param->cq_period_mode = NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE;
1998}
1999
2000static void mlx5e_build_icosq_param(struct mlx5e_priv *priv,
2001 u8 log_wq_size,
2002 struct mlx5e_sq_param *param)
2003{
2004 void *sqc = param->sqc;
2005 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2006
2007 mlx5e_build_sq_param_common(priv, param);
2008
2009 MLX5_SET(wq, wq, log_wq_sz, log_wq_size);
2010 MLX5_SET(sqc, sqc, reg_umr, MLX5_CAP_ETH(priv->mdev, reg_umr_sq));
2011}
2012
2013static void mlx5e_build_xdpsq_param(struct mlx5e_priv *priv,
2014 struct mlx5e_params *params,
2015 struct mlx5e_sq_param *param)
2016{
2017 void *sqc = param->sqc;
2018 void *wq = MLX5_ADDR_OF(sqc, sqc, wq);
2019
2020 mlx5e_build_sq_param_common(priv, param);
2021 MLX5_SET(wq, wq, log_wq_sz, params->log_sq_size);
2022}
2023
2024static void mlx5e_build_channel_param(struct mlx5e_priv *priv,
2025 struct mlx5e_params *params,
2026 struct mlx5e_channel_param *cparam)
2027{
2028 u8 icosq_log_wq_sz = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
2029
2030 mlx5e_build_rq_param(priv, params, &cparam->rq);
2031 mlx5e_build_sq_param(priv, params, &cparam->sq);
2032 mlx5e_build_xdpsq_param(priv, params, &cparam->xdp_sq);
2033 mlx5e_build_icosq_param(priv, icosq_log_wq_sz, &cparam->icosq);
2034 mlx5e_build_rx_cq_param(priv, params, &cparam->rx_cq);
2035 mlx5e_build_tx_cq_param(priv, params, &cparam->tx_cq);
2036 mlx5e_build_ico_cq_param(priv, icosq_log_wq_sz, &cparam->icosq_cq);
2037}
2038
2039int mlx5e_open_channels(struct mlx5e_priv *priv,
2040 struct mlx5e_channels *chs)
2041{
2042 struct mlx5e_channel_param *cparam;
2043 int err = -ENOMEM;
2044 int i;
2045
2046 chs->num = chs->params.num_channels;
2047
2048 chs->c = kcalloc(chs->num, sizeof(struct mlx5e_channel *), GFP_KERNEL);
2049 cparam = kzalloc(sizeof(struct mlx5e_channel_param), GFP_KERNEL);
2050 if (!chs->c || !cparam)
2051 goto err_free;
2052
2053 mlx5e_build_channel_param(priv, &chs->params, cparam);
2054 for (i = 0; i < chs->num; i++) {
2055 err = mlx5e_open_channel(priv, i, &chs->params, cparam, &chs->c[i]);
2056 if (err)
2057 goto err_close_channels;
2058 }
2059
2060 kfree(cparam);
2061 return 0;
2062
2063err_close_channels:
2064 for (i--; i >= 0; i--)
2065 mlx5e_close_channel(chs->c[i]);
2066
2067err_free:
2068 kfree(chs->c);
2069 kfree(cparam);
2070 chs->num = 0;
2071 return err;
2072}
2073
2074static void mlx5e_activate_channels(struct mlx5e_channels *chs)
2075{
2076 int i;
2077
2078 for (i = 0; i < chs->num; i++)
2079 mlx5e_activate_channel(chs->c[i]);
2080}
2081
2082static int mlx5e_wait_channels_min_rx_wqes(struct mlx5e_channels *chs)
2083{
2084 int err = 0;
2085 int i;
2086
2087 for (i = 0; i < chs->num; i++) {
2088 err = mlx5e_wait_for_min_rx_wqes(&chs->c[i]->rq);
2089 if (err)
2090 break;
2091 }
2092
2093 return err;
2094}
2095
2096static void mlx5e_deactivate_channels(struct mlx5e_channels *chs)
2097{
2098 int i;
2099
2100 for (i = 0; i < chs->num; i++)
2101 mlx5e_deactivate_channel(chs->c[i]);
2102}
2103
2104void mlx5e_close_channels(struct mlx5e_channels *chs)
2105{
2106 int i;
2107
2108 for (i = 0; i < chs->num; i++)
2109 mlx5e_close_channel(chs->c[i]);
2110
2111 kfree(chs->c);
2112 chs->num = 0;
2113}
2114
2115static int
2116mlx5e_create_rqt(struct mlx5e_priv *priv, int sz, struct mlx5e_rqt *rqt)
2117{
2118 struct mlx5_core_dev *mdev = priv->mdev;
2119 void *rqtc;
2120 int inlen;
2121 int err;
2122 u32 *in;
2123 int i;
2124
2125 inlen = MLX5_ST_SZ_BYTES(create_rqt_in) + sizeof(u32) * sz;
2126 in = kvzalloc(inlen, GFP_KERNEL);
2127 if (!in)
2128 return -ENOMEM;
2129
2130 rqtc = MLX5_ADDR_OF(create_rqt_in, in, rqt_context);
2131
2132 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2133 MLX5_SET(rqtc, rqtc, rqt_max_size, sz);
2134
2135 for (i = 0; i < sz; i++)
2136 MLX5_SET(rqtc, rqtc, rq_num[i], priv->drop_rq.rqn);
2137
2138 err = mlx5_core_create_rqt(mdev, in, inlen, &rqt->rqtn);
2139 if (!err)
2140 rqt->enabled = true;
2141
2142 kvfree(in);
2143 return err;
2144}
2145
2146void mlx5e_destroy_rqt(struct mlx5e_priv *priv, struct mlx5e_rqt *rqt)
2147{
2148 rqt->enabled = false;
2149 mlx5_core_destroy_rqt(priv->mdev, rqt->rqtn);
2150}
2151
2152int mlx5e_create_indirect_rqt(struct mlx5e_priv *priv)
2153{
2154 struct mlx5e_rqt *rqt = &priv->indir_rqt;
2155 int err;
2156
2157 err = mlx5e_create_rqt(priv, MLX5E_INDIR_RQT_SIZE, rqt);
2158 if (err)
2159 mlx5_core_warn(priv->mdev, "create indirect rqts failed, %d\n", err);
2160 return err;
2161}
2162
2163int mlx5e_create_direct_rqts(struct mlx5e_priv *priv)
2164{
2165 struct mlx5e_rqt *rqt;
2166 int err;
2167 int ix;
2168
2169 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2170 rqt = &priv->direct_tir[ix].rqt;
2171 err = mlx5e_create_rqt(priv, 1 , rqt);
2172 if (err)
2173 goto err_destroy_rqts;
2174 }
2175
2176 return 0;
2177
2178err_destroy_rqts:
2179 mlx5_core_warn(priv->mdev, "create direct rqts failed, %d\n", err);
2180 for (ix--; ix >= 0; ix--)
2181 mlx5e_destroy_rqt(priv, &priv->direct_tir[ix].rqt);
2182
2183 return err;
2184}
2185
2186void mlx5e_destroy_direct_rqts(struct mlx5e_priv *priv)
2187{
2188 int i;
2189
2190 for (i = 0; i < priv->profile->max_nch(priv->mdev); i++)
2191 mlx5e_destroy_rqt(priv, &priv->direct_tir[i].rqt);
2192}
2193
2194static int mlx5e_rx_hash_fn(int hfunc)
2195{
2196 return (hfunc == ETH_RSS_HASH_TOP) ?
2197 MLX5_RX_HASH_FN_TOEPLITZ :
2198 MLX5_RX_HASH_FN_INVERTED_XOR8;
2199}
2200
2201int mlx5e_bits_invert(unsigned long a, int size)
2202{
2203 int inv = 0;
2204 int i;
2205
2206 for (i = 0; i < size; i++)
2207 inv |= (test_bit(size - i - 1, &a) ? 1 : 0) << i;
2208
2209 return inv;
2210}
2211
2212static void mlx5e_fill_rqt_rqns(struct mlx5e_priv *priv, int sz,
2213 struct mlx5e_redirect_rqt_param rrp, void *rqtc)
2214{
2215 int i;
2216
2217 for (i = 0; i < sz; i++) {
2218 u32 rqn;
2219
2220 if (rrp.is_rss) {
2221 int ix = i;
2222
2223 if (rrp.rss.hfunc == ETH_RSS_HASH_XOR)
2224 ix = mlx5e_bits_invert(i, ilog2(sz));
2225
2226 ix = priv->channels.params.indirection_rqt[ix];
2227 rqn = rrp.rss.channels->c[ix]->rq.rqn;
2228 } else {
2229 rqn = rrp.rqn;
2230 }
2231 MLX5_SET(rqtc, rqtc, rq_num[i], rqn);
2232 }
2233}
2234
2235int mlx5e_redirect_rqt(struct mlx5e_priv *priv, u32 rqtn, int sz,
2236 struct mlx5e_redirect_rqt_param rrp)
2237{
2238 struct mlx5_core_dev *mdev = priv->mdev;
2239 void *rqtc;
2240 int inlen;
2241 u32 *in;
2242 int err;
2243
2244 inlen = MLX5_ST_SZ_BYTES(modify_rqt_in) + sizeof(u32) * sz;
2245 in = kvzalloc(inlen, GFP_KERNEL);
2246 if (!in)
2247 return -ENOMEM;
2248
2249 rqtc = MLX5_ADDR_OF(modify_rqt_in, in, ctx);
2250
2251 MLX5_SET(rqtc, rqtc, rqt_actual_size, sz);
2252 MLX5_SET(modify_rqt_in, in, bitmask.rqn_list, 1);
2253 mlx5e_fill_rqt_rqns(priv, sz, rrp, rqtc);
2254 err = mlx5_core_modify_rqt(mdev, rqtn, in, inlen);
2255
2256 kvfree(in);
2257 return err;
2258}
2259
2260static u32 mlx5e_get_direct_rqn(struct mlx5e_priv *priv, int ix,
2261 struct mlx5e_redirect_rqt_param rrp)
2262{
2263 if (!rrp.is_rss)
2264 return rrp.rqn;
2265
2266 if (ix >= rrp.rss.channels->num)
2267 return priv->drop_rq.rqn;
2268
2269 return rrp.rss.channels->c[ix]->rq.rqn;
2270}
2271
2272static void mlx5e_redirect_rqts(struct mlx5e_priv *priv,
2273 struct mlx5e_redirect_rqt_param rrp)
2274{
2275 u32 rqtn;
2276 int ix;
2277
2278 if (priv->indir_rqt.enabled) {
2279
2280 rqtn = priv->indir_rqt.rqtn;
2281 mlx5e_redirect_rqt(priv, rqtn, MLX5E_INDIR_RQT_SIZE, rrp);
2282 }
2283
2284 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2285 struct mlx5e_redirect_rqt_param direct_rrp = {
2286 .is_rss = false,
2287 {
2288 .rqn = mlx5e_get_direct_rqn(priv, ix, rrp)
2289 },
2290 };
2291
2292
2293 if (!priv->direct_tir[ix].rqt.enabled)
2294 continue;
2295
2296 rqtn = priv->direct_tir[ix].rqt.rqtn;
2297 mlx5e_redirect_rqt(priv, rqtn, 1, direct_rrp);
2298 }
2299}
2300
2301static void mlx5e_redirect_rqts_to_channels(struct mlx5e_priv *priv,
2302 struct mlx5e_channels *chs)
2303{
2304 struct mlx5e_redirect_rqt_param rrp = {
2305 .is_rss = true,
2306 {
2307 .rss = {
2308 .channels = chs,
2309 .hfunc = chs->params.rss_hfunc,
2310 }
2311 },
2312 };
2313
2314 mlx5e_redirect_rqts(priv, rrp);
2315}
2316
2317static void mlx5e_redirect_rqts_to_drop(struct mlx5e_priv *priv)
2318{
2319 struct mlx5e_redirect_rqt_param drop_rrp = {
2320 .is_rss = false,
2321 {
2322 .rqn = priv->drop_rq.rqn,
2323 },
2324 };
2325
2326 mlx5e_redirect_rqts(priv, drop_rrp);
2327}
2328
2329static void mlx5e_build_tir_ctx_lro(struct mlx5e_params *params, void *tirc)
2330{
2331 if (!params->lro_en)
2332 return;
2333
2334#define ROUGH_MAX_L2_L3_HDR_SZ 256
2335
2336 MLX5_SET(tirc, tirc, lro_enable_mask,
2337 MLX5_TIRC_LRO_ENABLE_MASK_IPV4_LRO |
2338 MLX5_TIRC_LRO_ENABLE_MASK_IPV6_LRO);
2339 MLX5_SET(tirc, tirc, lro_max_ip_payload_size,
2340 (params->lro_wqe_sz - ROUGH_MAX_L2_L3_HDR_SZ) >> 8);
2341 MLX5_SET(tirc, tirc, lro_timeout_period_usecs, params->lro_timeout);
2342}
2343
2344void mlx5e_build_indir_tir_ctx_hash(struct mlx5e_params *params,
2345 enum mlx5e_traffic_types tt,
2346 void *tirc, bool inner)
2347{
2348 void *hfso = inner ? MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_inner) :
2349 MLX5_ADDR_OF(tirc, tirc, rx_hash_field_selector_outer);
2350
2351#define MLX5_HASH_IP (MLX5_HASH_FIELD_SEL_SRC_IP |\
2352 MLX5_HASH_FIELD_SEL_DST_IP)
2353
2354#define MLX5_HASH_IP_L4PORTS (MLX5_HASH_FIELD_SEL_SRC_IP |\
2355 MLX5_HASH_FIELD_SEL_DST_IP |\
2356 MLX5_HASH_FIELD_SEL_L4_SPORT |\
2357 MLX5_HASH_FIELD_SEL_L4_DPORT)
2358
2359#define MLX5_HASH_IP_IPSEC_SPI (MLX5_HASH_FIELD_SEL_SRC_IP |\
2360 MLX5_HASH_FIELD_SEL_DST_IP |\
2361 MLX5_HASH_FIELD_SEL_IPSEC_SPI)
2362
2363 MLX5_SET(tirc, tirc, rx_hash_fn, mlx5e_rx_hash_fn(params->rss_hfunc));
2364 if (params->rss_hfunc == ETH_RSS_HASH_TOP) {
2365 void *rss_key = MLX5_ADDR_OF(tirc, tirc,
2366 rx_hash_toeplitz_key);
2367 size_t len = MLX5_FLD_SZ_BYTES(tirc,
2368 rx_hash_toeplitz_key);
2369
2370 MLX5_SET(tirc, tirc, rx_hash_symmetric, 1);
2371 memcpy(rss_key, params->toeplitz_hash_key, len);
2372 }
2373
2374 switch (tt) {
2375 case MLX5E_TT_IPV4_TCP:
2376 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2377 MLX5_L3_PROT_TYPE_IPV4);
2378 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2379 MLX5_L4_PROT_TYPE_TCP);
2380 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2381 MLX5_HASH_IP_L4PORTS);
2382 break;
2383
2384 case MLX5E_TT_IPV6_TCP:
2385 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2386 MLX5_L3_PROT_TYPE_IPV6);
2387 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2388 MLX5_L4_PROT_TYPE_TCP);
2389 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2390 MLX5_HASH_IP_L4PORTS);
2391 break;
2392
2393 case MLX5E_TT_IPV4_UDP:
2394 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2395 MLX5_L3_PROT_TYPE_IPV4);
2396 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2397 MLX5_L4_PROT_TYPE_UDP);
2398 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2399 MLX5_HASH_IP_L4PORTS);
2400 break;
2401
2402 case MLX5E_TT_IPV6_UDP:
2403 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2404 MLX5_L3_PROT_TYPE_IPV6);
2405 MLX5_SET(rx_hash_field_select, hfso, l4_prot_type,
2406 MLX5_L4_PROT_TYPE_UDP);
2407 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2408 MLX5_HASH_IP_L4PORTS);
2409 break;
2410
2411 case MLX5E_TT_IPV4_IPSEC_AH:
2412 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2413 MLX5_L3_PROT_TYPE_IPV4);
2414 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2415 MLX5_HASH_IP_IPSEC_SPI);
2416 break;
2417
2418 case MLX5E_TT_IPV6_IPSEC_AH:
2419 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2420 MLX5_L3_PROT_TYPE_IPV6);
2421 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2422 MLX5_HASH_IP_IPSEC_SPI);
2423 break;
2424
2425 case MLX5E_TT_IPV4_IPSEC_ESP:
2426 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2427 MLX5_L3_PROT_TYPE_IPV4);
2428 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2429 MLX5_HASH_IP_IPSEC_SPI);
2430 break;
2431
2432 case MLX5E_TT_IPV6_IPSEC_ESP:
2433 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2434 MLX5_L3_PROT_TYPE_IPV6);
2435 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2436 MLX5_HASH_IP_IPSEC_SPI);
2437 break;
2438
2439 case MLX5E_TT_IPV4:
2440 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2441 MLX5_L3_PROT_TYPE_IPV4);
2442 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2443 MLX5_HASH_IP);
2444 break;
2445
2446 case MLX5E_TT_IPV6:
2447 MLX5_SET(rx_hash_field_select, hfso, l3_prot_type,
2448 MLX5_L3_PROT_TYPE_IPV6);
2449 MLX5_SET(rx_hash_field_select, hfso, selected_fields,
2450 MLX5_HASH_IP);
2451 break;
2452 default:
2453 WARN_ONCE(true, "%s: bad traffic type!\n", __func__);
2454 }
2455}
2456
2457static int mlx5e_modify_tirs_lro(struct mlx5e_priv *priv)
2458{
2459 struct mlx5_core_dev *mdev = priv->mdev;
2460
2461 void *in;
2462 void *tirc;
2463 int inlen;
2464 int err;
2465 int tt;
2466 int ix;
2467
2468 inlen = MLX5_ST_SZ_BYTES(modify_tir_in);
2469 in = kvzalloc(inlen, GFP_KERNEL);
2470 if (!in)
2471 return -ENOMEM;
2472
2473 MLX5_SET(modify_tir_in, in, bitmask.lro, 1);
2474 tirc = MLX5_ADDR_OF(modify_tir_in, in, ctx);
2475
2476 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2477
2478 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2479 err = mlx5_core_modify_tir(mdev, priv->indir_tir[tt].tirn, in,
2480 inlen);
2481 if (err)
2482 goto free_in;
2483 }
2484
2485 for (ix = 0; ix < priv->profile->max_nch(priv->mdev); ix++) {
2486 err = mlx5_core_modify_tir(mdev, priv->direct_tir[ix].tirn,
2487 in, inlen);
2488 if (err)
2489 goto free_in;
2490 }
2491
2492free_in:
2493 kvfree(in);
2494
2495 return err;
2496}
2497
2498static void mlx5e_build_inner_indir_tir_ctx(struct mlx5e_priv *priv,
2499 enum mlx5e_traffic_types tt,
2500 u32 *tirc)
2501{
2502 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2503
2504 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2505
2506 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2507 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2508 MLX5_SET(tirc, tirc, tunneled_offload_en, 0x1);
2509
2510 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, true);
2511}
2512
2513static int mlx5e_set_mtu(struct mlx5_core_dev *mdev,
2514 struct mlx5e_params *params, u16 mtu)
2515{
2516 u16 hw_mtu = MLX5E_SW2HW_MTU(params, mtu);
2517 int err;
2518
2519 err = mlx5_set_port_mtu(mdev, hw_mtu, 1);
2520 if (err)
2521 return err;
2522
2523
2524 mlx5_modify_nic_vport_mtu(mdev, hw_mtu);
2525 return 0;
2526}
2527
2528static void mlx5e_query_mtu(struct mlx5_core_dev *mdev,
2529 struct mlx5e_params *params, u16 *mtu)
2530{
2531 u16 hw_mtu = 0;
2532 int err;
2533
2534 err = mlx5_query_nic_vport_mtu(mdev, &hw_mtu);
2535 if (err || !hw_mtu)
2536 mlx5_query_port_oper_mtu(mdev, &hw_mtu, 1);
2537
2538 *mtu = MLX5E_HW2SW_MTU(params, hw_mtu);
2539}
2540
2541static int mlx5e_set_dev_port_mtu(struct mlx5e_priv *priv)
2542{
2543 struct mlx5e_params *params = &priv->channels.params;
2544 struct net_device *netdev = priv->netdev;
2545 struct mlx5_core_dev *mdev = priv->mdev;
2546 u16 mtu;
2547 int err;
2548
2549 err = mlx5e_set_mtu(mdev, params, params->sw_mtu);
2550 if (err)
2551 return err;
2552
2553 mlx5e_query_mtu(mdev, params, &mtu);
2554 if (mtu != params->sw_mtu)
2555 netdev_warn(netdev, "%s: VPort MTU %d is different than netdev mtu %d\n",
2556 __func__, mtu, params->sw_mtu);
2557
2558 params->sw_mtu = mtu;
2559 return 0;
2560}
2561
2562static void mlx5e_netdev_set_tcs(struct net_device *netdev)
2563{
2564 struct mlx5e_priv *priv = netdev_priv(netdev);
2565 int nch = priv->channels.params.num_channels;
2566 int ntc = priv->channels.params.num_tc;
2567 int tc;
2568
2569 netdev_reset_tc(netdev);
2570
2571 if (ntc == 1)
2572 return;
2573
2574 netdev_set_num_tc(netdev, ntc);
2575
2576
2577
2578
2579 for (tc = 0; tc < ntc; tc++)
2580 netdev_set_tc_queue(netdev, tc, nch, 0);
2581}
2582
2583static void mlx5e_build_channels_tx_maps(struct mlx5e_priv *priv)
2584{
2585 struct mlx5e_channel *c;
2586 struct mlx5e_txqsq *sq;
2587 int i, tc;
2588
2589 for (i = 0; i < priv->channels.num; i++)
2590 for (tc = 0; tc < priv->profile->max_tc; tc++)
2591 priv->channel_tc2txq[i][tc] = i + tc * priv->channels.num;
2592
2593 for (i = 0; i < priv->channels.num; i++) {
2594 c = priv->channels.c[i];
2595 for (tc = 0; tc < c->num_tc; tc++) {
2596 sq = &c->sq[tc];
2597 priv->txq2sq[sq->txq_ix] = sq;
2598 }
2599 }
2600}
2601
2602void mlx5e_activate_priv_channels(struct mlx5e_priv *priv)
2603{
2604 int num_txqs = priv->channels.num * priv->channels.params.num_tc;
2605 struct net_device *netdev = priv->netdev;
2606
2607 mlx5e_netdev_set_tcs(netdev);
2608 netif_set_real_num_tx_queues(netdev, num_txqs);
2609 netif_set_real_num_rx_queues(netdev, priv->channels.num);
2610
2611 mlx5e_build_channels_tx_maps(priv);
2612 mlx5e_activate_channels(&priv->channels);
2613 netif_tx_start_all_queues(priv->netdev);
2614
2615 if (MLX5_VPORT_MANAGER(priv->mdev))
2616 mlx5e_add_sqs_fwd_rules(priv);
2617
2618 mlx5e_wait_channels_min_rx_wqes(&priv->channels);
2619 mlx5e_redirect_rqts_to_channels(priv, &priv->channels);
2620}
2621
2622void mlx5e_deactivate_priv_channels(struct mlx5e_priv *priv)
2623{
2624 mlx5e_redirect_rqts_to_drop(priv);
2625
2626 if (MLX5_VPORT_MANAGER(priv->mdev))
2627 mlx5e_remove_sqs_fwd_rules(priv);
2628
2629
2630
2631
2632 netif_tx_stop_all_queues(priv->netdev);
2633 netif_tx_disable(priv->netdev);
2634 mlx5e_deactivate_channels(&priv->channels);
2635}
2636
2637void mlx5e_switch_priv_channels(struct mlx5e_priv *priv,
2638 struct mlx5e_channels *new_chs,
2639 mlx5e_fp_hw_modify hw_modify)
2640{
2641 struct net_device *netdev = priv->netdev;
2642 int new_num_txqs;
2643 int carrier_ok;
2644 new_num_txqs = new_chs->num * new_chs->params.num_tc;
2645
2646 carrier_ok = netif_carrier_ok(netdev);
2647 netif_carrier_off(netdev);
2648
2649 if (new_num_txqs < netdev->real_num_tx_queues)
2650 netif_set_real_num_tx_queues(netdev, new_num_txqs);
2651
2652 mlx5e_deactivate_priv_channels(priv);
2653 mlx5e_close_channels(&priv->channels);
2654
2655 priv->channels = *new_chs;
2656
2657
2658 if (hw_modify)
2659 hw_modify(priv);
2660
2661 mlx5e_refresh_tirs(priv, false);
2662 mlx5e_activate_priv_channels(priv);
2663
2664
2665 if (carrier_ok)
2666 netif_carrier_on(netdev);
2667}
2668
2669void mlx5e_timestamp_init(struct mlx5e_priv *priv)
2670{
2671 priv->tstamp.tx_type = HWTSTAMP_TX_OFF;
2672 priv->tstamp.rx_filter = HWTSTAMP_FILTER_NONE;
2673}
2674
2675int mlx5e_open_locked(struct net_device *netdev)
2676{
2677 struct mlx5e_priv *priv = netdev_priv(netdev);
2678 int err;
2679
2680 set_bit(MLX5E_STATE_OPENED, &priv->state);
2681
2682 err = mlx5e_open_channels(priv, &priv->channels);
2683 if (err)
2684 goto err_clear_state_opened_flag;
2685
2686 mlx5e_refresh_tirs(priv, false);
2687 mlx5e_activate_priv_channels(priv);
2688 if (priv->profile->update_carrier)
2689 priv->profile->update_carrier(priv);
2690
2691 if (priv->profile->update_stats)
2692 queue_delayed_work(priv->wq, &priv->update_stats_work, 0);
2693
2694 return 0;
2695
2696err_clear_state_opened_flag:
2697 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2698 return err;
2699}
2700
2701int mlx5e_open(struct net_device *netdev)
2702{
2703 struct mlx5e_priv *priv = netdev_priv(netdev);
2704 int err;
2705
2706 mutex_lock(&priv->state_lock);
2707 err = mlx5e_open_locked(netdev);
2708 if (!err)
2709 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_UP);
2710 mutex_unlock(&priv->state_lock);
2711
2712 if (mlx5e_vxlan_allowed(priv->mdev))
2713 udp_tunnel_get_rx_info(netdev);
2714
2715 return err;
2716}
2717
2718int mlx5e_close_locked(struct net_device *netdev)
2719{
2720 struct mlx5e_priv *priv = netdev_priv(netdev);
2721
2722
2723
2724
2725 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
2726 return 0;
2727
2728 clear_bit(MLX5E_STATE_OPENED, &priv->state);
2729
2730 netif_carrier_off(priv->netdev);
2731 mlx5e_deactivate_priv_channels(priv);
2732 mlx5e_close_channels(&priv->channels);
2733
2734 return 0;
2735}
2736
2737int mlx5e_close(struct net_device *netdev)
2738{
2739 struct mlx5e_priv *priv = netdev_priv(netdev);
2740 int err;
2741
2742 if (!netif_device_present(netdev))
2743 return -ENODEV;
2744
2745 mutex_lock(&priv->state_lock);
2746 mlx5_set_port_admin_status(priv->mdev, MLX5_PORT_DOWN);
2747 err = mlx5e_close_locked(netdev);
2748 mutex_unlock(&priv->state_lock);
2749
2750 return err;
2751}
2752
2753static int mlx5e_alloc_drop_rq(struct mlx5_core_dev *mdev,
2754 struct mlx5e_rq *rq,
2755 struct mlx5e_rq_param *param)
2756{
2757 void *rqc = param->rqc;
2758 void *rqc_wq = MLX5_ADDR_OF(rqc, rqc, wq);
2759 int err;
2760
2761 param->wq.db_numa_node = param->wq.buf_numa_node;
2762
2763 err = mlx5_wq_ll_create(mdev, ¶m->wq, rqc_wq, &rq->wq,
2764 &rq->wq_ctrl);
2765 if (err)
2766 return err;
2767
2768
2769 xdp_rxq_info_unused(&rq->xdp_rxq);
2770
2771 rq->mdev = mdev;
2772
2773 return 0;
2774}
2775
2776static int mlx5e_alloc_drop_cq(struct mlx5_core_dev *mdev,
2777 struct mlx5e_cq *cq,
2778 struct mlx5e_cq_param *param)
2779{
2780 param->wq.buf_numa_node = dev_to_node(&mdev->pdev->dev);
2781 param->wq.db_numa_node = dev_to_node(&mdev->pdev->dev);
2782
2783 return mlx5e_alloc_cq_common(mdev, param, cq);
2784}
2785
2786static int mlx5e_open_drop_rq(struct mlx5e_priv *priv,
2787 struct mlx5e_rq *drop_rq)
2788{
2789 struct mlx5_core_dev *mdev = priv->mdev;
2790 struct mlx5e_cq_param cq_param = {};
2791 struct mlx5e_rq_param rq_param = {};
2792 struct mlx5e_cq *cq = &drop_rq->cq;
2793 int err;
2794
2795 mlx5e_build_drop_rq_param(priv, &rq_param);
2796
2797 err = mlx5e_alloc_drop_cq(mdev, cq, &cq_param);
2798 if (err)
2799 return err;
2800
2801 err = mlx5e_create_cq(cq, &cq_param);
2802 if (err)
2803 goto err_free_cq;
2804
2805 err = mlx5e_alloc_drop_rq(mdev, drop_rq, &rq_param);
2806 if (err)
2807 goto err_destroy_cq;
2808
2809 err = mlx5e_create_rq(drop_rq, &rq_param);
2810 if (err)
2811 goto err_free_rq;
2812
2813 err = mlx5e_modify_rq_state(drop_rq, MLX5_RQC_STATE_RST, MLX5_RQC_STATE_RDY);
2814 if (err)
2815 mlx5_core_warn(priv->mdev, "modify_rq_state failed, rx_if_down_packets won't be counted %d\n", err);
2816
2817 return 0;
2818
2819err_free_rq:
2820 mlx5e_free_rq(drop_rq);
2821
2822err_destroy_cq:
2823 mlx5e_destroy_cq(cq);
2824
2825err_free_cq:
2826 mlx5e_free_cq(cq);
2827
2828 return err;
2829}
2830
2831static void mlx5e_close_drop_rq(struct mlx5e_rq *drop_rq)
2832{
2833 mlx5e_destroy_rq(drop_rq);
2834 mlx5e_free_rq(drop_rq);
2835 mlx5e_destroy_cq(&drop_rq->cq);
2836 mlx5e_free_cq(&drop_rq->cq);
2837}
2838
2839int mlx5e_create_tis(struct mlx5_core_dev *mdev, int tc,
2840 u32 underlay_qpn, u32 *tisn)
2841{
2842 u32 in[MLX5_ST_SZ_DW(create_tis_in)] = {0};
2843 void *tisc = MLX5_ADDR_OF(create_tis_in, in, ctx);
2844
2845 MLX5_SET(tisc, tisc, prio, tc << 1);
2846 MLX5_SET(tisc, tisc, underlay_qpn, underlay_qpn);
2847 MLX5_SET(tisc, tisc, transport_domain, mdev->mlx5e_res.td.tdn);
2848
2849 if (mlx5_lag_is_lacp_owner(mdev))
2850 MLX5_SET(tisc, tisc, strict_lag_tx_port_affinity, 1);
2851
2852 return mlx5_core_create_tis(mdev, in, sizeof(in), tisn);
2853}
2854
2855void mlx5e_destroy_tis(struct mlx5_core_dev *mdev, u32 tisn)
2856{
2857 mlx5_core_destroy_tis(mdev, tisn);
2858}
2859
2860int mlx5e_create_tises(struct mlx5e_priv *priv)
2861{
2862 int err;
2863 int tc;
2864
2865 for (tc = 0; tc < priv->profile->max_tc; tc++) {
2866 err = mlx5e_create_tis(priv->mdev, tc, 0, &priv->tisn[tc]);
2867 if (err)
2868 goto err_close_tises;
2869 }
2870
2871 return 0;
2872
2873err_close_tises:
2874 for (tc--; tc >= 0; tc--)
2875 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2876
2877 return err;
2878}
2879
2880void mlx5e_cleanup_nic_tx(struct mlx5e_priv *priv)
2881{
2882 int tc;
2883
2884 for (tc = 0; tc < priv->profile->max_tc; tc++)
2885 mlx5e_destroy_tis(priv->mdev, priv->tisn[tc]);
2886}
2887
2888static void mlx5e_build_indir_tir_ctx(struct mlx5e_priv *priv,
2889 enum mlx5e_traffic_types tt,
2890 u32 *tirc)
2891{
2892 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2893
2894 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2895
2896 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2897 MLX5_SET(tirc, tirc, indirect_table, priv->indir_rqt.rqtn);
2898 mlx5e_build_indir_tir_ctx_hash(&priv->channels.params, tt, tirc, false);
2899}
2900
2901static void mlx5e_build_direct_tir_ctx(struct mlx5e_priv *priv, u32 rqtn, u32 *tirc)
2902{
2903 MLX5_SET(tirc, tirc, transport_domain, priv->mdev->mlx5e_res.td.tdn);
2904
2905 mlx5e_build_tir_ctx_lro(&priv->channels.params, tirc);
2906
2907 MLX5_SET(tirc, tirc, disp_type, MLX5_TIRC_DISP_TYPE_INDIRECT);
2908 MLX5_SET(tirc, tirc, indirect_table, rqtn);
2909 MLX5_SET(tirc, tirc, rx_hash_fn, MLX5_RX_HASH_FN_INVERTED_XOR8);
2910}
2911
2912int mlx5e_create_indirect_tirs(struct mlx5e_priv *priv)
2913{
2914 struct mlx5e_tir *tir;
2915 void *tirc;
2916 int inlen;
2917 int i = 0;
2918 int err;
2919 u32 *in;
2920 int tt;
2921
2922 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2923 in = kvzalloc(inlen, GFP_KERNEL);
2924 if (!in)
2925 return -ENOMEM;
2926
2927 for (tt = 0; tt < MLX5E_NUM_INDIR_TIRS; tt++) {
2928 memset(in, 0, inlen);
2929 tir = &priv->indir_tir[tt];
2930 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2931 mlx5e_build_indir_tir_ctx(priv, tt, tirc);
2932 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2933 if (err) {
2934 mlx5_core_warn(priv->mdev, "create indirect tirs failed, %d\n", err);
2935 goto err_destroy_inner_tirs;
2936 }
2937 }
2938
2939 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
2940 goto out;
2941
2942 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++) {
2943 memset(in, 0, inlen);
2944 tir = &priv->inner_indir_tir[i];
2945 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2946 mlx5e_build_inner_indir_tir_ctx(priv, i, tirc);
2947 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2948 if (err) {
2949 mlx5_core_warn(priv->mdev, "create inner indirect tirs failed, %d\n", err);
2950 goto err_destroy_inner_tirs;
2951 }
2952 }
2953
2954out:
2955 kvfree(in);
2956
2957 return 0;
2958
2959err_destroy_inner_tirs:
2960 for (i--; i >= 0; i--)
2961 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
2962
2963 for (tt--; tt >= 0; tt--)
2964 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[tt]);
2965
2966 kvfree(in);
2967
2968 return err;
2969}
2970
2971int mlx5e_create_direct_tirs(struct mlx5e_priv *priv)
2972{
2973 int nch = priv->profile->max_nch(priv->mdev);
2974 struct mlx5e_tir *tir;
2975 void *tirc;
2976 int inlen;
2977 int err;
2978 u32 *in;
2979 int ix;
2980
2981 inlen = MLX5_ST_SZ_BYTES(create_tir_in);
2982 in = kvzalloc(inlen, GFP_KERNEL);
2983 if (!in)
2984 return -ENOMEM;
2985
2986 for (ix = 0; ix < nch; ix++) {
2987 memset(in, 0, inlen);
2988 tir = &priv->direct_tir[ix];
2989 tirc = MLX5_ADDR_OF(create_tir_in, in, ctx);
2990 mlx5e_build_direct_tir_ctx(priv, priv->direct_tir[ix].rqt.rqtn, tirc);
2991 err = mlx5e_create_tir(priv->mdev, tir, in, inlen);
2992 if (err)
2993 goto err_destroy_ch_tirs;
2994 }
2995
2996 kvfree(in);
2997
2998 return 0;
2999
3000err_destroy_ch_tirs:
3001 mlx5_core_warn(priv->mdev, "create direct tirs failed, %d\n", err);
3002 for (ix--; ix >= 0; ix--)
3003 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[ix]);
3004
3005 kvfree(in);
3006
3007 return err;
3008}
3009
3010void mlx5e_destroy_indirect_tirs(struct mlx5e_priv *priv)
3011{
3012 int i;
3013
3014 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3015 mlx5e_destroy_tir(priv->mdev, &priv->indir_tir[i]);
3016
3017 if (!mlx5e_tunnel_inner_ft_supported(priv->mdev))
3018 return;
3019
3020 for (i = 0; i < MLX5E_NUM_INDIR_TIRS; i++)
3021 mlx5e_destroy_tir(priv->mdev, &priv->inner_indir_tir[i]);
3022}
3023
3024void mlx5e_destroy_direct_tirs(struct mlx5e_priv *priv)
3025{
3026 int nch = priv->profile->max_nch(priv->mdev);
3027 int i;
3028
3029 for (i = 0; i < nch; i++)
3030 mlx5e_destroy_tir(priv->mdev, &priv->direct_tir[i]);
3031}
3032
3033static int mlx5e_modify_channels_scatter_fcs(struct mlx5e_channels *chs, bool enable)
3034{
3035 int err = 0;
3036 int i;
3037
3038 for (i = 0; i < chs->num; i++) {
3039 err = mlx5e_modify_rq_scatter_fcs(&chs->c[i]->rq, enable);
3040 if (err)
3041 return err;
3042 }
3043
3044 return 0;
3045}
3046
3047static int mlx5e_modify_channels_vsd(struct mlx5e_channels *chs, bool vsd)
3048{
3049 int err = 0;
3050 int i;
3051
3052 for (i = 0; i < chs->num; i++) {
3053 err = mlx5e_modify_rq_vsd(&chs->c[i]->rq, vsd);
3054 if (err)
3055 return err;
3056 }
3057
3058 return 0;
3059}
3060
3061static int mlx5e_setup_tc_mqprio(struct net_device *netdev,
3062 struct tc_mqprio_qopt *mqprio)
3063{
3064 struct mlx5e_priv *priv = netdev_priv(netdev);
3065 struct mlx5e_channels new_channels = {};
3066 u8 tc = mqprio->num_tc;
3067 int err = 0;
3068
3069 mqprio->hw = TC_MQPRIO_HW_OFFLOAD_TCS;
3070
3071 if (tc && tc != MLX5E_MAX_NUM_TC)
3072 return -EINVAL;
3073
3074 mutex_lock(&priv->state_lock);
3075
3076 new_channels.params = priv->channels.params;
3077 new_channels.params.num_tc = tc ? tc : 1;
3078
3079 if (!test_bit(MLX5E_STATE_OPENED, &priv->state)) {
3080 priv->channels.params = new_channels.params;
3081 goto out;
3082 }
3083
3084 err = mlx5e_open_channels(priv, &new_channels);
3085 if (err)
3086 goto out;
3087
3088 mlx5e_switch_priv_channels(priv, &new_channels, NULL);
3089out:
3090 mutex_unlock(&priv->state_lock);
3091 return err;
3092}
3093
3094#ifdef CONFIG_MLX5_ESWITCH
3095static int mlx5e_setup_tc_cls_flower(struct mlx5e_priv *priv,
3096 struct tc_cls_flower_offload *cls_flower)
3097{
3098 switch (cls_flower->command) {
3099 case TC_CLSFLOWER_REPLACE:
3100 return mlx5e_configure_flower(priv, cls_flower);
3101 case TC_CLSFLOWER_DESTROY:
3102 return mlx5e_delete_flower(priv, cls_flower);
3103 case TC_CLSFLOWER_STATS:
3104 return mlx5e_stats_flower(priv, cls_flower);
3105 default:
3106 return -EOPNOTSUPP;
3107 }
3108}
3109
3110int mlx5e_setup_tc_block_cb(enum tc_setup_type type, void *type_data,
3111 void *cb_priv)
3112{
3113 struct mlx5e_priv *priv = cb_priv;
3114
3115 if (!tc_cls_can_offload_and_chain0(priv->netdev, type_data))
3116 return -EOPNOTSUPP;
3117
3118 switch (type) {
3119 case TC_SETUP_CLSFLOWER:
3120 return mlx5e_setup_tc_cls_flower(priv, type_data);
3121 default:
3122 return -EOPNOTSUPP;
3123 }
3124}
3125
3126static int mlx5e_setup_tc_block(struct net_device *dev,
3127 struct tc_block_offload *f)
3128{
3129 struct mlx5e_priv *priv = netdev_priv(dev);
3130
3131 if (f->binder_type != TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS)
3132 return -EOPNOTSUPP;
3133
3134 switch (f->command) {
3135 case TC_BLOCK_BIND:
3136 return tcf_block_cb_register(f->block, mlx5e_setup_tc_block_cb,
3137 priv, priv);
3138 case TC_BLOCK_UNBIND:
3139 tcf_block_cb_unregister(f->block, mlx5e_setup_tc_block_cb,
3140 priv);
3141 return 0;
3142 default:
3143 return -EOPNOTSUPP;
3144 }
3145}
3146#endif
3147
3148static int mlx5e_setup_tc(struct net_device *dev, enum tc_setup_type type,
3149 void *type_data)
3150{
3151 switch (type) {
3152#ifdef CONFIG_MLX5_ESWITCH
3153 case TC_SETUP_BLOCK:
3154 return mlx5e_setup_tc_block(dev, type_data);
3155#endif
3156 case TC_SETUP_QDISC_MQPRIO:
3157 return mlx5e_setup_tc_mqprio(dev, type_data);
3158 default:
3159 return -EOPNOTSUPP;
3160 }
3161}
3162
3163static void
3164mlx5e_get_stats(struct net_device *dev, struct rtnl_link_stats64 *stats)
3165{
3166 struct mlx5e_priv *priv = netdev_priv(dev);
3167 struct mlx5e_sw_stats *sstats = &priv->stats.sw;
3168 struct mlx5e_vport_stats *vstats = &priv->stats.vport;
3169 struct mlx5e_pport_stats *pstats = &priv->stats.pport;
3170
3171 if (mlx5e_is_uplink_rep(priv)) {
3172 stats->rx_packets = PPORT_802_3_GET(pstats, a_frames_received_ok);
3173 stats->rx_bytes = PPORT_802_3_GET(pstats, a_octets_received_ok);
3174 stats->tx_packets = PPORT_802_3_GET(pstats, a_frames_transmitted_ok);
3175 stats->tx_bytes = PPORT_802_3_GET(pstats, a_octets_transmitted_ok);
3176 } else {
3177 stats->rx_packets = sstats->rx_packets;
3178 stats->rx_bytes = sstats->rx_bytes;
3179 stats->tx_packets = sstats->tx_packets;
3180 stats->tx_bytes = sstats->tx_bytes;
3181 stats->tx_dropped = sstats->tx_queue_dropped;
3182 }
3183
3184 stats->rx_dropped = priv->stats.qcnt.rx_out_of_buffer;
3185
3186 stats->rx_length_errors =
3187 PPORT_802_3_GET(pstats, a_in_range_length_errors) +
3188 PPORT_802_3_GET(pstats, a_out_of_range_length_field) +
3189 PPORT_802_3_GET(pstats, a_frame_too_long_errors);
3190 stats->rx_crc_errors =
3191 PPORT_802_3_GET(pstats, a_frame_check_sequence_errors);
3192 stats->rx_frame_errors = PPORT_802_3_GET(pstats, a_alignment_errors);
3193 stats->tx_aborted_errors = PPORT_2863_GET(pstats, if_out_discards);
3194 stats->rx_errors = stats->rx_length_errors + stats->rx_crc_errors +
3195 stats->rx_frame_errors;
3196 stats->tx_errors = stats->tx_aborted_errors + stats->tx_carrier_errors;
3197
3198
3199
3200
3201 stats->multicast =
3202 VPORT_COUNTER_GET(vstats, received_eth_multicast.packets);
3203}
3204
3205static void mlx5e_set_rx_mode(struct net_device *dev)
3206{
3207 struct mlx5e_priv *priv = netdev_priv(dev);
3208
3209 queue_work(priv->wq, &priv->set_rx_mode_work);
3210}
3211
3212static int mlx5e_set_mac(struct net_device *netdev, void *addr)
3213{
3214 struct mlx5e_priv *priv = netdev_priv(netdev);
3215 struct sockaddr *saddr = addr;
3216
3217 if (!is_valid_ether_addr(saddr->sa_data))
3218 return -EADDRNOTAVAIL;
3219
3220 netif_addr_lock_bh(netdev);
3221 ether_addr_copy(netdev->dev_addr, saddr->sa_data);
3222 netif_addr_unlock_bh(netdev);
3223
3224 queue_work(priv->wq, &priv->set_rx_mode_work);
3225
3226 return 0;
3227}
3228
3229#define MLX5E_SET_FEATURE(features, feature, enable) \
3230 do { \
3231 if (enable) \
3232 *features |= feature; \
3233 else \
3234 *features &= ~feature; \
3235 } while (0)
3236
3237typedef int (*mlx5e_feature_handler)(struct net_device *netdev, bool enable);
3238
3239static int set_feature_lro(struct net_device *netdev, bool enable)
3240{
3241 struct mlx5e_priv *priv = netdev_priv(netdev);
3242 struct mlx5_core_dev *mdev = priv->mdev;
3243 struct mlx5e_channels new_channels = {};
3244 struct mlx5e_params *old_params;
3245 int err = 0;
3246 bool reset;
3247
3248 mutex_lock(&priv->state_lock);
3249
3250 old_params = &priv->channels.params;
3251 reset = test_bit(MLX5E_STATE_OPENED, &priv->state);
3252
3253 new_channels.params = *old_params;
3254 new_channels.params.lro_en = enable;
3255
3256 if (old_params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3257 if (mlx5e_rx_mpwqe_is_linear_skb(mdev, old_params) ==
3258 mlx5e_rx_mpwqe_is_linear_skb(mdev, &new_channels.params))
3259 reset = false;
3260 }
3261
3262 if (!reset) {
3263 *old_params = new_channels.params;
3264 err = mlx5e_modify_tirs_lro(priv);
3265 goto out;
3266 }
3267
3268 err = mlx5e_open_channels(priv, &new_channels);
3269 if (err)
3270 goto out;
3271
3272 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_modify_tirs_lro);
3273out:
3274 mutex_unlock(&priv->state_lock);
3275 return err;
3276}
3277
3278static int set_feature_cvlan_filter(struct net_device *netdev, bool enable)
3279{
3280 struct mlx5e_priv *priv = netdev_priv(netdev);
3281
3282 if (enable)
3283 mlx5e_enable_cvlan_filter(priv);
3284 else
3285 mlx5e_disable_cvlan_filter(priv);
3286
3287 return 0;
3288}
3289
3290static int set_feature_tc_num_filters(struct net_device *netdev, bool enable)
3291{
3292 struct mlx5e_priv *priv = netdev_priv(netdev);
3293
3294 if (!enable && mlx5e_tc_num_filters(priv)) {
3295 netdev_err(netdev,
3296 "Active offloaded tc filters, can't turn hw_tc_offload off\n");
3297 return -EINVAL;
3298 }
3299
3300 return 0;
3301}
3302
3303static int set_feature_rx_all(struct net_device *netdev, bool enable)
3304{
3305 struct mlx5e_priv *priv = netdev_priv(netdev);
3306 struct mlx5_core_dev *mdev = priv->mdev;
3307
3308 return mlx5_set_port_fcs(mdev, !enable);
3309}
3310
3311static int set_feature_rx_fcs(struct net_device *netdev, bool enable)
3312{
3313 struct mlx5e_priv *priv = netdev_priv(netdev);
3314 int err;
3315
3316 mutex_lock(&priv->state_lock);
3317
3318 priv->channels.params.scatter_fcs_en = enable;
3319 err = mlx5e_modify_channels_scatter_fcs(&priv->channels, enable);
3320 if (err)
3321 priv->channels.params.scatter_fcs_en = !enable;
3322
3323 mutex_unlock(&priv->state_lock);
3324
3325 return err;
3326}
3327
3328static int set_feature_rx_vlan(struct net_device *netdev, bool enable)
3329{
3330 struct mlx5e_priv *priv = netdev_priv(netdev);
3331 int err = 0;
3332
3333 mutex_lock(&priv->state_lock);
3334
3335 priv->channels.params.vlan_strip_disable = !enable;
3336 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3337 goto unlock;
3338
3339 err = mlx5e_modify_channels_vsd(&priv->channels, !enable);
3340 if (err)
3341 priv->channels.params.vlan_strip_disable = enable;
3342
3343unlock:
3344 mutex_unlock(&priv->state_lock);
3345
3346 return err;
3347}
3348
3349#ifdef CONFIG_RFS_ACCEL
3350static int set_feature_arfs(struct net_device *netdev, bool enable)
3351{
3352 struct mlx5e_priv *priv = netdev_priv(netdev);
3353 int err;
3354
3355 if (enable)
3356 err = mlx5e_arfs_enable(priv);
3357 else
3358 err = mlx5e_arfs_disable(priv);
3359
3360 return err;
3361}
3362#endif
3363
3364static int mlx5e_handle_feature(struct net_device *netdev,
3365 netdev_features_t *features,
3366 netdev_features_t wanted_features,
3367 netdev_features_t feature,
3368 mlx5e_feature_handler feature_handler)
3369{
3370 netdev_features_t changes = wanted_features ^ netdev->features;
3371 bool enable = !!(wanted_features & feature);
3372 int err;
3373
3374 if (!(changes & feature))
3375 return 0;
3376
3377 err = feature_handler(netdev, enable);
3378 if (err) {
3379 netdev_err(netdev, "%s feature %pNF failed, err %d\n",
3380 enable ? "Enable" : "Disable", &feature, err);
3381 return err;
3382 }
3383
3384 MLX5E_SET_FEATURE(features, feature, enable);
3385 return 0;
3386}
3387
3388static int mlx5e_set_features(struct net_device *netdev,
3389 netdev_features_t features)
3390{
3391 netdev_features_t oper_features = netdev->features;
3392 int err = 0;
3393
3394#define MLX5E_HANDLE_FEATURE(feature, handler) \
3395 mlx5e_handle_feature(netdev, &oper_features, features, feature, handler)
3396
3397 err |= MLX5E_HANDLE_FEATURE(NETIF_F_LRO, set_feature_lro);
3398 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_FILTER,
3399 set_feature_cvlan_filter);
3400 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_TC, set_feature_tc_num_filters);
3401 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXALL, set_feature_rx_all);
3402 err |= MLX5E_HANDLE_FEATURE(NETIF_F_RXFCS, set_feature_rx_fcs);
3403 err |= MLX5E_HANDLE_FEATURE(NETIF_F_HW_VLAN_CTAG_RX, set_feature_rx_vlan);
3404#ifdef CONFIG_RFS_ACCEL
3405 err |= MLX5E_HANDLE_FEATURE(NETIF_F_NTUPLE, set_feature_arfs);
3406#endif
3407
3408 if (err) {
3409 netdev->features = oper_features;
3410 return -EINVAL;
3411 }
3412
3413 return 0;
3414}
3415
3416static netdev_features_t mlx5e_fix_features(struct net_device *netdev,
3417 netdev_features_t features)
3418{
3419 struct mlx5e_priv *priv = netdev_priv(netdev);
3420
3421 mutex_lock(&priv->state_lock);
3422 if (!bitmap_empty(priv->fs.vlan.active_svlans, VLAN_N_VID)) {
3423
3424
3425
3426 features &= ~NETIF_F_HW_VLAN_CTAG_RX;
3427 if (!priv->channels.params.vlan_strip_disable)
3428 netdev_warn(netdev, "Dropping C-tag vlan stripping offload due to S-tag vlan\n");
3429 }
3430 mutex_unlock(&priv->state_lock);
3431
3432 return features;
3433}
3434
3435static int mlx5e_change_mtu(struct net_device *netdev, int new_mtu)
3436{
3437 struct mlx5e_priv *priv = netdev_priv(netdev);
3438 struct mlx5e_channels new_channels = {};
3439 struct mlx5e_params *params;
3440 int err = 0;
3441 bool reset;
3442
3443 mutex_lock(&priv->state_lock);
3444
3445 params = &priv->channels.params;
3446
3447 reset = !params->lro_en;
3448 reset = reset && test_bit(MLX5E_STATE_OPENED, &priv->state);
3449
3450 new_channels.params = *params;
3451 new_channels.params.sw_mtu = new_mtu;
3452
3453 if (params->rq_wq_type != MLX5_WQ_TYPE_LINKED_LIST) {
3454 u8 ppw_old = mlx5e_mpwqe_log_pkts_per_wqe(params);
3455 u8 ppw_new = mlx5e_mpwqe_log_pkts_per_wqe(&new_channels.params);
3456
3457 reset = reset && (ppw_old != ppw_new);
3458 }
3459
3460 if (!reset) {
3461 params->sw_mtu = new_mtu;
3462 mlx5e_set_dev_port_mtu(priv);
3463 netdev->mtu = params->sw_mtu;
3464 goto out;
3465 }
3466
3467 err = mlx5e_open_channels(priv, &new_channels);
3468 if (err)
3469 goto out;
3470
3471 mlx5e_switch_priv_channels(priv, &new_channels, mlx5e_set_dev_port_mtu);
3472 netdev->mtu = new_channels.params.sw_mtu;
3473
3474out:
3475 mutex_unlock(&priv->state_lock);
3476 return err;
3477}
3478
3479int mlx5e_hwstamp_set(struct mlx5e_priv *priv, struct ifreq *ifr)
3480{
3481 struct hwtstamp_config config;
3482 int err;
3483
3484 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3485 return -EOPNOTSUPP;
3486
3487 if (copy_from_user(&config, ifr->ifr_data, sizeof(config)))
3488 return -EFAULT;
3489
3490
3491 switch (config.tx_type) {
3492 case HWTSTAMP_TX_OFF:
3493 case HWTSTAMP_TX_ON:
3494 break;
3495 default:
3496 return -ERANGE;
3497 }
3498
3499 mutex_lock(&priv->state_lock);
3500
3501 switch (config.rx_filter) {
3502 case HWTSTAMP_FILTER_NONE:
3503
3504 mlx5e_modify_rx_cqe_compression_locked(priv, priv->channels.params.rx_cqe_compress_def);
3505 break;
3506 case HWTSTAMP_FILTER_ALL:
3507 case HWTSTAMP_FILTER_SOME:
3508 case HWTSTAMP_FILTER_PTP_V1_L4_EVENT:
3509 case HWTSTAMP_FILTER_PTP_V1_L4_SYNC:
3510 case HWTSTAMP_FILTER_PTP_V1_L4_DELAY_REQ:
3511 case HWTSTAMP_FILTER_PTP_V2_L4_EVENT:
3512 case HWTSTAMP_FILTER_PTP_V2_L4_SYNC:
3513 case HWTSTAMP_FILTER_PTP_V2_L4_DELAY_REQ:
3514 case HWTSTAMP_FILTER_PTP_V2_L2_EVENT:
3515 case HWTSTAMP_FILTER_PTP_V2_L2_SYNC:
3516 case HWTSTAMP_FILTER_PTP_V2_L2_DELAY_REQ:
3517 case HWTSTAMP_FILTER_PTP_V2_EVENT:
3518 case HWTSTAMP_FILTER_PTP_V2_SYNC:
3519 case HWTSTAMP_FILTER_PTP_V2_DELAY_REQ:
3520 case HWTSTAMP_FILTER_NTP_ALL:
3521
3522 netdev_warn(priv->netdev, "Disabling cqe compression");
3523 err = mlx5e_modify_rx_cqe_compression_locked(priv, false);
3524 if (err) {
3525 netdev_err(priv->netdev, "Failed disabling cqe compression err=%d\n", err);
3526 mutex_unlock(&priv->state_lock);
3527 return err;
3528 }
3529 config.rx_filter = HWTSTAMP_FILTER_ALL;
3530 break;
3531 default:
3532 mutex_unlock(&priv->state_lock);
3533 return -ERANGE;
3534 }
3535
3536 memcpy(&priv->tstamp, &config, sizeof(config));
3537 mutex_unlock(&priv->state_lock);
3538
3539 return copy_to_user(ifr->ifr_data, &config,
3540 sizeof(config)) ? -EFAULT : 0;
3541}
3542
3543int mlx5e_hwstamp_get(struct mlx5e_priv *priv, struct ifreq *ifr)
3544{
3545 struct hwtstamp_config *cfg = &priv->tstamp;
3546
3547 if (!MLX5_CAP_GEN(priv->mdev, device_frequency_khz))
3548 return -EOPNOTSUPP;
3549
3550 return copy_to_user(ifr->ifr_data, cfg, sizeof(*cfg)) ? -EFAULT : 0;
3551}
3552
3553static int mlx5e_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
3554{
3555 struct mlx5e_priv *priv = netdev_priv(dev);
3556
3557 switch (cmd) {
3558 case SIOCSHWTSTAMP:
3559 return mlx5e_hwstamp_set(priv, ifr);
3560 case SIOCGHWTSTAMP:
3561 return mlx5e_hwstamp_get(priv, ifr);
3562 default:
3563 return -EOPNOTSUPP;
3564 }
3565}
3566
3567#ifdef CONFIG_MLX5_ESWITCH
3568static int mlx5e_set_vf_mac(struct net_device *dev, int vf, u8 *mac)
3569{
3570 struct mlx5e_priv *priv = netdev_priv(dev);
3571 struct mlx5_core_dev *mdev = priv->mdev;
3572
3573 return mlx5_eswitch_set_vport_mac(mdev->priv.eswitch, vf + 1, mac);
3574}
3575
3576static int mlx5e_set_vf_vlan(struct net_device *dev, int vf, u16 vlan, u8 qos,
3577 __be16 vlan_proto)
3578{
3579 struct mlx5e_priv *priv = netdev_priv(dev);
3580 struct mlx5_core_dev *mdev = priv->mdev;
3581
3582 if (vlan_proto != htons(ETH_P_8021Q))
3583 return -EPROTONOSUPPORT;
3584
3585 return mlx5_eswitch_set_vport_vlan(mdev->priv.eswitch, vf + 1,
3586 vlan, qos);
3587}
3588
3589static int mlx5e_set_vf_spoofchk(struct net_device *dev, int vf, bool setting)
3590{
3591 struct mlx5e_priv *priv = netdev_priv(dev);
3592 struct mlx5_core_dev *mdev = priv->mdev;
3593
3594 return mlx5_eswitch_set_vport_spoofchk(mdev->priv.eswitch, vf + 1, setting);
3595}
3596
3597static int mlx5e_set_vf_trust(struct net_device *dev, int vf, bool setting)
3598{
3599 struct mlx5e_priv *priv = netdev_priv(dev);
3600 struct mlx5_core_dev *mdev = priv->mdev;
3601
3602 return mlx5_eswitch_set_vport_trust(mdev->priv.eswitch, vf + 1, setting);
3603}
3604
3605static int mlx5e_set_vf_rate(struct net_device *dev, int vf, int min_tx_rate,
3606 int max_tx_rate)
3607{
3608 struct mlx5e_priv *priv = netdev_priv(dev);
3609 struct mlx5_core_dev *mdev = priv->mdev;
3610
3611 return mlx5_eswitch_set_vport_rate(mdev->priv.eswitch, vf + 1,
3612 max_tx_rate, min_tx_rate);
3613}
3614
3615static int mlx5_vport_link2ifla(u8 esw_link)
3616{
3617 switch (esw_link) {
3618 case MLX5_ESW_VPORT_ADMIN_STATE_DOWN:
3619 return IFLA_VF_LINK_STATE_DISABLE;
3620 case MLX5_ESW_VPORT_ADMIN_STATE_UP:
3621 return IFLA_VF_LINK_STATE_ENABLE;
3622 }
3623 return IFLA_VF_LINK_STATE_AUTO;
3624}
3625
3626static int mlx5_ifla_link2vport(u8 ifla_link)
3627{
3628 switch (ifla_link) {
3629 case IFLA_VF_LINK_STATE_DISABLE:
3630 return MLX5_ESW_VPORT_ADMIN_STATE_DOWN;
3631 case IFLA_VF_LINK_STATE_ENABLE:
3632 return MLX5_ESW_VPORT_ADMIN_STATE_UP;
3633 }
3634 return MLX5_ESW_VPORT_ADMIN_STATE_AUTO;
3635}
3636
3637static int mlx5e_set_vf_link_state(struct net_device *dev, int vf,
3638 int link_state)
3639{
3640 struct mlx5e_priv *priv = netdev_priv(dev);
3641 struct mlx5_core_dev *mdev = priv->mdev;
3642
3643 return mlx5_eswitch_set_vport_state(mdev->priv.eswitch, vf + 1,
3644 mlx5_ifla_link2vport(link_state));
3645}
3646
3647static int mlx5e_get_vf_config(struct net_device *dev,
3648 int vf, struct ifla_vf_info *ivi)
3649{
3650 struct mlx5e_priv *priv = netdev_priv(dev);
3651 struct mlx5_core_dev *mdev = priv->mdev;
3652 int err;
3653
3654 err = mlx5_eswitch_get_vport_config(mdev->priv.eswitch, vf + 1, ivi);
3655 if (err)
3656 return err;
3657 ivi->linkstate = mlx5_vport_link2ifla(ivi->linkstate);
3658 return 0;
3659}
3660
3661static int mlx5e_get_vf_stats(struct net_device *dev,
3662 int vf, struct ifla_vf_stats *vf_stats)
3663{
3664 struct mlx5e_priv *priv = netdev_priv(dev);
3665 struct mlx5_core_dev *mdev = priv->mdev;
3666
3667 return mlx5_eswitch_get_vport_stats(mdev->priv.eswitch, vf + 1,
3668 vf_stats);
3669}
3670#endif
3671
3672static void mlx5e_add_vxlan_port(struct net_device *netdev,
3673 struct udp_tunnel_info *ti)
3674{
3675 struct mlx5e_priv *priv = netdev_priv(netdev);
3676
3677 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3678 return;
3679
3680 if (!mlx5e_vxlan_allowed(priv->mdev))
3681 return;
3682
3683 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 1);
3684}
3685
3686static void mlx5e_del_vxlan_port(struct net_device *netdev,
3687 struct udp_tunnel_info *ti)
3688{
3689 struct mlx5e_priv *priv = netdev_priv(netdev);
3690
3691 if (ti->type != UDP_TUNNEL_TYPE_VXLAN)
3692 return;
3693
3694 if (!mlx5e_vxlan_allowed(priv->mdev))
3695 return;
3696
3697 mlx5e_vxlan_queue_work(priv, ti->sa_family, be16_to_cpu(ti->port), 0);
3698}
3699
3700static netdev_features_t mlx5e_tunnel_features_check(struct mlx5e_priv *priv,
3701 struct sk_buff *skb,
3702 netdev_features_t features)
3703{
3704 unsigned int offset = 0;
3705 struct udphdr *udph;
3706 u8 proto;
3707 u16 port;
3708
3709 switch (vlan_get_protocol(skb)) {
3710 case htons(ETH_P_IP):
3711 proto = ip_hdr(skb)->protocol;
3712 break;
3713 case htons(ETH_P_IPV6):
3714 proto = ipv6_find_hdr(skb, &offset, -1, NULL, NULL);
3715 break;
3716 default:
3717 goto out;
3718 }
3719
3720 switch (proto) {
3721 case IPPROTO_GRE:
3722 return features;
3723 case IPPROTO_UDP:
3724 udph = udp_hdr(skb);
3725 port = be16_to_cpu(udph->dest);
3726
3727
3728 if (mlx5e_vxlan_lookup_port(priv, port))
3729 return features;
3730 }
3731
3732out:
3733
3734 return features & ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK);
3735}
3736
3737static netdev_features_t mlx5e_features_check(struct sk_buff *skb,
3738 struct net_device *netdev,
3739 netdev_features_t features)
3740{
3741 struct mlx5e_priv *priv = netdev_priv(netdev);
3742
3743 features = vlan_features_check(skb, features);
3744 features = vxlan_features_check(skb, features);
3745
3746#ifdef CONFIG_MLX5_EN_IPSEC
3747 if (mlx5e_ipsec_feature_check(skb, netdev, features))
3748 return features;
3749#endif
3750
3751
3752 if (skb->encapsulation &&
3753 (features & NETIF_F_CSUM_MASK || features & NETIF_F_GSO_MASK))
3754 return mlx5e_tunnel_features_check(priv, skb, features);
3755
3756 return features;
3757}
3758
3759static bool mlx5e_tx_timeout_eq_recover(struct net_device *dev,
3760 struct mlx5e_txqsq *sq)
3761{
3762 struct mlx5_eq *eq = sq->cq.mcq.eq;
3763 u32 eqe_count;
3764
3765 netdev_err(dev, "EQ 0x%x: Cons = 0x%x, irqn = 0x%x\n",
3766 eq->eqn, eq->cons_index, eq->irqn);
3767
3768 eqe_count = mlx5_eq_poll_irq_disabled(eq);
3769 if (!eqe_count)
3770 return false;
3771
3772 netdev_err(dev, "Recover %d eqes on EQ 0x%x\n", eqe_count, eq->eqn);
3773 sq->channel->stats.eq_rearm++;
3774 return true;
3775}
3776
3777static void mlx5e_tx_timeout_work(struct work_struct *work)
3778{
3779 struct mlx5e_priv *priv = container_of(work, struct mlx5e_priv,
3780 tx_timeout_work);
3781 struct net_device *dev = priv->netdev;
3782 bool reopen_channels = false;
3783 int i, err;
3784
3785 rtnl_lock();
3786 mutex_lock(&priv->state_lock);
3787
3788 if (!test_bit(MLX5E_STATE_OPENED, &priv->state))
3789 goto unlock;
3790
3791 for (i = 0; i < priv->channels.num * priv->channels.params.num_tc; i++) {
3792 struct netdev_queue *dev_queue = netdev_get_tx_queue(dev, i);
3793 struct mlx5e_txqsq *sq = priv->txq2sq[i];
3794
3795 if (!netif_xmit_stopped(dev_queue))
3796 continue;
3797
3798 netdev_err(dev,
3799 "TX timeout on queue: %d, SQ: 0x%x, CQ: 0x%x, SQ Cons: 0x%x SQ Prod: 0x%x, usecs since last trans: %u\n",
3800 i, sq->sqn, sq->cq.mcq.cqn, sq->cc, sq->pc,
3801 jiffies_to_usecs(jiffies - dev_queue->trans_start));
3802
3803
3804
3805
3806 if (!mlx5e_tx_timeout_eq_recover(dev, sq)) {
3807 clear_bit(MLX5E_SQ_STATE_ENABLED, &sq->state);
3808 reopen_channels = true;
3809 }
3810 }
3811
3812 if (!reopen_channels)
3813 goto unlock;
3814
3815 mlx5e_close_locked(dev);
3816 err = mlx5e_open_locked(dev);
3817 if (err)
3818 netdev_err(priv->netdev,
3819 "mlx5e_open_locked failed recovering from a tx_timeout, err(%d).\n",
3820 err);
3821
3822unlock:
3823 mutex_unlock(&priv->state_lock);
3824 rtnl_unlock();
3825}
3826
3827static void mlx5e_tx_timeout(struct net_device *dev)
3828{
3829 struct mlx5e_priv *priv = netdev_priv(dev);
3830
3831 netdev_err(dev, "TX timeout detected\n");
3832 queue_work(priv->wq, &priv->tx_timeout_work);
3833}
3834
3835static int mlx5e_xdp_set(struct net_device *netdev, struct bpf_prog *prog)
3836{
3837 struct mlx5e_priv *priv = netdev_priv(netdev);
3838 struct bpf_prog *old_prog;
3839 int err = 0;
3840 bool reset, was_opened;
3841 int i;
3842
3843 mutex_lock(&priv->state_lock);
3844
3845 if ((netdev->features & NETIF_F_LRO) && prog) {
3846 netdev_warn(netdev, "can't set XDP while LRO is on, disable LRO first\n");
3847 err = -EINVAL;
3848 goto unlock;
3849 }
3850
3851 if ((netdev->features & NETIF_F_HW_ESP) && prog) {
3852 netdev_warn(netdev, "can't set XDP with IPSec offload\n");
3853 err = -EINVAL;
3854 goto unlock;
3855 }
3856
3857 was_opened = test_bit(MLX5E_STATE_OPENED, &priv->state);
3858
3859 reset = (!priv->channels.params.xdp_prog || !prog);
3860
3861 if (was_opened && reset)
3862 mlx5e_close_locked(netdev);
3863 if (was_opened && !reset) {
3864
3865
3866
3867 prog = bpf_prog_add(prog, priv->channels.num);
3868 if (IS_ERR(prog)) {
3869 err = PTR_ERR(prog);
3870 goto unlock;
3871 }
3872 }
3873
3874
3875
3876
3877 old_prog = xchg(&priv->channels.params.xdp_prog, prog);
3878 if (old_prog)
3879 bpf_prog_put(old_prog);
3880
3881 if (reset)
3882 mlx5e_set_rq_type(priv->mdev, &priv->channels.params);
3883
3884 if (was_opened && reset)
3885 mlx5e_open_locked(netdev);
3886
3887 if (!test_bit(MLX5E_STATE_OPENED, &priv->state) || reset)
3888 goto unlock;
3889
3890
3891
3892
3893 for (i = 0; i < priv->channels.num; i++) {
3894 struct mlx5e_channel *c = priv->channels.c[i];
3895
3896 clear_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3897 napi_synchronize(&c->napi);
3898
3899
3900 old_prog = xchg(&c->rq.xdp_prog, prog);
3901
3902 set_bit(MLX5E_RQ_STATE_ENABLED, &c->rq.state);
3903
3904 napi_schedule(&c->napi);
3905
3906 if (old_prog)
3907 bpf_prog_put(old_prog);
3908 }
3909
3910unlock:
3911 mutex_unlock(&priv->state_lock);
3912 return err;
3913}
3914
3915static u32 mlx5e_xdp_query(struct net_device *dev)
3916{
3917 struct mlx5e_priv *priv = netdev_priv(dev);
3918 const struct bpf_prog *xdp_prog;
3919 u32 prog_id = 0;
3920
3921 mutex_lock(&priv->state_lock);
3922 xdp_prog = priv->channels.params.xdp_prog;
3923 if (xdp_prog)
3924 prog_id = xdp_prog->aux->id;
3925 mutex_unlock(&priv->state_lock);
3926
3927 return prog_id;
3928}
3929
3930static int mlx5e_xdp(struct net_device *dev, struct netdev_bpf *xdp)
3931{
3932 switch (xdp->command) {
3933 case XDP_SETUP_PROG:
3934 return mlx5e_xdp_set(dev, xdp->prog);
3935 case XDP_QUERY_PROG:
3936 xdp->prog_id = mlx5e_xdp_query(dev);
3937 xdp->prog_attached = !!xdp->prog_id;
3938 return 0;
3939 default:
3940 return -EINVAL;
3941 }
3942}
3943
3944#ifdef CONFIG_NET_POLL_CONTROLLER
3945
3946
3947
3948static void mlx5e_netpoll(struct net_device *dev)
3949{
3950 struct mlx5e_priv *priv = netdev_priv(dev);
3951 struct mlx5e_channels *chs = &priv->channels;
3952
3953 int i;
3954
3955 for (i = 0; i < chs->num; i++)
3956 napi_schedule(&chs->c[i]->napi);
3957}
3958#endif
3959
3960static const struct net_device_ops mlx5e_netdev_ops = {
3961 .ndo_open = mlx5e_open,
3962 .ndo_stop = mlx5e_close,
3963 .ndo_start_xmit = mlx5e_xmit,
3964 .ndo_setup_tc = mlx5e_setup_tc,
3965 .ndo_select_queue = mlx5e_select_queue,
3966 .ndo_get_stats64 = mlx5e_get_stats,
3967 .ndo_set_rx_mode = mlx5e_set_rx_mode,
3968 .ndo_set_mac_address = mlx5e_set_mac,
3969 .ndo_vlan_rx_add_vid = mlx5e_vlan_rx_add_vid,
3970 .ndo_vlan_rx_kill_vid = mlx5e_vlan_rx_kill_vid,
3971 .ndo_set_features = mlx5e_set_features,
3972 .ndo_fix_features = mlx5e_fix_features,
3973 .ndo_change_mtu = mlx5e_change_mtu,
3974 .ndo_do_ioctl = mlx5e_ioctl,
3975 .ndo_set_tx_maxrate = mlx5e_set_tx_maxrate,
3976 .ndo_udp_tunnel_add = mlx5e_add_vxlan_port,
3977 .ndo_udp_tunnel_del = mlx5e_del_vxlan_port,
3978 .ndo_features_check = mlx5e_features_check,
3979#ifdef CONFIG_RFS_ACCEL
3980 .ndo_rx_flow_steer = mlx5e_rx_flow_steer,
3981#endif
3982 .ndo_tx_timeout = mlx5e_tx_timeout,
3983 .ndo_bpf = mlx5e_xdp,
3984#ifdef CONFIG_NET_POLL_CONTROLLER
3985 .ndo_poll_controller = mlx5e_netpoll,
3986#endif
3987#ifdef CONFIG_MLX5_ESWITCH
3988
3989 .ndo_set_vf_mac = mlx5e_set_vf_mac,
3990 .ndo_set_vf_vlan = mlx5e_set_vf_vlan,
3991 .ndo_set_vf_spoofchk = mlx5e_set_vf_spoofchk,
3992 .ndo_set_vf_trust = mlx5e_set_vf_trust,
3993 .ndo_set_vf_rate = mlx5e_set_vf_rate,
3994 .ndo_get_vf_config = mlx5e_get_vf_config,
3995 .ndo_set_vf_link_state = mlx5e_set_vf_link_state,
3996 .ndo_get_vf_stats = mlx5e_get_vf_stats,
3997 .ndo_has_offload_stats = mlx5e_has_offload_stats,
3998 .ndo_get_offload_stats = mlx5e_get_offload_stats,
3999#endif
4000};
4001
4002static int mlx5e_check_required_hca_cap(struct mlx5_core_dev *mdev)
4003{
4004 if (MLX5_CAP_GEN(mdev, port_type) != MLX5_CAP_PORT_TYPE_ETH)
4005 return -EOPNOTSUPP;
4006 if (!MLX5_CAP_GEN(mdev, eth_net_offloads) ||
4007 !MLX5_CAP_GEN(mdev, nic_flow_table) ||
4008 !MLX5_CAP_ETH(mdev, csum_cap) ||
4009 !MLX5_CAP_ETH(mdev, max_lso_cap) ||
4010 !MLX5_CAP_ETH(mdev, vlan_cap) ||
4011 !MLX5_CAP_ETH(mdev, rss_ind_tbl_cap) ||
4012 MLX5_CAP_FLOWTABLE(mdev,
4013 flow_table_properties_nic_receive.max_ft_level)
4014 < 3) {
4015 mlx5_core_warn(mdev,
4016 "Not creating net device, some required device capabilities are missing\n");
4017 return -EOPNOTSUPP;
4018 }
4019 if (!MLX5_CAP_ETH(mdev, self_lb_en_modifiable))
4020 mlx5_core_warn(mdev, "Self loop back prevention is not supported\n");
4021 if (!MLX5_CAP_GEN(mdev, cq_moderation))
4022 mlx5_core_warn(mdev, "CQ moderation is not supported\n");
4023
4024 return 0;
4025}
4026
4027void mlx5e_build_default_indir_rqt(u32 *indirection_rqt, int len,
4028 int num_channels)
4029{
4030 int i;
4031
4032 for (i = 0; i < len; i++)
4033 indirection_rqt[i] = i % num_channels;
4034}
4035
4036static bool slow_pci_heuristic(struct mlx5_core_dev *mdev)
4037{
4038 u32 link_speed = 0;
4039 u32 pci_bw = 0;
4040
4041 mlx5e_get_max_linkspeed(mdev, &link_speed);
4042 pci_bw = pcie_bandwidth_available(mdev->pdev, NULL, NULL, NULL);
4043 mlx5_core_dbg_once(mdev, "Max link speed = %d, PCI BW = %d\n",
4044 link_speed, pci_bw);
4045
4046#define MLX5E_SLOW_PCI_RATIO (2)
4047
4048 return link_speed && pci_bw &&
4049 link_speed > MLX5E_SLOW_PCI_RATIO * pci_bw;
4050}
4051
4052void mlx5e_set_tx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4053{
4054 params->tx_cq_moderation.cq_period_mode = cq_period_mode;
4055
4056 params->tx_cq_moderation.pkts =
4057 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_PKTS;
4058 params->tx_cq_moderation.usec =
4059 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC;
4060
4061 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4062 params->tx_cq_moderation.usec =
4063 MLX5E_PARAMS_DEFAULT_TX_CQ_MODERATION_USEC_FROM_CQE;
4064
4065 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_TX_CQE_BASED_MODER,
4066 params->tx_cq_moderation.cq_period_mode ==
4067 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4068}
4069
4070void mlx5e_set_rx_cq_mode_params(struct mlx5e_params *params, u8 cq_period_mode)
4071{
4072 params->rx_cq_moderation.cq_period_mode = cq_period_mode;
4073
4074 params->rx_cq_moderation.pkts =
4075 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_PKTS;
4076 params->rx_cq_moderation.usec =
4077 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC;
4078
4079 if (cq_period_mode == MLX5_CQ_PERIOD_MODE_START_FROM_CQE)
4080 params->rx_cq_moderation.usec =
4081 MLX5E_PARAMS_DEFAULT_RX_CQ_MODERATION_USEC_FROM_CQE;
4082
4083 if (params->rx_dim_enabled) {
4084 switch (cq_period_mode) {
4085 case MLX5_CQ_PERIOD_MODE_START_FROM_CQE:
4086 params->rx_cq_moderation =
4087 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_CQE);
4088 break;
4089 case MLX5_CQ_PERIOD_MODE_START_FROM_EQE:
4090 default:
4091 params->rx_cq_moderation =
4092 net_dim_get_def_profile(NET_DIM_CQ_PERIOD_MODE_START_FROM_EQE);
4093 }
4094 }
4095
4096 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_BASED_MODER,
4097 params->rx_cq_moderation.cq_period_mode ==
4098 MLX5_CQ_PERIOD_MODE_START_FROM_CQE);
4099}
4100
4101static u32 mlx5e_choose_lro_timeout(struct mlx5_core_dev *mdev, u32 wanted_timeout)
4102{
4103 int i;
4104
4105
4106 for (i = 0; i < MLX5E_LRO_TIMEOUT_ARR_SIZE - 1; i++)
4107 if (MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]) >= wanted_timeout)
4108 break;
4109
4110 return MLX5_CAP_ETH(mdev, lro_timer_supported_periods[i]);
4111}
4112
4113void mlx5e_build_nic_params(struct mlx5_core_dev *mdev,
4114 struct mlx5e_params *params,
4115 u16 max_channels, u16 mtu)
4116{
4117 u8 rx_cq_period_mode;
4118
4119 params->sw_mtu = mtu;
4120 params->hard_mtu = MLX5E_ETH_HARD_MTU;
4121 params->num_channels = max_channels;
4122 params->num_tc = 1;
4123
4124
4125 params->log_sq_size = is_kdump_kernel() ?
4126 MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE :
4127 MLX5E_PARAMS_DEFAULT_LOG_SQ_SIZE;
4128
4129
4130 params->rx_cqe_compress_def = false;
4131 if (MLX5_CAP_GEN(mdev, cqe_compression) &&
4132 MLX5_CAP_GEN(mdev, vport_group_manager))
4133 params->rx_cqe_compress_def = slow_pci_heuristic(mdev);
4134
4135 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_CQE_COMPRESS, params->rx_cqe_compress_def);
4136
4137
4138 if (mlx5e_striding_rq_possible(mdev, params))
4139 MLX5E_SET_PFLAG(params, MLX5E_PFLAG_RX_STRIDING_RQ,
4140 !slow_pci_heuristic(mdev));
4141 mlx5e_set_rq_type(mdev, params);
4142 mlx5e_init_rq_type_params(mdev, params);
4143
4144
4145
4146
4147 if (params->rq_wq_type == MLX5_WQ_TYPE_LINKED_LIST_STRIDING_RQ)
4148 if (!mlx5e_rx_mpwqe_is_linear_skb(mdev, params))
4149 params->lro_en = !slow_pci_heuristic(mdev);
4150 params->lro_timeout = mlx5e_choose_lro_timeout(mdev, MLX5E_DEFAULT_LRO_TIMEOUT);
4151
4152
4153 rx_cq_period_mode = MLX5_CAP_GEN(mdev, cq_period_start_from_cqe) ?
4154 MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
4155 MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
4156 params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
4157 mlx5e_set_rx_cq_mode_params(params, rx_cq_period_mode);
4158 mlx5e_set_tx_cq_mode_params(params, MLX5_CQ_PERIOD_MODE_START_FROM_EQE);
4159
4160
4161 params->tx_min_inline_mode = mlx5e_params_calculate_tx_min_inline(mdev);
4162
4163
4164 params->rss_hfunc = ETH_RSS_HASH_XOR;
4165 netdev_rss_key_fill(params->toeplitz_hash_key, sizeof(params->toeplitz_hash_key));
4166 mlx5e_build_default_indir_rqt(params->indirection_rqt,
4167 MLX5E_INDIR_RQT_SIZE, max_channels);
4168}
4169
4170static void mlx5e_build_nic_netdev_priv(struct mlx5_core_dev *mdev,
4171 struct net_device *netdev,
4172 const struct mlx5e_profile *profile,
4173 void *ppriv)
4174{
4175 struct mlx5e_priv *priv = netdev_priv(netdev);
4176
4177 priv->mdev = mdev;
4178 priv->netdev = netdev;
4179 priv->profile = profile;
4180 priv->ppriv = ppriv;
4181 priv->msglevel = MLX5E_MSG_LEVEL;
4182
4183 mlx5e_build_nic_params(mdev, &priv->channels.params,
4184 profile->max_nch(mdev), netdev->mtu);
4185
4186 mutex_init(&priv->state_lock);
4187
4188 INIT_WORK(&priv->update_carrier_work, mlx5e_update_carrier_work);
4189 INIT_WORK(&priv->set_rx_mode_work, mlx5e_set_rx_mode_work);
4190 INIT_WORK(&priv->tx_timeout_work, mlx5e_tx_timeout_work);
4191 INIT_DELAYED_WORK(&priv->update_stats_work, mlx5e_update_stats_work);
4192
4193 mlx5e_timestamp_init(priv);
4194}
4195
4196static void mlx5e_set_netdev_dev_addr(struct net_device *netdev)
4197{
4198 struct mlx5e_priv *priv = netdev_priv(netdev);
4199
4200 mlx5_query_nic_vport_mac_address(priv->mdev, 0, netdev->dev_addr);
4201 if (is_zero_ether_addr(netdev->dev_addr) &&
4202 !MLX5_CAP_GEN(priv->mdev, vport_group_manager)) {
4203 eth_hw_addr_random(netdev);
4204 mlx5_core_info(priv->mdev, "Assigned random MAC address %pM\n", netdev->dev_addr);
4205 }
4206}
4207
4208#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4209static const struct switchdev_ops mlx5e_switchdev_ops = {
4210 .switchdev_port_attr_get = mlx5e_attr_get,
4211};
4212#endif
4213
4214static void mlx5e_build_nic_netdev(struct net_device *netdev)
4215{
4216 struct mlx5e_priv *priv = netdev_priv(netdev);
4217 struct mlx5_core_dev *mdev = priv->mdev;
4218 bool fcs_supported;
4219 bool fcs_enabled;
4220
4221 SET_NETDEV_DEV(netdev, &mdev->pdev->dev);
4222
4223 netdev->netdev_ops = &mlx5e_netdev_ops;
4224
4225#ifdef CONFIG_MLX5_CORE_EN_DCB
4226 if (MLX5_CAP_GEN(mdev, vport_group_manager) && MLX5_CAP_GEN(mdev, qos))
4227 netdev->dcbnl_ops = &mlx5e_dcbnl_ops;
4228#endif
4229
4230 netdev->watchdog_timeo = 15 * HZ;
4231
4232 netdev->ethtool_ops = &mlx5e_ethtool_ops;
4233
4234 netdev->vlan_features |= NETIF_F_SG;
4235 netdev->vlan_features |= NETIF_F_IP_CSUM;
4236 netdev->vlan_features |= NETIF_F_IPV6_CSUM;
4237 netdev->vlan_features |= NETIF_F_GRO;
4238 netdev->vlan_features |= NETIF_F_TSO;
4239 netdev->vlan_features |= NETIF_F_TSO6;
4240 netdev->vlan_features |= NETIF_F_RXCSUM;
4241 netdev->vlan_features |= NETIF_F_RXHASH;
4242
4243 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_TX;
4244 netdev->hw_enc_features |= NETIF_F_HW_VLAN_CTAG_RX;
4245
4246 if (!!MLX5_CAP_ETH(mdev, lro_cap))
4247 netdev->vlan_features |= NETIF_F_LRO;
4248
4249 netdev->hw_features = netdev->vlan_features;
4250 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_TX;
4251 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_RX;
4252 netdev->hw_features |= NETIF_F_HW_VLAN_CTAG_FILTER;
4253 netdev->hw_features |= NETIF_F_HW_VLAN_STAG_TX;
4254
4255 if (mlx5e_vxlan_allowed(mdev) || MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4256 netdev->hw_features |= NETIF_F_GSO_PARTIAL;
4257 netdev->hw_enc_features |= NETIF_F_IP_CSUM;
4258 netdev->hw_enc_features |= NETIF_F_IPV6_CSUM;
4259 netdev->hw_enc_features |= NETIF_F_TSO;
4260 netdev->hw_enc_features |= NETIF_F_TSO6;
4261 netdev->hw_enc_features |= NETIF_F_GSO_PARTIAL;
4262 }
4263
4264 if (mlx5e_vxlan_allowed(mdev)) {
4265 netdev->hw_features |= NETIF_F_GSO_UDP_TUNNEL |
4266 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4267 netdev->hw_enc_features |= NETIF_F_GSO_UDP_TUNNEL |
4268 NETIF_F_GSO_UDP_TUNNEL_CSUM;
4269 netdev->gso_partial_features = NETIF_F_GSO_UDP_TUNNEL_CSUM;
4270 }
4271
4272 if (MLX5_CAP_ETH(mdev, tunnel_stateless_gre)) {
4273 netdev->hw_features |= NETIF_F_GSO_GRE |
4274 NETIF_F_GSO_GRE_CSUM;
4275 netdev->hw_enc_features |= NETIF_F_GSO_GRE |
4276 NETIF_F_GSO_GRE_CSUM;
4277 netdev->gso_partial_features |= NETIF_F_GSO_GRE |
4278 NETIF_F_GSO_GRE_CSUM;
4279 }
4280
4281 mlx5_query_port_fcs(mdev, &fcs_supported, &fcs_enabled);
4282
4283 if (fcs_supported)
4284 netdev->hw_features |= NETIF_F_RXALL;
4285
4286 if (MLX5_CAP_ETH(mdev, scatter_fcs))
4287 netdev->hw_features |= NETIF_F_RXFCS;
4288
4289 netdev->features = netdev->hw_features;
4290 if (!priv->channels.params.lro_en)
4291 netdev->features &= ~NETIF_F_LRO;
4292
4293 if (fcs_enabled)
4294 netdev->features &= ~NETIF_F_RXALL;
4295
4296 if (!priv->channels.params.scatter_fcs_en)
4297 netdev->features &= ~NETIF_F_RXFCS;
4298
4299#define FT_CAP(f) MLX5_CAP_FLOWTABLE(mdev, flow_table_properties_nic_receive.f)
4300 if (FT_CAP(flow_modify_en) &&
4301 FT_CAP(modify_root) &&
4302 FT_CAP(identified_miss_table_mode) &&
4303 FT_CAP(flow_table_modify)) {
4304 netdev->hw_features |= NETIF_F_HW_TC;
4305#ifdef CONFIG_RFS_ACCEL
4306 netdev->hw_features |= NETIF_F_NTUPLE;
4307#endif
4308 }
4309
4310 netdev->features |= NETIF_F_HIGHDMA;
4311 netdev->features |= NETIF_F_HW_VLAN_STAG_FILTER;
4312
4313 netdev->priv_flags |= IFF_UNICAST_FLT;
4314
4315 mlx5e_set_netdev_dev_addr(netdev);
4316
4317#if IS_ENABLED(CONFIG_MLX5_ESWITCH)
4318 if (MLX5_VPORT_MANAGER(mdev))
4319 netdev->switchdev_ops = &mlx5e_switchdev_ops;
4320#endif
4321
4322 mlx5e_ipsec_build_netdev(priv);
4323}
4324
4325static void mlx5e_create_q_counters(struct mlx5e_priv *priv)
4326{
4327 struct mlx5_core_dev *mdev = priv->mdev;
4328 int err;
4329
4330 err = mlx5_core_alloc_q_counter(mdev, &priv->q_counter);
4331 if (err) {
4332 mlx5_core_warn(mdev, "alloc queue counter failed, %d\n", err);
4333 priv->q_counter = 0;
4334 }
4335
4336 err = mlx5_core_alloc_q_counter(mdev, &priv->drop_rq_q_counter);
4337 if (err) {
4338 mlx5_core_warn(mdev, "alloc drop RQ counter failed, %d\n", err);
4339 priv->drop_rq_q_counter = 0;
4340 }
4341}
4342
4343static void mlx5e_destroy_q_counters(struct mlx5e_priv *priv)
4344{
4345 if (priv->q_counter)
4346 mlx5_core_dealloc_q_counter(priv->mdev, priv->q_counter);
4347
4348 if (priv->drop_rq_q_counter)
4349 mlx5_core_dealloc_q_counter(priv->mdev, priv->drop_rq_q_counter);
4350}
4351
4352static void mlx5e_nic_init(struct mlx5_core_dev *mdev,
4353 struct net_device *netdev,
4354 const struct mlx5e_profile *profile,
4355 void *ppriv)
4356{
4357 struct mlx5e_priv *priv = netdev_priv(netdev);
4358 int err;
4359
4360 mlx5e_build_nic_netdev_priv(mdev, netdev, profile, ppriv);
4361 err = mlx5e_ipsec_init(priv);
4362 if (err)
4363 mlx5_core_err(mdev, "IPSec initialization failed, %d\n", err);
4364 mlx5e_build_nic_netdev(netdev);
4365 mlx5e_vxlan_init(priv);
4366}
4367
4368static void mlx5e_nic_cleanup(struct mlx5e_priv *priv)
4369{
4370 mlx5e_ipsec_cleanup(priv);
4371 mlx5e_vxlan_cleanup(priv);
4372}
4373
4374static int mlx5e_init_nic_rx(struct mlx5e_priv *priv)
4375{
4376 struct mlx5_core_dev *mdev = priv->mdev;
4377 int err;
4378
4379 err = mlx5e_create_indirect_rqt(priv);
4380 if (err)
4381 return err;
4382
4383 err = mlx5e_create_direct_rqts(priv);
4384 if (err)
4385 goto err_destroy_indirect_rqts;
4386
4387 err = mlx5e_create_indirect_tirs(priv);
4388 if (err)
4389 goto err_destroy_direct_rqts;
4390
4391 err = mlx5e_create_direct_tirs(priv);
4392 if (err)
4393 goto err_destroy_indirect_tirs;
4394
4395 err = mlx5e_create_flow_steering(priv);
4396 if (err) {
4397 mlx5_core_warn(mdev, "create flow steering failed, %d\n", err);
4398 goto err_destroy_direct_tirs;
4399 }
4400
4401 err = mlx5e_tc_init(priv);
4402 if (err)
4403 goto err_destroy_flow_steering;
4404
4405 return 0;
4406
4407err_destroy_flow_steering:
4408 mlx5e_destroy_flow_steering(priv);
4409err_destroy_direct_tirs:
4410 mlx5e_destroy_direct_tirs(priv);
4411err_destroy_indirect_tirs:
4412 mlx5e_destroy_indirect_tirs(priv);
4413err_destroy_direct_rqts:
4414 mlx5e_destroy_direct_rqts(priv);
4415err_destroy_indirect_rqts:
4416 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4417 return err;
4418}
4419
4420static void mlx5e_cleanup_nic_rx(struct mlx5e_priv *priv)
4421{
4422 mlx5e_tc_cleanup(priv);
4423 mlx5e_destroy_flow_steering(priv);
4424 mlx5e_destroy_direct_tirs(priv);
4425 mlx5e_destroy_indirect_tirs(priv);
4426 mlx5e_destroy_direct_rqts(priv);
4427 mlx5e_destroy_rqt(priv, &priv->indir_rqt);
4428}
4429
4430static int mlx5e_init_nic_tx(struct mlx5e_priv *priv)
4431{
4432 int err;
4433
4434 err = mlx5e_create_tises(priv);
4435 if (err) {
4436 mlx5_core_warn(priv->mdev, "create tises failed, %d\n", err);
4437 return err;
4438 }
4439
4440#ifdef CONFIG_MLX5_CORE_EN_DCB
4441 mlx5e_dcbnl_initialize(priv);
4442#endif
4443 return 0;
4444}
4445
4446static void mlx5e_nic_enable(struct mlx5e_priv *priv)
4447{
4448 struct net_device *netdev = priv->netdev;
4449 struct mlx5_core_dev *mdev = priv->mdev;
4450 u16 max_mtu;
4451
4452 mlx5e_init_l2_addr(priv);
4453
4454
4455 if (!netif_running(netdev))
4456 mlx5_set_port_admin_status(mdev, MLX5_PORT_DOWN);
4457
4458
4459 netdev->min_mtu = ETH_MIN_MTU;
4460 mlx5_query_port_max_mtu(priv->mdev, &max_mtu, 1);
4461 netdev->max_mtu = MLX5E_HW2SW_MTU(&priv->channels.params, max_mtu);
4462 mlx5e_set_dev_port_mtu(priv);
4463
4464 mlx5_lag_add(mdev, netdev);
4465
4466 mlx5e_enable_async_events(priv);
4467
4468 if (MLX5_VPORT_MANAGER(priv->mdev))
4469 mlx5e_register_vport_reps(priv);
4470
4471 if (netdev->reg_state != NETREG_REGISTERED)
4472 return;
4473#ifdef CONFIG_MLX5_CORE_EN_DCB
4474 mlx5e_dcbnl_init_app(priv);
4475#endif
4476
4477 queue_work(priv->wq, &priv->set_rx_mode_work);
4478
4479 rtnl_lock();
4480 if (netif_running(netdev))
4481 mlx5e_open(netdev);
4482 netif_device_attach(netdev);
4483 rtnl_unlock();
4484}
4485
4486static void mlx5e_nic_disable(struct mlx5e_priv *priv)
4487{
4488 struct mlx5_core_dev *mdev = priv->mdev;
4489
4490#ifdef CONFIG_MLX5_CORE_EN_DCB
4491 if (priv->netdev->reg_state == NETREG_REGISTERED)
4492 mlx5e_dcbnl_delete_app(priv);
4493#endif
4494
4495 rtnl_lock();
4496 if (netif_running(priv->netdev))
4497 mlx5e_close(priv->netdev);
4498 netif_device_detach(priv->netdev);
4499 rtnl_unlock();
4500
4501 queue_work(priv->wq, &priv->set_rx_mode_work);
4502
4503 if (MLX5_VPORT_MANAGER(priv->mdev))
4504 mlx5e_unregister_vport_reps(priv);
4505
4506 mlx5e_disable_async_events(priv);
4507 mlx5_lag_remove(mdev);
4508}
4509
4510static const struct mlx5e_profile mlx5e_nic_profile = {
4511 .init = mlx5e_nic_init,
4512 .cleanup = mlx5e_nic_cleanup,
4513 .init_rx = mlx5e_init_nic_rx,
4514 .cleanup_rx = mlx5e_cleanup_nic_rx,
4515 .init_tx = mlx5e_init_nic_tx,
4516 .cleanup_tx = mlx5e_cleanup_nic_tx,
4517 .enable = mlx5e_nic_enable,
4518 .disable = mlx5e_nic_disable,
4519 .update_stats = mlx5e_update_ndo_stats,
4520 .max_nch = mlx5e_get_max_num_channels,
4521 .update_carrier = mlx5e_update_carrier,
4522 .rx_handlers.handle_rx_cqe = mlx5e_handle_rx_cqe,
4523 .rx_handlers.handle_rx_cqe_mpwqe = mlx5e_handle_rx_cqe_mpwrq,
4524 .max_tc = MLX5E_MAX_NUM_TC,
4525};
4526
4527
4528
4529struct net_device *mlx5e_create_netdev(struct mlx5_core_dev *mdev,
4530 const struct mlx5e_profile *profile,
4531 void *ppriv)
4532{
4533 int nch = profile->max_nch(mdev);
4534 struct net_device *netdev;
4535 struct mlx5e_priv *priv;
4536
4537 netdev = alloc_etherdev_mqs(sizeof(struct mlx5e_priv),
4538 nch * profile->max_tc,
4539 nch);
4540 if (!netdev) {
4541 mlx5_core_err(mdev, "alloc_etherdev_mqs() failed\n");
4542 return NULL;
4543 }
4544
4545#ifdef CONFIG_RFS_ACCEL
4546 netdev->rx_cpu_rmap = mdev->rmap;
4547#endif
4548
4549 profile->init(mdev, netdev, profile, ppriv);
4550
4551 netif_carrier_off(netdev);
4552
4553 priv = netdev_priv(netdev);
4554
4555 priv->wq = create_singlethread_workqueue("mlx5e");
4556 if (!priv->wq)
4557 goto err_cleanup_nic;
4558
4559 return netdev;
4560
4561err_cleanup_nic:
4562 if (profile->cleanup)
4563 profile->cleanup(priv);
4564 free_netdev(netdev);
4565
4566 return NULL;
4567}
4568
4569int mlx5e_attach_netdev(struct mlx5e_priv *priv)
4570{
4571 struct mlx5_core_dev *mdev = priv->mdev;
4572 const struct mlx5e_profile *profile;
4573 int err;
4574
4575 profile = priv->profile;
4576 clear_bit(MLX5E_STATE_DESTROYING, &priv->state);
4577
4578 err = profile->init_tx(priv);
4579 if (err)
4580 goto out;
4581
4582 mlx5e_create_q_counters(priv);
4583
4584 err = mlx5e_open_drop_rq(priv, &priv->drop_rq);
4585 if (err) {
4586 mlx5_core_err(mdev, "open drop rq failed, %d\n", err);
4587 goto err_destroy_q_counters;
4588 }
4589
4590 err = profile->init_rx(priv);
4591 if (err)
4592 goto err_close_drop_rq;
4593
4594 if (profile->enable)
4595 profile->enable(priv);
4596
4597 return 0;
4598
4599err_close_drop_rq:
4600 mlx5e_close_drop_rq(&priv->drop_rq);
4601
4602err_destroy_q_counters:
4603 mlx5e_destroy_q_counters(priv);
4604 profile->cleanup_tx(priv);
4605
4606out:
4607 return err;
4608}
4609
4610void mlx5e_detach_netdev(struct mlx5e_priv *priv)
4611{
4612 const struct mlx5e_profile *profile = priv->profile;
4613
4614 set_bit(MLX5E_STATE_DESTROYING, &priv->state);
4615
4616 if (profile->disable)
4617 profile->disable(priv);
4618 flush_workqueue(priv->wq);
4619
4620 profile->cleanup_rx(priv);
4621 mlx5e_close_drop_rq(&priv->drop_rq);
4622 mlx5e_destroy_q_counters(priv);
4623 profile->cleanup_tx(priv);
4624 cancel_delayed_work_sync(&priv->update_stats_work);
4625}
4626
4627void mlx5e_destroy_netdev(struct mlx5e_priv *priv)
4628{
4629 const struct mlx5e_profile *profile = priv->profile;
4630 struct net_device *netdev = priv->netdev;
4631
4632 destroy_workqueue(priv->wq);
4633 if (profile->cleanup)
4634 profile->cleanup(priv);
4635 free_netdev(netdev);
4636}
4637
4638
4639
4640
4641static int mlx5e_attach(struct mlx5_core_dev *mdev, void *vpriv)
4642{
4643 struct mlx5e_priv *priv = vpriv;
4644 struct net_device *netdev = priv->netdev;
4645 int err;
4646
4647 if (netif_device_present(netdev))
4648 return 0;
4649
4650 err = mlx5e_create_mdev_resources(mdev);
4651 if (err)
4652 return err;
4653
4654 err = mlx5e_attach_netdev(priv);
4655 if (err) {
4656 mlx5e_destroy_mdev_resources(mdev);
4657 return err;
4658 }
4659
4660 return 0;
4661}
4662
4663static void mlx5e_detach(struct mlx5_core_dev *mdev, void *vpriv)
4664{
4665 struct mlx5e_priv *priv = vpriv;
4666 struct net_device *netdev = priv->netdev;
4667
4668 if (!netif_device_present(netdev))
4669 return;
4670
4671 mlx5e_detach_netdev(priv);
4672 mlx5e_destroy_mdev_resources(mdev);
4673}
4674
4675static void *mlx5e_add(struct mlx5_core_dev *mdev)
4676{
4677 struct net_device *netdev;
4678 void *rpriv = NULL;
4679 void *priv;
4680 int err;
4681
4682 err = mlx5e_check_required_hca_cap(mdev);
4683 if (err)
4684 return NULL;
4685
4686#ifdef CONFIG_MLX5_ESWITCH
4687 if (MLX5_VPORT_MANAGER(mdev)) {
4688 rpriv = mlx5e_alloc_nic_rep_priv(mdev);
4689 if (!rpriv) {
4690 mlx5_core_warn(mdev, "Failed to alloc NIC rep priv data\n");
4691 return NULL;
4692 }
4693 }
4694#endif
4695
4696 netdev = mlx5e_create_netdev(mdev, &mlx5e_nic_profile, rpriv);
4697 if (!netdev) {
4698 mlx5_core_err(mdev, "mlx5e_create_netdev failed\n");
4699 goto err_free_rpriv;
4700 }
4701
4702 priv = netdev_priv(netdev);
4703
4704 err = mlx5e_attach(mdev, priv);
4705 if (err) {
4706 mlx5_core_err(mdev, "mlx5e_attach failed, %d\n", err);
4707 goto err_destroy_netdev;
4708 }
4709
4710 err = register_netdev(netdev);
4711 if (err) {
4712 mlx5_core_err(mdev, "register_netdev failed, %d\n", err);
4713 goto err_detach;
4714 }
4715
4716#ifdef CONFIG_MLX5_CORE_EN_DCB
4717 mlx5e_dcbnl_init_app(priv);
4718#endif
4719 return priv;
4720
4721err_detach:
4722 mlx5e_detach(mdev, priv);
4723err_destroy_netdev:
4724 mlx5e_destroy_netdev(priv);
4725err_free_rpriv:
4726 kfree(rpriv);
4727 return NULL;
4728}
4729
4730static void mlx5e_remove(struct mlx5_core_dev *mdev, void *vpriv)
4731{
4732 struct mlx5e_priv *priv = vpriv;
4733 void *ppriv = priv->ppriv;
4734
4735#ifdef CONFIG_MLX5_CORE_EN_DCB
4736 mlx5e_dcbnl_delete_app(priv);
4737#endif
4738 unregister_netdev(priv->netdev);
4739 mlx5e_detach(mdev, vpriv);
4740 mlx5e_destroy_netdev(priv);
4741 kfree(ppriv);
4742}
4743
4744static void *mlx5e_get_netdev(void *vpriv)
4745{
4746 struct mlx5e_priv *priv = vpriv;
4747
4748 return priv->netdev;
4749}
4750
4751static struct mlx5_interface mlx5e_interface = {
4752 .add = mlx5e_add,
4753 .remove = mlx5e_remove,
4754 .attach = mlx5e_attach,
4755 .detach = mlx5e_detach,
4756 .event = mlx5e_async_event,
4757 .protocol = MLX5_INTERFACE_PROTOCOL_ETH,
4758 .get_dev = mlx5e_get_netdev,
4759};
4760
4761void mlx5e_init(void)
4762{
4763 mlx5e_ipsec_build_inverse_table();
4764 mlx5e_build_ptys2ethtool_map();
4765 mlx5_register_interface(&mlx5e_interface);
4766}
4767
4768void mlx5e_cleanup(void)
4769{
4770 mlx5_unregister_interface(&mlx5e_interface);
4771}
4772