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33#include <linux/highmem.h>
34#include <linux/module.h>
35#include <linux/init.h>
36#include <linux/errno.h>
37#include <linux/pci.h>
38#include <linux/dma-mapping.h>
39#include <linux/slab.h>
40#include <linux/io-mapping.h>
41#include <linux/interrupt.h>
42#include <linux/delay.h>
43#include <linux/mlx5/driver.h>
44#include <linux/mlx5/cq.h>
45#include <linux/mlx5/qp.h>
46#include <linux/mlx5/srq.h>
47#include <linux/debugfs.h>
48#include <linux/kmod.h>
49#include <linux/mlx5/mlx5_ifc.h>
50#include <linux/mlx5/vport.h>
51#ifdef CONFIG_RFS_ACCEL
52#include <linux/cpu_rmap.h>
53#endif
54#include <net/devlink.h>
55#include "mlx5_core.h"
56#include "fs_core.h"
57#include "lib/mpfs.h"
58#include "eswitch.h"
59#include "lib/mlx5.h"
60#include "fpga/core.h"
61#include "fpga/ipsec.h"
62#include "accel/ipsec.h"
63#include "lib/clock.h"
64
65MODULE_AUTHOR("Eli Cohen <eli@mellanox.com>");
66MODULE_DESCRIPTION("Mellanox Connect-IB, ConnectX-4 core driver");
67MODULE_LICENSE("Dual BSD/GPL");
68MODULE_VERSION(DRIVER_VERSION);
69
70unsigned int mlx5_core_debug_mask;
71module_param_named(debug_mask, mlx5_core_debug_mask, uint, 0644);
72MODULE_PARM_DESC(debug_mask, "debug mask: 1 = dump cmd data, 2 = dump cmd exec time, 3 = both. Default=0");
73
74#define MLX5_DEFAULT_PROF 2
75static unsigned int prof_sel = MLX5_DEFAULT_PROF;
76module_param_named(prof_sel, prof_sel, uint, 0444);
77MODULE_PARM_DESC(prof_sel, "profile selector. Valid range 0 - 2");
78
79static u32 sw_owner_id[4];
80
81enum {
82 MLX5_ATOMIC_REQ_MODE_BE = 0x0,
83 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS = 0x1,
84};
85
86static struct mlx5_profile profile[] = {
87 [0] = {
88 .mask = 0,
89 },
90 [1] = {
91 .mask = MLX5_PROF_MASK_QP_SIZE,
92 .log_max_qp = 12,
93 },
94 [2] = {
95 .mask = MLX5_PROF_MASK_QP_SIZE |
96 MLX5_PROF_MASK_MR_CACHE,
97 .log_max_qp = 18,
98 .mr_cache[0] = {
99 .size = 500,
100 .limit = 250
101 },
102 .mr_cache[1] = {
103 .size = 500,
104 .limit = 250
105 },
106 .mr_cache[2] = {
107 .size = 500,
108 .limit = 250
109 },
110 .mr_cache[3] = {
111 .size = 500,
112 .limit = 250
113 },
114 .mr_cache[4] = {
115 .size = 500,
116 .limit = 250
117 },
118 .mr_cache[5] = {
119 .size = 500,
120 .limit = 250
121 },
122 .mr_cache[6] = {
123 .size = 500,
124 .limit = 250
125 },
126 .mr_cache[7] = {
127 .size = 500,
128 .limit = 250
129 },
130 .mr_cache[8] = {
131 .size = 500,
132 .limit = 250
133 },
134 .mr_cache[9] = {
135 .size = 500,
136 .limit = 250
137 },
138 .mr_cache[10] = {
139 .size = 500,
140 .limit = 250
141 },
142 .mr_cache[11] = {
143 .size = 500,
144 .limit = 250
145 },
146 .mr_cache[12] = {
147 .size = 64,
148 .limit = 32
149 },
150 .mr_cache[13] = {
151 .size = 32,
152 .limit = 16
153 },
154 .mr_cache[14] = {
155 .size = 16,
156 .limit = 8
157 },
158 .mr_cache[15] = {
159 .size = 8,
160 .limit = 4
161 },
162 .mr_cache[16] = {
163 .size = 8,
164 .limit = 4
165 },
166 .mr_cache[17] = {
167 .size = 8,
168 .limit = 4
169 },
170 .mr_cache[18] = {
171 .size = 8,
172 .limit = 4
173 },
174 .mr_cache[19] = {
175 .size = 4,
176 .limit = 2
177 },
178 .mr_cache[20] = {
179 .size = 4,
180 .limit = 2
181 },
182 },
183};
184
185#define FW_INIT_TIMEOUT_MILI 2000
186#define FW_INIT_WAIT_MS 2
187#define FW_PRE_INIT_TIMEOUT_MILI 10000
188
189static int wait_fw_init(struct mlx5_core_dev *dev, u32 max_wait_mili)
190{
191 unsigned long end = jiffies + msecs_to_jiffies(max_wait_mili);
192 int err = 0;
193
194 while (fw_initializing(dev)) {
195 if (time_after(jiffies, end)) {
196 err = -EBUSY;
197 break;
198 }
199 msleep(FW_INIT_WAIT_MS);
200 }
201
202 return err;
203}
204
205static void mlx5_set_driver_version(struct mlx5_core_dev *dev)
206{
207 int driver_ver_sz = MLX5_FLD_SZ_BYTES(set_driver_version_in,
208 driver_version);
209 u8 in[MLX5_ST_SZ_BYTES(set_driver_version_in)] = {0};
210 u8 out[MLX5_ST_SZ_BYTES(set_driver_version_out)] = {0};
211 int remaining_size = driver_ver_sz;
212 char *string;
213
214 if (!MLX5_CAP_GEN(dev, driver_version))
215 return;
216
217 string = MLX5_ADDR_OF(set_driver_version_in, in, driver_version);
218
219 strncpy(string, "Linux", remaining_size);
220
221 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
222 strncat(string, ",", remaining_size);
223
224 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
225 strncat(string, DRIVER_NAME, remaining_size);
226
227 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
228 strncat(string, ",", remaining_size);
229
230 remaining_size = max_t(int, 0, driver_ver_sz - strlen(string));
231 strncat(string, DRIVER_VERSION, remaining_size);
232
233
234 MLX5_SET(set_driver_version_in, in, opcode,
235 MLX5_CMD_OP_SET_DRIVER_VERSION);
236
237 mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
238}
239
240static int set_dma_caps(struct pci_dev *pdev)
241{
242 int err;
243
244 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
245 if (err) {
246 dev_warn(&pdev->dev, "Warning: couldn't set 64-bit PCI DMA mask\n");
247 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
248 if (err) {
249 dev_err(&pdev->dev, "Can't set PCI DMA mask, aborting\n");
250 return err;
251 }
252 }
253
254 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
255 if (err) {
256 dev_warn(&pdev->dev,
257 "Warning: couldn't set 64-bit consistent PCI DMA mask\n");
258 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
259 if (err) {
260 dev_err(&pdev->dev,
261 "Can't set consistent PCI DMA mask, aborting\n");
262 return err;
263 }
264 }
265
266 dma_set_max_seg_size(&pdev->dev, 2u * 1024 * 1024 * 1024);
267 return err;
268}
269
270static int mlx5_pci_enable_device(struct mlx5_core_dev *dev)
271{
272 struct pci_dev *pdev = dev->pdev;
273 int err = 0;
274
275 mutex_lock(&dev->pci_status_mutex);
276 if (dev->pci_status == MLX5_PCI_STATUS_DISABLED) {
277 err = pci_enable_device(pdev);
278 if (!err)
279 dev->pci_status = MLX5_PCI_STATUS_ENABLED;
280 }
281 mutex_unlock(&dev->pci_status_mutex);
282
283 return err;
284}
285
286static void mlx5_pci_disable_device(struct mlx5_core_dev *dev)
287{
288 struct pci_dev *pdev = dev->pdev;
289
290 mutex_lock(&dev->pci_status_mutex);
291 if (dev->pci_status == MLX5_PCI_STATUS_ENABLED) {
292 pci_disable_device(pdev);
293 dev->pci_status = MLX5_PCI_STATUS_DISABLED;
294 }
295 mutex_unlock(&dev->pci_status_mutex);
296}
297
298static int request_bar(struct pci_dev *pdev)
299{
300 int err = 0;
301
302 if (!(pci_resource_flags(pdev, 0) & IORESOURCE_MEM)) {
303 dev_err(&pdev->dev, "Missing registers BAR, aborting\n");
304 return -ENODEV;
305 }
306
307 err = pci_request_regions(pdev, DRIVER_NAME);
308 if (err)
309 dev_err(&pdev->dev, "Couldn't get PCI resources, aborting\n");
310
311 return err;
312}
313
314static void release_bar(struct pci_dev *pdev)
315{
316 pci_release_regions(pdev);
317}
318
319static int mlx5_alloc_irq_vectors(struct mlx5_core_dev *dev)
320{
321 struct mlx5_priv *priv = &dev->priv;
322 struct mlx5_eq_table *table = &priv->eq_table;
323 int num_eqs = 1 << MLX5_CAP_GEN(dev, log_max_eq);
324 int nvec;
325 int err;
326
327 nvec = MLX5_CAP_GEN(dev, num_ports) * num_online_cpus() +
328 MLX5_EQ_VEC_COMP_BASE;
329 nvec = min_t(int, nvec, num_eqs);
330 if (nvec <= MLX5_EQ_VEC_COMP_BASE)
331 return -ENOMEM;
332
333 priv->irq_info = kcalloc(nvec, sizeof(*priv->irq_info), GFP_KERNEL);
334 if (!priv->irq_info)
335 return -ENOMEM;
336
337 nvec = pci_alloc_irq_vectors(dev->pdev,
338 MLX5_EQ_VEC_COMP_BASE + 1, nvec,
339 PCI_IRQ_MSIX);
340 if (nvec < 0) {
341 err = nvec;
342 goto err_free_irq_info;
343 }
344
345 table->num_comp_vectors = nvec - MLX5_EQ_VEC_COMP_BASE;
346
347 return 0;
348
349err_free_irq_info:
350 kfree(priv->irq_info);
351 return err;
352}
353
354static void mlx5_free_irq_vectors(struct mlx5_core_dev *dev)
355{
356 struct mlx5_priv *priv = &dev->priv;
357
358 pci_free_irq_vectors(dev->pdev);
359 kfree(priv->irq_info);
360}
361
362struct mlx5_reg_host_endianness {
363 u8 he;
364 u8 rsvd[15];
365};
366
367#define CAP_MASK(pos, size) ((u64)((1 << (size)) - 1) << (pos))
368
369enum {
370 MLX5_CAP_BITS_RW_MASK = CAP_MASK(MLX5_CAP_OFF_CMDIF_CSUM, 2) |
371 MLX5_DEV_CAP_FLAG_DCT,
372};
373
374static u16 to_fw_pkey_sz(struct mlx5_core_dev *dev, u32 size)
375{
376 switch (size) {
377 case 128:
378 return 0;
379 case 256:
380 return 1;
381 case 512:
382 return 2;
383 case 1024:
384 return 3;
385 case 2048:
386 return 4;
387 case 4096:
388 return 5;
389 default:
390 mlx5_core_warn(dev, "invalid pkey table size %d\n", size);
391 return 0;
392 }
393}
394
395static int mlx5_core_get_caps_mode(struct mlx5_core_dev *dev,
396 enum mlx5_cap_type cap_type,
397 enum mlx5_cap_mode cap_mode)
398{
399 u8 in[MLX5_ST_SZ_BYTES(query_hca_cap_in)];
400 int out_sz = MLX5_ST_SZ_BYTES(query_hca_cap_out);
401 void *out, *hca_caps;
402 u16 opmod = (cap_type << 1) | (cap_mode & 0x01);
403 int err;
404
405 memset(in, 0, sizeof(in));
406 out = kzalloc(out_sz, GFP_KERNEL);
407 if (!out)
408 return -ENOMEM;
409
410 MLX5_SET(query_hca_cap_in, in, opcode, MLX5_CMD_OP_QUERY_HCA_CAP);
411 MLX5_SET(query_hca_cap_in, in, op_mod, opmod);
412 err = mlx5_cmd_exec(dev, in, sizeof(in), out, out_sz);
413 if (err) {
414 mlx5_core_warn(dev,
415 "QUERY_HCA_CAP : type(%x) opmode(%x) Failed(%d)\n",
416 cap_type, cap_mode, err);
417 goto query_ex;
418 }
419
420 hca_caps = MLX5_ADDR_OF(query_hca_cap_out, out, capability);
421
422 switch (cap_mode) {
423 case HCA_CAP_OPMOD_GET_MAX:
424 memcpy(dev->caps.hca_max[cap_type], hca_caps,
425 MLX5_UN_SZ_BYTES(hca_cap_union));
426 break;
427 case HCA_CAP_OPMOD_GET_CUR:
428 memcpy(dev->caps.hca_cur[cap_type], hca_caps,
429 MLX5_UN_SZ_BYTES(hca_cap_union));
430 break;
431 default:
432 mlx5_core_warn(dev,
433 "Tried to query dev cap type(%x) with wrong opmode(%x)\n",
434 cap_type, cap_mode);
435 err = -EINVAL;
436 break;
437 }
438query_ex:
439 kfree(out);
440 return err;
441}
442
443int mlx5_core_get_caps(struct mlx5_core_dev *dev, enum mlx5_cap_type cap_type)
444{
445 int ret;
446
447 ret = mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_CUR);
448 if (ret)
449 return ret;
450 return mlx5_core_get_caps_mode(dev, cap_type, HCA_CAP_OPMOD_GET_MAX);
451}
452
453static int set_caps(struct mlx5_core_dev *dev, void *in, int in_sz, int opmod)
454{
455 u32 out[MLX5_ST_SZ_DW(set_hca_cap_out)] = {0};
456
457 MLX5_SET(set_hca_cap_in, in, opcode, MLX5_CMD_OP_SET_HCA_CAP);
458 MLX5_SET(set_hca_cap_in, in, op_mod, opmod << 1);
459 return mlx5_cmd_exec(dev, in, in_sz, out, sizeof(out));
460}
461
462static int handle_hca_cap_atomic(struct mlx5_core_dev *dev)
463{
464 void *set_ctx;
465 void *set_hca_cap;
466 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
467 int req_endianness;
468 int err;
469
470 if (MLX5_CAP_GEN(dev, atomic)) {
471 err = mlx5_core_get_caps(dev, MLX5_CAP_ATOMIC);
472 if (err)
473 return err;
474 } else {
475 return 0;
476 }
477
478 req_endianness =
479 MLX5_CAP_ATOMIC(dev,
480 supported_atomic_req_8B_endianness_mode_1);
481
482 if (req_endianness != MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS)
483 return 0;
484
485 set_ctx = kzalloc(set_sz, GFP_KERNEL);
486 if (!set_ctx)
487 return -ENOMEM;
488
489 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx, capability);
490
491
492 MLX5_SET(atomic_caps, set_hca_cap, atomic_req_8B_endianness_mode,
493 MLX5_ATOMIC_REQ_MODE_HOST_ENDIANNESS);
494
495 err = set_caps(dev, set_ctx, set_sz, MLX5_SET_HCA_CAP_OP_MOD_ATOMIC);
496
497 kfree(set_ctx);
498 return err;
499}
500
501static int handle_hca_cap(struct mlx5_core_dev *dev)
502{
503 void *set_ctx = NULL;
504 struct mlx5_profile *prof = dev->profile;
505 int err = -ENOMEM;
506 int set_sz = MLX5_ST_SZ_BYTES(set_hca_cap_in);
507 void *set_hca_cap;
508
509 set_ctx = kzalloc(set_sz, GFP_KERNEL);
510 if (!set_ctx)
511 goto query_ex;
512
513 err = mlx5_core_get_caps(dev, MLX5_CAP_GENERAL);
514 if (err)
515 goto query_ex;
516
517 set_hca_cap = MLX5_ADDR_OF(set_hca_cap_in, set_ctx,
518 capability);
519 memcpy(set_hca_cap, dev->caps.hca_cur[MLX5_CAP_GENERAL],
520 MLX5_ST_SZ_BYTES(cmd_hca_cap));
521
522 mlx5_core_dbg(dev, "Current Pkey table size %d Setting new size %d\n",
523 mlx5_to_sw_pkey_sz(MLX5_CAP_GEN(dev, pkey_table_size)),
524 128);
525
526 MLX5_SET(cmd_hca_cap, set_hca_cap, pkey_table_size,
527 to_fw_pkey_sz(dev, 128));
528
529
530 if (MLX5_CAP_GEN_MAX(dev, log_max_qp) < profile[prof_sel].log_max_qp) {
531 mlx5_core_warn(dev, "log_max_qp value in current profile is %d, changing it to HCA capability limit (%d)\n",
532 profile[prof_sel].log_max_qp,
533 MLX5_CAP_GEN_MAX(dev, log_max_qp));
534 profile[prof_sel].log_max_qp = MLX5_CAP_GEN_MAX(dev, log_max_qp);
535 }
536 if (prof->mask & MLX5_PROF_MASK_QP_SIZE)
537 MLX5_SET(cmd_hca_cap, set_hca_cap, log_max_qp,
538 prof->log_max_qp);
539
540
541 MLX5_SET(cmd_hca_cap, set_hca_cap, cmdif_checksum, 0);
542
543
544
545
546 if (MLX5_CAP_GEN_MAX(dev, uar_4k) && PAGE_SIZE > 4096)
547 MLX5_SET(cmd_hca_cap, set_hca_cap, uar_4k, 1);
548
549 MLX5_SET(cmd_hca_cap, set_hca_cap, log_uar_page_sz, PAGE_SHIFT - 12);
550
551 if (MLX5_CAP_GEN_MAX(dev, cache_line_128byte))
552 MLX5_SET(cmd_hca_cap,
553 set_hca_cap,
554 cache_line_128byte,
555 cache_line_size() >= 128 ? 1 : 0);
556
557 if (MLX5_CAP_GEN_MAX(dev, dct))
558 MLX5_SET(cmd_hca_cap, set_hca_cap, dct, 1);
559
560 if (MLX5_CAP_GEN_MAX(dev, num_vhca_ports))
561 MLX5_SET(cmd_hca_cap,
562 set_hca_cap,
563 num_vhca_ports,
564 MLX5_CAP_GEN_MAX(dev, num_vhca_ports));
565
566 err = set_caps(dev, set_ctx, set_sz,
567 MLX5_SET_HCA_CAP_OP_MOD_GENERAL_DEVICE);
568
569query_ex:
570 kfree(set_ctx);
571 return err;
572}
573
574static int set_hca_ctrl(struct mlx5_core_dev *dev)
575{
576 struct mlx5_reg_host_endianness he_in;
577 struct mlx5_reg_host_endianness he_out;
578 int err;
579
580 if (!mlx5_core_is_pf(dev))
581 return 0;
582
583 memset(&he_in, 0, sizeof(he_in));
584 he_in.he = MLX5_SET_HOST_ENDIANNESS;
585 err = mlx5_core_access_reg(dev, &he_in, sizeof(he_in),
586 &he_out, sizeof(he_out),
587 MLX5_REG_HOST_ENDIANNESS, 0, 1);
588 return err;
589}
590
591static int mlx5_core_set_hca_defaults(struct mlx5_core_dev *dev)
592{
593 int ret = 0;
594
595
596 if (MLX5_CAP_GEN(dev, port_type) == MLX5_CAP_PORT_TYPE_ETH)
597 ret = mlx5_nic_vport_update_local_lb(dev, false);
598
599 return ret;
600}
601
602int mlx5_core_enable_hca(struct mlx5_core_dev *dev, u16 func_id)
603{
604 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {0};
605 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {0};
606
607 MLX5_SET(enable_hca_in, in, opcode, MLX5_CMD_OP_ENABLE_HCA);
608 MLX5_SET(enable_hca_in, in, function_id, func_id);
609 return mlx5_cmd_exec(dev, &in, sizeof(in), &out, sizeof(out));
610}
611
612int mlx5_core_disable_hca(struct mlx5_core_dev *dev, u16 func_id)
613{
614 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {0};
615 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {0};
616
617 MLX5_SET(disable_hca_in, in, opcode, MLX5_CMD_OP_DISABLE_HCA);
618 MLX5_SET(disable_hca_in, in, function_id, func_id);
619 return mlx5_cmd_exec(dev, in, sizeof(in), out, sizeof(out));
620}
621
622u64 mlx5_read_internal_timer(struct mlx5_core_dev *dev)
623{
624 u32 timer_h, timer_h1, timer_l;
625
626 timer_h = ioread32be(&dev->iseg->internal_timer_h);
627 timer_l = ioread32be(&dev->iseg->internal_timer_l);
628 timer_h1 = ioread32be(&dev->iseg->internal_timer_h);
629 if (timer_h != timer_h1)
630 timer_l = ioread32be(&dev->iseg->internal_timer_l);
631
632 return (u64)timer_l | (u64)timer_h1 << 32;
633}
634
635static int mlx5_irq_set_affinity_hint(struct mlx5_core_dev *mdev, int i)
636{
637 struct mlx5_priv *priv = &mdev->priv;
638 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
639
640 if (!zalloc_cpumask_var(&priv->irq_info[i].mask, GFP_KERNEL)) {
641 mlx5_core_warn(mdev, "zalloc_cpumask_var failed");
642 return -ENOMEM;
643 }
644
645 cpumask_set_cpu(cpumask_local_spread(i, priv->numa_node),
646 priv->irq_info[i].mask);
647
648 if (IS_ENABLED(CONFIG_SMP) &&
649 irq_set_affinity_hint(irq, priv->irq_info[i].mask))
650 mlx5_core_warn(mdev, "irq_set_affinity_hint failed, irq 0x%.4x", irq);
651
652 return 0;
653}
654
655static void mlx5_irq_clear_affinity_hint(struct mlx5_core_dev *mdev, int i)
656{
657 struct mlx5_priv *priv = &mdev->priv;
658 int irq = pci_irq_vector(mdev->pdev, MLX5_EQ_VEC_COMP_BASE + i);
659
660 irq_set_affinity_hint(irq, NULL);
661 free_cpumask_var(priv->irq_info[i].mask);
662}
663
664static int mlx5_irq_set_affinity_hints(struct mlx5_core_dev *mdev)
665{
666 int err;
667 int i;
668
669 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++) {
670 err = mlx5_irq_set_affinity_hint(mdev, i);
671 if (err)
672 goto err_out;
673 }
674
675 return 0;
676
677err_out:
678 for (i--; i >= 0; i--)
679 mlx5_irq_clear_affinity_hint(mdev, i);
680
681 return err;
682}
683
684static void mlx5_irq_clear_affinity_hints(struct mlx5_core_dev *mdev)
685{
686 int i;
687
688 for (i = 0; i < mdev->priv.eq_table.num_comp_vectors; i++)
689 mlx5_irq_clear_affinity_hint(mdev, i);
690}
691
692int mlx5_vector2eqn(struct mlx5_core_dev *dev, int vector, int *eqn,
693 unsigned int *irqn)
694{
695 struct mlx5_eq_table *table = &dev->priv.eq_table;
696 struct mlx5_eq *eq, *n;
697 int err = -ENOENT;
698
699 spin_lock(&table->lock);
700 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
701 if (eq->index == vector) {
702 *eqn = eq->eqn;
703 *irqn = eq->irqn;
704 err = 0;
705 break;
706 }
707 }
708 spin_unlock(&table->lock);
709
710 return err;
711}
712EXPORT_SYMBOL(mlx5_vector2eqn);
713
714struct mlx5_eq *mlx5_eqn2eq(struct mlx5_core_dev *dev, int eqn)
715{
716 struct mlx5_eq_table *table = &dev->priv.eq_table;
717 struct mlx5_eq *eq;
718
719 spin_lock(&table->lock);
720 list_for_each_entry(eq, &table->comp_eqs_list, list)
721 if (eq->eqn == eqn) {
722 spin_unlock(&table->lock);
723 return eq;
724 }
725
726 spin_unlock(&table->lock);
727
728 return ERR_PTR(-ENOENT);
729}
730
731static void free_comp_eqs(struct mlx5_core_dev *dev)
732{
733 struct mlx5_eq_table *table = &dev->priv.eq_table;
734 struct mlx5_eq *eq, *n;
735
736#ifdef CONFIG_RFS_ACCEL
737 if (dev->rmap) {
738 free_irq_cpu_rmap(dev->rmap);
739 dev->rmap = NULL;
740 }
741#endif
742 spin_lock(&table->lock);
743 list_for_each_entry_safe(eq, n, &table->comp_eqs_list, list) {
744 list_del(&eq->list);
745 spin_unlock(&table->lock);
746 if (mlx5_destroy_unmap_eq(dev, eq))
747 mlx5_core_warn(dev, "failed to destroy EQ 0x%x\n",
748 eq->eqn);
749 kfree(eq);
750 spin_lock(&table->lock);
751 }
752 spin_unlock(&table->lock);
753}
754
755static int alloc_comp_eqs(struct mlx5_core_dev *dev)
756{
757 struct mlx5_eq_table *table = &dev->priv.eq_table;
758 char name[MLX5_MAX_IRQ_NAME];
759 struct mlx5_eq *eq;
760 int ncomp_vec;
761 int nent;
762 int err;
763 int i;
764
765 INIT_LIST_HEAD(&table->comp_eqs_list);
766 ncomp_vec = table->num_comp_vectors;
767 nent = MLX5_COMP_EQ_SIZE;
768#ifdef CONFIG_RFS_ACCEL
769 dev->rmap = alloc_irq_cpu_rmap(ncomp_vec);
770 if (!dev->rmap)
771 return -ENOMEM;
772#endif
773 for (i = 0; i < ncomp_vec; i++) {
774 eq = kzalloc(sizeof(*eq), GFP_KERNEL);
775 if (!eq) {
776 err = -ENOMEM;
777 goto clean;
778 }
779
780#ifdef CONFIG_RFS_ACCEL
781 irq_cpu_rmap_add(dev->rmap, pci_irq_vector(dev->pdev,
782 MLX5_EQ_VEC_COMP_BASE + i));
783#endif
784 snprintf(name, MLX5_MAX_IRQ_NAME, "mlx5_comp%d", i);
785 err = mlx5_create_map_eq(dev, eq,
786 i + MLX5_EQ_VEC_COMP_BASE, nent, 0,
787 name, MLX5_EQ_TYPE_COMP);
788 if (err) {
789 kfree(eq);
790 goto clean;
791 }
792 mlx5_core_dbg(dev, "allocated completion EQN %d\n", eq->eqn);
793 eq->index = i;
794 spin_lock(&table->lock);
795 list_add_tail(&eq->list, &table->comp_eqs_list);
796 spin_unlock(&table->lock);
797 }
798
799 return 0;
800
801clean:
802 free_comp_eqs(dev);
803 return err;
804}
805
806static int mlx5_core_set_issi(struct mlx5_core_dev *dev)
807{
808 u32 query_in[MLX5_ST_SZ_DW(query_issi_in)] = {0};
809 u32 query_out[MLX5_ST_SZ_DW(query_issi_out)] = {0};
810 u32 sup_issi;
811 int err;
812
813 MLX5_SET(query_issi_in, query_in, opcode, MLX5_CMD_OP_QUERY_ISSI);
814 err = mlx5_cmd_exec(dev, query_in, sizeof(query_in),
815 query_out, sizeof(query_out));
816 if (err) {
817 u32 syndrome;
818 u8 status;
819
820 mlx5_cmd_mbox_status(query_out, &status, &syndrome);
821 if (!status || syndrome == MLX5_DRIVER_SYND) {
822 mlx5_core_err(dev, "Failed to query ISSI err(%d) status(%d) synd(%d)\n",
823 err, status, syndrome);
824 return err;
825 }
826
827 mlx5_core_warn(dev, "Query ISSI is not supported by FW, ISSI is 0\n");
828 dev->issi = 0;
829 return 0;
830 }
831
832 sup_issi = MLX5_GET(query_issi_out, query_out, supported_issi_dw0);
833
834 if (sup_issi & (1 << 1)) {
835 u32 set_in[MLX5_ST_SZ_DW(set_issi_in)] = {0};
836 u32 set_out[MLX5_ST_SZ_DW(set_issi_out)] = {0};
837
838 MLX5_SET(set_issi_in, set_in, opcode, MLX5_CMD_OP_SET_ISSI);
839 MLX5_SET(set_issi_in, set_in, current_issi, 1);
840 err = mlx5_cmd_exec(dev, set_in, sizeof(set_in),
841 set_out, sizeof(set_out));
842 if (err) {
843 mlx5_core_err(dev, "Failed to set ISSI to 1 err(%d)\n",
844 err);
845 return err;
846 }
847
848 dev->issi = 1;
849
850 return 0;
851 } else if (sup_issi & (1 << 0) || !sup_issi) {
852 return 0;
853 }
854
855 return -EOPNOTSUPP;
856}
857
858static int mlx5_pci_init(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
859{
860 struct pci_dev *pdev = dev->pdev;
861 int err = 0;
862
863 pci_set_drvdata(dev->pdev, dev);
864 strncpy(priv->name, dev_name(&pdev->dev), MLX5_MAX_NAME_LEN);
865 priv->name[MLX5_MAX_NAME_LEN - 1] = 0;
866
867 mutex_init(&priv->pgdir_mutex);
868 INIT_LIST_HEAD(&priv->pgdir_list);
869 spin_lock_init(&priv->mkey_lock);
870
871 mutex_init(&priv->alloc_mutex);
872
873 priv->numa_node = dev_to_node(&dev->pdev->dev);
874
875 priv->dbg_root = debugfs_create_dir(dev_name(&pdev->dev), mlx5_debugfs_root);
876 if (!priv->dbg_root)
877 return -ENOMEM;
878
879 err = mlx5_pci_enable_device(dev);
880 if (err) {
881 dev_err(&pdev->dev, "Cannot enable PCI device, aborting\n");
882 goto err_dbg;
883 }
884
885 err = request_bar(pdev);
886 if (err) {
887 dev_err(&pdev->dev, "error requesting BARs, aborting\n");
888 goto err_disable;
889 }
890
891 pci_set_master(pdev);
892
893 err = set_dma_caps(pdev);
894 if (err) {
895 dev_err(&pdev->dev, "Failed setting DMA capabilities mask, aborting\n");
896 goto err_clr_master;
897 }
898
899 dev->iseg_base = pci_resource_start(dev->pdev, 0);
900 dev->iseg = ioremap(dev->iseg_base, sizeof(*dev->iseg));
901 if (!dev->iseg) {
902 err = -ENOMEM;
903 dev_err(&pdev->dev, "Failed mapping initialization segment, aborting\n");
904 goto err_clr_master;
905 }
906
907 return 0;
908
909err_clr_master:
910 pci_clear_master(dev->pdev);
911 release_bar(dev->pdev);
912err_disable:
913 mlx5_pci_disable_device(dev);
914
915err_dbg:
916 debugfs_remove(priv->dbg_root);
917 return err;
918}
919
920static void mlx5_pci_close(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
921{
922 iounmap(dev->iseg);
923 pci_clear_master(dev->pdev);
924 release_bar(dev->pdev);
925 mlx5_pci_disable_device(dev);
926 debugfs_remove(priv->dbg_root);
927}
928
929static int mlx5_init_once(struct mlx5_core_dev *dev, struct mlx5_priv *priv)
930{
931 struct pci_dev *pdev = dev->pdev;
932 int err;
933
934 err = mlx5_query_board_id(dev);
935 if (err) {
936 dev_err(&pdev->dev, "query board id failed\n");
937 goto out;
938 }
939
940 err = mlx5_eq_init(dev);
941 if (err) {
942 dev_err(&pdev->dev, "failed to initialize eq\n");
943 goto out;
944 }
945
946 err = mlx5_cq_debugfs_init(dev);
947 if (err) {
948 dev_err(&pdev->dev, "failed to initialize cq debugfs\n");
949 goto err_eq_cleanup;
950 }
951
952 mlx5_init_qp_table(dev);
953
954 mlx5_init_srq_table(dev);
955
956 mlx5_init_mkey_table(dev);
957
958 mlx5_init_reserved_gids(dev);
959
960 mlx5_init_clock(dev);
961
962 err = mlx5_init_rl_table(dev);
963 if (err) {
964 dev_err(&pdev->dev, "Failed to init rate limiting\n");
965 goto err_tables_cleanup;
966 }
967
968 err = mlx5_mpfs_init(dev);
969 if (err) {
970 dev_err(&pdev->dev, "Failed to init l2 table %d\n", err);
971 goto err_rl_cleanup;
972 }
973
974 err = mlx5_eswitch_init(dev);
975 if (err) {
976 dev_err(&pdev->dev, "Failed to init eswitch %d\n", err);
977 goto err_mpfs_cleanup;
978 }
979
980 err = mlx5_sriov_init(dev);
981 if (err) {
982 dev_err(&pdev->dev, "Failed to init sriov %d\n", err);
983 goto err_eswitch_cleanup;
984 }
985
986 err = mlx5_fpga_init(dev);
987 if (err) {
988 dev_err(&pdev->dev, "Failed to init fpga device %d\n", err);
989 goto err_sriov_cleanup;
990 }
991
992 return 0;
993
994err_sriov_cleanup:
995 mlx5_sriov_cleanup(dev);
996err_eswitch_cleanup:
997 mlx5_eswitch_cleanup(dev->priv.eswitch);
998err_mpfs_cleanup:
999 mlx5_mpfs_cleanup(dev);
1000err_rl_cleanup:
1001 mlx5_cleanup_rl_table(dev);
1002err_tables_cleanup:
1003 mlx5_cleanup_mkey_table(dev);
1004 mlx5_cleanup_srq_table(dev);
1005 mlx5_cleanup_qp_table(dev);
1006 mlx5_cq_debugfs_cleanup(dev);
1007
1008err_eq_cleanup:
1009 mlx5_eq_cleanup(dev);
1010
1011out:
1012 return err;
1013}
1014
1015static void mlx5_cleanup_once(struct mlx5_core_dev *dev)
1016{
1017 mlx5_fpga_cleanup(dev);
1018 mlx5_sriov_cleanup(dev);
1019 mlx5_eswitch_cleanup(dev->priv.eswitch);
1020 mlx5_mpfs_cleanup(dev);
1021 mlx5_cleanup_rl_table(dev);
1022 mlx5_cleanup_clock(dev);
1023 mlx5_cleanup_reserved_gids(dev);
1024 mlx5_cleanup_mkey_table(dev);
1025 mlx5_cleanup_srq_table(dev);
1026 mlx5_cleanup_qp_table(dev);
1027 mlx5_cq_debugfs_cleanup(dev);
1028 mlx5_eq_cleanup(dev);
1029}
1030
1031static int mlx5_load_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1032 bool boot)
1033{
1034 struct pci_dev *pdev = dev->pdev;
1035 int err;
1036
1037 mutex_lock(&dev->intf_state_mutex);
1038 if (test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1039 dev_warn(&dev->pdev->dev, "%s: interface is up, NOP\n",
1040 __func__);
1041 goto out;
1042 }
1043
1044 dev_info(&pdev->dev, "firmware version: %d.%d.%d\n", fw_rev_maj(dev),
1045 fw_rev_min(dev), fw_rev_sub(dev));
1046
1047
1048 if (mlx5_core_is_pf(dev))
1049 pcie_print_link_status(dev->pdev);
1050
1051
1052
1053
1054 dev->state = MLX5_DEVICE_STATE_UP;
1055
1056
1057
1058 err = wait_fw_init(dev, FW_PRE_INIT_TIMEOUT_MILI);
1059 if (err) {
1060 dev_err(&dev->pdev->dev, "Firmware over %d MS in pre-initializing state, aborting\n",
1061 FW_PRE_INIT_TIMEOUT_MILI);
1062 goto out_err;
1063 }
1064
1065 err = mlx5_cmd_init(dev);
1066 if (err) {
1067 dev_err(&pdev->dev, "Failed initializing command interface, aborting\n");
1068 goto out_err;
1069 }
1070
1071 err = wait_fw_init(dev, FW_INIT_TIMEOUT_MILI);
1072 if (err) {
1073 dev_err(&dev->pdev->dev, "Firmware over %d MS in initializing state, aborting\n",
1074 FW_INIT_TIMEOUT_MILI);
1075 goto err_cmd_cleanup;
1076 }
1077
1078 err = mlx5_core_enable_hca(dev, 0);
1079 if (err) {
1080 dev_err(&pdev->dev, "enable hca failed\n");
1081 goto err_cmd_cleanup;
1082 }
1083
1084 err = mlx5_core_set_issi(dev);
1085 if (err) {
1086 dev_err(&pdev->dev, "failed to set issi\n");
1087 goto err_disable_hca;
1088 }
1089
1090 err = mlx5_satisfy_startup_pages(dev, 1);
1091 if (err) {
1092 dev_err(&pdev->dev, "failed to allocate boot pages\n");
1093 goto err_disable_hca;
1094 }
1095
1096 err = set_hca_ctrl(dev);
1097 if (err) {
1098 dev_err(&pdev->dev, "set_hca_ctrl failed\n");
1099 goto reclaim_boot_pages;
1100 }
1101
1102 err = handle_hca_cap(dev);
1103 if (err) {
1104 dev_err(&pdev->dev, "handle_hca_cap failed\n");
1105 goto reclaim_boot_pages;
1106 }
1107
1108 err = handle_hca_cap_atomic(dev);
1109 if (err) {
1110 dev_err(&pdev->dev, "handle_hca_cap_atomic failed\n");
1111 goto reclaim_boot_pages;
1112 }
1113
1114 err = mlx5_satisfy_startup_pages(dev, 0);
1115 if (err) {
1116 dev_err(&pdev->dev, "failed to allocate init pages\n");
1117 goto reclaim_boot_pages;
1118 }
1119
1120 err = mlx5_pagealloc_start(dev);
1121 if (err) {
1122 dev_err(&pdev->dev, "mlx5_pagealloc_start failed\n");
1123 goto reclaim_boot_pages;
1124 }
1125
1126 err = mlx5_cmd_init_hca(dev, sw_owner_id);
1127 if (err) {
1128 dev_err(&pdev->dev, "init hca failed\n");
1129 goto err_pagealloc_stop;
1130 }
1131
1132 mlx5_set_driver_version(dev);
1133
1134 mlx5_start_health_poll(dev);
1135
1136 err = mlx5_query_hca_caps(dev);
1137 if (err) {
1138 dev_err(&pdev->dev, "query hca failed\n");
1139 goto err_stop_poll;
1140 }
1141
1142 if (boot) {
1143 err = mlx5_init_once(dev, priv);
1144 if (err) {
1145 dev_err(&pdev->dev, "sw objs init failed\n");
1146 goto err_stop_poll;
1147 }
1148 }
1149
1150 err = mlx5_alloc_irq_vectors(dev);
1151 if (err) {
1152 dev_err(&pdev->dev, "alloc irq vectors failed\n");
1153 goto err_cleanup_once;
1154 }
1155
1156 dev->priv.uar = mlx5_get_uars_page(dev);
1157 if (IS_ERR(dev->priv.uar)) {
1158 dev_err(&pdev->dev, "Failed allocating uar, aborting\n");
1159 err = PTR_ERR(dev->priv.uar);
1160 goto err_disable_msix;
1161 }
1162
1163 err = mlx5_start_eqs(dev);
1164 if (err) {
1165 dev_err(&pdev->dev, "Failed to start pages and async EQs\n");
1166 goto err_put_uars;
1167 }
1168
1169 err = alloc_comp_eqs(dev);
1170 if (err) {
1171 dev_err(&pdev->dev, "Failed to alloc completion EQs\n");
1172 goto err_stop_eqs;
1173 }
1174
1175 err = mlx5_irq_set_affinity_hints(dev);
1176 if (err) {
1177 dev_err(&pdev->dev, "Failed to alloc affinity hint cpumask\n");
1178 goto err_affinity_hints;
1179 }
1180
1181 err = mlx5_fpga_device_start(dev);
1182 if (err) {
1183 dev_err(&pdev->dev, "fpga device start failed %d\n", err);
1184 goto err_fpga_start;
1185 }
1186
1187 err = mlx5_accel_ipsec_init(dev);
1188 if (err) {
1189 dev_err(&pdev->dev, "IPSec device start failed %d\n", err);
1190 goto err_ipsec_start;
1191 }
1192
1193 err = mlx5_init_fs(dev);
1194 if (err) {
1195 dev_err(&pdev->dev, "Failed to init flow steering\n");
1196 goto err_fs;
1197 }
1198
1199 err = mlx5_core_set_hca_defaults(dev);
1200 if (err) {
1201 dev_err(&pdev->dev, "Failed to set hca defaults\n");
1202 goto err_fs;
1203 }
1204
1205 err = mlx5_sriov_attach(dev);
1206 if (err) {
1207 dev_err(&pdev->dev, "sriov init failed %d\n", err);
1208 goto err_sriov;
1209 }
1210
1211 if (mlx5_device_registered(dev)) {
1212 mlx5_attach_device(dev);
1213 } else {
1214 err = mlx5_register_device(dev);
1215 if (err) {
1216 dev_err(&pdev->dev, "mlx5_register_device failed %d\n", err);
1217 goto err_reg_dev;
1218 }
1219 }
1220
1221 set_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1222out:
1223 mutex_unlock(&dev->intf_state_mutex);
1224
1225 return 0;
1226
1227err_reg_dev:
1228 mlx5_sriov_detach(dev);
1229
1230err_sriov:
1231 mlx5_cleanup_fs(dev);
1232
1233err_fs:
1234 mlx5_accel_ipsec_cleanup(dev);
1235
1236err_ipsec_start:
1237 mlx5_fpga_device_stop(dev);
1238
1239err_fpga_start:
1240 mlx5_irq_clear_affinity_hints(dev);
1241
1242err_affinity_hints:
1243 free_comp_eqs(dev);
1244
1245err_stop_eqs:
1246 mlx5_stop_eqs(dev);
1247
1248err_put_uars:
1249 mlx5_put_uars_page(dev, priv->uar);
1250
1251err_disable_msix:
1252 mlx5_free_irq_vectors(dev);
1253
1254err_cleanup_once:
1255 if (boot)
1256 mlx5_cleanup_once(dev);
1257
1258err_stop_poll:
1259 mlx5_stop_health_poll(dev);
1260 if (mlx5_cmd_teardown_hca(dev)) {
1261 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1262 goto out_err;
1263 }
1264
1265err_pagealloc_stop:
1266 mlx5_pagealloc_stop(dev);
1267
1268reclaim_boot_pages:
1269 mlx5_reclaim_startup_pages(dev);
1270
1271err_disable_hca:
1272 mlx5_core_disable_hca(dev, 0);
1273
1274err_cmd_cleanup:
1275 mlx5_cmd_cleanup(dev);
1276
1277out_err:
1278 dev->state = MLX5_DEVICE_STATE_INTERNAL_ERROR;
1279 mutex_unlock(&dev->intf_state_mutex);
1280
1281 return err;
1282}
1283
1284static int mlx5_unload_one(struct mlx5_core_dev *dev, struct mlx5_priv *priv,
1285 bool cleanup)
1286{
1287 int err = 0;
1288
1289 if (cleanup)
1290 mlx5_drain_health_recovery(dev);
1291
1292 mutex_lock(&dev->intf_state_mutex);
1293 if (!test_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state)) {
1294 dev_warn(&dev->pdev->dev, "%s: interface is down, NOP\n",
1295 __func__);
1296 if (cleanup)
1297 mlx5_cleanup_once(dev);
1298 goto out;
1299 }
1300
1301 clear_bit(MLX5_INTERFACE_STATE_UP, &dev->intf_state);
1302
1303 if (mlx5_device_registered(dev))
1304 mlx5_detach_device(dev);
1305
1306 mlx5_sriov_detach(dev);
1307 mlx5_cleanup_fs(dev);
1308 mlx5_accel_ipsec_cleanup(dev);
1309 mlx5_fpga_device_stop(dev);
1310 mlx5_irq_clear_affinity_hints(dev);
1311 free_comp_eqs(dev);
1312 mlx5_stop_eqs(dev);
1313 mlx5_put_uars_page(dev, priv->uar);
1314 mlx5_free_irq_vectors(dev);
1315 if (cleanup)
1316 mlx5_cleanup_once(dev);
1317 mlx5_stop_health_poll(dev);
1318 err = mlx5_cmd_teardown_hca(dev);
1319 if (err) {
1320 dev_err(&dev->pdev->dev, "tear_down_hca failed, skip cleanup\n");
1321 goto out;
1322 }
1323 mlx5_pagealloc_stop(dev);
1324 mlx5_reclaim_startup_pages(dev);
1325 mlx5_core_disable_hca(dev, 0);
1326 mlx5_cmd_cleanup(dev);
1327
1328out:
1329 mutex_unlock(&dev->intf_state_mutex);
1330 return err;
1331}
1332
1333struct mlx5_core_event_handler {
1334 void (*event)(struct mlx5_core_dev *dev,
1335 enum mlx5_dev_event event,
1336 void *data);
1337};
1338
1339static const struct devlink_ops mlx5_devlink_ops = {
1340#ifdef CONFIG_MLX5_ESWITCH
1341 .eswitch_mode_set = mlx5_devlink_eswitch_mode_set,
1342 .eswitch_mode_get = mlx5_devlink_eswitch_mode_get,
1343 .eswitch_inline_mode_set = mlx5_devlink_eswitch_inline_mode_set,
1344 .eswitch_inline_mode_get = mlx5_devlink_eswitch_inline_mode_get,
1345 .eswitch_encap_mode_set = mlx5_devlink_eswitch_encap_mode_set,
1346 .eswitch_encap_mode_get = mlx5_devlink_eswitch_encap_mode_get,
1347#endif
1348};
1349
1350#define MLX5_IB_MOD "mlx5_ib"
1351static int init_one(struct pci_dev *pdev,
1352 const struct pci_device_id *id)
1353{
1354 struct mlx5_core_dev *dev;
1355 struct devlink *devlink;
1356 struct mlx5_priv *priv;
1357 int err;
1358
1359 devlink = devlink_alloc(&mlx5_devlink_ops, sizeof(*dev));
1360 if (!devlink) {
1361 dev_err(&pdev->dev, "kzalloc failed\n");
1362 return -ENOMEM;
1363 }
1364
1365 dev = devlink_priv(devlink);
1366 priv = &dev->priv;
1367 priv->pci_dev_data = id->driver_data;
1368
1369 pci_set_drvdata(pdev, dev);
1370
1371 dev->pdev = pdev;
1372 dev->event = mlx5_core_event;
1373 dev->profile = &profile[prof_sel];
1374
1375 INIT_LIST_HEAD(&priv->ctx_list);
1376 spin_lock_init(&priv->ctx_lock);
1377 mutex_init(&dev->pci_status_mutex);
1378 mutex_init(&dev->intf_state_mutex);
1379
1380 INIT_LIST_HEAD(&priv->waiting_events_list);
1381 priv->is_accum_events = false;
1382
1383#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1384 err = init_srcu_struct(&priv->pfault_srcu);
1385 if (err) {
1386 dev_err(&pdev->dev, "init_srcu_struct failed with error code %d\n",
1387 err);
1388 goto clean_dev;
1389 }
1390#endif
1391 mutex_init(&priv->bfregs.reg_head.lock);
1392 mutex_init(&priv->bfregs.wc_head.lock);
1393 INIT_LIST_HEAD(&priv->bfregs.reg_head.list);
1394 INIT_LIST_HEAD(&priv->bfregs.wc_head.list);
1395
1396 err = mlx5_pci_init(dev, priv);
1397 if (err) {
1398 dev_err(&pdev->dev, "mlx5_pci_init failed with error code %d\n", err);
1399 goto clean_srcu;
1400 }
1401
1402 err = mlx5_health_init(dev);
1403 if (err) {
1404 dev_err(&pdev->dev, "mlx5_health_init failed with error code %d\n", err);
1405 goto close_pci;
1406 }
1407
1408 mlx5_pagealloc_init(dev);
1409
1410 err = mlx5_load_one(dev, priv, true);
1411 if (err) {
1412 dev_err(&pdev->dev, "mlx5_load_one failed with error code %d\n", err);
1413 goto clean_health;
1414 }
1415
1416 request_module_nowait(MLX5_IB_MOD);
1417
1418 err = devlink_register(devlink, &pdev->dev);
1419 if (err)
1420 goto clean_load;
1421
1422 pci_save_state(pdev);
1423 return 0;
1424
1425clean_load:
1426 mlx5_unload_one(dev, priv, true);
1427clean_health:
1428 mlx5_pagealloc_cleanup(dev);
1429 mlx5_health_cleanup(dev);
1430close_pci:
1431 mlx5_pci_close(dev, priv);
1432clean_srcu:
1433#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1434 cleanup_srcu_struct(&priv->pfault_srcu);
1435clean_dev:
1436#endif
1437 devlink_free(devlink);
1438
1439 return err;
1440}
1441
1442static void remove_one(struct pci_dev *pdev)
1443{
1444 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1445 struct devlink *devlink = priv_to_devlink(dev);
1446 struct mlx5_priv *priv = &dev->priv;
1447
1448 devlink_unregister(devlink);
1449 mlx5_unregister_device(dev);
1450
1451 if (mlx5_unload_one(dev, priv, true)) {
1452 dev_err(&dev->pdev->dev, "mlx5_unload_one failed\n");
1453 mlx5_health_cleanup(dev);
1454 return;
1455 }
1456
1457 mlx5_pagealloc_cleanup(dev);
1458 mlx5_health_cleanup(dev);
1459 mlx5_pci_close(dev, priv);
1460#ifdef CONFIG_INFINIBAND_ON_DEMAND_PAGING
1461 cleanup_srcu_struct(&priv->pfault_srcu);
1462#endif
1463 devlink_free(devlink);
1464}
1465
1466static pci_ers_result_t mlx5_pci_err_detected(struct pci_dev *pdev,
1467 pci_channel_state_t state)
1468{
1469 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1470 struct mlx5_priv *priv = &dev->priv;
1471
1472 dev_info(&pdev->dev, "%s was called\n", __func__);
1473
1474 mlx5_enter_error_state(dev, false);
1475 mlx5_unload_one(dev, priv, false);
1476
1477 if (state) {
1478 mlx5_drain_health_wq(dev);
1479 mlx5_pci_disable_device(dev);
1480 }
1481
1482 return state == pci_channel_io_perm_failure ?
1483 PCI_ERS_RESULT_DISCONNECT : PCI_ERS_RESULT_NEED_RESET;
1484}
1485
1486
1487
1488
1489static int wait_vital(struct pci_dev *pdev)
1490{
1491 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1492 struct mlx5_core_health *health = &dev->priv.health;
1493 const int niter = 100;
1494 u32 last_count = 0;
1495 u32 count;
1496 int i;
1497
1498 for (i = 0; i < niter; i++) {
1499 count = ioread32be(health->health_counter);
1500 if (count && count != 0xffffffff) {
1501 if (last_count && last_count != count) {
1502 dev_info(&pdev->dev, "Counter value 0x%x after %d iterations\n", count, i);
1503 return 0;
1504 }
1505 last_count = count;
1506 }
1507 msleep(50);
1508 }
1509
1510 return -ETIMEDOUT;
1511}
1512
1513static pci_ers_result_t mlx5_pci_slot_reset(struct pci_dev *pdev)
1514{
1515 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1516 int err;
1517
1518 dev_info(&pdev->dev, "%s was called\n", __func__);
1519
1520 err = mlx5_pci_enable_device(dev);
1521 if (err) {
1522 dev_err(&pdev->dev, "%s: mlx5_pci_enable_device failed with error code: %d\n"
1523 , __func__, err);
1524 return PCI_ERS_RESULT_DISCONNECT;
1525 }
1526
1527 pci_set_master(pdev);
1528 pci_restore_state(pdev);
1529 pci_save_state(pdev);
1530
1531 if (wait_vital(pdev)) {
1532 dev_err(&pdev->dev, "%s: wait_vital timed out\n", __func__);
1533 return PCI_ERS_RESULT_DISCONNECT;
1534 }
1535
1536 return PCI_ERS_RESULT_RECOVERED;
1537}
1538
1539static void mlx5_pci_resume(struct pci_dev *pdev)
1540{
1541 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1542 struct mlx5_priv *priv = &dev->priv;
1543 int err;
1544
1545 dev_info(&pdev->dev, "%s was called\n", __func__);
1546
1547 err = mlx5_load_one(dev, priv, false);
1548 if (err)
1549 dev_err(&pdev->dev, "%s: mlx5_load_one failed with error code: %d\n"
1550 , __func__, err);
1551 else
1552 dev_info(&pdev->dev, "%s: device recovered\n", __func__);
1553}
1554
1555static const struct pci_error_handlers mlx5_err_handler = {
1556 .error_detected = mlx5_pci_err_detected,
1557 .slot_reset = mlx5_pci_slot_reset,
1558 .resume = mlx5_pci_resume
1559};
1560
1561static int mlx5_try_fast_unload(struct mlx5_core_dev *dev)
1562{
1563 int ret;
1564
1565 if (!MLX5_CAP_GEN(dev, force_teardown)) {
1566 mlx5_core_dbg(dev, "force teardown is not supported in the firmware\n");
1567 return -EOPNOTSUPP;
1568 }
1569
1570 if (dev->state == MLX5_DEVICE_STATE_INTERNAL_ERROR) {
1571 mlx5_core_dbg(dev, "Device in internal error state, giving up\n");
1572 return -EAGAIN;
1573 }
1574
1575
1576
1577
1578 mlx5_drain_health_wq(dev);
1579 mlx5_stop_health_poll(dev);
1580
1581 ret = mlx5_cmd_force_teardown_hca(dev);
1582 if (ret) {
1583 mlx5_core_dbg(dev, "Firmware couldn't do fast unload error: %d\n", ret);
1584 mlx5_start_health_poll(dev);
1585 return ret;
1586 }
1587
1588 mlx5_enter_error_state(dev, true);
1589
1590
1591
1592
1593
1594
1595 mlx5_irq_clear_affinity_hints(dev);
1596 mlx5_core_eq_free_irqs(dev);
1597
1598 return 0;
1599}
1600
1601static void shutdown(struct pci_dev *pdev)
1602{
1603 struct mlx5_core_dev *dev = pci_get_drvdata(pdev);
1604 struct mlx5_priv *priv = &dev->priv;
1605 int err;
1606
1607 dev_info(&pdev->dev, "Shutdown was called\n");
1608 err = mlx5_try_fast_unload(dev);
1609 if (err)
1610 mlx5_unload_one(dev, priv, false);
1611 mlx5_pci_disable_device(dev);
1612}
1613
1614static const struct pci_device_id mlx5_core_pci_table[] = {
1615 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTIB) },
1616 { PCI_VDEVICE(MELLANOX, 0x1012), MLX5_PCI_DEV_IS_VF},
1617 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4) },
1618 { PCI_VDEVICE(MELLANOX, 0x1014), MLX5_PCI_DEV_IS_VF},
1619 { PCI_VDEVICE(MELLANOX, PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX) },
1620 { PCI_VDEVICE(MELLANOX, 0x1016), MLX5_PCI_DEV_IS_VF},
1621 { PCI_VDEVICE(MELLANOX, 0x1017) },
1622 { PCI_VDEVICE(MELLANOX, 0x1018), MLX5_PCI_DEV_IS_VF},
1623 { PCI_VDEVICE(MELLANOX, 0x1019) },
1624 { PCI_VDEVICE(MELLANOX, 0x101a), MLX5_PCI_DEV_IS_VF},
1625 { PCI_VDEVICE(MELLANOX, 0x101b) },
1626 { PCI_VDEVICE(MELLANOX, 0x101c), MLX5_PCI_DEV_IS_VF},
1627 { PCI_VDEVICE(MELLANOX, 0xa2d2) },
1628 { PCI_VDEVICE(MELLANOX, 0xa2d3), MLX5_PCI_DEV_IS_VF},
1629 { 0, }
1630};
1631
1632MODULE_DEVICE_TABLE(pci, mlx5_core_pci_table);
1633
1634void mlx5_disable_device(struct mlx5_core_dev *dev)
1635{
1636 mlx5_pci_err_detected(dev->pdev, 0);
1637}
1638
1639void mlx5_recover_device(struct mlx5_core_dev *dev)
1640{
1641 mlx5_pci_disable_device(dev);
1642 if (mlx5_pci_slot_reset(dev->pdev) == PCI_ERS_RESULT_RECOVERED)
1643 mlx5_pci_resume(dev->pdev);
1644}
1645
1646static struct pci_driver mlx5_core_driver = {
1647 .name = DRIVER_NAME,
1648 .id_table = mlx5_core_pci_table,
1649 .probe = init_one,
1650 .remove = remove_one,
1651 .shutdown = shutdown,
1652 .err_handler = &mlx5_err_handler,
1653 .sriov_configure = mlx5_core_sriov_configure,
1654};
1655
1656static void mlx5_core_verify_params(void)
1657{
1658 if (prof_sel >= ARRAY_SIZE(profile)) {
1659 pr_warn("mlx5_core: WARNING: Invalid module parameter prof_sel %d, valid range 0-%zu, changing back to default(%d)\n",
1660 prof_sel,
1661 ARRAY_SIZE(profile) - 1,
1662 MLX5_DEFAULT_PROF);
1663 prof_sel = MLX5_DEFAULT_PROF;
1664 }
1665}
1666
1667static int __init init(void)
1668{
1669 int err;
1670
1671 get_random_bytes(&sw_owner_id, sizeof(sw_owner_id));
1672
1673 mlx5_core_verify_params();
1674 mlx5_fpga_ipsec_build_fs_cmds();
1675 mlx5_register_debugfs();
1676
1677 err = pci_register_driver(&mlx5_core_driver);
1678 if (err)
1679 goto err_debug;
1680
1681#ifdef CONFIG_MLX5_CORE_EN
1682 mlx5e_init();
1683#endif
1684
1685 return 0;
1686
1687err_debug:
1688 mlx5_unregister_debugfs();
1689 return err;
1690}
1691
1692static void __exit cleanup(void)
1693{
1694#ifdef CONFIG_MLX5_CORE_EN
1695 mlx5e_cleanup();
1696#endif
1697 pci_unregister_driver(&mlx5_core_driver);
1698 mlx5_unregister_debugfs();
1699}
1700
1701module_init(init);
1702module_exit(cleanup);
1703
