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39#ifndef _MLXSW_REG_H
40#define _MLXSW_REG_H
41
42#include <linux/string.h>
43#include <linux/bitops.h>
44#include <linux/if_vlan.h>
45
46#include "item.h"
47#include "port.h"
48
49struct mlxsw_reg_info {
50 u16 id;
51 u16 len;
52 const char *name;
53};
54
55#define MLXSW_REG_DEFINE(_name, _id, _len) \
56static const struct mlxsw_reg_info mlxsw_reg_##_name = { \
57 .id = _id, \
58 .len = _len, \
59 .name = #_name, \
60}
61
62#define MLXSW_REG(type) (&mlxsw_reg_##type)
63#define MLXSW_REG_LEN(type) MLXSW_REG(type)->len
64#define MLXSW_REG_ZERO(type, payload) memset(payload, 0, MLXSW_REG(type)->len)
65
66
67
68
69
70#define MLXSW_REG_SGCR_ID 0x2000
71#define MLXSW_REG_SGCR_LEN 0x10
72
73MLXSW_REG_DEFINE(sgcr, MLXSW_REG_SGCR_ID, MLXSW_REG_SGCR_LEN);
74
75
76
77
78
79
80
81MLXSW_ITEM32(reg, sgcr, llb, 0x04, 0, 1);
82
83static inline void mlxsw_reg_sgcr_pack(char *payload, bool llb)
84{
85 MLXSW_REG_ZERO(sgcr, payload);
86 mlxsw_reg_sgcr_llb_set(payload, !!llb);
87}
88
89
90
91
92
93#define MLXSW_REG_SPAD_ID 0x2002
94#define MLXSW_REG_SPAD_LEN 0x10
95
96MLXSW_REG_DEFINE(spad, MLXSW_REG_SPAD_ID, MLXSW_REG_SPAD_LEN);
97
98
99
100
101
102
103
104MLXSW_ITEM_BUF(reg, spad, base_mac, 0x02, 6);
105
106
107
108
109
110
111
112#define MLXSW_REG_SMID_ID 0x2007
113#define MLXSW_REG_SMID_LEN 0x240
114
115MLXSW_REG_DEFINE(smid, MLXSW_REG_SMID_ID, MLXSW_REG_SMID_LEN);
116
117
118
119
120
121MLXSW_ITEM32(reg, smid, swid, 0x00, 24, 8);
122
123
124
125
126
127
128MLXSW_ITEM32(reg, smid, mid, 0x00, 0, 16);
129
130
131
132
133
134MLXSW_ITEM_BIT_ARRAY(reg, smid, port, 0x20, 0x20, 1);
135
136
137
138
139
140MLXSW_ITEM_BIT_ARRAY(reg, smid, port_mask, 0x220, 0x20, 1);
141
142static inline void mlxsw_reg_smid_pack(char *payload, u16 mid,
143 u8 port, bool set)
144{
145 MLXSW_REG_ZERO(smid, payload);
146 mlxsw_reg_smid_swid_set(payload, 0);
147 mlxsw_reg_smid_mid_set(payload, mid);
148 mlxsw_reg_smid_port_set(payload, port, set);
149 mlxsw_reg_smid_port_mask_set(payload, port, 1);
150}
151
152
153
154
155
156#define MLXSW_REG_SSPR_ID 0x2008
157#define MLXSW_REG_SSPR_LEN 0x8
158
159MLXSW_REG_DEFINE(sspr, MLXSW_REG_SSPR_ID, MLXSW_REG_SSPR_LEN);
160
161
162
163
164
165
166
167
168
169
170
171MLXSW_ITEM32(reg, sspr, m, 0x00, 31, 1);
172
173
174
175
176
177
178MLXSW_ITEM32(reg, sspr, local_port, 0x00, 16, 8);
179
180
181
182
183
184
185
186MLXSW_ITEM32(reg, sspr, sub_port, 0x00, 8, 8);
187
188
189
190
191
192
193
194
195
196MLXSW_ITEM32(reg, sspr, system_port, 0x04, 0, 16);
197
198static inline void mlxsw_reg_sspr_pack(char *payload, u8 local_port)
199{
200 MLXSW_REG_ZERO(sspr, payload);
201 mlxsw_reg_sspr_m_set(payload, 1);
202 mlxsw_reg_sspr_local_port_set(payload, local_port);
203 mlxsw_reg_sspr_sub_port_set(payload, 0);
204 mlxsw_reg_sspr_system_port_set(payload, local_port);
205}
206
207
208
209
210
211
212#define MLXSW_REG_SFDAT_ID 0x2009
213#define MLXSW_REG_SFDAT_LEN 0x8
214
215MLXSW_REG_DEFINE(sfdat, MLXSW_REG_SFDAT_ID, MLXSW_REG_SFDAT_LEN);
216
217
218
219
220
221MLXSW_ITEM32(reg, sfdat, swid, 0x00, 24, 8);
222
223
224
225
226
227
228
229
230MLXSW_ITEM32(reg, sfdat, age_time, 0x04, 0, 20);
231
232static inline void mlxsw_reg_sfdat_pack(char *payload, u32 age_time)
233{
234 MLXSW_REG_ZERO(sfdat, payload);
235 mlxsw_reg_sfdat_swid_set(payload, 0);
236 mlxsw_reg_sfdat_age_time_set(payload, age_time);
237}
238
239
240
241
242
243
244
245
246#define MLXSW_REG_SFD_ID 0x200A
247#define MLXSW_REG_SFD_BASE_LEN 0x10
248#define MLXSW_REG_SFD_REC_LEN 0x10
249#define MLXSW_REG_SFD_REC_MAX_COUNT 64
250#define MLXSW_REG_SFD_LEN (MLXSW_REG_SFD_BASE_LEN + \
251 MLXSW_REG_SFD_REC_LEN * MLXSW_REG_SFD_REC_MAX_COUNT)
252
253MLXSW_REG_DEFINE(sfd, MLXSW_REG_SFD_ID, MLXSW_REG_SFD_LEN);
254
255
256
257
258
259MLXSW_ITEM32(reg, sfd, swid, 0x00, 24, 8);
260
261enum mlxsw_reg_sfd_op {
262
263 MLXSW_REG_SFD_OP_QUERY_DUMP = 0,
264
265 MLXSW_REG_SFD_OP_QUERY_QUERY = 1,
266
267 MLXSW_REG_SFD_OP_QUERY_QUERY_AND_CLEAR_ACTIVITY = 2,
268
269
270
271 MLXSW_REG_SFD_OP_WRITE_TEST = 0,
272
273
274
275
276 MLXSW_REG_SFD_OP_WRITE_EDIT = 1,
277
278
279
280
281
282 MLXSW_REG_SFD_OP_WRITE_REMOVE = 2,
283
284
285
286 MLXSW_REG_SFD_OP_WRITE_REMOVE_NOTIFICATION = 2,
287};
288
289
290
291
292
293MLXSW_ITEM32(reg, sfd, op, 0x04, 30, 2);
294
295
296
297
298
299
300
301
302MLXSW_ITEM32(reg, sfd, record_locator, 0x04, 0, 30);
303
304
305
306
307
308
309
310
311MLXSW_ITEM32(reg, sfd, num_rec, 0x08, 0, 8);
312
313static inline void mlxsw_reg_sfd_pack(char *payload, enum mlxsw_reg_sfd_op op,
314 u32 record_locator)
315{
316 MLXSW_REG_ZERO(sfd, payload);
317 mlxsw_reg_sfd_op_set(payload, op);
318 mlxsw_reg_sfd_record_locator_set(payload, record_locator);
319}
320
321
322
323
324
325MLXSW_ITEM32_INDEXED(reg, sfd, rec_swid, MLXSW_REG_SFD_BASE_LEN, 24, 8,
326 MLXSW_REG_SFD_REC_LEN, 0x00, false);
327
328enum mlxsw_reg_sfd_rec_type {
329 MLXSW_REG_SFD_REC_TYPE_UNICAST = 0x0,
330 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG = 0x1,
331 MLXSW_REG_SFD_REC_TYPE_MULTICAST = 0x2,
332};
333
334
335
336
337
338MLXSW_ITEM32_INDEXED(reg, sfd, rec_type, MLXSW_REG_SFD_BASE_LEN, 20, 4,
339 MLXSW_REG_SFD_REC_LEN, 0x00, false);
340
341enum mlxsw_reg_sfd_rec_policy {
342
343 MLXSW_REG_SFD_REC_POLICY_STATIC_ENTRY = 0,
344
345
346
347 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_MLAG = 1,
348
349 MLXSW_REG_SFD_REC_POLICY_DYNAMIC_ENTRY_INGRESS = 3,
350};
351
352
353
354
355
356MLXSW_ITEM32_INDEXED(reg, sfd, rec_policy, MLXSW_REG_SFD_BASE_LEN, 18, 2,
357 MLXSW_REG_SFD_REC_LEN, 0x00, false);
358
359
360
361
362
363
364
365MLXSW_ITEM32_INDEXED(reg, sfd, rec_a, MLXSW_REG_SFD_BASE_LEN, 16, 1,
366 MLXSW_REG_SFD_REC_LEN, 0x00, false);
367
368
369
370
371
372MLXSW_ITEM_BUF_INDEXED(reg, sfd, rec_mac, MLXSW_REG_SFD_BASE_LEN, 6,
373 MLXSW_REG_SFD_REC_LEN, 0x02);
374
375enum mlxsw_reg_sfd_rec_action {
376
377 MLXSW_REG_SFD_REC_ACTION_NOP = 0,
378
379 MLXSW_REG_SFD_REC_ACTION_MIRROR_TO_CPU = 1,
380
381 MLXSW_REG_SFD_REC_ACTION_TRAP = 2,
382
383 MLXSW_REG_SFD_REC_ACTION_FORWARD_IP_ROUTER = 3,
384 MLXSW_REG_SFD_REC_ACTION_DISCARD_ERROR = 15,
385};
386
387
388
389
390
391
392MLXSW_ITEM32_INDEXED(reg, sfd, rec_action, MLXSW_REG_SFD_BASE_LEN, 28, 4,
393 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
394
395
396
397
398
399
400
401MLXSW_ITEM32_INDEXED(reg, sfd, uc_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
402 MLXSW_REG_SFD_REC_LEN, 0x08, false);
403
404
405
406
407
408
409
410
411
412
413
414MLXSW_ITEM32_INDEXED(reg, sfd, uc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
415 MLXSW_REG_SFD_REC_LEN, 0x08, false);
416
417
418
419
420
421MLXSW_ITEM32_INDEXED(reg, sfd, uc_system_port, MLXSW_REG_SFD_BASE_LEN, 0, 16,
422 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
423
424static inline void mlxsw_reg_sfd_rec_pack(char *payload, int rec_index,
425 enum mlxsw_reg_sfd_rec_type rec_type,
426 const char *mac,
427 enum mlxsw_reg_sfd_rec_action action)
428{
429 u8 num_rec = mlxsw_reg_sfd_num_rec_get(payload);
430
431 if (rec_index >= num_rec)
432 mlxsw_reg_sfd_num_rec_set(payload, rec_index + 1);
433 mlxsw_reg_sfd_rec_swid_set(payload, rec_index, 0);
434 mlxsw_reg_sfd_rec_type_set(payload, rec_index, rec_type);
435 mlxsw_reg_sfd_rec_mac_memcpy_to(payload, rec_index, mac);
436 mlxsw_reg_sfd_rec_action_set(payload, rec_index, action);
437}
438
439static inline void mlxsw_reg_sfd_uc_pack(char *payload, int rec_index,
440 enum mlxsw_reg_sfd_rec_policy policy,
441 const char *mac, u16 fid_vid,
442 enum mlxsw_reg_sfd_rec_action action,
443 u8 local_port)
444{
445 mlxsw_reg_sfd_rec_pack(payload, rec_index,
446 MLXSW_REG_SFD_REC_TYPE_UNICAST, mac, action);
447 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
448 mlxsw_reg_sfd_uc_sub_port_set(payload, rec_index, 0);
449 mlxsw_reg_sfd_uc_fid_vid_set(payload, rec_index, fid_vid);
450 mlxsw_reg_sfd_uc_system_port_set(payload, rec_index, local_port);
451}
452
453static inline void mlxsw_reg_sfd_uc_unpack(char *payload, int rec_index,
454 char *mac, u16 *p_fid_vid,
455 u8 *p_local_port)
456{
457 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
458 *p_fid_vid = mlxsw_reg_sfd_uc_fid_vid_get(payload, rec_index);
459 *p_local_port = mlxsw_reg_sfd_uc_system_port_get(payload, rec_index);
460}
461
462
463
464
465
466
467MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_sub_port, MLXSW_REG_SFD_BASE_LEN, 16, 8,
468 MLXSW_REG_SFD_REC_LEN, 0x08, false);
469
470
471
472
473
474
475
476
477
478
479
480MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
481 MLXSW_REG_SFD_REC_LEN, 0x08, false);
482
483
484
485
486
487MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_vid, MLXSW_REG_SFD_BASE_LEN, 16, 12,
488 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
489
490
491
492
493
494MLXSW_ITEM32_INDEXED(reg, sfd, uc_lag_lag_id, MLXSW_REG_SFD_BASE_LEN, 0, 10,
495 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
496
497static inline void
498mlxsw_reg_sfd_uc_lag_pack(char *payload, int rec_index,
499 enum mlxsw_reg_sfd_rec_policy policy,
500 const char *mac, u16 fid_vid,
501 enum mlxsw_reg_sfd_rec_action action, u16 lag_vid,
502 u16 lag_id)
503{
504 mlxsw_reg_sfd_rec_pack(payload, rec_index,
505 MLXSW_REG_SFD_REC_TYPE_UNICAST_LAG,
506 mac, action);
507 mlxsw_reg_sfd_rec_policy_set(payload, rec_index, policy);
508 mlxsw_reg_sfd_uc_lag_sub_port_set(payload, rec_index, 0);
509 mlxsw_reg_sfd_uc_lag_fid_vid_set(payload, rec_index, fid_vid);
510 mlxsw_reg_sfd_uc_lag_lag_vid_set(payload, rec_index, lag_vid);
511 mlxsw_reg_sfd_uc_lag_lag_id_set(payload, rec_index, lag_id);
512}
513
514static inline void mlxsw_reg_sfd_uc_lag_unpack(char *payload, int rec_index,
515 char *mac, u16 *p_vid,
516 u16 *p_lag_id)
517{
518 mlxsw_reg_sfd_rec_mac_memcpy_from(payload, rec_index, mac);
519 *p_vid = mlxsw_reg_sfd_uc_lag_fid_vid_get(payload, rec_index);
520 *p_lag_id = mlxsw_reg_sfd_uc_lag_lag_id_get(payload, rec_index);
521}
522
523
524
525
526
527
528
529
530MLXSW_ITEM32_INDEXED(reg, sfd, mc_pgi, MLXSW_REG_SFD_BASE_LEN, 16, 13,
531 MLXSW_REG_SFD_REC_LEN, 0x08, false);
532
533
534
535
536
537
538MLXSW_ITEM32_INDEXED(reg, sfd, mc_fid_vid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
539 MLXSW_REG_SFD_REC_LEN, 0x08, false);
540
541
542
543
544
545
546
547MLXSW_ITEM32_INDEXED(reg, sfd, mc_mid, MLXSW_REG_SFD_BASE_LEN, 0, 16,
548 MLXSW_REG_SFD_REC_LEN, 0x0C, false);
549
550static inline void
551mlxsw_reg_sfd_mc_pack(char *payload, int rec_index,
552 const char *mac, u16 fid_vid,
553 enum mlxsw_reg_sfd_rec_action action, u16 mid)
554{
555 mlxsw_reg_sfd_rec_pack(payload, rec_index,
556 MLXSW_REG_SFD_REC_TYPE_MULTICAST, mac, action);
557 mlxsw_reg_sfd_mc_pgi_set(payload, rec_index, 0x1FFF);
558 mlxsw_reg_sfd_mc_fid_vid_set(payload, rec_index, fid_vid);
559 mlxsw_reg_sfd_mc_mid_set(payload, rec_index, mid);
560}
561
562
563
564
565
566
567#define MLXSW_REG_SFN_ID 0x200B
568#define MLXSW_REG_SFN_BASE_LEN 0x10
569#define MLXSW_REG_SFN_REC_LEN 0x10
570#define MLXSW_REG_SFN_REC_MAX_COUNT 64
571#define MLXSW_REG_SFN_LEN (MLXSW_REG_SFN_BASE_LEN + \
572 MLXSW_REG_SFN_REC_LEN * MLXSW_REG_SFN_REC_MAX_COUNT)
573
574MLXSW_REG_DEFINE(sfn, MLXSW_REG_SFN_ID, MLXSW_REG_SFN_LEN);
575
576
577
578
579
580MLXSW_ITEM32(reg, sfn, swid, 0x00, 24, 8);
581
582
583
584
585
586MLXSW_ITEM32(reg, sfn, end, 0x04, 20, 1);
587
588
589
590
591
592
593
594
595
596MLXSW_ITEM32(reg, sfn, num_rec, 0x04, 0, 8);
597
598static inline void mlxsw_reg_sfn_pack(char *payload)
599{
600 MLXSW_REG_ZERO(sfn, payload);
601 mlxsw_reg_sfn_swid_set(payload, 0);
602 mlxsw_reg_sfn_end_set(payload, 1);
603 mlxsw_reg_sfn_num_rec_set(payload, MLXSW_REG_SFN_REC_MAX_COUNT);
604}
605
606
607
608
609
610MLXSW_ITEM32_INDEXED(reg, sfn, rec_swid, MLXSW_REG_SFN_BASE_LEN, 24, 8,
611 MLXSW_REG_SFN_REC_LEN, 0x00, false);
612
613enum mlxsw_reg_sfn_rec_type {
614
615 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC = 0x5,
616
617 MLXSW_REG_SFN_REC_TYPE_LEARNED_MAC_LAG = 0x6,
618
619 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC = 0x7,
620
621 MLXSW_REG_SFN_REC_TYPE_AGED_OUT_MAC_LAG = 0x8,
622};
623
624
625
626
627
628MLXSW_ITEM32_INDEXED(reg, sfn, rec_type, MLXSW_REG_SFN_BASE_LEN, 20, 4,
629 MLXSW_REG_SFN_REC_LEN, 0x00, false);
630
631
632
633
634
635MLXSW_ITEM_BUF_INDEXED(reg, sfn, rec_mac, MLXSW_REG_SFN_BASE_LEN, 6,
636 MLXSW_REG_SFN_REC_LEN, 0x02);
637
638
639
640
641
642
643MLXSW_ITEM32_INDEXED(reg, sfn, mac_sub_port, MLXSW_REG_SFN_BASE_LEN, 16, 8,
644 MLXSW_REG_SFN_REC_LEN, 0x08, false);
645
646
647
648
649
650MLXSW_ITEM32_INDEXED(reg, sfn, mac_fid, MLXSW_REG_SFN_BASE_LEN, 0, 16,
651 MLXSW_REG_SFN_REC_LEN, 0x08, false);
652
653
654
655
656
657MLXSW_ITEM32_INDEXED(reg, sfn, mac_system_port, MLXSW_REG_SFN_BASE_LEN, 0, 16,
658 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
659
660static inline void mlxsw_reg_sfn_mac_unpack(char *payload, int rec_index,
661 char *mac, u16 *p_vid,
662 u8 *p_local_port)
663{
664 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
665 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
666 *p_local_port = mlxsw_reg_sfn_mac_system_port_get(payload, rec_index);
667}
668
669
670
671
672
673MLXSW_ITEM32_INDEXED(reg, sfn, mac_lag_lag_id, MLXSW_REG_SFN_BASE_LEN, 0, 10,
674 MLXSW_REG_SFN_REC_LEN, 0x0C, false);
675
676static inline void mlxsw_reg_sfn_mac_lag_unpack(char *payload, int rec_index,
677 char *mac, u16 *p_vid,
678 u16 *p_lag_id)
679{
680 mlxsw_reg_sfn_rec_mac_memcpy_from(payload, rec_index, mac);
681 *p_vid = mlxsw_reg_sfn_mac_fid_get(payload, rec_index);
682 *p_lag_id = mlxsw_reg_sfn_mac_lag_lag_id_get(payload, rec_index);
683}
684
685
686
687
688
689#define MLXSW_REG_SPMS_ID 0x200D
690#define MLXSW_REG_SPMS_LEN 0x404
691
692MLXSW_REG_DEFINE(spms, MLXSW_REG_SPMS_ID, MLXSW_REG_SPMS_LEN);
693
694
695
696
697
698MLXSW_ITEM32(reg, spms, local_port, 0x00, 16, 8);
699
700enum mlxsw_reg_spms_state {
701 MLXSW_REG_SPMS_STATE_NO_CHANGE,
702 MLXSW_REG_SPMS_STATE_DISCARDING,
703 MLXSW_REG_SPMS_STATE_LEARNING,
704 MLXSW_REG_SPMS_STATE_FORWARDING,
705};
706
707
708
709
710
711
712
713
714
715MLXSW_ITEM_BIT_ARRAY(reg, spms, state, 0x04, 0x400, 2);
716
717static inline void mlxsw_reg_spms_pack(char *payload, u8 local_port)
718{
719 MLXSW_REG_ZERO(spms, payload);
720 mlxsw_reg_spms_local_port_set(payload, local_port);
721}
722
723static inline void mlxsw_reg_spms_vid_pack(char *payload, u16 vid,
724 enum mlxsw_reg_spms_state state)
725{
726 mlxsw_reg_spms_state_set(payload, vid, state);
727}
728
729
730
731
732
733#define MLXSW_REG_SPVID_ID 0x200E
734#define MLXSW_REG_SPVID_LEN 0x08
735
736MLXSW_REG_DEFINE(spvid, MLXSW_REG_SPVID_ID, MLXSW_REG_SPVID_LEN);
737
738
739
740
741
742MLXSW_ITEM32(reg, spvid, local_port, 0x00, 16, 8);
743
744
745
746
747
748
749MLXSW_ITEM32(reg, spvid, sub_port, 0x00, 8, 8);
750
751
752
753
754
755MLXSW_ITEM32(reg, spvid, pvid, 0x04, 0, 12);
756
757static inline void mlxsw_reg_spvid_pack(char *payload, u8 local_port, u16 pvid)
758{
759 MLXSW_REG_ZERO(spvid, payload);
760 mlxsw_reg_spvid_local_port_set(payload, local_port);
761 mlxsw_reg_spvid_pvid_set(payload, pvid);
762}
763
764
765
766
767
768
769
770#define MLXSW_REG_SPVM_ID 0x200F
771#define MLXSW_REG_SPVM_BASE_LEN 0x04
772#define MLXSW_REG_SPVM_REC_LEN 0x04
773#define MLXSW_REG_SPVM_REC_MAX_COUNT 255
774#define MLXSW_REG_SPVM_LEN (MLXSW_REG_SPVM_BASE_LEN + \
775 MLXSW_REG_SPVM_REC_LEN * MLXSW_REG_SPVM_REC_MAX_COUNT)
776
777MLXSW_REG_DEFINE(spvm, MLXSW_REG_SPVM_ID, MLXSW_REG_SPVM_LEN);
778
779
780
781
782
783
784
785MLXSW_ITEM32(reg, spvm, pt, 0x00, 31, 1);
786
787
788
789
790
791
792MLXSW_ITEM32(reg, spvm, pte, 0x00, 30, 1);
793
794
795
796
797
798MLXSW_ITEM32(reg, spvm, local_port, 0x00, 16, 8);
799
800
801
802
803
804
805MLXSW_ITEM32(reg, spvm, sub_port, 0x00, 8, 8);
806
807
808
809
810
811MLXSW_ITEM32(reg, spvm, num_rec, 0x00, 0, 8);
812
813
814
815
816
817MLXSW_ITEM32_INDEXED(reg, spvm, rec_i,
818 MLXSW_REG_SPVM_BASE_LEN, 14, 1,
819 MLXSW_REG_SPVM_REC_LEN, 0, false);
820
821
822
823
824
825MLXSW_ITEM32_INDEXED(reg, spvm, rec_e,
826 MLXSW_REG_SPVM_BASE_LEN, 13, 1,
827 MLXSW_REG_SPVM_REC_LEN, 0, false);
828
829
830
831
832
833
834MLXSW_ITEM32_INDEXED(reg, spvm, rec_u,
835 MLXSW_REG_SPVM_BASE_LEN, 12, 1,
836 MLXSW_REG_SPVM_REC_LEN, 0, false);
837
838
839
840
841
842MLXSW_ITEM32_INDEXED(reg, spvm, rec_vid,
843 MLXSW_REG_SPVM_BASE_LEN, 0, 12,
844 MLXSW_REG_SPVM_REC_LEN, 0, false);
845
846static inline void mlxsw_reg_spvm_pack(char *payload, u8 local_port,
847 u16 vid_begin, u16 vid_end,
848 bool is_member, bool untagged)
849{
850 int size = vid_end - vid_begin + 1;
851 int i;
852
853 MLXSW_REG_ZERO(spvm, payload);
854 mlxsw_reg_spvm_local_port_set(payload, local_port);
855 mlxsw_reg_spvm_num_rec_set(payload, size);
856
857 for (i = 0; i < size; i++) {
858 mlxsw_reg_spvm_rec_i_set(payload, i, is_member);
859 mlxsw_reg_spvm_rec_e_set(payload, i, is_member);
860 mlxsw_reg_spvm_rec_u_set(payload, i, untagged);
861 mlxsw_reg_spvm_rec_vid_set(payload, i, vid_begin + i);
862 }
863}
864
865
866
867
868
869
870#define MLXSW_REG_SPAFT_ID 0x2010
871#define MLXSW_REG_SPAFT_LEN 0x08
872
873MLXSW_REG_DEFINE(spaft, MLXSW_REG_SPAFT_ID, MLXSW_REG_SPAFT_LEN);
874
875
876
877
878
879
880
881MLXSW_ITEM32(reg, spaft, local_port, 0x00, 16, 8);
882
883
884
885
886
887
888MLXSW_ITEM32(reg, spaft, sub_port, 0x00, 8, 8);
889
890
891
892
893
894MLXSW_ITEM32(reg, spaft, allow_untagged, 0x04, 31, 1);
895
896
897
898
899
900MLXSW_ITEM32(reg, spaft, allow_prio_tagged, 0x04, 30, 1);
901
902
903
904
905
906MLXSW_ITEM32(reg, spaft, allow_tagged, 0x04, 29, 1);
907
908static inline void mlxsw_reg_spaft_pack(char *payload, u8 local_port,
909 bool allow_untagged)
910{
911 MLXSW_REG_ZERO(spaft, payload);
912 mlxsw_reg_spaft_local_port_set(payload, local_port);
913 mlxsw_reg_spaft_allow_untagged_set(payload, allow_untagged);
914 mlxsw_reg_spaft_allow_prio_tagged_set(payload, true);
915 mlxsw_reg_spaft_allow_tagged_set(payload, true);
916}
917
918
919
920
921
922
923#define MLXSW_REG_SFGC_ID 0x2011
924#define MLXSW_REG_SFGC_LEN 0x10
925
926MLXSW_REG_DEFINE(sfgc, MLXSW_REG_SFGC_ID, MLXSW_REG_SFGC_LEN);
927
928enum mlxsw_reg_sfgc_type {
929 MLXSW_REG_SFGC_TYPE_BROADCAST,
930 MLXSW_REG_SFGC_TYPE_UNKNOWN_UNICAST,
931 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV4,
932 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_IPV6,
933 MLXSW_REG_SFGC_TYPE_RESERVED,
934 MLXSW_REG_SFGC_TYPE_UNREGISTERED_MULTICAST_NON_IP,
935 MLXSW_REG_SFGC_TYPE_IPV4_LINK_LOCAL,
936 MLXSW_REG_SFGC_TYPE_IPV6_ALL_HOST,
937 MLXSW_REG_SFGC_TYPE_MAX,
938};
939
940
941
942
943
944MLXSW_ITEM32(reg, sfgc, type, 0x00, 0, 4);
945
946enum mlxsw_reg_sfgc_bridge_type {
947 MLXSW_REG_SFGC_BRIDGE_TYPE_1Q_FID = 0,
948 MLXSW_REG_SFGC_BRIDGE_TYPE_VFID = 1,
949};
950
951
952
953
954
955
956MLXSW_ITEM32(reg, sfgc, bridge_type, 0x04, 24, 3);
957
958enum mlxsw_flood_table_type {
959 MLXSW_REG_SFGC_TABLE_TYPE_VID = 1,
960 MLXSW_REG_SFGC_TABLE_TYPE_SINGLE = 2,
961 MLXSW_REG_SFGC_TABLE_TYPE_ANY = 0,
962 MLXSW_REG_SFGC_TABLE_TYPE_FID_OFFSET = 3,
963 MLXSW_REG_SFGC_TABLE_TYPE_FID = 4,
964};
965
966
967
968
969
970
971
972MLXSW_ITEM32(reg, sfgc, table_type, 0x04, 16, 3);
973
974
975
976
977
978
979MLXSW_ITEM32(reg, sfgc, flood_table, 0x04, 0, 6);
980
981
982
983
984
985MLXSW_ITEM32(reg, sfgc, mid, 0x08, 0, 16);
986
987
988
989
990
991MLXSW_ITEM32(reg, sfgc, counter_set_type, 0x0C, 24, 8);
992
993
994
995
996
997MLXSW_ITEM32(reg, sfgc, counter_index, 0x0C, 0, 24);
998
999static inline void
1000mlxsw_reg_sfgc_pack(char *payload, enum mlxsw_reg_sfgc_type type,
1001 enum mlxsw_reg_sfgc_bridge_type bridge_type,
1002 enum mlxsw_flood_table_type table_type,
1003 unsigned int flood_table)
1004{
1005 MLXSW_REG_ZERO(sfgc, payload);
1006 mlxsw_reg_sfgc_type_set(payload, type);
1007 mlxsw_reg_sfgc_bridge_type_set(payload, bridge_type);
1008 mlxsw_reg_sfgc_table_type_set(payload, table_type);
1009 mlxsw_reg_sfgc_flood_table_set(payload, flood_table);
1010 mlxsw_reg_sfgc_mid_set(payload, MLXSW_PORT_MID);
1011}
1012
1013
1014
1015
1016
1017
1018#define MLXSW_REG_SFTR_ID 0x2012
1019#define MLXSW_REG_SFTR_LEN 0x420
1020
1021MLXSW_REG_DEFINE(sftr, MLXSW_REG_SFTR_ID, MLXSW_REG_SFTR_LEN);
1022
1023
1024
1025
1026
1027MLXSW_ITEM32(reg, sftr, swid, 0x00, 24, 8);
1028
1029
1030
1031
1032
1033
1034MLXSW_ITEM32(reg, sftr, flood_table, 0x00, 16, 6);
1035
1036
1037
1038
1039
1040
1041MLXSW_ITEM32(reg, sftr, index, 0x00, 0, 16);
1042
1043
1044
1045
1046
1047MLXSW_ITEM32(reg, sftr, table_type, 0x04, 16, 3);
1048
1049
1050
1051
1052
1053MLXSW_ITEM32(reg, sftr, range, 0x04, 0, 16);
1054
1055
1056
1057
1058
1059MLXSW_ITEM_BIT_ARRAY(reg, sftr, port, 0x20, 0x20, 1);
1060
1061
1062
1063
1064
1065MLXSW_ITEM_BIT_ARRAY(reg, sftr, port_mask, 0x220, 0x20, 1);
1066
1067static inline void mlxsw_reg_sftr_pack(char *payload,
1068 unsigned int flood_table,
1069 unsigned int index,
1070 enum mlxsw_flood_table_type table_type,
1071 unsigned int range, u8 port, bool set)
1072{
1073 MLXSW_REG_ZERO(sftr, payload);
1074 mlxsw_reg_sftr_swid_set(payload, 0);
1075 mlxsw_reg_sftr_flood_table_set(payload, flood_table);
1076 mlxsw_reg_sftr_index_set(payload, index);
1077 mlxsw_reg_sftr_table_type_set(payload, table_type);
1078 mlxsw_reg_sftr_range_set(payload, range);
1079 mlxsw_reg_sftr_port_set(payload, port, set);
1080 mlxsw_reg_sftr_port_mask_set(payload, port, 1);
1081}
1082
1083
1084
1085
1086
1087
1088#define MLXSW_REG_SFDF_ID 0x2013
1089#define MLXSW_REG_SFDF_LEN 0x14
1090
1091MLXSW_REG_DEFINE(sfdf, MLXSW_REG_SFDF_ID, MLXSW_REG_SFDF_LEN);
1092
1093
1094
1095
1096
1097MLXSW_ITEM32(reg, sfdf, swid, 0x00, 24, 8);
1098
1099enum mlxsw_reg_sfdf_flush_type {
1100 MLXSW_REG_SFDF_FLUSH_PER_SWID,
1101 MLXSW_REG_SFDF_FLUSH_PER_FID,
1102 MLXSW_REG_SFDF_FLUSH_PER_PORT,
1103 MLXSW_REG_SFDF_FLUSH_PER_PORT_AND_FID,
1104 MLXSW_REG_SFDF_FLUSH_PER_LAG,
1105 MLXSW_REG_SFDF_FLUSH_PER_LAG_AND_FID,
1106};
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118MLXSW_ITEM32(reg, sfdf, flush_type, 0x04, 28, 4);
1119
1120
1121
1122
1123
1124
1125
1126MLXSW_ITEM32(reg, sfdf, flush_static, 0x04, 24, 1);
1127
1128static inline void mlxsw_reg_sfdf_pack(char *payload,
1129 enum mlxsw_reg_sfdf_flush_type type)
1130{
1131 MLXSW_REG_ZERO(sfdf, payload);
1132 mlxsw_reg_sfdf_flush_type_set(payload, type);
1133 mlxsw_reg_sfdf_flush_static_set(payload, true);
1134}
1135
1136
1137
1138
1139
1140MLXSW_ITEM32(reg, sfdf, fid, 0x0C, 0, 16);
1141
1142
1143
1144
1145
1146MLXSW_ITEM32(reg, sfdf, system_port, 0x0C, 0, 16);
1147
1148
1149
1150
1151
1152MLXSW_ITEM32(reg, sfdf, port_fid_system_port, 0x08, 0, 16);
1153
1154
1155
1156
1157
1158MLXSW_ITEM32(reg, sfdf, lag_id, 0x0C, 0, 10);
1159
1160
1161
1162
1163
1164MLXSW_ITEM32(reg, sfdf, lag_fid_lag_id, 0x08, 0, 10);
1165
1166
1167
1168
1169
1170
1171
1172#define MLXSW_REG_SLDR_ID 0x2014
1173#define MLXSW_REG_SLDR_LEN 0x0C
1174
1175MLXSW_REG_DEFINE(sldr, MLXSW_REG_SLDR_ID, MLXSW_REG_SLDR_LEN);
1176
1177enum mlxsw_reg_sldr_op {
1178
1179 MLXSW_REG_SLDR_OP_LAG_CREATE,
1180 MLXSW_REG_SLDR_OP_LAG_DESTROY,
1181
1182 MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST,
1183
1184 MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST,
1185};
1186
1187
1188
1189
1190
1191MLXSW_ITEM32(reg, sldr, op, 0x00, 29, 3);
1192
1193
1194
1195
1196
1197MLXSW_ITEM32(reg, sldr, lag_id, 0x00, 0, 10);
1198
1199static inline void mlxsw_reg_sldr_lag_create_pack(char *payload, u8 lag_id)
1200{
1201 MLXSW_REG_ZERO(sldr, payload);
1202 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_CREATE);
1203 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1204}
1205
1206static inline void mlxsw_reg_sldr_lag_destroy_pack(char *payload, u8 lag_id)
1207{
1208 MLXSW_REG_ZERO(sldr, payload);
1209 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_DESTROY);
1210 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1211}
1212
1213
1214
1215
1216
1217
1218
1219MLXSW_ITEM32(reg, sldr, num_ports, 0x04, 24, 8);
1220
1221
1222
1223
1224
1225MLXSW_ITEM32_INDEXED(reg, sldr, system_port, 0x08, 0, 16, 4, 0, false);
1226
1227static inline void mlxsw_reg_sldr_lag_add_port_pack(char *payload, u8 lag_id,
1228 u8 local_port)
1229{
1230 MLXSW_REG_ZERO(sldr, payload);
1231 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_ADD_PORT_LIST);
1232 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1233 mlxsw_reg_sldr_num_ports_set(payload, 1);
1234 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1235}
1236
1237static inline void mlxsw_reg_sldr_lag_remove_port_pack(char *payload, u8 lag_id,
1238 u8 local_port)
1239{
1240 MLXSW_REG_ZERO(sldr, payload);
1241 mlxsw_reg_sldr_op_set(payload, MLXSW_REG_SLDR_OP_LAG_REMOVE_PORT_LIST);
1242 mlxsw_reg_sldr_lag_id_set(payload, lag_id);
1243 mlxsw_reg_sldr_num_ports_set(payload, 1);
1244 mlxsw_reg_sldr_system_port_set(payload, 0, local_port);
1245}
1246
1247
1248
1249
1250
1251
1252#define MLXSW_REG_SLCR_ID 0x2015
1253#define MLXSW_REG_SLCR_LEN 0x10
1254
1255MLXSW_REG_DEFINE(slcr, MLXSW_REG_SLCR_ID, MLXSW_REG_SLCR_LEN);
1256
1257enum mlxsw_reg_slcr_pp {
1258
1259 MLXSW_REG_SLCR_PP_GLOBAL,
1260
1261 MLXSW_REG_SLCR_PP_PER_PORT,
1262};
1263
1264
1265
1266
1267
1268
1269MLXSW_ITEM32(reg, slcr, pp, 0x00, 24, 1);
1270
1271
1272
1273
1274
1275
1276
1277
1278MLXSW_ITEM32(reg, slcr, local_port, 0x00, 16, 8);
1279
1280enum mlxsw_reg_slcr_type {
1281 MLXSW_REG_SLCR_TYPE_CRC,
1282 MLXSW_REG_SLCR_TYPE_XOR,
1283 MLXSW_REG_SLCR_TYPE_RANDOM,
1284};
1285
1286
1287
1288
1289
1290MLXSW_ITEM32(reg, slcr, type, 0x00, 0, 4);
1291
1292
1293#define MLXSW_REG_SLCR_LAG_HASH_IN_PORT BIT(0)
1294
1295#define MLXSW_REG_SLCR_LAG_HASH_SMAC_IP BIT(1)
1296
1297#define MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP BIT(2)
1298#define MLXSW_REG_SLCR_LAG_HASH_SMAC \
1299 (MLXSW_REG_SLCR_LAG_HASH_SMAC_IP | \
1300 MLXSW_REG_SLCR_LAG_HASH_SMAC_NONIP)
1301
1302#define MLXSW_REG_SLCR_LAG_HASH_DMAC_IP BIT(3)
1303
1304#define MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP BIT(4)
1305#define MLXSW_REG_SLCR_LAG_HASH_DMAC \
1306 (MLXSW_REG_SLCR_LAG_HASH_DMAC_IP | \
1307 MLXSW_REG_SLCR_LAG_HASH_DMAC_NONIP)
1308
1309#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP BIT(5)
1310
1311#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP BIT(6)
1312#define MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE \
1313 (MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_IP | \
1314 MLXSW_REG_SLCR_LAG_HASH_ETHERTYPE_NONIP)
1315
1316#define MLXSW_REG_SLCR_LAG_HASH_VLANID_IP BIT(7)
1317
1318#define MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP BIT(8)
1319#define MLXSW_REG_SLCR_LAG_HASH_VLANID \
1320 (MLXSW_REG_SLCR_LAG_HASH_VLANID_IP | \
1321 MLXSW_REG_SLCR_LAG_HASH_VLANID_NONIP)
1322
1323#define MLXSW_REG_SLCR_LAG_HASH_SIP BIT(9)
1324
1325#define MLXSW_REG_SLCR_LAG_HASH_DIP BIT(10)
1326
1327#define MLXSW_REG_SLCR_LAG_HASH_SPORT BIT(11)
1328
1329#define MLXSW_REG_SLCR_LAG_HASH_DPORT BIT(12)
1330
1331#define MLXSW_REG_SLCR_LAG_HASH_IPPROTO BIT(13)
1332
1333#define MLXSW_REG_SLCR_LAG_HASH_FLOWLABEL BIT(14)
1334
1335#define MLXSW_REG_SLCR_LAG_HASH_FCOE_SID BIT(15)
1336
1337#define MLXSW_REG_SLCR_LAG_HASH_FCOE_DID BIT(16)
1338
1339#define MLXSW_REG_SLCR_LAG_HASH_FCOE_OXID BIT(17)
1340
1341#define MLXSW_REG_SLCR_LAG_HASH_ROCE_DQP BIT(19)
1342
1343
1344
1345
1346
1347
1348
1349
1350MLXSW_ITEM32(reg, slcr, lag_hash, 0x04, 0, 20);
1351
1352static inline void mlxsw_reg_slcr_pack(char *payload, u16 lag_hash)
1353{
1354 MLXSW_REG_ZERO(slcr, payload);
1355 mlxsw_reg_slcr_pp_set(payload, MLXSW_REG_SLCR_PP_GLOBAL);
1356 mlxsw_reg_slcr_type_set(payload, MLXSW_REG_SLCR_TYPE_CRC);
1357 mlxsw_reg_slcr_lag_hash_set(payload, lag_hash);
1358}
1359
1360
1361
1362
1363
1364
1365#define MLXSW_REG_SLCOR_ID 0x2016
1366#define MLXSW_REG_SLCOR_LEN 0x10
1367
1368MLXSW_REG_DEFINE(slcor, MLXSW_REG_SLCOR_ID, MLXSW_REG_SLCOR_LEN);
1369
1370enum mlxsw_reg_slcor_col {
1371
1372 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT,
1373 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED,
1374 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_DISABLED,
1375 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT,
1376};
1377
1378
1379
1380
1381
1382MLXSW_ITEM32(reg, slcor, col, 0x00, 30, 2);
1383
1384
1385
1386
1387
1388
1389MLXSW_ITEM32(reg, slcor, local_port, 0x00, 16, 8);
1390
1391
1392
1393
1394
1395MLXSW_ITEM32(reg, slcor, lag_id, 0x00, 0, 10);
1396
1397
1398
1399
1400
1401
1402MLXSW_ITEM32(reg, slcor, port_index, 0x04, 0, 10);
1403
1404static inline void mlxsw_reg_slcor_pack(char *payload,
1405 u8 local_port, u16 lag_id,
1406 enum mlxsw_reg_slcor_col col)
1407{
1408 MLXSW_REG_ZERO(slcor, payload);
1409 mlxsw_reg_slcor_col_set(payload, col);
1410 mlxsw_reg_slcor_local_port_set(payload, local_port);
1411 mlxsw_reg_slcor_lag_id_set(payload, lag_id);
1412}
1413
1414static inline void mlxsw_reg_slcor_port_add_pack(char *payload,
1415 u8 local_port, u16 lag_id,
1416 u8 port_index)
1417{
1418 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1419 MLXSW_REG_SLCOR_COL_LAG_ADD_PORT);
1420 mlxsw_reg_slcor_port_index_set(payload, port_index);
1421}
1422
1423static inline void mlxsw_reg_slcor_port_remove_pack(char *payload,
1424 u8 local_port, u16 lag_id)
1425{
1426 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1427 MLXSW_REG_SLCOR_COL_LAG_REMOVE_PORT);
1428}
1429
1430static inline void mlxsw_reg_slcor_col_enable_pack(char *payload,
1431 u8 local_port, u16 lag_id)
1432{
1433 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1434 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1435}
1436
1437static inline void mlxsw_reg_slcor_col_disable_pack(char *payload,
1438 u8 local_port, u16 lag_id)
1439{
1440 mlxsw_reg_slcor_pack(payload, local_port, lag_id,
1441 MLXSW_REG_SLCOR_COL_LAG_COLLECTOR_ENABLED);
1442}
1443
1444
1445
1446
1447
1448#define MLXSW_REG_SPMLR_ID 0x2018
1449#define MLXSW_REG_SPMLR_LEN 0x8
1450
1451MLXSW_REG_DEFINE(spmlr, MLXSW_REG_SPMLR_ID, MLXSW_REG_SPMLR_LEN);
1452
1453
1454
1455
1456
1457MLXSW_ITEM32(reg, spmlr, local_port, 0x00, 16, 8);
1458
1459
1460
1461
1462
1463
1464MLXSW_ITEM32(reg, spmlr, sub_port, 0x00, 8, 8);
1465
1466enum mlxsw_reg_spmlr_learn_mode {
1467 MLXSW_REG_SPMLR_LEARN_MODE_DISABLE = 0,
1468 MLXSW_REG_SPMLR_LEARN_MODE_ENABLE = 2,
1469 MLXSW_REG_SPMLR_LEARN_MODE_SEC = 3,
1470};
1471
1472
1473
1474
1475
1476
1477
1478
1479
1480
1481
1482
1483MLXSW_ITEM32(reg, spmlr, learn_mode, 0x04, 30, 2);
1484
1485static inline void mlxsw_reg_spmlr_pack(char *payload, u8 local_port,
1486 enum mlxsw_reg_spmlr_learn_mode mode)
1487{
1488 MLXSW_REG_ZERO(spmlr, payload);
1489 mlxsw_reg_spmlr_local_port_set(payload, local_port);
1490 mlxsw_reg_spmlr_sub_port_set(payload, 0);
1491 mlxsw_reg_spmlr_learn_mode_set(payload, mode);
1492}
1493
1494
1495
1496
1497
1498
1499#define MLXSW_REG_SVFA_ID 0x201C
1500#define MLXSW_REG_SVFA_LEN 0x10
1501
1502MLXSW_REG_DEFINE(svfa, MLXSW_REG_SVFA_ID, MLXSW_REG_SVFA_LEN);
1503
1504
1505
1506
1507
1508MLXSW_ITEM32(reg, svfa, swid, 0x00, 24, 8);
1509
1510
1511
1512
1513
1514
1515
1516MLXSW_ITEM32(reg, svfa, local_port, 0x00, 16, 8);
1517
1518enum mlxsw_reg_svfa_mt {
1519 MLXSW_REG_SVFA_MT_VID_TO_FID,
1520 MLXSW_REG_SVFA_MT_PORT_VID_TO_FID,
1521};
1522
1523
1524
1525
1526
1527
1528
1529
1530
1531MLXSW_ITEM32(reg, svfa, mapping_table, 0x00, 8, 3);
1532
1533
1534
1535
1536
1537
1538
1539
1540MLXSW_ITEM32(reg, svfa, v, 0x00, 0, 1);
1541
1542
1543
1544
1545
1546MLXSW_ITEM32(reg, svfa, fid, 0x04, 16, 16);
1547
1548
1549
1550
1551
1552MLXSW_ITEM32(reg, svfa, vid, 0x04, 0, 12);
1553
1554
1555
1556
1557
1558
1559
1560MLXSW_ITEM32(reg, svfa, counter_set_type, 0x08, 24, 8);
1561
1562
1563
1564
1565
1566
1567
1568MLXSW_ITEM32(reg, svfa, counter_index, 0x08, 0, 24);
1569
1570static inline void mlxsw_reg_svfa_pack(char *payload, u8 local_port,
1571 enum mlxsw_reg_svfa_mt mt, bool valid,
1572 u16 fid, u16 vid)
1573{
1574 MLXSW_REG_ZERO(svfa, payload);
1575 local_port = mt == MLXSW_REG_SVFA_MT_VID_TO_FID ? 0 : local_port;
1576 mlxsw_reg_svfa_swid_set(payload, 0);
1577 mlxsw_reg_svfa_local_port_set(payload, local_port);
1578 mlxsw_reg_svfa_mapping_table_set(payload, mt);
1579 mlxsw_reg_svfa_v_set(payload, valid);
1580 mlxsw_reg_svfa_fid_set(payload, fid);
1581 mlxsw_reg_svfa_vid_set(payload, vid);
1582}
1583
1584
1585
1586
1587
1588#define MLXSW_REG_SVPE_ID 0x201E
1589#define MLXSW_REG_SVPE_LEN 0x4
1590
1591MLXSW_REG_DEFINE(svpe, MLXSW_REG_SVPE_ID, MLXSW_REG_SVPE_LEN);
1592
1593
1594
1595
1596
1597
1598
1599MLXSW_ITEM32(reg, svpe, local_port, 0x00, 16, 8);
1600
1601
1602
1603
1604
1605
1606
1607MLXSW_ITEM32(reg, svpe, vp_en, 0x00, 8, 1);
1608
1609static inline void mlxsw_reg_svpe_pack(char *payload, u8 local_port,
1610 bool enable)
1611{
1612 MLXSW_REG_ZERO(svpe, payload);
1613 mlxsw_reg_svpe_local_port_set(payload, local_port);
1614 mlxsw_reg_svpe_vp_en_set(payload, enable);
1615}
1616
1617
1618
1619
1620
1621#define MLXSW_REG_SFMR_ID 0x201F
1622#define MLXSW_REG_SFMR_LEN 0x18
1623
1624MLXSW_REG_DEFINE(sfmr, MLXSW_REG_SFMR_ID, MLXSW_REG_SFMR_LEN);
1625
1626enum mlxsw_reg_sfmr_op {
1627 MLXSW_REG_SFMR_OP_CREATE_FID,
1628 MLXSW_REG_SFMR_OP_DESTROY_FID,
1629};
1630
1631
1632
1633
1634
1635
1636
1637MLXSW_ITEM32(reg, sfmr, op, 0x00, 24, 4);
1638
1639
1640
1641
1642
1643MLXSW_ITEM32(reg, sfmr, fid, 0x00, 0, 16);
1644
1645
1646
1647
1648
1649
1650
1651MLXSW_ITEM32(reg, sfmr, fid_offset, 0x08, 0, 16);
1652
1653
1654
1655
1656
1657
1658
1659
1660MLXSW_ITEM32(reg, sfmr, vtfp, 0x0C, 31, 1);
1661
1662
1663
1664
1665
1666
1667
1668MLXSW_ITEM32(reg, sfmr, nve_tunnel_flood_ptr, 0x0C, 0, 24);
1669
1670
1671
1672
1673
1674
1675
1676
1677MLXSW_ITEM32(reg, sfmr, vv, 0x10, 31, 1);
1678
1679
1680
1681
1682
1683
1684
1685MLXSW_ITEM32(reg, sfmr, vni, 0x10, 0, 24);
1686
1687static inline void mlxsw_reg_sfmr_pack(char *payload,
1688 enum mlxsw_reg_sfmr_op op, u16 fid,
1689 u16 fid_offset)
1690{
1691 MLXSW_REG_ZERO(sfmr, payload);
1692 mlxsw_reg_sfmr_op_set(payload, op);
1693 mlxsw_reg_sfmr_fid_set(payload, fid);
1694 mlxsw_reg_sfmr_fid_offset_set(payload, fid_offset);
1695 mlxsw_reg_sfmr_vtfp_set(payload, false);
1696 mlxsw_reg_sfmr_vv_set(payload, false);
1697}
1698
1699
1700
1701
1702
1703#define MLXSW_REG_SPVMLR_ID 0x2020
1704#define MLXSW_REG_SPVMLR_BASE_LEN 0x04
1705#define MLXSW_REG_SPVMLR_REC_LEN 0x04
1706#define MLXSW_REG_SPVMLR_REC_MAX_COUNT 255
1707#define MLXSW_REG_SPVMLR_LEN (MLXSW_REG_SPVMLR_BASE_LEN + \
1708 MLXSW_REG_SPVMLR_REC_LEN * \
1709 MLXSW_REG_SPVMLR_REC_MAX_COUNT)
1710
1711MLXSW_REG_DEFINE(spvmlr, MLXSW_REG_SPVMLR_ID, MLXSW_REG_SPVMLR_LEN);
1712
1713
1714
1715
1716
1717
1718
1719MLXSW_ITEM32(reg, spvmlr, local_port, 0x00, 16, 8);
1720
1721
1722
1723
1724
1725MLXSW_ITEM32(reg, spvmlr, num_rec, 0x00, 0, 8);
1726
1727
1728
1729
1730
1731
1732MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_learn_enable, MLXSW_REG_SPVMLR_BASE_LEN,
1733 31, 1, MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1734
1735
1736
1737
1738
1739MLXSW_ITEM32_INDEXED(reg, spvmlr, rec_vid, MLXSW_REG_SPVMLR_BASE_LEN, 0, 12,
1740 MLXSW_REG_SPVMLR_REC_LEN, 0x00, false);
1741
1742static inline void mlxsw_reg_spvmlr_pack(char *payload, u8 local_port,
1743 u16 vid_begin, u16 vid_end,
1744 bool learn_enable)
1745{
1746 int num_rec = vid_end - vid_begin + 1;
1747 int i;
1748
1749 WARN_ON(num_rec < 1 || num_rec > MLXSW_REG_SPVMLR_REC_MAX_COUNT);
1750
1751 MLXSW_REG_ZERO(spvmlr, payload);
1752 mlxsw_reg_spvmlr_local_port_set(payload, local_port);
1753 mlxsw_reg_spvmlr_num_rec_set(payload, num_rec);
1754
1755 for (i = 0; i < num_rec; i++) {
1756 mlxsw_reg_spvmlr_rec_learn_enable_set(payload, i, learn_enable);
1757 mlxsw_reg_spvmlr_rec_vid_set(payload, i, vid_begin + i);
1758 }
1759}
1760
1761
1762
1763
1764
1765#define MLXSW_REG_CWTP_ID 0x2802
1766#define MLXSW_REG_CWTP_BASE_LEN 0x28
1767#define MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN 0x08
1768#define MLXSW_REG_CWTP_LEN 0x40
1769
1770MLXSW_REG_DEFINE(cwtp, MLXSW_REG_CWTP_ID, MLXSW_REG_CWTP_LEN);
1771
1772
1773
1774
1775
1776
1777MLXSW_ITEM32(reg, cwtp, local_port, 0, 16, 8);
1778
1779
1780
1781
1782
1783MLXSW_ITEM32(reg, cwtp, traffic_class, 32, 0, 8);
1784
1785
1786
1787
1788
1789MLXSW_ITEM32_INDEXED(reg, cwtp, profile_min, MLXSW_REG_CWTP_BASE_LEN,
1790 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 0, false);
1791
1792
1793
1794
1795
1796
1797MLXSW_ITEM32_INDEXED(reg, cwtp, profile_percent, MLXSW_REG_CWTP_BASE_LEN,
1798 24, 7, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1799
1800
1801
1802
1803
1804MLXSW_ITEM32_INDEXED(reg, cwtp, profile_max, MLXSW_REG_CWTP_BASE_LEN,
1805 0, 20, MLXSW_REG_CWTP_PROFILE_DATA_REC_LEN, 4, false);
1806
1807#define MLXSW_REG_CWTP_MIN_VALUE 64
1808#define MLXSW_REG_CWTP_MAX_PROFILE 2
1809#define MLXSW_REG_CWTP_DEFAULT_PROFILE 1
1810
1811static inline void mlxsw_reg_cwtp_pack(char *payload, u8 local_port,
1812 u8 traffic_class)
1813{
1814 int i;
1815
1816 MLXSW_REG_ZERO(cwtp, payload);
1817 mlxsw_reg_cwtp_local_port_set(payload, local_port);
1818 mlxsw_reg_cwtp_traffic_class_set(payload, traffic_class);
1819
1820 for (i = 0; i <= MLXSW_REG_CWTP_MAX_PROFILE; i++) {
1821 mlxsw_reg_cwtp_profile_min_set(payload, i,
1822 MLXSW_REG_CWTP_MIN_VALUE);
1823 mlxsw_reg_cwtp_profile_max_set(payload, i,
1824 MLXSW_REG_CWTP_MIN_VALUE);
1825 }
1826}
1827
1828#define MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile) (profile - 1)
1829
1830static inline void
1831mlxsw_reg_cwtp_profile_pack(char *payload, u8 profile, u32 min, u32 max,
1832 u32 probability)
1833{
1834 u8 index = MLXSW_REG_CWTP_PROFILE_TO_INDEX(profile);
1835
1836 mlxsw_reg_cwtp_profile_min_set(payload, index, min);
1837 mlxsw_reg_cwtp_profile_max_set(payload, index, max);
1838 mlxsw_reg_cwtp_profile_percent_set(payload, index, probability);
1839}
1840
1841
1842
1843
1844
1845#define MLXSW_REG_CWTPM_ID 0x2803
1846#define MLXSW_REG_CWTPM_LEN 0x44
1847
1848MLXSW_REG_DEFINE(cwtpm, MLXSW_REG_CWTPM_ID, MLXSW_REG_CWTPM_LEN);
1849
1850
1851
1852
1853
1854
1855MLXSW_ITEM32(reg, cwtpm, local_port, 0, 16, 8);
1856
1857
1858
1859
1860
1861MLXSW_ITEM32(reg, cwtpm, traffic_class, 32, 0, 8);
1862
1863
1864
1865
1866
1867
1868
1869MLXSW_ITEM32(reg, cwtpm, ew, 36, 1, 1);
1870
1871
1872
1873
1874
1875
1876
1877MLXSW_ITEM32(reg, cwtpm, ee, 36, 0, 1);
1878
1879
1880
1881
1882
1883
1884
1885MLXSW_ITEM32(reg, cwtpm, tcp_g, 52, 0, 2);
1886
1887
1888
1889
1890
1891
1892
1893MLXSW_ITEM32(reg, cwtpm, tcp_y, 56, 16, 2);
1894
1895
1896
1897
1898
1899
1900
1901MLXSW_ITEM32(reg, cwtpm, tcp_r, 56, 0, 2);
1902
1903
1904
1905
1906
1907
1908
1909MLXSW_ITEM32(reg, cwtpm, ntcp_g, 60, 0, 2);
1910
1911
1912
1913
1914
1915
1916
1917MLXSW_ITEM32(reg, cwtpm, ntcp_y, 64, 16, 2);
1918
1919
1920
1921
1922
1923
1924
1925MLXSW_ITEM32(reg, cwtpm, ntcp_r, 64, 0, 2);
1926
1927#define MLXSW_REG_CWTPM_RESET_PROFILE 0
1928
1929static inline void mlxsw_reg_cwtpm_pack(char *payload, u8 local_port,
1930 u8 traffic_class, u8 profile,
1931 bool wred, bool ecn)
1932{
1933 MLXSW_REG_ZERO(cwtpm, payload);
1934 mlxsw_reg_cwtpm_local_port_set(payload, local_port);
1935 mlxsw_reg_cwtpm_traffic_class_set(payload, traffic_class);
1936 mlxsw_reg_cwtpm_ew_set(payload, wred);
1937 mlxsw_reg_cwtpm_ee_set(payload, ecn);
1938 mlxsw_reg_cwtpm_tcp_g_set(payload, profile);
1939 mlxsw_reg_cwtpm_tcp_y_set(payload, profile);
1940 mlxsw_reg_cwtpm_tcp_r_set(payload, profile);
1941 mlxsw_reg_cwtpm_ntcp_g_set(payload, profile);
1942 mlxsw_reg_cwtpm_ntcp_y_set(payload, profile);
1943 mlxsw_reg_cwtpm_ntcp_r_set(payload, profile);
1944}
1945
1946
1947
1948
1949
1950#define MLXSW_REG_PPBT_ID 0x3002
1951#define MLXSW_REG_PPBT_LEN 0x14
1952
1953MLXSW_REG_DEFINE(ppbt, MLXSW_REG_PPBT_ID, MLXSW_REG_PPBT_LEN);
1954
1955enum mlxsw_reg_pxbt_e {
1956 MLXSW_REG_PXBT_E_IACL,
1957 MLXSW_REG_PXBT_E_EACL,
1958};
1959
1960
1961
1962
1963MLXSW_ITEM32(reg, ppbt, e, 0x00, 31, 1);
1964
1965enum mlxsw_reg_pxbt_op {
1966 MLXSW_REG_PXBT_OP_BIND,
1967 MLXSW_REG_PXBT_OP_UNBIND,
1968};
1969
1970
1971
1972
1973MLXSW_ITEM32(reg, ppbt, op, 0x00, 28, 3);
1974
1975
1976
1977
1978
1979MLXSW_ITEM32(reg, ppbt, local_port, 0x00, 16, 8);
1980
1981
1982
1983
1984
1985
1986
1987MLXSW_ITEM32(reg, ppbt, g, 0x10, 31, 1);
1988
1989
1990
1991
1992
1993
1994MLXSW_ITEM32(reg, ppbt, acl_info, 0x10, 0, 16);
1995
1996static inline void mlxsw_reg_ppbt_pack(char *payload, enum mlxsw_reg_pxbt_e e,
1997 enum mlxsw_reg_pxbt_op op,
1998 u8 local_port, u16 acl_info)
1999{
2000 MLXSW_REG_ZERO(ppbt, payload);
2001 mlxsw_reg_ppbt_e_set(payload, e);
2002 mlxsw_reg_ppbt_op_set(payload, op);
2003 mlxsw_reg_ppbt_local_port_set(payload, local_port);
2004 mlxsw_reg_ppbt_g_set(payload, true);
2005 mlxsw_reg_ppbt_acl_info_set(payload, acl_info);
2006}
2007
2008
2009
2010
2011
2012#define MLXSW_REG_PACL_ID 0x3004
2013#define MLXSW_REG_PACL_LEN 0x70
2014
2015MLXSW_REG_DEFINE(pacl, MLXSW_REG_PACL_ID, MLXSW_REG_PACL_LEN);
2016
2017
2018
2019
2020
2021
2022MLXSW_ITEM32(reg, pacl, v, 0x00, 24, 1);
2023
2024
2025
2026
2027
2028
2029MLXSW_ITEM32(reg, pacl, acl_id, 0x08, 0, 16);
2030
2031#define MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN 16
2032
2033
2034
2035
2036
2037
2038MLXSW_ITEM_BUF(reg, pacl, tcam_region_info, 0x30,
2039 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2040
2041static inline void mlxsw_reg_pacl_pack(char *payload, u16 acl_id,
2042 bool valid, const char *tcam_region_info)
2043{
2044 MLXSW_REG_ZERO(pacl, payload);
2045 mlxsw_reg_pacl_acl_id_set(payload, acl_id);
2046 mlxsw_reg_pacl_v_set(payload, valid);
2047 mlxsw_reg_pacl_tcam_region_info_memcpy_to(payload, tcam_region_info);
2048}
2049
2050
2051
2052
2053
2054#define MLXSW_REG_PAGT_ID 0x3005
2055#define MLXSW_REG_PAGT_BASE_LEN 0x30
2056#define MLXSW_REG_PAGT_ACL_LEN 4
2057#define MLXSW_REG_PAGT_ACL_MAX_NUM 16
2058#define MLXSW_REG_PAGT_LEN (MLXSW_REG_PAGT_BASE_LEN + \
2059 MLXSW_REG_PAGT_ACL_MAX_NUM * MLXSW_REG_PAGT_ACL_LEN)
2060
2061MLXSW_REG_DEFINE(pagt, MLXSW_REG_PAGT_ID, MLXSW_REG_PAGT_LEN);
2062
2063
2064
2065
2066
2067
2068
2069
2070
2071
2072MLXSW_ITEM32(reg, pagt, size, 0x00, 0, 8);
2073
2074
2075
2076
2077
2078
2079MLXSW_ITEM32(reg, pagt, acl_group_id, 0x08, 0, 16);
2080
2081
2082
2083
2084
2085MLXSW_ITEM32_INDEXED(reg, pagt, acl_id, 0x30, 0, 16, 0x04, 0x00, false);
2086
2087static inline void mlxsw_reg_pagt_pack(char *payload, u16 acl_group_id)
2088{
2089 MLXSW_REG_ZERO(pagt, payload);
2090 mlxsw_reg_pagt_acl_group_id_set(payload, acl_group_id);
2091}
2092
2093static inline void mlxsw_reg_pagt_acl_id_pack(char *payload, int index,
2094 u16 acl_id)
2095{
2096 u8 size = mlxsw_reg_pagt_size_get(payload);
2097
2098 if (index >= size)
2099 mlxsw_reg_pagt_size_set(payload, index + 1);
2100 mlxsw_reg_pagt_acl_id_set(payload, index, acl_id);
2101}
2102
2103
2104
2105
2106
2107
2108#define MLXSW_REG_PTAR_ID 0x3006
2109#define MLXSW_REG_PTAR_BASE_LEN 0x20
2110#define MLXSW_REG_PTAR_KEY_ID_LEN 1
2111#define MLXSW_REG_PTAR_KEY_ID_MAX_NUM 16
2112#define MLXSW_REG_PTAR_LEN (MLXSW_REG_PTAR_BASE_LEN + \
2113 MLXSW_REG_PTAR_KEY_ID_MAX_NUM * MLXSW_REG_PTAR_KEY_ID_LEN)
2114
2115MLXSW_REG_DEFINE(ptar, MLXSW_REG_PTAR_ID, MLXSW_REG_PTAR_LEN);
2116
2117enum mlxsw_reg_ptar_op {
2118
2119 MLXSW_REG_PTAR_OP_ALLOC,
2120
2121 MLXSW_REG_PTAR_OP_RESIZE,
2122
2123 MLXSW_REG_PTAR_OP_FREE,
2124
2125 MLXSW_REG_PTAR_OP_TEST,
2126};
2127
2128
2129
2130
2131MLXSW_ITEM32(reg, ptar, op, 0x00, 28, 4);
2132
2133
2134
2135
2136
2137
2138MLXSW_ITEM32(reg, ptar, action_set_type, 0x00, 16, 8);
2139
2140
2141
2142
2143
2144
2145MLXSW_ITEM32(reg, ptar, key_type, 0x00, 0, 8);
2146
2147
2148
2149
2150
2151
2152
2153
2154
2155MLXSW_ITEM32(reg, ptar, region_size, 0x04, 0, 16);
2156
2157
2158
2159
2160
2161
2162MLXSW_ITEM32(reg, ptar, region_id, 0x08, 0, 16);
2163
2164
2165
2166
2167
2168
2169
2170MLXSW_ITEM_BUF(reg, ptar, tcam_region_info, 0x10,
2171 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2172
2173
2174
2175
2176
2177
2178
2179
2180
2181MLXSW_ITEM8_INDEXED(reg, ptar, flexible_key_id, 0x20, 0, 8,
2182 MLXSW_REG_PTAR_KEY_ID_LEN, 0x00, false);
2183
2184static inline void mlxsw_reg_ptar_pack(char *payload, enum mlxsw_reg_ptar_op op,
2185 u16 region_size, u16 region_id,
2186 const char *tcam_region_info)
2187{
2188 MLXSW_REG_ZERO(ptar, payload);
2189 mlxsw_reg_ptar_op_set(payload, op);
2190 mlxsw_reg_ptar_action_set_type_set(payload, 2);
2191 mlxsw_reg_ptar_key_type_set(payload, 0x50);
2192 mlxsw_reg_ptar_region_size_set(payload, region_size);
2193 mlxsw_reg_ptar_region_id_set(payload, region_id);
2194 mlxsw_reg_ptar_tcam_region_info_memcpy_to(payload, tcam_region_info);
2195}
2196
2197static inline void mlxsw_reg_ptar_key_id_pack(char *payload, int index,
2198 u16 key_id)
2199{
2200 mlxsw_reg_ptar_flexible_key_id_set(payload, index, key_id);
2201}
2202
2203static inline void mlxsw_reg_ptar_unpack(char *payload, char *tcam_region_info)
2204{
2205 mlxsw_reg_ptar_tcam_region_info_memcpy_from(payload, tcam_region_info);
2206}
2207
2208
2209
2210
2211
2212#define MLXSW_REG_PPBS_ID 0x300C
2213#define MLXSW_REG_PPBS_LEN 0x14
2214
2215MLXSW_REG_DEFINE(ppbs, MLXSW_REG_PPBS_ID, MLXSW_REG_PPBS_LEN);
2216
2217
2218
2219
2220
2221
2222MLXSW_ITEM32(reg, ppbs, pbs_ptr, 0x08, 0, 24);
2223
2224
2225
2226
2227
2228MLXSW_ITEM32(reg, ppbs, system_port, 0x10, 0, 16);
2229
2230static inline void mlxsw_reg_ppbs_pack(char *payload, u32 pbs_ptr,
2231 u16 system_port)
2232{
2233 MLXSW_REG_ZERO(ppbs, payload);
2234 mlxsw_reg_ppbs_pbs_ptr_set(payload, pbs_ptr);
2235 mlxsw_reg_ppbs_system_port_set(payload, system_port);
2236}
2237
2238
2239
2240
2241
2242#define MLXSW_REG_PRCR_ID 0x300D
2243#define MLXSW_REG_PRCR_LEN 0x40
2244
2245MLXSW_REG_DEFINE(prcr, MLXSW_REG_PRCR_ID, MLXSW_REG_PRCR_LEN);
2246
2247enum mlxsw_reg_prcr_op {
2248
2249
2250
2251
2252 MLXSW_REG_PRCR_OP_MOVE,
2253
2254
2255
2256
2257 MLXSW_REG_PRCR_OP_COPY,
2258};
2259
2260
2261
2262
2263MLXSW_ITEM32(reg, prcr, op, 0x00, 28, 4);
2264
2265
2266
2267
2268
2269MLXSW_ITEM32(reg, prcr, offset, 0x00, 0, 16);
2270
2271
2272
2273
2274
2275MLXSW_ITEM32(reg, prcr, size, 0x04, 0, 16);
2276
2277
2278
2279
2280
2281MLXSW_ITEM_BUF(reg, prcr, tcam_region_info, 0x10,
2282 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2283
2284
2285
2286
2287
2288MLXSW_ITEM32(reg, prcr, dest_offset, 0x20, 0, 16);
2289
2290
2291
2292
2293
2294MLXSW_ITEM_BUF(reg, prcr, dest_tcam_region_info, 0x30,
2295 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2296
2297static inline void mlxsw_reg_prcr_pack(char *payload, enum mlxsw_reg_prcr_op op,
2298 const char *src_tcam_region_info,
2299 u16 src_offset,
2300 const char *dest_tcam_region_info,
2301 u16 dest_offset, u16 size)
2302{
2303 MLXSW_REG_ZERO(prcr, payload);
2304 mlxsw_reg_prcr_op_set(payload, op);
2305 mlxsw_reg_prcr_offset_set(payload, src_offset);
2306 mlxsw_reg_prcr_size_set(payload, size);
2307 mlxsw_reg_prcr_tcam_region_info_memcpy_to(payload,
2308 src_tcam_region_info);
2309 mlxsw_reg_prcr_dest_offset_set(payload, dest_offset);
2310 mlxsw_reg_prcr_dest_tcam_region_info_memcpy_to(payload,
2311 dest_tcam_region_info);
2312}
2313
2314
2315
2316
2317
2318
2319#define MLXSW_REG_PEFA_ID 0x300F
2320#define MLXSW_REG_PEFA_LEN 0xB0
2321
2322MLXSW_REG_DEFINE(pefa, MLXSW_REG_PEFA_ID, MLXSW_REG_PEFA_LEN);
2323
2324
2325
2326
2327
2328MLXSW_ITEM32(reg, pefa, index, 0x00, 0, 24);
2329
2330#define MLXSW_REG_FLEX_ACTION_SET_LEN 0xA8
2331
2332
2333
2334
2335
2336
2337MLXSW_ITEM_BUF(reg, pefa, flex_action_set, 0x08, MLXSW_REG_FLEX_ACTION_SET_LEN);
2338
2339static inline void mlxsw_reg_pefa_pack(char *payload, u32 index,
2340 const char *flex_action_set)
2341{
2342 MLXSW_REG_ZERO(pefa, payload);
2343 mlxsw_reg_pefa_index_set(payload, index);
2344 mlxsw_reg_pefa_flex_action_set_memcpy_to(payload, flex_action_set);
2345}
2346
2347
2348
2349
2350
2351
2352
2353
2354#define MLXSW_REG_PTCE2_ID 0x3017
2355#define MLXSW_REG_PTCE2_LEN 0x1D8
2356
2357MLXSW_REG_DEFINE(ptce2, MLXSW_REG_PTCE2_ID, MLXSW_REG_PTCE2_LEN);
2358
2359
2360
2361
2362
2363MLXSW_ITEM32(reg, ptce2, v, 0x00, 31, 1);
2364
2365
2366
2367
2368
2369
2370MLXSW_ITEM32(reg, ptce2, a, 0x00, 30, 1);
2371
2372enum mlxsw_reg_ptce2_op {
2373
2374 MLXSW_REG_PTCE2_OP_QUERY_READ = 0,
2375
2376
2377
2378 MLXSW_REG_PTCE2_OP_QUERY_CLEAR_ON_READ = 1,
2379
2380
2381
2382
2383 MLXSW_REG_PTCE2_OP_WRITE_WRITE = 0,
2384
2385 MLXSW_REG_PTCE2_OP_WRITE_UPDATE = 1,
2386
2387 MLXSW_REG_PTCE2_OP_WRITE_CLEAR_ACTIVITY = 2,
2388};
2389
2390
2391
2392
2393MLXSW_ITEM32(reg, ptce2, op, 0x00, 20, 3);
2394
2395
2396
2397
2398MLXSW_ITEM32(reg, ptce2, offset, 0x00, 0, 16);
2399
2400
2401
2402
2403
2404MLXSW_ITEM_BUF(reg, ptce2, tcam_region_info, 0x10,
2405 MLXSW_REG_PXXX_TCAM_REGION_INFO_LEN);
2406
2407#define MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN 96
2408
2409
2410
2411
2412
2413MLXSW_ITEM_BUF(reg, ptce2, flex_key_blocks, 0x20,
2414 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN);
2415
2416
2417
2418
2419
2420
2421
2422MLXSW_ITEM_BUF(reg, ptce2, mask, 0x80,
2423 MLXSW_REG_PTCE2_FLEX_KEY_BLOCKS_LEN);
2424
2425
2426
2427
2428
2429MLXSW_ITEM_BUF(reg, ptce2, flex_action_set, 0xE0,
2430 MLXSW_REG_FLEX_ACTION_SET_LEN);
2431
2432static inline void mlxsw_reg_ptce2_pack(char *payload, bool valid,
2433 enum mlxsw_reg_ptce2_op op,
2434 const char *tcam_region_info,
2435 u16 offset)
2436{
2437 MLXSW_REG_ZERO(ptce2, payload);
2438 mlxsw_reg_ptce2_v_set(payload, valid);
2439 mlxsw_reg_ptce2_op_set(payload, op);
2440 mlxsw_reg_ptce2_offset_set(payload, offset);
2441 mlxsw_reg_ptce2_tcam_region_info_memcpy_to(payload, tcam_region_info);
2442}
2443
2444
2445
2446
2447
2448
2449#define MLXSW_REG_QPCR_ID 0x4004
2450#define MLXSW_REG_QPCR_LEN 0x28
2451
2452MLXSW_REG_DEFINE(qpcr, MLXSW_REG_QPCR_ID, MLXSW_REG_QPCR_LEN);
2453
2454enum mlxsw_reg_qpcr_g {
2455 MLXSW_REG_QPCR_G_GLOBAL = 2,
2456 MLXSW_REG_QPCR_G_STORM_CONTROL = 3,
2457};
2458
2459
2460
2461
2462
2463MLXSW_ITEM32(reg, qpcr, g, 0x00, 14, 2);
2464
2465
2466
2467
2468
2469MLXSW_ITEM32(reg, qpcr, pid, 0x00, 0, 14);
2470
2471
2472
2473
2474
2475
2476MLXSW_ITEM32(reg, qpcr, color_aware, 0x04, 15, 1);
2477
2478
2479
2480
2481
2482
2483
2484MLXSW_ITEM32(reg, qpcr, bytes, 0x04, 14, 1);
2485
2486enum mlxsw_reg_qpcr_ir_units {
2487 MLXSW_REG_QPCR_IR_UNITS_M,
2488 MLXSW_REG_QPCR_IR_UNITS_K,
2489};
2490
2491
2492
2493
2494
2495
2496
2497MLXSW_ITEM32(reg, qpcr, ir_units, 0x04, 12, 1);
2498
2499enum mlxsw_reg_qpcr_rate_type {
2500 MLXSW_REG_QPCR_RATE_TYPE_SINGLE = 1,
2501 MLXSW_REG_QPCR_RATE_TYPE_DOUBLE = 2,
2502};
2503
2504
2505
2506
2507
2508
2509
2510MLXSW_ITEM32(reg, qpcr, rate_type, 0x04, 8, 2);
2511
2512
2513
2514
2515
2516
2517
2518
2519
2520
2521
2522
2523MLXSW_ITEM32(reg, qpcr, cbs, 0x08, 24, 6);
2524
2525
2526
2527
2528
2529
2530
2531
2532MLXSW_ITEM32(reg, qpcr, cir, 0x0C, 0, 32);
2533
2534
2535
2536
2537
2538
2539
2540
2541
2542MLXSW_ITEM32(reg, qpcr, eir, 0x10, 0, 32);
2543
2544#define MLXSW_REG_QPCR_DOUBLE_RATE_ACTION 2
2545
2546
2547
2548
2549
2550MLXSW_ITEM32(reg, qpcr, exceed_action, 0x14, 0, 4);
2551
2552enum mlxsw_reg_qpcr_action {
2553
2554 MLXSW_REG_QPCR_ACTION_DISCARD = 1,
2555
2556
2557
2558 MLXSW_REG_QPCR_ACTION_FORWARD = 2,
2559};
2560
2561
2562
2563
2564
2565
2566MLXSW_ITEM32(reg, qpcr, violate_action, 0x18, 0, 4);
2567
2568static inline void mlxsw_reg_qpcr_pack(char *payload, u16 pid,
2569 enum mlxsw_reg_qpcr_ir_units ir_units,
2570 bool bytes, u32 cir, u16 cbs)
2571{
2572 MLXSW_REG_ZERO(qpcr, payload);
2573 mlxsw_reg_qpcr_pid_set(payload, pid);
2574 mlxsw_reg_qpcr_g_set(payload, MLXSW_REG_QPCR_G_GLOBAL);
2575 mlxsw_reg_qpcr_rate_type_set(payload, MLXSW_REG_QPCR_RATE_TYPE_SINGLE);
2576 mlxsw_reg_qpcr_violate_action_set(payload,
2577 MLXSW_REG_QPCR_ACTION_DISCARD);
2578 mlxsw_reg_qpcr_cir_set(payload, cir);
2579 mlxsw_reg_qpcr_ir_units_set(payload, ir_units);
2580 mlxsw_reg_qpcr_bytes_set(payload, bytes);
2581 mlxsw_reg_qpcr_cbs_set(payload, cbs);
2582}
2583
2584
2585
2586
2587
2588
2589#define MLXSW_REG_QTCT_ID 0x400A
2590#define MLXSW_REG_QTCT_LEN 0x08
2591
2592MLXSW_REG_DEFINE(qtct, MLXSW_REG_QTCT_ID, MLXSW_REG_QTCT_LEN);
2593
2594
2595
2596
2597
2598
2599
2600MLXSW_ITEM32(reg, qtct, local_port, 0x00, 16, 8);
2601
2602
2603
2604
2605
2606
2607MLXSW_ITEM32(reg, qtct, sub_port, 0x00, 8, 8);
2608
2609
2610
2611
2612
2613MLXSW_ITEM32(reg, qtct, switch_prio, 0x00, 0, 4);
2614
2615
2616
2617
2618
2619
2620
2621
2622
2623MLXSW_ITEM32(reg, qtct, tclass, 0x04, 0, 4);
2624
2625static inline void mlxsw_reg_qtct_pack(char *payload, u8 local_port,
2626 u8 switch_prio, u8 tclass)
2627{
2628 MLXSW_REG_ZERO(qtct, payload);
2629 mlxsw_reg_qtct_local_port_set(payload, local_port);
2630 mlxsw_reg_qtct_switch_prio_set(payload, switch_prio);
2631 mlxsw_reg_qtct_tclass_set(payload, tclass);
2632}
2633
2634
2635
2636
2637
2638#define MLXSW_REG_QEEC_ID 0x400D
2639#define MLXSW_REG_QEEC_LEN 0x1C
2640
2641MLXSW_REG_DEFINE(qeec, MLXSW_REG_QEEC_ID, MLXSW_REG_QEEC_LEN);
2642
2643
2644
2645
2646
2647
2648
2649MLXSW_ITEM32(reg, qeec, local_port, 0x00, 16, 8);
2650
2651enum mlxsw_reg_qeec_hr {
2652 MLXSW_REG_QEEC_HIERARCY_PORT,
2653 MLXSW_REG_QEEC_HIERARCY_GROUP,
2654 MLXSW_REG_QEEC_HIERARCY_SUBGROUP,
2655 MLXSW_REG_QEEC_HIERARCY_TC,
2656};
2657
2658
2659
2660
2661
2662
2663
2664
2665MLXSW_ITEM32(reg, qeec, element_hierarchy, 0x04, 16, 4);
2666
2667
2668
2669
2670
2671MLXSW_ITEM32(reg, qeec, element_index, 0x04, 0, 8);
2672
2673
2674
2675
2676
2677
2678
2679MLXSW_ITEM32(reg, qeec, next_element_index, 0x08, 0, 8);
2680
2681enum {
2682 MLXSW_REG_QEEC_BYTES_MODE,
2683 MLXSW_REG_QEEC_PACKETS_MODE,
2684};
2685
2686
2687
2688
2689
2690
2691
2692
2693
2694
2695MLXSW_ITEM32(reg, qeec, pb, 0x0C, 28, 1);
2696
2697
2698
2699
2700
2701
2702
2703
2704MLXSW_ITEM32(reg, qeec, mase, 0x10, 31, 1);
2705
2706
2707#define MLXSW_REG_QEEC_MAS_DIS 200000000
2708
2709
2710
2711
2712
2713
2714
2715MLXSW_ITEM32(reg, qeec, max_shaper_rate, 0x10, 0, 28);
2716
2717
2718
2719
2720
2721
2722
2723
2724MLXSW_ITEM32(reg, qeec, de, 0x18, 31, 1);
2725
2726
2727
2728
2729
2730
2731
2732
2733MLXSW_ITEM32(reg, qeec, dwrr, 0x18, 15, 1);
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743MLXSW_ITEM32(reg, qeec, dwrr_weight, 0x18, 0, 8);
2744
2745static inline void mlxsw_reg_qeec_pack(char *payload, u8 local_port,
2746 enum mlxsw_reg_qeec_hr hr, u8 index,
2747 u8 next_index)
2748{
2749 MLXSW_REG_ZERO(qeec, payload);
2750 mlxsw_reg_qeec_local_port_set(payload, local_port);
2751 mlxsw_reg_qeec_element_hierarchy_set(payload, hr);
2752 mlxsw_reg_qeec_element_index_set(payload, index);
2753 mlxsw_reg_qeec_next_element_index_set(payload, next_index);
2754}
2755
2756
2757
2758
2759
2760#define MLXSW_REG_PMLP_ID 0x5002
2761#define MLXSW_REG_PMLP_LEN 0x40
2762
2763MLXSW_REG_DEFINE(pmlp, MLXSW_REG_PMLP_ID, MLXSW_REG_PMLP_LEN);
2764
2765
2766
2767
2768
2769
2770MLXSW_ITEM32(reg, pmlp, rxtx, 0x00, 31, 1);
2771
2772
2773
2774
2775
2776MLXSW_ITEM32(reg, pmlp, local_port, 0x00, 16, 8);
2777
2778
2779
2780
2781
2782
2783
2784
2785MLXSW_ITEM32(reg, pmlp, width, 0x00, 0, 8);
2786
2787
2788
2789
2790
2791MLXSW_ITEM32_INDEXED(reg, pmlp, module, 0x04, 0, 8, 0x04, 0x00, false);
2792
2793
2794
2795
2796
2797MLXSW_ITEM32_INDEXED(reg, pmlp, tx_lane, 0x04, 16, 2, 0x04, 0x00, false);
2798
2799
2800
2801
2802
2803
2804MLXSW_ITEM32_INDEXED(reg, pmlp, rx_lane, 0x04, 24, 2, 0x04, 0x00, false);
2805
2806static inline void mlxsw_reg_pmlp_pack(char *payload, u8 local_port)
2807{
2808 MLXSW_REG_ZERO(pmlp, payload);
2809 mlxsw_reg_pmlp_local_port_set(payload, local_port);
2810}
2811
2812
2813
2814
2815
2816#define MLXSW_REG_PMTU_ID 0x5003
2817#define MLXSW_REG_PMTU_LEN 0x10
2818
2819MLXSW_REG_DEFINE(pmtu, MLXSW_REG_PMTU_ID, MLXSW_REG_PMTU_LEN);
2820
2821
2822
2823
2824
2825MLXSW_ITEM32(reg, pmtu, local_port, 0x00, 16, 8);
2826
2827
2828
2829
2830
2831
2832
2833
2834MLXSW_ITEM32(reg, pmtu, max_mtu, 0x04, 16, 16);
2835
2836
2837
2838
2839
2840
2841
2842MLXSW_ITEM32(reg, pmtu, admin_mtu, 0x08, 16, 16);
2843
2844
2845
2846
2847
2848
2849
2850
2851MLXSW_ITEM32(reg, pmtu, oper_mtu, 0x0C, 16, 16);
2852
2853static inline void mlxsw_reg_pmtu_pack(char *payload, u8 local_port,
2854 u16 new_mtu)
2855{
2856 MLXSW_REG_ZERO(pmtu, payload);
2857 mlxsw_reg_pmtu_local_port_set(payload, local_port);
2858 mlxsw_reg_pmtu_max_mtu_set(payload, 0);
2859 mlxsw_reg_pmtu_admin_mtu_set(payload, new_mtu);
2860 mlxsw_reg_pmtu_oper_mtu_set(payload, 0);
2861}
2862
2863
2864
2865
2866
2867
2868
2869
2870#define MLXSW_REG_PTYS_ID 0x5004
2871#define MLXSW_REG_PTYS_LEN 0x40
2872
2873MLXSW_REG_DEFINE(ptys, MLXSW_REG_PTYS_ID, MLXSW_REG_PTYS_LEN);
2874
2875
2876
2877
2878
2879
2880
2881MLXSW_ITEM32(reg, ptys, an_disable_admin, 0x00, 30, 1);
2882
2883
2884
2885
2886
2887MLXSW_ITEM32(reg, ptys, local_port, 0x00, 16, 8);
2888
2889#define MLXSW_REG_PTYS_PROTO_MASK_IB BIT(0)
2890#define MLXSW_REG_PTYS_PROTO_MASK_ETH BIT(2)
2891
2892
2893
2894
2895
2896
2897
2898
2899MLXSW_ITEM32(reg, ptys, proto_mask, 0x00, 0, 3);
2900
2901enum {
2902 MLXSW_REG_PTYS_AN_STATUS_NA,
2903 MLXSW_REG_PTYS_AN_STATUS_OK,
2904 MLXSW_REG_PTYS_AN_STATUS_FAIL,
2905};
2906
2907
2908
2909
2910
2911MLXSW_ITEM32(reg, ptys, an_status, 0x04, 28, 4);
2912
2913#define MLXSW_REG_PTYS_ETH_SPEED_SGMII BIT(0)
2914#define MLXSW_REG_PTYS_ETH_SPEED_1000BASE_KX BIT(1)
2915#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CX4 BIT(2)
2916#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KX4 BIT(3)
2917#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_KR BIT(4)
2918#define MLXSW_REG_PTYS_ETH_SPEED_20GBASE_KR2 BIT(5)
2919#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_CR4 BIT(6)
2920#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_KR4 BIT(7)
2921#define MLXSW_REG_PTYS_ETH_SPEED_56GBASE_R4 BIT(8)
2922#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_CR BIT(12)
2923#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_SR BIT(13)
2924#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_ER_LR BIT(14)
2925#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_SR4 BIT(15)
2926#define MLXSW_REG_PTYS_ETH_SPEED_40GBASE_LR4_ER4 BIT(16)
2927#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_SR2 BIT(18)
2928#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR4 BIT(19)
2929#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_CR4 BIT(20)
2930#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_SR4 BIT(21)
2931#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_KR4 BIT(22)
2932#define MLXSW_REG_PTYS_ETH_SPEED_100GBASE_LR4_ER4 BIT(23)
2933#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_TX BIT(24)
2934#define MLXSW_REG_PTYS_ETH_SPEED_100BASE_T BIT(25)
2935#define MLXSW_REG_PTYS_ETH_SPEED_10GBASE_T BIT(26)
2936#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_CR BIT(27)
2937#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_KR BIT(28)
2938#define MLXSW_REG_PTYS_ETH_SPEED_25GBASE_SR BIT(29)
2939#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_CR2 BIT(30)
2940#define MLXSW_REG_PTYS_ETH_SPEED_50GBASE_KR2 BIT(31)
2941
2942
2943
2944
2945
2946MLXSW_ITEM32(reg, ptys, eth_proto_cap, 0x0C, 0, 32);
2947
2948
2949
2950
2951
2952MLXSW_ITEM32(reg, ptys, ib_link_width_cap, 0x10, 16, 16);
2953
2954#define MLXSW_REG_PTYS_IB_SPEED_SDR BIT(0)
2955#define MLXSW_REG_PTYS_IB_SPEED_DDR BIT(1)
2956#define MLXSW_REG_PTYS_IB_SPEED_QDR BIT(2)
2957#define MLXSW_REG_PTYS_IB_SPEED_FDR10 BIT(3)
2958#define MLXSW_REG_PTYS_IB_SPEED_FDR BIT(4)
2959#define MLXSW_REG_PTYS_IB_SPEED_EDR BIT(5)
2960
2961
2962
2963
2964
2965MLXSW_ITEM32(reg, ptys, ib_proto_cap, 0x10, 0, 16);
2966
2967
2968
2969
2970
2971MLXSW_ITEM32(reg, ptys, eth_proto_admin, 0x18, 0, 32);
2972
2973
2974
2975
2976
2977MLXSW_ITEM32(reg, ptys, ib_link_width_admin, 0x1C, 16, 16);
2978
2979
2980
2981
2982
2983MLXSW_ITEM32(reg, ptys, ib_proto_admin, 0x1C, 0, 16);
2984
2985
2986
2987
2988
2989MLXSW_ITEM32(reg, ptys, eth_proto_oper, 0x24, 0, 32);
2990
2991
2992
2993
2994
2995MLXSW_ITEM32(reg, ptys, ib_link_width_oper, 0x28, 16, 16);
2996
2997
2998
2999
3000
3001MLXSW_ITEM32(reg, ptys, ib_proto_oper, 0x28, 0, 16);
3002
3003
3004
3005
3006
3007
3008MLXSW_ITEM32(reg, ptys, eth_proto_lp_advertise, 0x30, 0, 32);
3009
3010static inline void mlxsw_reg_ptys_eth_pack(char *payload, u8 local_port,
3011 u32 proto_admin, bool autoneg)
3012{
3013 MLXSW_REG_ZERO(ptys, payload);
3014 mlxsw_reg_ptys_local_port_set(payload, local_port);
3015 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_ETH);
3016 mlxsw_reg_ptys_eth_proto_admin_set(payload, proto_admin);
3017 mlxsw_reg_ptys_an_disable_admin_set(payload, !autoneg);
3018}
3019
3020static inline void mlxsw_reg_ptys_eth_unpack(char *payload,
3021 u32 *p_eth_proto_cap,
3022 u32 *p_eth_proto_adm,
3023 u32 *p_eth_proto_oper)
3024{
3025 if (p_eth_proto_cap)
3026 *p_eth_proto_cap = mlxsw_reg_ptys_eth_proto_cap_get(payload);
3027 if (p_eth_proto_adm)
3028 *p_eth_proto_adm = mlxsw_reg_ptys_eth_proto_admin_get(payload);
3029 if (p_eth_proto_oper)
3030 *p_eth_proto_oper = mlxsw_reg_ptys_eth_proto_oper_get(payload);
3031}
3032
3033static inline void mlxsw_reg_ptys_ib_pack(char *payload, u8 local_port,
3034 u16 proto_admin, u16 link_width)
3035{
3036 MLXSW_REG_ZERO(ptys, payload);
3037 mlxsw_reg_ptys_local_port_set(payload, local_port);
3038 mlxsw_reg_ptys_proto_mask_set(payload, MLXSW_REG_PTYS_PROTO_MASK_IB);
3039 mlxsw_reg_ptys_ib_proto_admin_set(payload, proto_admin);
3040 mlxsw_reg_ptys_ib_link_width_admin_set(payload, link_width);
3041}
3042
3043static inline void mlxsw_reg_ptys_ib_unpack(char *payload, u16 *p_ib_proto_cap,
3044 u16 *p_ib_link_width_cap,
3045 u16 *p_ib_proto_oper,
3046 u16 *p_ib_link_width_oper)
3047{
3048 if (p_ib_proto_cap)
3049 *p_ib_proto_cap = mlxsw_reg_ptys_ib_proto_cap_get(payload);
3050 if (p_ib_link_width_cap)
3051 *p_ib_link_width_cap =
3052 mlxsw_reg_ptys_ib_link_width_cap_get(payload);
3053 if (p_ib_proto_oper)
3054 *p_ib_proto_oper = mlxsw_reg_ptys_ib_proto_oper_get(payload);
3055 if (p_ib_link_width_oper)
3056 *p_ib_link_width_oper =
3057 mlxsw_reg_ptys_ib_link_width_oper_get(payload);
3058}
3059
3060
3061
3062
3063
3064#define MLXSW_REG_PPAD_ID 0x5005
3065#define MLXSW_REG_PPAD_LEN 0x10
3066
3067MLXSW_REG_DEFINE(ppad, MLXSW_REG_PPAD_ID, MLXSW_REG_PPAD_LEN);
3068
3069
3070
3071
3072
3073
3074
3075MLXSW_ITEM32(reg, ppad, single_base_mac, 0x00, 28, 1);
3076
3077
3078
3079
3080
3081MLXSW_ITEM32(reg, ppad, local_port, 0x00, 16, 8);
3082
3083
3084
3085
3086
3087
3088MLXSW_ITEM_BUF(reg, ppad, mac, 0x02, 6);
3089
3090static inline void mlxsw_reg_ppad_pack(char *payload, bool single_base_mac,
3091 u8 local_port)
3092{
3093 MLXSW_REG_ZERO(ppad, payload);
3094 mlxsw_reg_ppad_single_base_mac_set(payload, !!single_base_mac);
3095 mlxsw_reg_ppad_local_port_set(payload, local_port);
3096}
3097
3098
3099
3100
3101
3102#define MLXSW_REG_PAOS_ID 0x5006
3103#define MLXSW_REG_PAOS_LEN 0x10
3104
3105MLXSW_REG_DEFINE(paos, MLXSW_REG_PAOS_ID, MLXSW_REG_PAOS_LEN);
3106
3107
3108
3109
3110
3111
3112
3113
3114MLXSW_ITEM32(reg, paos, swid, 0x00, 24, 8);
3115
3116
3117
3118
3119
3120MLXSW_ITEM32(reg, paos, local_port, 0x00, 16, 8);
3121
3122
3123
3124
3125
3126
3127
3128
3129
3130
3131MLXSW_ITEM32(reg, paos, admin_status, 0x00, 8, 4);
3132
3133
3134
3135
3136
3137
3138
3139
3140
3141MLXSW_ITEM32(reg, paos, oper_status, 0x00, 0, 4);
3142
3143
3144
3145
3146
3147MLXSW_ITEM32(reg, paos, ase, 0x04, 31, 1);
3148
3149
3150
3151
3152
3153
3154MLXSW_ITEM32(reg, paos, ee, 0x04, 30, 1);
3155
3156
3157
3158
3159
3160
3161
3162
3163MLXSW_ITEM32(reg, paos, e, 0x04, 0, 2);
3164
3165static inline void mlxsw_reg_paos_pack(char *payload, u8 local_port,
3166 enum mlxsw_port_admin_status status)
3167{
3168 MLXSW_REG_ZERO(paos, payload);
3169 mlxsw_reg_paos_swid_set(payload, 0);
3170 mlxsw_reg_paos_local_port_set(payload, local_port);
3171 mlxsw_reg_paos_admin_status_set(payload, status);
3172 mlxsw_reg_paos_oper_status_set(payload, 0);
3173 mlxsw_reg_paos_ase_set(payload, 1);
3174 mlxsw_reg_paos_ee_set(payload, 1);
3175 mlxsw_reg_paos_e_set(payload, 1);
3176}
3177
3178
3179
3180
3181
3182#define MLXSW_REG_PFCC_ID 0x5007
3183#define MLXSW_REG_PFCC_LEN 0x20
3184
3185MLXSW_REG_DEFINE(pfcc, MLXSW_REG_PFCC_ID, MLXSW_REG_PFCC_LEN);
3186
3187
3188
3189
3190
3191MLXSW_ITEM32(reg, pfcc, local_port, 0x00, 16, 8);
3192
3193
3194
3195
3196
3197
3198
3199MLXSW_ITEM32(reg, pfcc, pnat, 0x00, 14, 2);
3200
3201
3202
3203
3204
3205
3206
3207
3208MLXSW_ITEM32(reg, pfcc, shl_cap, 0x00, 1, 1);
3209
3210
3211
3212
3213
3214
3215
3216
3217MLXSW_ITEM32(reg, pfcc, shl_opr, 0x00, 0, 1);
3218
3219
3220
3221
3222
3223
3224
3225
3226
3227
3228
3229MLXSW_ITEM32(reg, pfcc, ppan, 0x04, 28, 4);
3230
3231
3232
3233
3234
3235
3236MLXSW_ITEM32(reg, pfcc, prio_mask_tx, 0x04, 16, 8);
3237
3238
3239
3240
3241
3242
3243MLXSW_ITEM32(reg, pfcc, prio_mask_rx, 0x04, 0, 8);
3244
3245
3246
3247
3248
3249
3250
3251MLXSW_ITEM32(reg, pfcc, pptx, 0x08, 31, 1);
3252
3253
3254
3255
3256
3257
3258
3259MLXSW_ITEM32(reg, pfcc, aptx, 0x08, 30, 1);
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269
3270
3271MLXSW_ITEM32(reg, pfcc, pfctx, 0x08, 16, 8);
3272
3273
3274
3275
3276
3277
3278
3279MLXSW_ITEM32(reg, pfcc, pprx, 0x0C, 31, 1);
3280
3281
3282
3283
3284
3285
3286
3287MLXSW_ITEM32(reg, pfcc, aprx, 0x0C, 30, 1);
3288
3289
3290
3291
3292
3293
3294
3295
3296MLXSW_ITEM32(reg, pfcc, pfcrx, 0x0C, 16, 8);
3297
3298#define MLXSW_REG_PFCC_ALL_PRIO 0xFF
3299
3300static inline void mlxsw_reg_pfcc_prio_pack(char *payload, u8 pfc_en)
3301{
3302 mlxsw_reg_pfcc_prio_mask_tx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
3303 mlxsw_reg_pfcc_prio_mask_rx_set(payload, MLXSW_REG_PFCC_ALL_PRIO);
3304 mlxsw_reg_pfcc_pfctx_set(payload, pfc_en);
3305 mlxsw_reg_pfcc_pfcrx_set(payload, pfc_en);
3306}
3307
3308static inline void mlxsw_reg_pfcc_pack(char *payload, u8 local_port)
3309{
3310 MLXSW_REG_ZERO(pfcc, payload);
3311 mlxsw_reg_pfcc_local_port_set(payload, local_port);
3312}
3313
3314
3315
3316
3317
3318#define MLXSW_REG_PPCNT_ID 0x5008
3319#define MLXSW_REG_PPCNT_LEN 0x100
3320#define MLXSW_REG_PPCNT_COUNTERS_OFFSET 0x08
3321
3322MLXSW_REG_DEFINE(ppcnt, MLXSW_REG_PPCNT_ID, MLXSW_REG_PPCNT_LEN);
3323
3324
3325
3326
3327
3328
3329
3330
3331
3332
3333MLXSW_ITEM32(reg, ppcnt, swid, 0x00, 24, 8);
3334
3335
3336
3337
3338
3339
3340
3341MLXSW_ITEM32(reg, ppcnt, local_port, 0x00, 16, 8);
3342
3343
3344
3345
3346
3347
3348
3349MLXSW_ITEM32(reg, ppcnt, pnat, 0x00, 14, 2);
3350
3351enum mlxsw_reg_ppcnt_grp {
3352 MLXSW_REG_PPCNT_IEEE_8023_CNT = 0x0,
3353 MLXSW_REG_PPCNT_EXT_CNT = 0x5,
3354 MLXSW_REG_PPCNT_PRIO_CNT = 0x10,
3355 MLXSW_REG_PPCNT_TC_CNT = 0x11,
3356 MLXSW_REG_PPCNT_TC_CONG_TC = 0x13,
3357};
3358
3359
3360
3361
3362
3363
3364
3365
3366
3367
3368
3369
3370
3371
3372
3373
3374
3375MLXSW_ITEM32(reg, ppcnt, grp, 0x00, 0, 6);
3376
3377
3378
3379
3380
3381
3382
3383MLXSW_ITEM32(reg, ppcnt, clr, 0x04, 31, 1);
3384
3385
3386
3387
3388
3389
3390
3391
3392
3393MLXSW_ITEM32(reg, ppcnt, prio_tc, 0x04, 0, 5);
3394
3395
3396
3397
3398
3399
3400MLXSW_ITEM64(reg, ppcnt, a_frames_transmitted_ok,
3401 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
3402
3403
3404
3405
3406MLXSW_ITEM64(reg, ppcnt, a_frames_received_ok,
3407 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
3408
3409
3410
3411
3412MLXSW_ITEM64(reg, ppcnt, a_frame_check_sequence_errors,
3413 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x10, 0, 64);
3414
3415
3416
3417
3418MLXSW_ITEM64(reg, ppcnt, a_alignment_errors,
3419 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x18, 0, 64);
3420
3421
3422
3423
3424MLXSW_ITEM64(reg, ppcnt, a_octets_transmitted_ok,
3425 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
3426
3427
3428
3429
3430MLXSW_ITEM64(reg, ppcnt, a_octets_received_ok,
3431 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
3432
3433
3434
3435
3436MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_xmitted_ok,
3437 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x30, 0, 64);
3438
3439
3440
3441
3442MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_xmitted_ok,
3443 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x38, 0, 64);
3444
3445
3446
3447
3448MLXSW_ITEM64(reg, ppcnt, a_multicast_frames_received_ok,
3449 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x40, 0, 64);
3450
3451
3452
3453
3454MLXSW_ITEM64(reg, ppcnt, a_broadcast_frames_received_ok,
3455 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
3456
3457
3458
3459
3460MLXSW_ITEM64(reg, ppcnt, a_in_range_length_errors,
3461 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
3462
3463
3464
3465
3466MLXSW_ITEM64(reg, ppcnt, a_out_of_range_length_field,
3467 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
3468
3469
3470
3471
3472MLXSW_ITEM64(reg, ppcnt, a_frame_too_long_errors,
3473 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
3474
3475
3476
3477
3478MLXSW_ITEM64(reg, ppcnt, a_symbol_error_during_carrier,
3479 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
3480
3481
3482
3483
3484MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_transmitted,
3485 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
3486
3487
3488
3489
3490MLXSW_ITEM64(reg, ppcnt, a_mac_control_frames_received,
3491 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x78, 0, 64);
3492
3493
3494
3495
3496MLXSW_ITEM64(reg, ppcnt, a_unsupported_opcodes_received,
3497 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x80, 0, 64);
3498
3499
3500
3501
3502MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_received,
3503 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x88, 0, 64);
3504
3505
3506
3507
3508MLXSW_ITEM64(reg, ppcnt, a_pause_mac_ctrl_frames_transmitted,
3509 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x90, 0, 64);
3510
3511
3512
3513
3514
3515
3516MLXSW_ITEM64(reg, ppcnt, ecn_marked,
3517 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
3518
3519
3520
3521
3522
3523
3524MLXSW_ITEM64(reg, ppcnt, rx_octets,
3525 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
3526
3527
3528
3529
3530MLXSW_ITEM64(reg, ppcnt, rx_frames,
3531 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x20, 0, 64);
3532
3533
3534
3535
3536MLXSW_ITEM64(reg, ppcnt, tx_octets,
3537 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x28, 0, 64);
3538
3539
3540
3541
3542MLXSW_ITEM64(reg, ppcnt, tx_frames,
3543 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x48, 0, 64);
3544
3545
3546
3547
3548MLXSW_ITEM64(reg, ppcnt, rx_pause,
3549 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x50, 0, 64);
3550
3551
3552
3553
3554MLXSW_ITEM64(reg, ppcnt, rx_pause_duration,
3555 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x58, 0, 64);
3556
3557
3558
3559
3560MLXSW_ITEM64(reg, ppcnt, tx_pause,
3561 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x60, 0, 64);
3562
3563
3564
3565
3566MLXSW_ITEM64(reg, ppcnt, tx_pause_duration,
3567 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x68, 0, 64);
3568
3569
3570
3571
3572MLXSW_ITEM64(reg, ppcnt, tx_pause_transition,
3573 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x70, 0, 64);
3574
3575
3576
3577
3578
3579
3580
3581
3582
3583MLXSW_ITEM64(reg, ppcnt, tc_transmit_queue,
3584 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
3585
3586
3587
3588
3589
3590
3591MLXSW_ITEM64(reg, ppcnt, tc_no_buffer_discard_uc,
3592 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x08, 0, 64);
3593
3594
3595
3596
3597
3598
3599MLXSW_ITEM64(reg, ppcnt, wred_discard,
3600 MLXSW_REG_PPCNT_COUNTERS_OFFSET + 0x00, 0, 64);
3601
3602static inline void mlxsw_reg_ppcnt_pack(char *payload, u8 local_port,
3603 enum mlxsw_reg_ppcnt_grp grp,
3604 u8 prio_tc)
3605{
3606 MLXSW_REG_ZERO(ppcnt, payload);
3607 mlxsw_reg_ppcnt_swid_set(payload, 0);
3608 mlxsw_reg_ppcnt_local_port_set(payload, local_port);
3609 mlxsw_reg_ppcnt_pnat_set(payload, 0);
3610 mlxsw_reg_ppcnt_grp_set(payload, grp);
3611 mlxsw_reg_ppcnt_clr_set(payload, 0);
3612 mlxsw_reg_ppcnt_prio_tc_set(payload, prio_tc);
3613}
3614
3615
3616
3617
3618
3619#define MLXSW_REG_PLIB_ID 0x500A
3620#define MLXSW_REG_PLIB_LEN 0x10
3621
3622MLXSW_REG_DEFINE(plib, MLXSW_REG_PLIB_ID, MLXSW_REG_PLIB_LEN);
3623
3624
3625
3626
3627
3628MLXSW_ITEM32(reg, plib, local_port, 0x00, 16, 8);
3629
3630
3631
3632
3633
3634MLXSW_ITEM32(reg, plib, ib_port, 0x00, 0, 8);
3635
3636
3637
3638
3639
3640#define MLXSW_REG_PPTB_ID 0x500B
3641#define MLXSW_REG_PPTB_LEN 0x10
3642
3643MLXSW_REG_DEFINE(pptb, MLXSW_REG_PPTB_ID, MLXSW_REG_PPTB_LEN);
3644
3645enum {
3646 MLXSW_REG_PPTB_MM_UM,
3647 MLXSW_REG_PPTB_MM_UNICAST,
3648 MLXSW_REG_PPTB_MM_MULTICAST,
3649};
3650
3651
3652
3653
3654
3655
3656
3657
3658
3659
3660MLXSW_ITEM32(reg, pptb, mm, 0x00, 28, 2);
3661
3662
3663
3664
3665
3666MLXSW_ITEM32(reg, pptb, local_port, 0x00, 16, 8);
3667
3668
3669
3670
3671
3672MLXSW_ITEM32(reg, pptb, um, 0x00, 8, 1);
3673
3674
3675
3676
3677
3678
3679MLXSW_ITEM32(reg, pptb, pm, 0x00, 0, 8);
3680
3681
3682
3683
3684
3685
3686MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff, 0x04, 0x04, 4);
3687
3688
3689
3690
3691
3692
3693MLXSW_ITEM32(reg, pptb, pm_msb, 0x08, 24, 8);
3694
3695
3696
3697
3698
3699
3700
3701
3702MLXSW_ITEM32(reg, pptb, untagged_buff, 0x08, 0, 4);
3703
3704
3705
3706
3707
3708
3709MLXSW_ITEM_BIT_ARRAY(reg, pptb, prio_to_buff_msb, 0x0C, 0x04, 4);
3710
3711#define MLXSW_REG_PPTB_ALL_PRIO 0xFF
3712
3713static inline void mlxsw_reg_pptb_pack(char *payload, u8 local_port)
3714{
3715 MLXSW_REG_ZERO(pptb, payload);
3716 mlxsw_reg_pptb_mm_set(payload, MLXSW_REG_PPTB_MM_UM);
3717 mlxsw_reg_pptb_local_port_set(payload, local_port);
3718 mlxsw_reg_pptb_pm_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
3719 mlxsw_reg_pptb_pm_msb_set(payload, MLXSW_REG_PPTB_ALL_PRIO);
3720}
3721
3722static inline void mlxsw_reg_pptb_prio_to_buff_pack(char *payload, u8 prio,
3723 u8 buff)
3724{
3725 mlxsw_reg_pptb_prio_to_buff_set(payload, prio, buff);
3726 mlxsw_reg_pptb_prio_to_buff_msb_set(payload, prio, buff);
3727}
3728
3729
3730
3731
3732
3733
3734#define MLXSW_REG_PBMC_ID 0x500C
3735#define MLXSW_REG_PBMC_LEN 0x6C
3736
3737MLXSW_REG_DEFINE(pbmc, MLXSW_REG_PBMC_ID, MLXSW_REG_PBMC_LEN);
3738
3739
3740
3741
3742
3743MLXSW_ITEM32(reg, pbmc, local_port, 0x00, 16, 8);
3744
3745
3746
3747
3748
3749
3750MLXSW_ITEM32(reg, pbmc, xoff_timer_value, 0x04, 16, 16);
3751
3752
3753
3754
3755
3756
3757
3758MLXSW_ITEM32(reg, pbmc, xoff_refresh, 0x04, 0, 16);
3759
3760#define MLXSW_REG_PBMC_PORT_SHARED_BUF_IDX 11
3761
3762
3763
3764
3765
3766
3767
3768MLXSW_ITEM32_INDEXED(reg, pbmc, buf_lossy, 0x0C, 25, 1, 0x08, 0x00, false);
3769
3770
3771
3772
3773
3774
3775
3776
3777MLXSW_ITEM32_INDEXED(reg, pbmc, buf_epsb, 0x0C, 24, 1, 0x08, 0x00, false);
3778
3779
3780
3781
3782
3783
3784MLXSW_ITEM32_INDEXED(reg, pbmc, buf_size, 0x0C, 0, 16, 0x08, 0x00, false);
3785
3786
3787
3788
3789
3790
3791
3792
3793
3794
3795MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xoff_threshold, 0x0C, 16, 16,
3796 0x08, 0x04, false);
3797
3798
3799
3800
3801
3802
3803
3804
3805
3806
3807MLXSW_ITEM32_INDEXED(reg, pbmc, buf_xon_threshold, 0x0C, 0, 16,
3808 0x08, 0x04, false);
3809
3810static inline void mlxsw_reg_pbmc_pack(char *payload, u8 local_port,
3811 u16 xoff_timer_value, u16 xoff_refresh)
3812{
3813 MLXSW_REG_ZERO(pbmc, payload);
3814 mlxsw_reg_pbmc_local_port_set(payload, local_port);
3815 mlxsw_reg_pbmc_xoff_timer_value_set(payload, xoff_timer_value);
3816 mlxsw_reg_pbmc_xoff_refresh_set(payload, xoff_refresh);
3817}
3818
3819static inline void mlxsw_reg_pbmc_lossy_buffer_pack(char *payload,
3820 int buf_index,
3821 u16 size)
3822{
3823 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 1);
3824 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
3825 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
3826}
3827
3828static inline void mlxsw_reg_pbmc_lossless_buffer_pack(char *payload,
3829 int buf_index, u16 size,
3830 u16 threshold)
3831{
3832 mlxsw_reg_pbmc_buf_lossy_set(payload, buf_index, 0);
3833 mlxsw_reg_pbmc_buf_epsb_set(payload, buf_index, 0);
3834 mlxsw_reg_pbmc_buf_size_set(payload, buf_index, size);
3835 mlxsw_reg_pbmc_buf_xoff_threshold_set(payload, buf_index, threshold);
3836 mlxsw_reg_pbmc_buf_xon_threshold_set(payload, buf_index, threshold);
3837}
3838
3839
3840
3841
3842
3843
3844#define MLXSW_REG_PSPA_ID 0x500D
3845#define MLXSW_REG_PSPA_LEN 0x8
3846
3847MLXSW_REG_DEFINE(pspa, MLXSW_REG_PSPA_ID, MLXSW_REG_PSPA_LEN);
3848
3849
3850
3851
3852
3853MLXSW_ITEM32(reg, pspa, swid, 0x00, 24, 8);
3854
3855
3856
3857
3858
3859MLXSW_ITEM32(reg, pspa, local_port, 0x00, 16, 8);
3860
3861
3862
3863
3864
3865
3866MLXSW_ITEM32(reg, pspa, sub_port, 0x00, 8, 8);
3867
3868static inline void mlxsw_reg_pspa_pack(char *payload, u8 swid, u8 local_port)
3869{
3870 MLXSW_REG_ZERO(pspa, payload);
3871 mlxsw_reg_pspa_swid_set(payload, swid);
3872 mlxsw_reg_pspa_local_port_set(payload, local_port);
3873 mlxsw_reg_pspa_sub_port_set(payload, 0);
3874}
3875
3876
3877
3878
3879
3880#define MLXSW_REG_HTGT_ID 0x7002
3881#define MLXSW_REG_HTGT_LEN 0x20
3882
3883MLXSW_REG_DEFINE(htgt, MLXSW_REG_HTGT_ID, MLXSW_REG_HTGT_LEN);
3884
3885
3886
3887
3888
3889MLXSW_ITEM32(reg, htgt, swid, 0x00, 24, 8);
3890
3891#define MLXSW_REG_HTGT_PATH_TYPE_LOCAL 0x0
3892
3893
3894
3895
3896
3897MLXSW_ITEM32(reg, htgt, type, 0x00, 8, 4);
3898
3899enum mlxsw_reg_htgt_trap_group {
3900 MLXSW_REG_HTGT_TRAP_GROUP_EMAD,
3901 MLXSW_REG_HTGT_TRAP_GROUP_SX2_RX,
3902 MLXSW_REG_HTGT_TRAP_GROUP_SX2_CTRL,
3903 MLXSW_REG_HTGT_TRAP_GROUP_SP_STP,
3904 MLXSW_REG_HTGT_TRAP_GROUP_SP_LACP,
3905 MLXSW_REG_HTGT_TRAP_GROUP_SP_LLDP,
3906 MLXSW_REG_HTGT_TRAP_GROUP_SP_IGMP,
3907 MLXSW_REG_HTGT_TRAP_GROUP_SP_BGP,
3908 MLXSW_REG_HTGT_TRAP_GROUP_SP_OSPF,
3909 MLXSW_REG_HTGT_TRAP_GROUP_SP_PIM,
3910 MLXSW_REG_HTGT_TRAP_GROUP_SP_MULTICAST,
3911 MLXSW_REG_HTGT_TRAP_GROUP_SP_ARP,
3912 MLXSW_REG_HTGT_TRAP_GROUP_SP_HOST_MISS,
3913 MLXSW_REG_HTGT_TRAP_GROUP_SP_ROUTER_EXP,
3914 MLXSW_REG_HTGT_TRAP_GROUP_SP_REMOTE_ROUTE,
3915 MLXSW_REG_HTGT_TRAP_GROUP_SP_IP2ME,
3916 MLXSW_REG_HTGT_TRAP_GROUP_SP_DHCP,
3917 MLXSW_REG_HTGT_TRAP_GROUP_SP_RPF,
3918 MLXSW_REG_HTGT_TRAP_GROUP_SP_EVENT,
3919 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_MLD,
3920 MLXSW_REG_HTGT_TRAP_GROUP_SP_IPV6_ND,
3921};
3922
3923
3924
3925
3926
3927
3928
3929MLXSW_ITEM32(reg, htgt, trap_group, 0x00, 0, 8);
3930
3931enum {
3932 MLXSW_REG_HTGT_POLICER_DISABLE,
3933 MLXSW_REG_HTGT_POLICER_ENABLE,
3934};
3935
3936
3937
3938
3939
3940MLXSW_ITEM32(reg, htgt, pide, 0x04, 15, 1);
3941
3942#define MLXSW_REG_HTGT_INVALID_POLICER 0xff
3943
3944
3945
3946
3947
3948MLXSW_ITEM32(reg, htgt, pid, 0x04, 0, 8);
3949
3950#define MLXSW_REG_HTGT_TRAP_TO_CPU 0x0
3951
3952
3953
3954
3955
3956
3957
3958
3959
3960
3961MLXSW_ITEM32(reg, htgt, mirror_action, 0x08, 8, 2);
3962
3963
3964
3965
3966
3967MLXSW_ITEM32(reg, htgt, mirroring_agent, 0x08, 0, 3);
3968
3969#define MLXSW_REG_HTGT_DEFAULT_PRIORITY 0
3970
3971
3972
3973
3974
3975
3976
3977
3978
3979
3980
3981
3982MLXSW_ITEM32(reg, htgt, priority, 0x0C, 0, 4);
3983
3984#define MLXSW_REG_HTGT_DEFAULT_TC 7
3985
3986
3987
3988
3989
3990MLXSW_ITEM32(reg, htgt, local_path_cpu_tclass, 0x10, 16, 6);
3991
3992enum mlxsw_reg_htgt_local_path_rdq {
3993 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_CTRL = 0x13,
3994 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_RX = 0x14,
3995 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SX2_EMAD = 0x15,
3996 MLXSW_REG_HTGT_LOCAL_PATH_RDQ_SIB_EMAD = 0x15,
3997};
3998
3999
4000
4001
4002MLXSW_ITEM32(reg, htgt, local_path_rdq, 0x10, 0, 6);
4003
4004static inline void mlxsw_reg_htgt_pack(char *payload, u8 group, u8 policer_id,
4005 u8 priority, u8 tc)
4006{
4007 MLXSW_REG_ZERO(htgt, payload);
4008
4009 if (policer_id == MLXSW_REG_HTGT_INVALID_POLICER) {
4010 mlxsw_reg_htgt_pide_set(payload,
4011 MLXSW_REG_HTGT_POLICER_DISABLE);
4012 } else {
4013 mlxsw_reg_htgt_pide_set(payload,
4014 MLXSW_REG_HTGT_POLICER_ENABLE);
4015 mlxsw_reg_htgt_pid_set(payload, policer_id);
4016 }
4017
4018 mlxsw_reg_htgt_type_set(payload, MLXSW_REG_HTGT_PATH_TYPE_LOCAL);
4019 mlxsw_reg_htgt_trap_group_set(payload, group);
4020 mlxsw_reg_htgt_mirror_action_set(payload, MLXSW_REG_HTGT_TRAP_TO_CPU);
4021 mlxsw_reg_htgt_mirroring_agent_set(payload, 0);
4022 mlxsw_reg_htgt_priority_set(payload, priority);
4023 mlxsw_reg_htgt_local_path_cpu_tclass_set(payload, tc);
4024 mlxsw_reg_htgt_local_path_rdq_set(payload, group);
4025}
4026
4027
4028
4029
4030
4031#define MLXSW_REG_HPKT_ID 0x7003
4032#define MLXSW_REG_HPKT_LEN 0x10
4033
4034MLXSW_REG_DEFINE(hpkt, MLXSW_REG_HPKT_ID, MLXSW_REG_HPKT_LEN);
4035
4036enum {
4037 MLXSW_REG_HPKT_ACK_NOT_REQUIRED,
4038 MLXSW_REG_HPKT_ACK_REQUIRED,
4039};
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049MLXSW_ITEM32(reg, hpkt, ack, 0x00, 24, 1);
4050
4051enum mlxsw_reg_hpkt_action {
4052 MLXSW_REG_HPKT_ACTION_FORWARD,
4053 MLXSW_REG_HPKT_ACTION_TRAP_TO_CPU,
4054 MLXSW_REG_HPKT_ACTION_MIRROR_TO_CPU,
4055 MLXSW_REG_HPKT_ACTION_DISCARD,
4056 MLXSW_REG_HPKT_ACTION_SOFT_DISCARD,
4057 MLXSW_REG_HPKT_ACTION_TRAP_AND_SOFT_DISCARD,
4058};
4059
4060
4061
4062
4063
4064
4065
4066
4067
4068
4069
4070
4071
4072
4073MLXSW_ITEM32(reg, hpkt, action, 0x00, 20, 3);
4074
4075
4076
4077
4078
4079MLXSW_ITEM32(reg, hpkt, trap_group, 0x00, 12, 6);
4080
4081
4082
4083
4084
4085
4086
4087
4088MLXSW_ITEM32(reg, hpkt, trap_id, 0x00, 0, 9);
4089
4090enum {
4091 MLXSW_REG_HPKT_CTRL_PACKET_DEFAULT,
4092 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER,
4093 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER,
4094};
4095
4096
4097
4098
4099
4100
4101
4102
4103
4104MLXSW_ITEM32(reg, hpkt, ctrl, 0x04, 16, 2);
4105
4106static inline void mlxsw_reg_hpkt_pack(char *payload, u8 action, u16 trap_id,
4107 enum mlxsw_reg_htgt_trap_group trap_group,
4108 bool is_ctrl)
4109{
4110 MLXSW_REG_ZERO(hpkt, payload);
4111 mlxsw_reg_hpkt_ack_set(payload, MLXSW_REG_HPKT_ACK_NOT_REQUIRED);
4112 mlxsw_reg_hpkt_action_set(payload, action);
4113 mlxsw_reg_hpkt_trap_group_set(payload, trap_group);
4114 mlxsw_reg_hpkt_trap_id_set(payload, trap_id);
4115 mlxsw_reg_hpkt_ctrl_set(payload, is_ctrl ?
4116 MLXSW_REG_HPKT_CTRL_PACKET_USE_BUFFER :
4117 MLXSW_REG_HPKT_CTRL_PACKET_NO_BUFFER);
4118}
4119
4120
4121
4122
4123
4124#define MLXSW_REG_RGCR_ID 0x8001
4125#define MLXSW_REG_RGCR_LEN 0x28
4126
4127MLXSW_REG_DEFINE(rgcr, MLXSW_REG_RGCR_ID, MLXSW_REG_RGCR_LEN);
4128
4129
4130
4131
4132
4133MLXSW_ITEM32(reg, rgcr, ipv4_en, 0x00, 31, 1);
4134
4135
4136
4137
4138
4139MLXSW_ITEM32(reg, rgcr, ipv6_en, 0x00, 30, 1);
4140
4141
4142
4143
4144
4145
4146MLXSW_ITEM32(reg, rgcr, max_router_interfaces, 0x10, 0, 16);
4147
4148
4149
4150
4151
4152
4153
4154
4155
4156MLXSW_ITEM32(reg, rgcr, usp, 0x18, 20, 1);
4157
4158
4159
4160
4161
4162
4163
4164
4165
4166
4167MLXSW_ITEM32(reg, rgcr, pcp_rw, 0x18, 16, 2);
4168
4169
4170
4171
4172
4173
4174
4175
4176
4177
4178
4179
4180
4181
4182
4183MLXSW_ITEM32(reg, rgcr, activity_dis, 0x20, 0, 8);
4184
4185static inline void mlxsw_reg_rgcr_pack(char *payload, bool ipv4_en,
4186 bool ipv6_en)
4187{
4188 MLXSW_REG_ZERO(rgcr, payload);
4189 mlxsw_reg_rgcr_ipv4_en_set(payload, ipv4_en);
4190 mlxsw_reg_rgcr_ipv6_en_set(payload, ipv6_en);
4191}
4192
4193
4194
4195
4196
4197#define MLXSW_REG_RITR_ID 0x8002
4198#define MLXSW_REG_RITR_LEN 0x40
4199
4200MLXSW_REG_DEFINE(ritr, MLXSW_REG_RITR_ID, MLXSW_REG_RITR_LEN);
4201
4202
4203
4204
4205
4206MLXSW_ITEM32(reg, ritr, enable, 0x00, 31, 1);
4207
4208
4209
4210
4211
4212
4213MLXSW_ITEM32(reg, ritr, ipv4, 0x00, 29, 1);
4214
4215
4216
4217
4218
4219
4220MLXSW_ITEM32(reg, ritr, ipv6, 0x00, 28, 1);
4221
4222
4223
4224
4225
4226MLXSW_ITEM32(reg, ritr, ipv4_mc, 0x00, 27, 1);
4227
4228
4229
4230
4231
4232MLXSW_ITEM32(reg, ritr, ipv6_mc, 0x00, 26, 1);
4233
4234enum mlxsw_reg_ritr_if_type {
4235
4236 MLXSW_REG_RITR_VLAN_IF,
4237
4238 MLXSW_REG_RITR_FID_IF,
4239
4240 MLXSW_REG_RITR_SP_IF,
4241
4242 MLXSW_REG_RITR_LOOPBACK_IF,
4243};
4244
4245
4246
4247
4248
4249MLXSW_ITEM32(reg, ritr, type, 0x00, 23, 3);
4250
4251enum {
4252 MLXSW_REG_RITR_RIF_CREATE,
4253 MLXSW_REG_RITR_RIF_DEL,
4254};
4255
4256
4257
4258
4259
4260
4261
4262
4263
4264
4265MLXSW_ITEM32(reg, ritr, op, 0x00, 20, 2);
4266
4267
4268
4269
4270
4271MLXSW_ITEM32(reg, ritr, rif, 0x00, 0, 16);
4272
4273
4274
4275
4276
4277
4278
4279
4280MLXSW_ITEM32(reg, ritr, ipv4_fe, 0x04, 29, 1);
4281
4282
4283
4284
4285
4286
4287
4288
4289MLXSW_ITEM32(reg, ritr, ipv6_fe, 0x04, 28, 1);
4290
4291
4292
4293
4294
4295
4296
4297MLXSW_ITEM32(reg, ritr, ipv4_mc_fe, 0x04, 27, 1);
4298
4299
4300
4301
4302
4303
4304
4305MLXSW_ITEM32(reg, ritr, ipv6_mc_fe, 0x04, 26, 1);
4306
4307
4308
4309
4310
4311
4312
4313
4314MLXSW_ITEM32(reg, ritr, lb_en, 0x04, 24, 1);
4315
4316
4317
4318
4319
4320MLXSW_ITEM32(reg, ritr, virtual_router, 0x04, 0, 16);
4321
4322
4323
4324
4325
4326MLXSW_ITEM32(reg, ritr, mtu, 0x34, 0, 16);
4327
4328
4329
4330
4331
4332MLXSW_ITEM32(reg, ritr, if_swid, 0x08, 24, 8);
4333
4334
4335
4336
4337
4338
4339MLXSW_ITEM_BUF(reg, ritr, if_mac, 0x12, 6);
4340
4341
4342
4343
4344
4345
4346
4347MLXSW_ITEM32(reg, ritr, vlan_if_vid, 0x08, 0, 12);
4348
4349
4350
4351
4352
4353
4354
4355
4356MLXSW_ITEM32(reg, ritr, fid_if_fid, 0x08, 0, 16);
4357
4358static inline void mlxsw_reg_ritr_fid_set(char *payload,
4359 enum mlxsw_reg_ritr_if_type rif_type,
4360 u16 fid)
4361{
4362 if (rif_type == MLXSW_REG_RITR_FID_IF)
4363 mlxsw_reg_ritr_fid_if_fid_set(payload, fid);
4364 else
4365 mlxsw_reg_ritr_vlan_if_vid_set(payload, fid);
4366}
4367
4368
4369
4370
4371
4372
4373
4374
4375MLXSW_ITEM32(reg, ritr, sp_if_lag, 0x08, 24, 1);
4376
4377
4378
4379
4380
4381
4382MLXSW_ITEM32(reg, ritr, sp_if_system_port, 0x08, 0, 16);
4383
4384
4385
4386
4387
4388MLXSW_ITEM32(reg, ritr, sp_if_vid, 0x18, 0, 12);
4389
4390
4391
4392enum mlxsw_reg_ritr_loopback_protocol {
4393
4394 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4,
4395
4396 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV6,
4397};
4398
4399
4400
4401
4402MLXSW_ITEM32(reg, ritr, loopback_protocol, 0x08, 28, 4);
4403
4404enum mlxsw_reg_ritr_loopback_ipip_type {
4405
4406 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_IP,
4407
4408 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_IN_IP,
4409
4410 MLXSW_REG_RITR_LOOPBACK_IPIP_TYPE_IP_IN_GRE_KEY_IN_IP,
4411};
4412
4413
4414
4415
4416
4417MLXSW_ITEM32(reg, ritr, loopback_ipip_type, 0x10, 24, 4);
4418
4419enum mlxsw_reg_ritr_loopback_ipip_options {
4420
4421 MLXSW_REG_RITR_LOOPBACK_IPIP_OPTIONS_GRE_KEY_PRESET,
4422};
4423
4424
4425
4426
4427MLXSW_ITEM32(reg, ritr, loopback_ipip_options, 0x10, 20, 4);
4428
4429
4430
4431
4432
4433
4434
4435MLXSW_ITEM32(reg, ritr, loopback_ipip_uvr, 0x10, 0, 16);
4436
4437
4438
4439
4440
4441MLXSW_ITEM_BUF(reg, ritr, loopback_ipip_usip6, 0x18, 16);
4442MLXSW_ITEM32(reg, ritr, loopback_ipip_usip4, 0x24, 0, 32);
4443
4444
4445
4446
4447
4448
4449MLXSW_ITEM32(reg, ritr, loopback_ipip_gre_key, 0x28, 0, 32);
4450
4451
4452enum mlxsw_reg_ritr_counter_set_type {
4453
4454 MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT = 0x0,
4455
4456
4457
4458
4459
4460
4461 MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC = 0x9,
4462};
4463
4464
4465
4466
4467
4468MLXSW_ITEM32(reg, ritr, ingress_counter_index, 0x38, 0, 24);
4469
4470
4471
4472
4473
4474MLXSW_ITEM32(reg, ritr, ingress_counter_set_type, 0x38, 24, 8);
4475
4476
4477
4478
4479
4480MLXSW_ITEM32(reg, ritr, egress_counter_index, 0x3C, 0, 24);
4481
4482
4483
4484
4485
4486MLXSW_ITEM32(reg, ritr, egress_counter_set_type, 0x3C, 24, 8);
4487
4488static inline void mlxsw_reg_ritr_counter_pack(char *payload, u32 index,
4489 bool enable, bool egress)
4490{
4491 enum mlxsw_reg_ritr_counter_set_type set_type;
4492
4493 if (enable)
4494 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_BASIC;
4495 else
4496 set_type = MLXSW_REG_RITR_COUNTER_SET_TYPE_NO_COUNT;
4497 mlxsw_reg_ritr_egress_counter_set_type_set(payload, set_type);
4498
4499 if (egress)
4500 mlxsw_reg_ritr_egress_counter_index_set(payload, index);
4501 else
4502 mlxsw_reg_ritr_ingress_counter_index_set(payload, index);
4503}
4504
4505static inline void mlxsw_reg_ritr_rif_pack(char *payload, u16 rif)
4506{
4507 MLXSW_REG_ZERO(ritr, payload);
4508 mlxsw_reg_ritr_rif_set(payload, rif);
4509}
4510
4511static inline void mlxsw_reg_ritr_sp_if_pack(char *payload, bool lag,
4512 u16 system_port, u16 vid)
4513{
4514 mlxsw_reg_ritr_sp_if_lag_set(payload, lag);
4515 mlxsw_reg_ritr_sp_if_system_port_set(payload, system_port);
4516 mlxsw_reg_ritr_sp_if_vid_set(payload, vid);
4517}
4518
4519static inline void mlxsw_reg_ritr_pack(char *payload, bool enable,
4520 enum mlxsw_reg_ritr_if_type type,
4521 u16 rif, u16 vr_id, u16 mtu)
4522{
4523 bool op = enable ? MLXSW_REG_RITR_RIF_CREATE : MLXSW_REG_RITR_RIF_DEL;
4524
4525 MLXSW_REG_ZERO(ritr, payload);
4526 mlxsw_reg_ritr_enable_set(payload, enable);
4527 mlxsw_reg_ritr_ipv4_set(payload, 1);
4528 mlxsw_reg_ritr_ipv6_set(payload, 1);
4529 mlxsw_reg_ritr_ipv4_mc_set(payload, 1);
4530 mlxsw_reg_ritr_ipv6_mc_set(payload, 1);
4531 mlxsw_reg_ritr_type_set(payload, type);
4532 mlxsw_reg_ritr_op_set(payload, op);
4533 mlxsw_reg_ritr_rif_set(payload, rif);
4534 mlxsw_reg_ritr_ipv4_fe_set(payload, 1);
4535 mlxsw_reg_ritr_ipv6_fe_set(payload, 1);
4536 mlxsw_reg_ritr_ipv4_mc_fe_set(payload, 1);
4537 mlxsw_reg_ritr_ipv6_mc_fe_set(payload, 1);
4538 mlxsw_reg_ritr_lb_en_set(payload, 1);
4539 mlxsw_reg_ritr_virtual_router_set(payload, vr_id);
4540 mlxsw_reg_ritr_mtu_set(payload, mtu);
4541}
4542
4543static inline void mlxsw_reg_ritr_mac_pack(char *payload, const char *mac)
4544{
4545 mlxsw_reg_ritr_if_mac_memcpy_to(payload, mac);
4546}
4547
4548static inline void
4549mlxsw_reg_ritr_loopback_ipip_common_pack(char *payload,
4550 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
4551 enum mlxsw_reg_ritr_loopback_ipip_options options,
4552 u16 uvr_id, u32 gre_key)
4553{
4554 mlxsw_reg_ritr_loopback_ipip_type_set(payload, ipip_type);
4555 mlxsw_reg_ritr_loopback_ipip_options_set(payload, options);
4556 mlxsw_reg_ritr_loopback_ipip_uvr_set(payload, uvr_id);
4557 mlxsw_reg_ritr_loopback_ipip_gre_key_set(payload, gre_key);
4558}
4559
4560static inline void
4561mlxsw_reg_ritr_loopback_ipip4_pack(char *payload,
4562 enum mlxsw_reg_ritr_loopback_ipip_type ipip_type,
4563 enum mlxsw_reg_ritr_loopback_ipip_options options,
4564 u16 uvr_id, u32 usip, u32 gre_key)
4565{
4566 mlxsw_reg_ritr_loopback_protocol_set(payload,
4567 MLXSW_REG_RITR_LOOPBACK_PROTOCOL_IPIP_IPV4);
4568 mlxsw_reg_ritr_loopback_ipip_common_pack(payload, ipip_type, options,
4569 uvr_id, gre_key);
4570 mlxsw_reg_ritr_loopback_ipip_usip4_set(payload, usip);
4571}
4572
4573
4574
4575
4576
4577#define MLXSW_REG_RTAR_ID 0x8004
4578#define MLXSW_REG_RTAR_LEN 0x20
4579
4580MLXSW_REG_DEFINE(rtar, MLXSW_REG_RTAR_ID, MLXSW_REG_RTAR_LEN);
4581
4582enum mlxsw_reg_rtar_op {
4583 MLXSW_REG_RTAR_OP_ALLOCATE,
4584 MLXSW_REG_RTAR_OP_RESIZE,
4585 MLXSW_REG_RTAR_OP_DEALLOCATE,
4586};
4587
4588
4589
4590
4591MLXSW_ITEM32(reg, rtar, op, 0x00, 28, 4);
4592
4593enum mlxsw_reg_rtar_key_type {
4594 MLXSW_REG_RTAR_KEY_TYPE_IPV4_MULTICAST = 1,
4595 MLXSW_REG_RTAR_KEY_TYPE_IPV6_MULTICAST = 3
4596};
4597
4598
4599
4600
4601
4602MLXSW_ITEM32(reg, rtar, key_type, 0x00, 0, 8);
4603
4604
4605
4606
4607
4608
4609
4610
4611MLXSW_ITEM32(reg, rtar, region_size, 0x04, 0, 16);
4612
4613static inline void mlxsw_reg_rtar_pack(char *payload,
4614 enum mlxsw_reg_rtar_op op,
4615 enum mlxsw_reg_rtar_key_type key_type,
4616 u16 region_size)
4617{
4618 MLXSW_REG_ZERO(rtar, payload);
4619 mlxsw_reg_rtar_op_set(payload, op);
4620 mlxsw_reg_rtar_key_type_set(payload, key_type);
4621 mlxsw_reg_rtar_region_size_set(payload, region_size);
4622}
4623
4624
4625
4626
4627
4628
4629#define MLXSW_REG_RATR_ID 0x8008
4630#define MLXSW_REG_RATR_LEN 0x2C
4631
4632MLXSW_REG_DEFINE(ratr, MLXSW_REG_RATR_ID, MLXSW_REG_RATR_LEN);
4633
4634enum mlxsw_reg_ratr_op {
4635
4636 MLXSW_REG_RATR_OP_QUERY_READ = 0,
4637
4638 MLXSW_REG_RATR_OP_QUERY_READ_CLEAR = 2,
4639
4640 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY = 1,
4641
4642
4643
4644
4645
4646
4647 MLXSW_REG_RATR_OP_WRITE_WRITE_ENTRY_ON_ACTIVITY = 3,
4648};
4649
4650
4651
4652
4653
4654
4655
4656MLXSW_ITEM32(reg, ratr, op, 0x00, 28, 4);
4657
4658
4659
4660
4661
4662
4663
4664
4665
4666
4667
4668
4669
4670MLXSW_ITEM32(reg, ratr, v, 0x00, 24, 1);
4671
4672
4673
4674
4675
4676
4677MLXSW_ITEM32(reg, ratr, a, 0x00, 16, 1);
4678
4679enum mlxsw_reg_ratr_type {
4680
4681 MLXSW_REG_RATR_TYPE_ETHERNET,
4682
4683
4684
4685 MLXSW_REG_RATR_TYPE_IPOIB_UC,
4686
4687
4688
4689
4690 MLXSW_REG_RATR_TYPE_IPOIB_UC_W_GRH,
4691
4692
4693
4694 MLXSW_REG_RATR_TYPE_IPOIB_MC,
4695
4696
4697
4698 MLXSW_REG_RATR_TYPE_MPLS,
4699
4700
4701
4702 MLXSW_REG_RATR_TYPE_IPIP,
4703};
4704
4705
4706
4707
4708
4709MLXSW_ITEM32(reg, ratr, type, 0x04, 28, 4);
4710
4711
4712
4713
4714
4715
4716
4717
4718MLXSW_ITEM32(reg, ratr, adjacency_index_low, 0x04, 0, 16);
4719
4720
4721
4722
4723
4724MLXSW_ITEM32(reg, ratr, egress_router_interface, 0x08, 0, 16);
4725
4726enum mlxsw_reg_ratr_trap_action {
4727 MLXSW_REG_RATR_TRAP_ACTION_NOP,
4728 MLXSW_REG_RATR_TRAP_ACTION_TRAP,
4729 MLXSW_REG_RATR_TRAP_ACTION_MIRROR_TO_CPU,
4730 MLXSW_REG_RATR_TRAP_ACTION_MIRROR,
4731 MLXSW_REG_RATR_TRAP_ACTION_DISCARD_ERRORS,
4732};
4733
4734
4735
4736
4737
4738MLXSW_ITEM32(reg, ratr, trap_action, 0x0C, 28, 4);
4739
4740
4741
4742
4743
4744MLXSW_ITEM32(reg, ratr, adjacency_index_high, 0x0C, 16, 8);
4745
4746enum mlxsw_reg_ratr_trap_id {
4747 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS0,
4748 MLXSW_REG_RATR_TRAP_ID_RTR_EGRESS1,
4749};
4750
4751
4752
4753
4754
4755
4756
4757MLXSW_ITEM32(reg, ratr, trap_id, 0x0C, 0, 8);
4758
4759
4760
4761
4762
4763MLXSW_ITEM_BUF(reg, ratr, eth_destination_mac, 0x12, 6);
4764
4765enum mlxsw_reg_ratr_ipip_type {
4766
4767 MLXSW_REG_RATR_IPIP_TYPE_IPV4,
4768
4769 MLXSW_REG_RATR_IPIP_TYPE_IPV6,
4770};
4771
4772
4773
4774
4775
4776
4777MLXSW_ITEM32(reg, ratr, ipip_type, 0x10, 16, 4);
4778
4779
4780
4781
4782
4783
4784MLXSW_ITEM32(reg, ratr, ipip_ipv4_udip, 0x18, 0, 32);
4785
4786
4787
4788
4789
4790
4791MLXSW_ITEM32(reg, ratr, ipip_ipv6_ptr, 0x1C, 0, 24);
4792
4793enum mlxsw_reg_flow_counter_set_type {
4794
4795 MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT = 0x00,
4796
4797 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES = 0x03,
4798
4799 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS = 0x05,
4800};
4801
4802
4803
4804
4805
4806MLXSW_ITEM32(reg, ratr, counter_set_type, 0x28, 24, 8);
4807
4808
4809
4810
4811
4812MLXSW_ITEM32(reg, ratr, counter_index, 0x28, 0, 24);
4813
4814static inline void
4815mlxsw_reg_ratr_pack(char *payload,
4816 enum mlxsw_reg_ratr_op op, bool valid,
4817 enum mlxsw_reg_ratr_type type,
4818 u32 adjacency_index, u16 egress_rif)
4819{
4820 MLXSW_REG_ZERO(ratr, payload);
4821 mlxsw_reg_ratr_op_set(payload, op);
4822 mlxsw_reg_ratr_v_set(payload, valid);
4823 mlxsw_reg_ratr_type_set(payload, type);
4824 mlxsw_reg_ratr_adjacency_index_low_set(payload, adjacency_index);
4825 mlxsw_reg_ratr_adjacency_index_high_set(payload, adjacency_index >> 16);
4826 mlxsw_reg_ratr_egress_router_interface_set(payload, egress_rif);
4827}
4828
4829static inline void mlxsw_reg_ratr_eth_entry_pack(char *payload,
4830 const char *dest_mac)
4831{
4832 mlxsw_reg_ratr_eth_destination_mac_memcpy_to(payload, dest_mac);
4833}
4834
4835static inline void mlxsw_reg_ratr_ipip4_entry_pack(char *payload, u32 ipv4_udip)
4836{
4837 mlxsw_reg_ratr_ipip_type_set(payload, MLXSW_REG_RATR_IPIP_TYPE_IPV4);
4838 mlxsw_reg_ratr_ipip_ipv4_udip_set(payload, ipv4_udip);
4839}
4840
4841static inline void mlxsw_reg_ratr_counter_pack(char *payload, u64 counter_index,
4842 bool counter_enable)
4843{
4844 enum mlxsw_reg_flow_counter_set_type set_type;
4845
4846 if (counter_enable)
4847 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES;
4848 else
4849 set_type = MLXSW_REG_FLOW_COUNTER_SET_TYPE_NO_COUNT;
4850
4851 mlxsw_reg_ratr_counter_index_set(payload, counter_index);
4852 mlxsw_reg_ratr_counter_set_type_set(payload, set_type);
4853}
4854
4855
4856
4857
4858
4859#define MLXSW_REG_RDPM_ID 0x8009
4860#define MLXSW_REG_RDPM_BASE_LEN 0x00
4861#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN 0x01
4862#define MLXSW_REG_RDPM_DSCP_ENTRY_REC_MAX_COUNT 64
4863#define MLXSW_REG_RDPM_LEN 0x40
4864#define MLXSW_REG_RDPM_LAST_ENTRY (MLXSW_REG_RDPM_BASE_LEN + \
4865 MLXSW_REG_RDPM_LEN - \
4866 MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN)
4867
4868MLXSW_REG_DEFINE(rdpm, MLXSW_REG_RDPM_ID, MLXSW_REG_RDPM_LEN);
4869
4870
4871
4872
4873
4874MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_e, MLXSW_REG_RDPM_LAST_ENTRY, 7, 1,
4875 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4876
4877
4878
4879
4880
4881MLXSW_ITEM8_INDEXED(reg, rdpm, dscp_entry_prio, MLXSW_REG_RDPM_LAST_ENTRY, 0, 4,
4882 -MLXSW_REG_RDPM_DSCP_ENTRY_REC_LEN, 0x00, false);
4883
4884static inline void mlxsw_reg_rdpm_pack(char *payload, unsigned short index,
4885 u8 prio)
4886{
4887 mlxsw_reg_rdpm_dscp_entry_e_set(payload, index, 1);
4888 mlxsw_reg_rdpm_dscp_entry_prio_set(payload, index, prio);
4889}
4890
4891
4892
4893
4894
4895#define MLXSW_REG_RICNT_ID 0x800B
4896#define MLXSW_REG_RICNT_LEN 0x100
4897
4898MLXSW_REG_DEFINE(ricnt, MLXSW_REG_RICNT_ID, MLXSW_REG_RICNT_LEN);
4899
4900
4901
4902
4903
4904MLXSW_ITEM32(reg, ricnt, counter_index, 0x04, 0, 24);
4905
4906enum mlxsw_reg_ricnt_counter_set_type {
4907
4908 MLXSW_REG_RICNT_COUNTER_SET_TYPE_NO_COUNT = 0x00,
4909
4910
4911
4912
4913
4914
4915 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC = 0x09,
4916};
4917
4918
4919
4920
4921
4922MLXSW_ITEM32(reg, ricnt, counter_set_type, 0x04, 24, 8);
4923
4924enum mlxsw_reg_ricnt_opcode {
4925
4926 MLXSW_REG_RICNT_OPCODE_NOP = 0x00,
4927
4928
4929
4930 MLXSW_REG_RICNT_OPCODE_CLEAR = 0x08,
4931};
4932
4933
4934
4935
4936
4937MLXSW_ITEM32(reg, ricnt, op, 0x00, 28, 4);
4938
4939
4940
4941
4942
4943MLXSW_ITEM64(reg, ricnt, good_unicast_packets, 0x08, 0, 64);
4944
4945
4946
4947
4948
4949MLXSW_ITEM64(reg, ricnt, good_multicast_packets, 0x10, 0, 64);
4950
4951
4952
4953
4954
4955MLXSW_ITEM64(reg, ricnt, good_broadcast_packets, 0x18, 0, 64);
4956
4957
4958
4959
4960
4961
4962MLXSW_ITEM64(reg, ricnt, good_unicast_bytes, 0x20, 0, 64);
4963
4964
4965
4966
4967
4968
4969MLXSW_ITEM64(reg, ricnt, good_multicast_bytes, 0x28, 0, 64);
4970
4971
4972
4973
4974
4975
4976MLXSW_ITEM64(reg, ricnt, good_broadcast_bytes, 0x30, 0, 64);
4977
4978
4979
4980
4981
4982MLXSW_ITEM64(reg, ricnt, error_packets, 0x38, 0, 64);
4983
4984
4985
4986
4987
4988MLXSW_ITEM64(reg, ricnt, discard_packets, 0x40, 0, 64);
4989
4990
4991
4992
4993
4994
4995MLXSW_ITEM64(reg, ricnt, error_bytes, 0x48, 0, 64);
4996
4997
4998
4999
5000
5001
5002MLXSW_ITEM64(reg, ricnt, discard_bytes, 0x50, 0, 64);
5003
5004static inline void mlxsw_reg_ricnt_pack(char *payload, u32 index,
5005 enum mlxsw_reg_ricnt_opcode op)
5006{
5007 MLXSW_REG_ZERO(ricnt, payload);
5008 mlxsw_reg_ricnt_op_set(payload, op);
5009 mlxsw_reg_ricnt_counter_index_set(payload, index);
5010 mlxsw_reg_ricnt_counter_set_type_set(payload,
5011 MLXSW_REG_RICNT_COUNTER_SET_TYPE_BASIC);
5012}
5013
5014
5015
5016
5017
5018#define MLXSW_REG_RRCR_ID 0x800F
5019#define MLXSW_REG_RRCR_LEN 0x24
5020
5021MLXSW_REG_DEFINE(rrcr, MLXSW_REG_RRCR_ID, MLXSW_REG_RRCR_LEN);
5022
5023enum mlxsw_reg_rrcr_op {
5024
5025 MLXSW_REG_RRCR_OP_MOVE,
5026
5027 MLXSW_REG_RRCR_OP_COPY,
5028};
5029
5030
5031
5032
5033MLXSW_ITEM32(reg, rrcr, op, 0x00, 28, 4);
5034
5035
5036
5037
5038
5039MLXSW_ITEM32(reg, rrcr, offset, 0x00, 0, 16);
5040
5041
5042
5043
5044
5045MLXSW_ITEM32(reg, rrcr, size, 0x04, 0, 16);
5046
5047
5048
5049
5050
5051
5052MLXSW_ITEM32(reg, rrcr, table_id, 0x10, 0, 4);
5053
5054
5055
5056
5057
5058MLXSW_ITEM32(reg, rrcr, dest_offset, 0x20, 0, 16);
5059
5060static inline void mlxsw_reg_rrcr_pack(char *payload, enum mlxsw_reg_rrcr_op op,
5061 u16 offset, u16 size,
5062 enum mlxsw_reg_rtar_key_type table_id,
5063 u16 dest_offset)
5064{
5065 MLXSW_REG_ZERO(rrcr, payload);
5066 mlxsw_reg_rrcr_op_set(payload, op);
5067 mlxsw_reg_rrcr_offset_set(payload, offset);
5068 mlxsw_reg_rrcr_size_set(payload, size);
5069 mlxsw_reg_rrcr_table_id_set(payload, table_id);
5070 mlxsw_reg_rrcr_dest_offset_set(payload, dest_offset);
5071}
5072
5073
5074
5075
5076
5077#define MLXSW_REG_RALTA_ID 0x8010
5078#define MLXSW_REG_RALTA_LEN 0x04
5079
5080MLXSW_REG_DEFINE(ralta, MLXSW_REG_RALTA_ID, MLXSW_REG_RALTA_LEN);
5081
5082
5083
5084
5085
5086
5087
5088MLXSW_ITEM32(reg, ralta, op, 0x00, 28, 2);
5089
5090enum mlxsw_reg_ralxx_protocol {
5091 MLXSW_REG_RALXX_PROTOCOL_IPV4,
5092 MLXSW_REG_RALXX_PROTOCOL_IPV6,
5093};
5094
5095
5096
5097
5098
5099
5100MLXSW_ITEM32(reg, ralta, protocol, 0x00, 24, 4);
5101
5102
5103
5104
5105
5106
5107
5108MLXSW_ITEM32(reg, ralta, tree_id, 0x00, 0, 8);
5109
5110static inline void mlxsw_reg_ralta_pack(char *payload, bool alloc,
5111 enum mlxsw_reg_ralxx_protocol protocol,
5112 u8 tree_id)
5113{
5114 MLXSW_REG_ZERO(ralta, payload);
5115 mlxsw_reg_ralta_op_set(payload, !alloc);
5116 mlxsw_reg_ralta_protocol_set(payload, protocol);
5117 mlxsw_reg_ralta_tree_id_set(payload, tree_id);
5118}
5119
5120
5121
5122
5123
5124
5125
5126
5127
5128
5129#define MLXSW_REG_RALST_ID 0x8011
5130#define MLXSW_REG_RALST_LEN 0x104
5131
5132MLXSW_REG_DEFINE(ralst, MLXSW_REG_RALST_ID, MLXSW_REG_RALST_LEN);
5133
5134
5135
5136
5137
5138
5139
5140MLXSW_ITEM32(reg, ralst, root_bin, 0x00, 16, 8);
5141
5142
5143
5144
5145
5146MLXSW_ITEM32(reg, ralst, tree_id, 0x00, 0, 8);
5147
5148#define MLXSW_REG_RALST_BIN_NO_CHILD 0xff
5149#define MLXSW_REG_RALST_BIN_OFFSET 0x04
5150#define MLXSW_REG_RALST_BIN_COUNT 128
5151
5152
5153
5154
5155
5156
5157
5158MLXSW_ITEM16_INDEXED(reg, ralst, left_child_bin, 0x04, 8, 8, 0x02, 0x00, false);
5159
5160
5161
5162
5163
5164
5165
5166MLXSW_ITEM16_INDEXED(reg, ralst, right_child_bin, 0x04, 0, 8, 0x02, 0x00,
5167 false);
5168
5169static inline void mlxsw_reg_ralst_pack(char *payload, u8 root_bin, u8 tree_id)
5170{
5171 MLXSW_REG_ZERO(ralst, payload);
5172
5173
5174 memset(payload + MLXSW_REG_RALST_BIN_OFFSET,
5175 MLXSW_REG_RALST_BIN_NO_CHILD, MLXSW_REG_RALST_BIN_COUNT * 2);
5176
5177 mlxsw_reg_ralst_root_bin_set(payload, root_bin);
5178 mlxsw_reg_ralst_tree_id_set(payload, tree_id);
5179}
5180
5181static inline void mlxsw_reg_ralst_bin_pack(char *payload, u8 bin_number,
5182 u8 left_child_bin,
5183 u8 right_child_bin)
5184{
5185 int bin_index = bin_number - 1;
5186
5187 mlxsw_reg_ralst_left_child_bin_set(payload, bin_index, left_child_bin);
5188 mlxsw_reg_ralst_right_child_bin_set(payload, bin_index,
5189 right_child_bin);
5190}
5191
5192
5193
5194
5195
5196#define MLXSW_REG_RALTB_ID 0x8012
5197#define MLXSW_REG_RALTB_LEN 0x04
5198
5199MLXSW_REG_DEFINE(raltb, MLXSW_REG_RALTB_ID, MLXSW_REG_RALTB_LEN);
5200
5201
5202
5203
5204
5205
5206MLXSW_ITEM32(reg, raltb, virtual_router, 0x00, 16, 16);
5207
5208
5209
5210
5211
5212MLXSW_ITEM32(reg, raltb, protocol, 0x00, 12, 4);
5213
5214
5215
5216
5217
5218
5219
5220MLXSW_ITEM32(reg, raltb, tree_id, 0x00, 0, 8);
5221
5222static inline void mlxsw_reg_raltb_pack(char *payload, u16 virtual_router,
5223 enum mlxsw_reg_ralxx_protocol protocol,
5224 u8 tree_id)
5225{
5226 MLXSW_REG_ZERO(raltb, payload);
5227 mlxsw_reg_raltb_virtual_router_set(payload, virtual_router);
5228 mlxsw_reg_raltb_protocol_set(payload, protocol);
5229 mlxsw_reg_raltb_tree_id_set(payload, tree_id);
5230}
5231
5232
5233
5234
5235
5236
5237#define MLXSW_REG_RALUE_ID 0x8013
5238#define MLXSW_REG_RALUE_LEN 0x38
5239
5240MLXSW_REG_DEFINE(ralue, MLXSW_REG_RALUE_ID, MLXSW_REG_RALUE_LEN);
5241
5242
5243
5244
5245
5246MLXSW_ITEM32(reg, ralue, protocol, 0x00, 24, 4);
5247
5248enum mlxsw_reg_ralue_op {
5249
5250 MLXSW_REG_RALUE_OP_QUERY_READ = 0,
5251
5252
5253
5254 MLXSW_REG_RALUE_OP_QUERY_CLEAR = 1,
5255
5256
5257
5258
5259 MLXSW_REG_RALUE_OP_WRITE_WRITE = 0,
5260
5261
5262
5263
5264 MLXSW_REG_RALUE_OP_WRITE_UPDATE = 1,
5265
5266
5267
5268 MLXSW_REG_RALUE_OP_WRITE_CLEAR = 2,
5269
5270
5271
5272 MLXSW_REG_RALUE_OP_WRITE_DELETE = 3,
5273};
5274
5275
5276
5277
5278
5279MLXSW_ITEM32(reg, ralue, op, 0x00, 20, 3);
5280
5281
5282
5283
5284
5285
5286
5287
5288MLXSW_ITEM32(reg, ralue, a, 0x00, 16, 1);
5289
5290
5291
5292
5293
5294
5295MLXSW_ITEM32(reg, ralue, virtual_router, 0x04, 16, 16);
5296
5297#define MLXSW_REG_RALUE_OP_U_MASK_ENTRY_TYPE BIT(0)
5298#define MLXSW_REG_RALUE_OP_U_MASK_BMP_LEN BIT(1)
5299#define MLXSW_REG_RALUE_OP_U_MASK_ACTION BIT(2)
5300
5301
5302
5303
5304
5305
5306
5307
5308MLXSW_ITEM32(reg, ralue, op_u_mask, 0x04, 8, 3);
5309
5310
5311
5312
5313
5314
5315
5316MLXSW_ITEM32(reg, ralue, prefix_len, 0x08, 0, 8);
5317
5318
5319
5320
5321
5322
5323
5324
5325
5326MLXSW_ITEM32(reg, ralue, dip4, 0x18, 0, 32);
5327MLXSW_ITEM_BUF(reg, ralue, dip6, 0x0C, 16);
5328
5329enum mlxsw_reg_ralue_entry_type {
5330 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_ENTRY = 1,
5331 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY = 2,
5332 MLXSW_REG_RALUE_ENTRY_TYPE_MARKER_AND_ROUTE_ENTRY = 3,
5333};
5334
5335
5336
5337
5338
5339
5340MLXSW_ITEM32(reg, ralue, entry_type, 0x1C, 30, 2);
5341
5342
5343
5344
5345
5346
5347
5348
5349
5350MLXSW_ITEM32(reg, ralue, bmp_len, 0x1C, 16, 8);
5351
5352enum mlxsw_reg_ralue_action_type {
5353 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE,
5354 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL,
5355 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME,
5356};
5357
5358
5359
5360
5361
5362
5363
5364
5365
5366
5367MLXSW_ITEM32(reg, ralue, action_type, 0x1C, 0, 2);
5368
5369enum mlxsw_reg_ralue_trap_action {
5370 MLXSW_REG_RALUE_TRAP_ACTION_NOP,
5371 MLXSW_REG_RALUE_TRAP_ACTION_TRAP,
5372 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR_TO_CPU,
5373 MLXSW_REG_RALUE_TRAP_ACTION_MIRROR,
5374 MLXSW_REG_RALUE_TRAP_ACTION_DISCARD_ERROR,
5375};
5376
5377
5378
5379
5380
5381
5382MLXSW_ITEM32(reg, ralue, trap_action, 0x20, 28, 4);
5383
5384
5385
5386
5387
5388
5389
5390MLXSW_ITEM32(reg, ralue, trap_id, 0x20, 0, 9);
5391
5392
5393
5394
5395
5396
5397MLXSW_ITEM32(reg, ralue, adjacency_index, 0x24, 0, 24);
5398
5399
5400
5401
5402
5403
5404
5405
5406
5407MLXSW_ITEM32(reg, ralue, ecmp_size, 0x28, 0, 13);
5408
5409
5410
5411
5412
5413
5414MLXSW_ITEM32(reg, ralue, local_erif, 0x24, 0, 16);
5415
5416
5417
5418
5419
5420
5421
5422
5423
5424
5425
5426MLXSW_ITEM32(reg, ralue, ip2me_v, 0x24, 31, 1);
5427
5428
5429
5430
5431
5432
5433
5434MLXSW_ITEM32(reg, ralue, ip2me_tunnel_ptr, 0x24, 0, 24);
5435
5436static inline void mlxsw_reg_ralue_pack(char *payload,
5437 enum mlxsw_reg_ralxx_protocol protocol,
5438 enum mlxsw_reg_ralue_op op,
5439 u16 virtual_router, u8 prefix_len)
5440{
5441 MLXSW_REG_ZERO(ralue, payload);
5442 mlxsw_reg_ralue_protocol_set(payload, protocol);
5443 mlxsw_reg_ralue_op_set(payload, op);
5444 mlxsw_reg_ralue_virtual_router_set(payload, virtual_router);
5445 mlxsw_reg_ralue_prefix_len_set(payload, prefix_len);
5446 mlxsw_reg_ralue_entry_type_set(payload,
5447 MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
5448 mlxsw_reg_ralue_bmp_len_set(payload, prefix_len);
5449}
5450
5451static inline void mlxsw_reg_ralue_pack4(char *payload,
5452 enum mlxsw_reg_ralxx_protocol protocol,
5453 enum mlxsw_reg_ralue_op op,
5454 u16 virtual_router, u8 prefix_len,
5455 u32 dip)
5456{
5457 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
5458 mlxsw_reg_ralue_dip4_set(payload, dip);
5459}
5460
5461static inline void mlxsw_reg_ralue_pack6(char *payload,
5462 enum mlxsw_reg_ralxx_protocol protocol,
5463 enum mlxsw_reg_ralue_op op,
5464 u16 virtual_router, u8 prefix_len,
5465 const void *dip)
5466{
5467 mlxsw_reg_ralue_pack(payload, protocol, op, virtual_router, prefix_len);
5468 mlxsw_reg_ralue_dip6_memcpy_to(payload, dip);
5469}
5470
5471static inline void
5472mlxsw_reg_ralue_act_remote_pack(char *payload,
5473 enum mlxsw_reg_ralue_trap_action trap_action,
5474 u16 trap_id, u32 adjacency_index, u16 ecmp_size)
5475{
5476 mlxsw_reg_ralue_action_type_set(payload,
5477 MLXSW_REG_RALUE_ACTION_TYPE_REMOTE);
5478 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
5479 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
5480 mlxsw_reg_ralue_adjacency_index_set(payload, adjacency_index);
5481 mlxsw_reg_ralue_ecmp_size_set(payload, ecmp_size);
5482}
5483
5484static inline void
5485mlxsw_reg_ralue_act_local_pack(char *payload,
5486 enum mlxsw_reg_ralue_trap_action trap_action,
5487 u16 trap_id, u16 local_erif)
5488{
5489 mlxsw_reg_ralue_action_type_set(payload,
5490 MLXSW_REG_RALUE_ACTION_TYPE_LOCAL);
5491 mlxsw_reg_ralue_trap_action_set(payload, trap_action);
5492 mlxsw_reg_ralue_trap_id_set(payload, trap_id);
5493 mlxsw_reg_ralue_local_erif_set(payload, local_erif);
5494}
5495
5496static inline void
5497mlxsw_reg_ralue_act_ip2me_pack(char *payload)
5498{
5499 mlxsw_reg_ralue_action_type_set(payload,
5500 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
5501}
5502
5503static inline void
5504mlxsw_reg_ralue_act_ip2me_tun_pack(char *payload, u32 tunnel_ptr)
5505{
5506 mlxsw_reg_ralue_action_type_set(payload,
5507 MLXSW_REG_RALUE_ACTION_TYPE_IP2ME);
5508 mlxsw_reg_ralue_ip2me_v_set(payload, 1);
5509 mlxsw_reg_ralue_ip2me_tunnel_ptr_set(payload, tunnel_ptr);
5510}
5511
5512
5513
5514
5515
5516
5517#define MLXSW_REG_RAUHT_ID 0x8014
5518#define MLXSW_REG_RAUHT_LEN 0x74
5519
5520MLXSW_REG_DEFINE(rauht, MLXSW_REG_RAUHT_ID, MLXSW_REG_RAUHT_LEN);
5521
5522enum mlxsw_reg_rauht_type {
5523 MLXSW_REG_RAUHT_TYPE_IPV4,
5524 MLXSW_REG_RAUHT_TYPE_IPV6,
5525};
5526
5527
5528
5529
5530MLXSW_ITEM32(reg, rauht, type, 0x00, 24, 2);
5531
5532enum mlxsw_reg_rauht_op {
5533 MLXSW_REG_RAUHT_OP_QUERY_READ = 0,
5534
5535 MLXSW_REG_RAUHT_OP_QUERY_CLEAR_ON_READ = 1,
5536
5537
5538
5539 MLXSW_REG_RAUHT_OP_WRITE_ADD = 0,
5540
5541
5542
5543 MLXSW_REG_RAUHT_OP_WRITE_UPDATE = 1,
5544
5545
5546
5547
5548 MLXSW_REG_RAUHT_OP_WRITE_CLEAR_ACTIVITY = 2,
5549
5550 MLXSW_REG_RAUHT_OP_WRITE_DELETE = 3,
5551
5552 MLXSW_REG_RAUHT_OP_WRITE_DELETE_ALL = 4,
5553
5554
5555
5556};
5557
5558
5559
5560
5561MLXSW_ITEM32(reg, rauht, op, 0x00, 20, 3);
5562
5563
5564
5565
5566
5567
5568
5569
5570MLXSW_ITEM32(reg, rauht, a, 0x00, 16, 1);
5571
5572
5573
5574
5575
5576MLXSW_ITEM32(reg, rauht, rif, 0x00, 0, 16);
5577
5578
5579
5580
5581
5582MLXSW_ITEM32(reg, rauht, dip4, 0x1C, 0x0, 32);
5583MLXSW_ITEM_BUF(reg, rauht, dip6, 0x10, 16);
5584
5585enum mlxsw_reg_rauht_trap_action {
5586 MLXSW_REG_RAUHT_TRAP_ACTION_NOP,
5587 MLXSW_REG_RAUHT_TRAP_ACTION_TRAP,
5588 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR_TO_CPU,
5589 MLXSW_REG_RAUHT_TRAP_ACTION_MIRROR,
5590 MLXSW_REG_RAUHT_TRAP_ACTION_DISCARD_ERRORS,
5591};
5592
5593
5594
5595
5596MLXSW_ITEM32(reg, rauht, trap_action, 0x60, 28, 4);
5597
5598enum mlxsw_reg_rauht_trap_id {
5599 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS0,
5600 MLXSW_REG_RAUHT_TRAP_ID_RTR_EGRESS1,
5601};
5602
5603
5604
5605
5606
5607
5608
5609
5610MLXSW_ITEM32(reg, rauht, trap_id, 0x60, 0, 9);
5611
5612
5613
5614
5615
5616MLXSW_ITEM32(reg, rauht, counter_set_type, 0x68, 24, 8);
5617
5618
5619
5620
5621
5622MLXSW_ITEM32(reg, rauht, counter_index, 0x68, 0, 24);
5623
5624
5625
5626
5627
5628MLXSW_ITEM_BUF(reg, rauht, mac, 0x6E, 6);
5629
5630static inline void mlxsw_reg_rauht_pack(char *payload,
5631 enum mlxsw_reg_rauht_op op, u16 rif,
5632 const char *mac)
5633{
5634 MLXSW_REG_ZERO(rauht, payload);
5635 mlxsw_reg_rauht_op_set(payload, op);
5636 mlxsw_reg_rauht_rif_set(payload, rif);
5637 mlxsw_reg_rauht_mac_memcpy_to(payload, mac);
5638}
5639
5640static inline void mlxsw_reg_rauht_pack4(char *payload,
5641 enum mlxsw_reg_rauht_op op, u16 rif,
5642 const char *mac, u32 dip)
5643{
5644 mlxsw_reg_rauht_pack(payload, op, rif, mac);
5645 mlxsw_reg_rauht_dip4_set(payload, dip);
5646}
5647
5648static inline void mlxsw_reg_rauht_pack6(char *payload,
5649 enum mlxsw_reg_rauht_op op, u16 rif,
5650 const char *mac, const char *dip)
5651{
5652 mlxsw_reg_rauht_pack(payload, op, rif, mac);
5653 mlxsw_reg_rauht_type_set(payload, MLXSW_REG_RAUHT_TYPE_IPV6);
5654 mlxsw_reg_rauht_dip6_memcpy_to(payload, dip);
5655}
5656
5657static inline void mlxsw_reg_rauht_pack_counter(char *payload,
5658 u64 counter_index)
5659{
5660 mlxsw_reg_rauht_counter_index_set(payload, counter_index);
5661 mlxsw_reg_rauht_counter_set_type_set(payload,
5662 MLXSW_REG_FLOW_COUNTER_SET_TYPE_PACKETS_BYTES);
5663}
5664
5665
5666
5667
5668
5669
5670
5671#define MLXSW_REG_RALEU_ID 0x8015
5672#define MLXSW_REG_RALEU_LEN 0x28
5673
5674MLXSW_REG_DEFINE(raleu, MLXSW_REG_RALEU_ID, MLXSW_REG_RALEU_LEN);
5675
5676
5677
5678
5679
5680MLXSW_ITEM32(reg, raleu, protocol, 0x00, 24, 4);
5681
5682
5683
5684
5685
5686
5687MLXSW_ITEM32(reg, raleu, virtual_router, 0x00, 0, 16);
5688
5689
5690
5691
5692
5693MLXSW_ITEM32(reg, raleu, adjacency_index, 0x10, 0, 24);
5694
5695
5696
5697
5698
5699MLXSW_ITEM32(reg, raleu, ecmp_size, 0x14, 0, 13);
5700
5701
5702
5703
5704
5705MLXSW_ITEM32(reg, raleu, new_adjacency_index, 0x20, 0, 24);
5706
5707
5708
5709
5710
5711MLXSW_ITEM32(reg, raleu, new_ecmp_size, 0x24, 0, 13);
5712
5713static inline void mlxsw_reg_raleu_pack(char *payload,
5714 enum mlxsw_reg_ralxx_protocol protocol,
5715 u16 virtual_router,
5716 u32 adjacency_index, u16 ecmp_size,
5717 u32 new_adjacency_index,
5718 u16 new_ecmp_size)
5719{
5720 MLXSW_REG_ZERO(raleu, payload);
5721 mlxsw_reg_raleu_protocol_set(payload, protocol);
5722 mlxsw_reg_raleu_virtual_router_set(payload, virtual_router);
5723 mlxsw_reg_raleu_adjacency_index_set(payload, adjacency_index);
5724 mlxsw_reg_raleu_ecmp_size_set(payload, ecmp_size);
5725 mlxsw_reg_raleu_new_adjacency_index_set(payload, new_adjacency_index);
5726 mlxsw_reg_raleu_new_ecmp_size_set(payload, new_ecmp_size);
5727}
5728
5729
5730
5731
5732
5733
5734
5735
5736
5737
5738#define MLXSW_REG_RAUHTD_ID 0x8018
5739#define MLXSW_REG_RAUHTD_BASE_LEN 0x20
5740#define MLXSW_REG_RAUHTD_REC_LEN 0x20
5741#define MLXSW_REG_RAUHTD_REC_MAX_NUM 32
5742#define MLXSW_REG_RAUHTD_LEN (MLXSW_REG_RAUHTD_BASE_LEN + \
5743 MLXSW_REG_RAUHTD_REC_MAX_NUM * MLXSW_REG_RAUHTD_REC_LEN)
5744#define MLXSW_REG_RAUHTD_IPV4_ENT_PER_REC 4
5745
5746MLXSW_REG_DEFINE(rauhtd, MLXSW_REG_RAUHTD_ID, MLXSW_REG_RAUHTD_LEN);
5747
5748#define MLXSW_REG_RAUHTD_FILTER_A BIT(0)
5749#define MLXSW_REG_RAUHTD_FILTER_RIF BIT(3)
5750
5751
5752
5753
5754
5755
5756
5757
5758MLXSW_ITEM32(reg, rauhtd, filter_fields, 0x00, 0, 8);
5759
5760enum mlxsw_reg_rauhtd_op {
5761 MLXSW_REG_RAUHTD_OP_DUMP,
5762 MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR,
5763};
5764
5765
5766
5767
5768MLXSW_ITEM32(reg, rauhtd, op, 0x04, 24, 2);
5769
5770
5771
5772
5773
5774
5775
5776
5777
5778MLXSW_ITEM32(reg, rauhtd, num_rec, 0x04, 0, 8);
5779
5780
5781
5782
5783
5784
5785MLXSW_ITEM32(reg, rauhtd, entry_a, 0x08, 16, 1);
5786
5787enum mlxsw_reg_rauhtd_type {
5788 MLXSW_REG_RAUHTD_TYPE_IPV4,
5789 MLXSW_REG_RAUHTD_TYPE_IPV6,
5790};
5791
5792
5793
5794
5795
5796
5797
5798MLXSW_ITEM32(reg, rauhtd, type, 0x08, 0, 4);
5799
5800
5801
5802
5803
5804
5805MLXSW_ITEM32(reg, rauhtd, entry_rif, 0x0C, 0, 16);
5806
5807static inline void mlxsw_reg_rauhtd_pack(char *payload,
5808 enum mlxsw_reg_rauhtd_type type)
5809{
5810 MLXSW_REG_ZERO(rauhtd, payload);
5811 mlxsw_reg_rauhtd_filter_fields_set(payload, MLXSW_REG_RAUHTD_FILTER_A);
5812 mlxsw_reg_rauhtd_op_set(payload, MLXSW_REG_RAUHTD_OP_DUMP_AND_CLEAR);
5813 mlxsw_reg_rauhtd_num_rec_set(payload, MLXSW_REG_RAUHTD_REC_MAX_NUM);
5814 mlxsw_reg_rauhtd_entry_a_set(payload, 1);
5815 mlxsw_reg_rauhtd_type_set(payload, type);
5816}
5817
5818
5819
5820
5821
5822
5823
5824
5825
5826MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_rec_num_entries,
5827 MLXSW_REG_RAUHTD_BASE_LEN, 28, 2,
5828 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
5829
5830
5831
5832
5833
5834
5835
5836MLXSW_ITEM32_INDEXED(reg, rauhtd, rec_type, MLXSW_REG_RAUHTD_BASE_LEN, 24, 2,
5837 MLXSW_REG_RAUHTD_REC_LEN, 0x00, false);
5838
5839#define MLXSW_REG_RAUHTD_IPV4_ENT_LEN 0x8
5840
5841
5842
5843
5844
5845
5846MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
5847 MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
5848
5849
5850
5851
5852
5853MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
5854 16, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x00, false);
5855
5856
5857
5858
5859
5860MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv4_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN, 0,
5861 32, MLXSW_REG_RAUHTD_IPV4_ENT_LEN, 0x04, false);
5862
5863#define MLXSW_REG_RAUHTD_IPV6_ENT_LEN 0x20
5864
5865
5866
5867
5868
5869
5870MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_a, MLXSW_REG_RAUHTD_BASE_LEN, 16, 1,
5871 MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
5872
5873
5874
5875
5876
5877MLXSW_ITEM32_INDEXED(reg, rauhtd, ipv6_ent_rif, MLXSW_REG_RAUHTD_BASE_LEN, 0,
5878 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x00, false);
5879
5880
5881
5882
5883
5884MLXSW_ITEM_BUF_INDEXED(reg, rauhtd, ipv6_ent_dip, MLXSW_REG_RAUHTD_BASE_LEN,
5885 16, MLXSW_REG_RAUHTD_IPV6_ENT_LEN, 0x10);
5886
5887static inline void mlxsw_reg_rauhtd_ent_ipv4_unpack(char *payload,
5888 int ent_index, u16 *p_rif,
5889 u32 *p_dip)
5890{
5891 *p_rif = mlxsw_reg_rauhtd_ipv4_ent_rif_get(payload, ent_index);
5892 *p_dip = mlxsw_reg_rauhtd_ipv4_ent_dip_get(payload, ent_index);
5893}
5894
5895static inline void mlxsw_reg_rauhtd_ent_ipv6_unpack(char *payload,
5896 int rec_index, u16 *p_rif,
5897 char *p_dip)
5898{
5899 *p_rif = mlxsw_reg_rauhtd_ipv6_ent_rif_get(payload, rec_index);
5900 mlxsw_reg_rauhtd_ipv6_ent_dip_memcpy_from(payload, rec_index, p_dip);
5901}
5902
5903
5904
5905
5906
5907
5908#define MLXSW_REG_RTDP_ID 0x8020
5909#define MLXSW_REG_RTDP_LEN 0x44
5910
5911MLXSW_REG_DEFINE(rtdp, MLXSW_REG_RTDP_ID, MLXSW_REG_RTDP_LEN);
5912
5913enum mlxsw_reg_rtdp_type {
5914 MLXSW_REG_RTDP_TYPE_NVE,
5915 MLXSW_REG_RTDP_TYPE_IPIP,
5916};
5917
5918
5919
5920
5921
5922MLXSW_ITEM32(reg, rtdp, type, 0x00, 28, 4);
5923
5924
5925
5926
5927
5928
5929MLXSW_ITEM32(reg, rtdp, tunnel_index, 0x00, 0, 24);
5930
5931
5932
5933
5934
5935
5936
5937MLXSW_ITEM32(reg, rtdp, ipip_irif, 0x04, 16, 16);
5938
5939enum mlxsw_reg_rtdp_ipip_sip_check {
5940
5941 MLXSW_REG_RTDP_IPIP_SIP_CHECK_NO,
5942
5943
5944
5945 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV4,
5946
5947
5948
5949 MLXSW_REG_RTDP_IPIP_SIP_CHECK_FILTER_IPV6 = 3,
5950};
5951
5952
5953
5954
5955
5956
5957MLXSW_ITEM32(reg, rtdp, ipip_sip_check, 0x04, 0, 3);
5958
5959
5960#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_IPIP BIT(0)
5961
5962#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE BIT(1)
5963
5964#define MLXSW_REG_RTDP_IPIP_TYPE_CHECK_ALLOW_GRE_KEY BIT(2)
5965
5966
5967
5968
5969
5970
5971MLXSW_ITEM32(reg, rtdp, ipip_type_check, 0x08, 24, 3);
5972
5973
5974
5975
5976
5977
5978
5979
5980
5981
5982MLXSW_ITEM32(reg, rtdp, ipip_gre_key_check, 0x08, 23, 1);
5983
5984
5985
5986
5987
5988
5989MLXSW_ITEM32(reg, rtdp, ipip_ipv4_usip, 0x0C, 0, 32);
5990
5991
5992
5993
5994
5995
5996
5997
5998MLXSW_ITEM32(reg, rtdp, ipip_ipv6_usip_ptr, 0x10, 0, 24);
5999
6000
6001
6002
6003
6004
6005MLXSW_ITEM32(reg, rtdp, ipip_expected_gre_key, 0x14, 0, 32);
6006
6007static inline void mlxsw_reg_rtdp_pack(char *payload,
6008 enum mlxsw_reg_rtdp_type type,
6009 u32 tunnel_index)
6010{
6011 MLXSW_REG_ZERO(rtdp, payload);
6012 mlxsw_reg_rtdp_type_set(payload, type);
6013 mlxsw_reg_rtdp_tunnel_index_set(payload, tunnel_index);
6014}
6015
6016static inline void
6017mlxsw_reg_rtdp_ipip4_pack(char *payload, u16 irif,
6018 enum mlxsw_reg_rtdp_ipip_sip_check sip_check,
6019 unsigned int type_check, bool gre_key_check,
6020 u32 ipv4_usip, u32 expected_gre_key)
6021{
6022 mlxsw_reg_rtdp_ipip_irif_set(payload, irif);
6023 mlxsw_reg_rtdp_ipip_sip_check_set(payload, sip_check);
6024 mlxsw_reg_rtdp_ipip_type_check_set(payload, type_check);
6025 mlxsw_reg_rtdp_ipip_gre_key_check_set(payload, gre_key_check);
6026 mlxsw_reg_rtdp_ipip_ipv4_usip_set(payload, ipv4_usip);
6027 mlxsw_reg_rtdp_ipip_expected_gre_key_set(payload, expected_gre_key);
6028}
6029
6030
6031
6032
6033
6034
6035#define MLXSW_REG_RIGR2_ID 0x8023
6036#define MLXSW_REG_RIGR2_LEN 0xB0
6037
6038#define MLXSW_REG_RIGR2_MAX_ERIFS 32
6039
6040MLXSW_REG_DEFINE(rigr2, MLXSW_REG_RIGR2_ID, MLXSW_REG_RIGR2_LEN);
6041
6042
6043
6044
6045
6046MLXSW_ITEM32(reg, rigr2, rigr_index, 0x04, 0, 24);
6047
6048
6049
6050
6051
6052MLXSW_ITEM32(reg, rigr2, vnext, 0x08, 31, 1);
6053
6054
6055
6056
6057
6058
6059MLXSW_ITEM32(reg, rigr2, next_rigr_index, 0x08, 0, 24);
6060
6061
6062
6063
6064
6065MLXSW_ITEM32(reg, rigr2, vrmid, 0x20, 31, 1);
6066
6067
6068
6069
6070
6071
6072
6073
6074MLXSW_ITEM32(reg, rigr2, rmid_index, 0x20, 0, 16);
6075
6076
6077
6078
6079
6080
6081
6082
6083
6084MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_v, 0x24, 31, 1, 4, 0, false);
6085
6086
6087
6088
6089
6090
6091
6092MLXSW_ITEM32_INDEXED(reg, rigr2, erif_entry_erif, 0x24, 0, 16, 4, 0, false);
6093
6094static inline void mlxsw_reg_rigr2_pack(char *payload, u32 rigr_index,
6095 bool vnext, u32 next_rigr_index)
6096{
6097 MLXSW_REG_ZERO(rigr2, payload);
6098 mlxsw_reg_rigr2_rigr_index_set(payload, rigr_index);
6099 mlxsw_reg_rigr2_vnext_set(payload, vnext);
6100 mlxsw_reg_rigr2_next_rigr_index_set(payload, next_rigr_index);
6101 mlxsw_reg_rigr2_vrmid_set(payload, 0);
6102 mlxsw_reg_rigr2_rmid_index_set(payload, 0);
6103}
6104
6105static inline void mlxsw_reg_rigr2_erif_entry_pack(char *payload, int index,
6106 bool v, u16 erif)
6107{
6108 mlxsw_reg_rigr2_erif_entry_v_set(payload, index, v);
6109 mlxsw_reg_rigr2_erif_entry_erif_set(payload, index, erif);
6110}
6111
6112
6113
6114
6115#define MLXSW_REG_RECR2_ID 0x8025
6116#define MLXSW_REG_RECR2_LEN 0x38
6117
6118MLXSW_REG_DEFINE(recr2, MLXSW_REG_RECR2_ID, MLXSW_REG_RECR2_LEN);
6119
6120
6121
6122
6123
6124MLXSW_ITEM32(reg, recr2, pp, 0x00, 24, 1);
6125
6126
6127
6128
6129
6130MLXSW_ITEM32(reg, recr2, sh, 0x00, 8, 1);
6131
6132
6133
6134
6135
6136MLXSW_ITEM32(reg, recr2, seed, 0x08, 0, 32);
6137
6138enum {
6139
6140 MLXSW_REG_RECR2_IPV4_EN_NOT_TCP_NOT_UDP = 3,
6141
6142 MLXSW_REG_RECR2_IPV4_EN_TCP_UDP = 4,
6143
6144 MLXSW_REG_RECR2_IPV6_EN_NOT_TCP_NOT_UDP = 5,
6145
6146 MLXSW_REG_RECR2_IPV6_EN_TCP_UDP = 6,
6147
6148 MLXSW_REG_RECR2_TCP_UDP_EN_IPV4 = 7,
6149
6150 MLXSW_REG_RECR2_TCP_UDP_EN_IPV6 = 8,
6151};
6152
6153
6154
6155
6156
6157
6158MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_enables, 0x10, 0x04, 1);
6159
6160enum {
6161
6162 MLXSW_REG_RECR2_IPV4_SIP0 = 9,
6163 MLXSW_REG_RECR2_IPV4_SIP3 = 12,
6164
6165 MLXSW_REG_RECR2_IPV4_DIP0 = 13,
6166 MLXSW_REG_RECR2_IPV4_DIP3 = 16,
6167
6168 MLXSW_REG_RECR2_IPV4_PROTOCOL = 17,
6169
6170 MLXSW_REG_RECR2_IPV6_SIP0_7 = 21,
6171 MLXSW_REG_RECR2_IPV6_SIP8 = 29,
6172 MLXSW_REG_RECR2_IPV6_SIP15 = 36,
6173
6174 MLXSW_REG_RECR2_IPV6_DIP0_7 = 37,
6175 MLXSW_REG_RECR2_IPV6_DIP8 = 45,
6176 MLXSW_REG_RECR2_IPV6_DIP15 = 52,
6177
6178 MLXSW_REG_RECR2_IPV6_NEXT_HEADER = 53,
6179
6180 MLXSW_REG_RECR2_IPV6_FLOW_LABEL = 57,
6181
6182 MLXSW_REG_RECR2_TCP_UDP_SPORT = 74,
6183
6184 MLXSW_REG_RECR2_TCP_UDP_DPORT = 75,
6185};
6186
6187
6188
6189
6190
6191MLXSW_ITEM_BIT_ARRAY(reg, recr2, outer_header_fields_enable, 0x14, 0x14, 1);
6192
6193static inline void mlxsw_reg_recr2_ipv4_sip_enable(char *payload)
6194{
6195 int i;
6196
6197 for (i = MLXSW_REG_RECR2_IPV4_SIP0; i <= MLXSW_REG_RECR2_IPV4_SIP3; i++)
6198 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
6199 true);
6200}
6201
6202static inline void mlxsw_reg_recr2_ipv4_dip_enable(char *payload)
6203{
6204 int i;
6205
6206 for (i = MLXSW_REG_RECR2_IPV4_DIP0; i <= MLXSW_REG_RECR2_IPV4_DIP3; i++)
6207 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
6208 true);
6209}
6210
6211static inline void mlxsw_reg_recr2_ipv6_sip_enable(char *payload)
6212{
6213 int i = MLXSW_REG_RECR2_IPV6_SIP0_7;
6214
6215 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
6216
6217 i = MLXSW_REG_RECR2_IPV6_SIP8;
6218 for (; i <= MLXSW_REG_RECR2_IPV6_SIP15; i++)
6219 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
6220 true);
6221}
6222
6223static inline void mlxsw_reg_recr2_ipv6_dip_enable(char *payload)
6224{
6225 int i = MLXSW_REG_RECR2_IPV6_DIP0_7;
6226
6227 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i, true);
6228
6229 i = MLXSW_REG_RECR2_IPV6_DIP8;
6230 for (; i <= MLXSW_REG_RECR2_IPV6_DIP15; i++)
6231 mlxsw_reg_recr2_outer_header_fields_enable_set(payload, i,
6232 true);
6233}
6234
6235static inline void mlxsw_reg_recr2_pack(char *payload, u32 seed)
6236{
6237 MLXSW_REG_ZERO(recr2, payload);
6238 mlxsw_reg_recr2_pp_set(payload, false);
6239 mlxsw_reg_recr2_sh_set(payload, true);
6240 mlxsw_reg_recr2_seed_set(payload, seed);
6241}
6242
6243
6244
6245
6246
6247#define MLXSW_REG_RMFT2_ID 0x8027
6248#define MLXSW_REG_RMFT2_LEN 0x174
6249
6250MLXSW_REG_DEFINE(rmft2, MLXSW_REG_RMFT2_ID, MLXSW_REG_RMFT2_LEN);
6251
6252
6253
6254
6255
6256MLXSW_ITEM32(reg, rmft2, v, 0x00, 31, 1);
6257
6258enum mlxsw_reg_rmft2_type {
6259 MLXSW_REG_RMFT2_TYPE_IPV4,
6260 MLXSW_REG_RMFT2_TYPE_IPV6
6261};
6262
6263
6264
6265
6266MLXSW_ITEM32(reg, rmft2, type, 0x00, 28, 2);
6267
6268enum mlxsw_sp_reg_rmft2_op {
6269
6270
6271
6272
6273
6274
6275
6276 MLXSW_REG_RMFT2_OP_READ_WRITE,
6277};
6278
6279
6280
6281
6282
6283MLXSW_ITEM32(reg, rmft2, op, 0x00, 20, 2);
6284
6285
6286
6287
6288
6289
6290MLXSW_ITEM32(reg, rmft2, a, 0x00, 16, 1);
6291
6292
6293
6294
6295
6296MLXSW_ITEM32(reg, rmft2, offset, 0x00, 0, 16);
6297
6298
6299
6300
6301
6302MLXSW_ITEM32(reg, rmft2, virtual_router, 0x04, 0, 16);
6303
6304enum mlxsw_reg_rmft2_irif_mask {
6305 MLXSW_REG_RMFT2_IRIF_MASK_IGNORE,
6306 MLXSW_REG_RMFT2_IRIF_MASK_COMPARE
6307};
6308
6309
6310
6311
6312
6313MLXSW_ITEM32(reg, rmft2, irif_mask, 0x08, 24, 1);
6314
6315
6316
6317
6318
6319MLXSW_ITEM32(reg, rmft2, irif, 0x08, 0, 16);
6320
6321
6322
6323
6324
6325MLXSW_ITEM_BUF(reg, rmft2, dip6, 0x10, 16);
6326MLXSW_ITEM32(reg, rmft2, dip4, 0x1C, 0, 32);
6327
6328
6329
6330
6331
6332
6333MLXSW_ITEM_BUF(reg, rmft2, dip6_mask, 0x20, 16);
6334MLXSW_ITEM32(reg, rmft2, dip4_mask, 0x2C, 0, 32);
6335
6336
6337
6338
6339
6340MLXSW_ITEM_BUF(reg, rmft2, sip6, 0x30, 16);
6341MLXSW_ITEM32(reg, rmft2, sip4, 0x3C, 0, 32);
6342
6343
6344
6345
6346
6347
6348MLXSW_ITEM_BUF(reg, rmft2, sip6_mask, 0x40, 16);
6349MLXSW_ITEM32(reg, rmft2, sip4_mask, 0x4C, 0, 32);
6350
6351
6352
6353
6354
6355
6356
6357
6358
6359
6360
6361
6362MLXSW_ITEM_BUF(reg, rmft2, flexible_action_set, 0x80,
6363 MLXSW_REG_FLEX_ACTION_SET_LEN);
6364
6365static inline void
6366mlxsw_reg_rmft2_common_pack(char *payload, bool v, u16 offset,
6367 u16 virtual_router,
6368 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
6369 const char *flex_action_set)
6370{
6371 MLXSW_REG_ZERO(rmft2, payload);
6372 mlxsw_reg_rmft2_v_set(payload, v);
6373 mlxsw_reg_rmft2_op_set(payload, MLXSW_REG_RMFT2_OP_READ_WRITE);
6374 mlxsw_reg_rmft2_offset_set(payload, offset);
6375 mlxsw_reg_rmft2_virtual_router_set(payload, virtual_router);
6376 mlxsw_reg_rmft2_irif_mask_set(payload, irif_mask);
6377 mlxsw_reg_rmft2_irif_set(payload, irif);
6378 if (flex_action_set)
6379 mlxsw_reg_rmft2_flexible_action_set_memcpy_to(payload,
6380 flex_action_set);
6381}
6382
6383static inline void
6384mlxsw_reg_rmft2_ipv4_pack(char *payload, bool v, u16 offset, u16 virtual_router,
6385 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
6386 u32 dip4, u32 dip4_mask, u32 sip4, u32 sip4_mask,
6387 const char *flexible_action_set)
6388{
6389 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
6390 irif_mask, irif, flexible_action_set);
6391 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV4);
6392 mlxsw_reg_rmft2_dip4_set(payload, dip4);
6393 mlxsw_reg_rmft2_dip4_mask_set(payload, dip4_mask);
6394 mlxsw_reg_rmft2_sip4_set(payload, sip4);
6395 mlxsw_reg_rmft2_sip4_mask_set(payload, sip4_mask);
6396}
6397
6398static inline void
6399mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
6400 enum mlxsw_reg_rmft2_irif_mask irif_mask, u16 irif,
6401 struct in6_addr dip6, struct in6_addr dip6_mask,
6402 struct in6_addr sip6, struct in6_addr sip6_mask,
6403 const char *flexible_action_set)
6404{
6405 mlxsw_reg_rmft2_common_pack(payload, v, offset, virtual_router,
6406 irif_mask, irif, flexible_action_set);
6407 mlxsw_reg_rmft2_type_set(payload, MLXSW_REG_RMFT2_TYPE_IPV6);
6408 mlxsw_reg_rmft2_dip6_memcpy_to(payload, (void *)&dip6);
6409 mlxsw_reg_rmft2_dip6_mask_memcpy_to(payload, (void *)&dip6_mask);
6410 mlxsw_reg_rmft2_sip6_memcpy_to(payload, (void *)&sip6);
6411 mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
6412}
6413
6414
6415
6416
6417
6418#define MLXSW_REG_MFCR_ID 0x9001
6419#define MLXSW_REG_MFCR_LEN 0x08
6420
6421MLXSW_REG_DEFINE(mfcr, MLXSW_REG_MFCR_ID, MLXSW_REG_MFCR_LEN);
6422
6423enum mlxsw_reg_mfcr_pwm_frequency {
6424 MLXSW_REG_MFCR_PWM_FEQ_11HZ = 0x00,
6425 MLXSW_REG_MFCR_PWM_FEQ_14_7HZ = 0x01,
6426 MLXSW_REG_MFCR_PWM_FEQ_22_1HZ = 0x02,
6427 MLXSW_REG_MFCR_PWM_FEQ_1_4KHZ = 0x40,
6428 MLXSW_REG_MFCR_PWM_FEQ_5KHZ = 0x41,
6429 MLXSW_REG_MFCR_PWM_FEQ_20KHZ = 0x42,
6430 MLXSW_REG_MFCR_PWM_FEQ_22_5KHZ = 0x43,
6431 MLXSW_REG_MFCR_PWM_FEQ_25KHZ = 0x44,
6432};
6433
6434
6435
6436
6437
6438MLXSW_ITEM32(reg, mfcr, pwm_frequency, 0x00, 0, 7);
6439
6440#define MLXSW_MFCR_TACHOS_MAX 10
6441
6442
6443
6444
6445
6446MLXSW_ITEM32(reg, mfcr, tacho_active, 0x04, 16, MLXSW_MFCR_TACHOS_MAX);
6447
6448#define MLXSW_MFCR_PWMS_MAX 5
6449
6450
6451
6452
6453
6454MLXSW_ITEM32(reg, mfcr, pwm_active, 0x04, 0, MLXSW_MFCR_PWMS_MAX);
6455
6456static inline void
6457mlxsw_reg_mfcr_pack(char *payload,
6458 enum mlxsw_reg_mfcr_pwm_frequency pwm_frequency)
6459{
6460 MLXSW_REG_ZERO(mfcr, payload);
6461 mlxsw_reg_mfcr_pwm_frequency_set(payload, pwm_frequency);
6462}
6463
6464static inline void
6465mlxsw_reg_mfcr_unpack(char *payload,
6466 enum mlxsw_reg_mfcr_pwm_frequency *p_pwm_frequency,
6467 u16 *p_tacho_active, u8 *p_pwm_active)
6468{
6469 *p_pwm_frequency = mlxsw_reg_mfcr_pwm_frequency_get(payload);
6470 *p_tacho_active = mlxsw_reg_mfcr_tacho_active_get(payload);
6471 *p_pwm_active = mlxsw_reg_mfcr_pwm_active_get(payload);
6472}
6473
6474
6475
6476
6477
6478#define MLXSW_REG_MFSC_ID 0x9002
6479#define MLXSW_REG_MFSC_LEN 0x08
6480
6481MLXSW_REG_DEFINE(mfsc, MLXSW_REG_MFSC_ID, MLXSW_REG_MFSC_LEN);
6482
6483
6484
6485
6486
6487MLXSW_ITEM32(reg, mfsc, pwm, 0x00, 24, 3);
6488
6489
6490
6491
6492
6493
6494MLXSW_ITEM32(reg, mfsc, pwm_duty_cycle, 0x04, 0, 8);
6495
6496static inline void mlxsw_reg_mfsc_pack(char *payload, u8 pwm,
6497 u8 pwm_duty_cycle)
6498{
6499 MLXSW_REG_ZERO(mfsc, payload);
6500 mlxsw_reg_mfsc_pwm_set(payload, pwm);
6501 mlxsw_reg_mfsc_pwm_duty_cycle_set(payload, pwm_duty_cycle);
6502}
6503
6504
6505
6506
6507
6508
6509#define MLXSW_REG_MFSM_ID 0x9003
6510#define MLXSW_REG_MFSM_LEN 0x08
6511
6512MLXSW_REG_DEFINE(mfsm, MLXSW_REG_MFSM_ID, MLXSW_REG_MFSM_LEN);
6513
6514
6515
6516
6517
6518MLXSW_ITEM32(reg, mfsm, tacho, 0x00, 24, 4);
6519
6520
6521
6522
6523
6524MLXSW_ITEM32(reg, mfsm, rpm, 0x04, 0, 16);
6525
6526static inline void mlxsw_reg_mfsm_pack(char *payload, u8 tacho)
6527{
6528 MLXSW_REG_ZERO(mfsm, payload);
6529 mlxsw_reg_mfsm_tacho_set(payload, tacho);
6530}
6531
6532
6533
6534
6535
6536
6537
6538#define MLXSW_REG_MFSL_ID 0x9004
6539#define MLXSW_REG_MFSL_LEN 0x0C
6540
6541MLXSW_REG_DEFINE(mfsl, MLXSW_REG_MFSL_ID, MLXSW_REG_MFSL_LEN);
6542
6543
6544
6545
6546
6547MLXSW_ITEM32(reg, mfsl, tacho, 0x00, 24, 4);
6548
6549
6550
6551
6552
6553MLXSW_ITEM32(reg, mfsl, tach_min, 0x04, 0, 16);
6554
6555
6556
6557
6558
6559MLXSW_ITEM32(reg, mfsl, tach_max, 0x08, 0, 16);
6560
6561static inline void mlxsw_reg_mfsl_pack(char *payload, u8 tacho,
6562 u16 tach_min, u16 tach_max)
6563{
6564 MLXSW_REG_ZERO(mfsl, payload);
6565 mlxsw_reg_mfsl_tacho_set(payload, tacho);
6566 mlxsw_reg_mfsl_tach_min_set(payload, tach_min);
6567 mlxsw_reg_mfsl_tach_max_set(payload, tach_max);
6568}
6569
6570static inline void mlxsw_reg_mfsl_unpack(char *payload, u8 tacho,
6571 u16 *p_tach_min, u16 *p_tach_max)
6572{
6573 if (p_tach_min)
6574 *p_tach_min = mlxsw_reg_mfsl_tach_min_get(payload);
6575
6576 if (p_tach_max)
6577 *p_tach_max = mlxsw_reg_mfsl_tach_max_get(payload);
6578}
6579
6580
6581
6582
6583
6584
6585#define MLXSW_REG_MTCAP_ID 0x9009
6586#define MLXSW_REG_MTCAP_LEN 0x08
6587
6588MLXSW_REG_DEFINE(mtcap, MLXSW_REG_MTCAP_ID, MLXSW_REG_MTCAP_LEN);
6589
6590
6591
6592
6593
6594
6595MLXSW_ITEM32(reg, mtcap, sensor_count, 0x00, 0, 7);
6596
6597
6598
6599
6600
6601
6602
6603#define MLXSW_REG_MTMP_ID 0x900A
6604#define MLXSW_REG_MTMP_LEN 0x20
6605
6606MLXSW_REG_DEFINE(mtmp, MLXSW_REG_MTMP_ID, MLXSW_REG_MTMP_LEN);
6607
6608
6609
6610
6611
6612
6613
6614MLXSW_ITEM32(reg, mtmp, sensor_index, 0x00, 0, 7);
6615
6616
6617#define MLXSW_REG_MTMP_TEMP_TO_MC(val) (val * 125)
6618
6619
6620
6621
6622
6623
6624MLXSW_ITEM32(reg, mtmp, temperature, 0x04, 0, 16);
6625
6626
6627
6628
6629
6630MLXSW_ITEM32(reg, mtmp, mte, 0x08, 31, 1);
6631
6632
6633
6634
6635
6636MLXSW_ITEM32(reg, mtmp, mtr, 0x08, 30, 1);
6637
6638
6639
6640
6641
6642
6643MLXSW_ITEM32(reg, mtmp, max_temperature, 0x08, 0, 16);
6644
6645
6646
6647
6648
6649
6650
6651
6652MLXSW_ITEM32(reg, mtmp, tee, 0x0C, 30, 2);
6653
6654#define MLXSW_REG_MTMP_THRESH_HI 0x348
6655
6656
6657
6658
6659
6660MLXSW_ITEM32(reg, mtmp, temperature_threshold_hi, 0x0C, 0, 16);
6661
6662
6663
6664
6665
6666MLXSW_ITEM32(reg, mtmp, temperature_threshold_lo, 0x10, 0, 16);
6667
6668#define MLXSW_REG_MTMP_SENSOR_NAME_SIZE 8
6669
6670
6671
6672
6673
6674MLXSW_ITEM_BUF(reg, mtmp, sensor_name, 0x18, MLXSW_REG_MTMP_SENSOR_NAME_SIZE);
6675
6676static inline void mlxsw_reg_mtmp_pack(char *payload, u8 sensor_index,
6677 bool max_temp_enable,
6678 bool max_temp_reset)
6679{
6680 MLXSW_REG_ZERO(mtmp, payload);
6681 mlxsw_reg_mtmp_sensor_index_set(payload, sensor_index);
6682 mlxsw_reg_mtmp_mte_set(payload, max_temp_enable);
6683 mlxsw_reg_mtmp_mtr_set(payload, max_temp_reset);
6684 mlxsw_reg_mtmp_temperature_threshold_hi_set(payload,
6685 MLXSW_REG_MTMP_THRESH_HI);
6686}
6687
6688static inline void mlxsw_reg_mtmp_unpack(char *payload, unsigned int *p_temp,
6689 unsigned int *p_max_temp,
6690 char *sensor_name)
6691{
6692 u16 temp;
6693
6694 if (p_temp) {
6695 temp = mlxsw_reg_mtmp_temperature_get(payload);
6696 *p_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
6697 }
6698 if (p_max_temp) {
6699 temp = mlxsw_reg_mtmp_max_temperature_get(payload);
6700 *p_max_temp = MLXSW_REG_MTMP_TEMP_TO_MC(temp);
6701 }
6702 if (sensor_name)
6703 mlxsw_reg_mtmp_sensor_name_memcpy_from(payload, sensor_name);
6704}
6705
6706
6707
6708
6709
6710
6711#define MLXSW_REG_MCIA_ID 0x9014
6712#define MLXSW_REG_MCIA_LEN 0x40
6713
6714MLXSW_REG_DEFINE(mcia, MLXSW_REG_MCIA_ID, MLXSW_REG_MCIA_LEN);
6715
6716
6717
6718
6719
6720
6721
6722MLXSW_ITEM32(reg, mcia, l, 0x00, 31, 1);
6723
6724
6725
6726
6727
6728MLXSW_ITEM32(reg, mcia, module, 0x00, 16, 8);
6729
6730
6731
6732
6733
6734MLXSW_ITEM32(reg, mcia, status, 0x00, 0, 8);
6735
6736
6737
6738
6739
6740MLXSW_ITEM32(reg, mcia, i2c_device_address, 0x04, 24, 8);
6741
6742
6743
6744
6745
6746MLXSW_ITEM32(reg, mcia, page_number, 0x04, 16, 8);
6747
6748
6749
6750
6751
6752MLXSW_ITEM32(reg, mcia, device_address, 0x04, 0, 16);
6753
6754
6755
6756
6757
6758MLXSW_ITEM32(reg, mcia, size, 0x08, 0, 16);
6759
6760#define MLXSW_SP_REG_MCIA_EEPROM_SIZE 48
6761
6762
6763
6764
6765
6766MLXSW_ITEM_BUF(reg, mcia, eeprom, 0x10, MLXSW_SP_REG_MCIA_EEPROM_SIZE);
6767
6768static inline void mlxsw_reg_mcia_pack(char *payload, u8 module, u8 lock,
6769 u8 page_number, u16 device_addr,
6770 u8 size, u8 i2c_device_addr)
6771{
6772 MLXSW_REG_ZERO(mcia, payload);
6773 mlxsw_reg_mcia_module_set(payload, module);
6774 mlxsw_reg_mcia_l_set(payload, lock);
6775 mlxsw_reg_mcia_page_number_set(payload, page_number);
6776 mlxsw_reg_mcia_device_address_set(payload, device_addr);
6777 mlxsw_reg_mcia_size_set(payload, size);
6778 mlxsw_reg_mcia_i2c_device_address_set(payload, i2c_device_addr);
6779}
6780
6781
6782
6783
6784
6785
6786#define MLXSW_REG_MPAT_ID 0x901A
6787#define MLXSW_REG_MPAT_LEN 0x78
6788
6789MLXSW_REG_DEFINE(mpat, MLXSW_REG_MPAT_ID, MLXSW_REG_MPAT_LEN);
6790
6791
6792
6793
6794
6795MLXSW_ITEM32(reg, mpat, pa_id, 0x00, 28, 4);
6796
6797
6798
6799
6800
6801MLXSW_ITEM32(reg, mpat, system_port, 0x00, 0, 16);
6802
6803
6804
6805
6806
6807MLXSW_ITEM32(reg, mpat, e, 0x04, 31, 1);
6808
6809
6810
6811
6812
6813
6814
6815
6816
6817
6818MLXSW_ITEM32(reg, mpat, qos, 0x04, 26, 1);
6819
6820
6821
6822
6823
6824
6825
6826
6827
6828MLXSW_ITEM32(reg, mpat, be, 0x04, 25, 1);
6829
6830enum mlxsw_reg_mpat_span_type {
6831
6832
6833
6834 MLXSW_REG_MPAT_SPAN_TYPE_LOCAL_ETH = 0x0,
6835
6836
6837
6838
6839 MLXSW_REG_MPAT_SPAN_TYPE_REMOTE_ETH_L3 = 0x3,
6840};
6841
6842
6843
6844
6845
6846MLXSW_ITEM32(reg, mpat, span_type, 0x04, 0, 4);
6847
6848
6849
6850
6851
6852
6853
6854
6855
6856MLXSW_ITEM32(reg, mpat, eth_rspan_vid, 0x18, 0, 12);
6857
6858
6859
6860
6861
6862enum mlxsw_reg_mpat_eth_rspan_version {
6863 MLXSW_REG_MPAT_ETH_RSPAN_VERSION_NO_HEADER = 15,
6864};
6865
6866
6867
6868
6869
6870MLXSW_ITEM32(reg, mpat, eth_rspan_version, 0x10, 18, 4);
6871
6872
6873
6874
6875
6876MLXSW_ITEM_BUF(reg, mpat, eth_rspan_mac, 0x12, 6);
6877
6878
6879
6880
6881
6882MLXSW_ITEM32(reg, mpat, eth_rspan_tp, 0x18, 16, 1);
6883
6884
6885
6886
6887
6888enum mlxsw_reg_mpat_eth_rspan_protocol {
6889 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4,
6890 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6,
6891};
6892
6893
6894
6895
6896
6897MLXSW_ITEM32(reg, mpat, eth_rspan_protocol, 0x18, 24, 4);
6898
6899
6900
6901
6902
6903MLXSW_ITEM32(reg, mpat, eth_rspan_ttl, 0x1C, 4, 8);
6904
6905
6906
6907
6908
6909MLXSW_ITEM_BUF(reg, mpat, eth_rspan_smac, 0x22, 6);
6910
6911
6912
6913
6914
6915MLXSW_ITEM32(reg, mpat, eth_rspan_dip4, 0x4C, 0, 32);
6916MLXSW_ITEM_BUF(reg, mpat, eth_rspan_dip6, 0x40, 16);
6917
6918
6919
6920
6921
6922MLXSW_ITEM32(reg, mpat, eth_rspan_sip4, 0x5C, 0, 32);
6923MLXSW_ITEM_BUF(reg, mpat, eth_rspan_sip6, 0x50, 16);
6924
6925static inline void mlxsw_reg_mpat_pack(char *payload, u8 pa_id,
6926 u16 system_port, bool e,
6927 enum mlxsw_reg_mpat_span_type span_type)
6928{
6929 MLXSW_REG_ZERO(mpat, payload);
6930 mlxsw_reg_mpat_pa_id_set(payload, pa_id);
6931 mlxsw_reg_mpat_system_port_set(payload, system_port);
6932 mlxsw_reg_mpat_e_set(payload, e);
6933 mlxsw_reg_mpat_qos_set(payload, 1);
6934 mlxsw_reg_mpat_be_set(payload, 1);
6935 mlxsw_reg_mpat_span_type_set(payload, span_type);
6936}
6937
6938static inline void mlxsw_reg_mpat_eth_rspan_pack(char *payload, u16 vid)
6939{
6940 mlxsw_reg_mpat_eth_rspan_vid_set(payload, vid);
6941}
6942
6943static inline void
6944mlxsw_reg_mpat_eth_rspan_l2_pack(char *payload,
6945 enum mlxsw_reg_mpat_eth_rspan_version version,
6946 const char *mac,
6947 bool tp)
6948{
6949 mlxsw_reg_mpat_eth_rspan_version_set(payload, version);
6950 mlxsw_reg_mpat_eth_rspan_mac_memcpy_to(payload, mac);
6951 mlxsw_reg_mpat_eth_rspan_tp_set(payload, tp);
6952}
6953
6954static inline void
6955mlxsw_reg_mpat_eth_rspan_l3_ipv4_pack(char *payload, u8 ttl,
6956 const char *smac,
6957 u32 sip, u32 dip)
6958{
6959 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
6960 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
6961 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
6962 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV4);
6963 mlxsw_reg_mpat_eth_rspan_sip4_set(payload, sip);
6964 mlxsw_reg_mpat_eth_rspan_dip4_set(payload, dip);
6965}
6966
6967static inline void
6968mlxsw_reg_mpat_eth_rspan_l3_ipv6_pack(char *payload, u8 ttl,
6969 const char *smac,
6970 struct in6_addr sip, struct in6_addr dip)
6971{
6972 mlxsw_reg_mpat_eth_rspan_ttl_set(payload, ttl);
6973 mlxsw_reg_mpat_eth_rspan_smac_memcpy_to(payload, smac);
6974 mlxsw_reg_mpat_eth_rspan_protocol_set(payload,
6975 MLXSW_REG_MPAT_ETH_RSPAN_PROTOCOL_IPV6);
6976 mlxsw_reg_mpat_eth_rspan_sip6_memcpy_to(payload, (void *)&sip);
6977 mlxsw_reg_mpat_eth_rspan_dip6_memcpy_to(payload, (void *)&dip);
6978}
6979
6980
6981
6982
6983
6984
6985#define MLXSW_REG_MPAR_ID 0x901B
6986#define MLXSW_REG_MPAR_LEN 0x08
6987
6988MLXSW_REG_DEFINE(mpar, MLXSW_REG_MPAR_ID, MLXSW_REG_MPAR_LEN);
6989
6990
6991
6992
6993
6994MLXSW_ITEM32(reg, mpar, local_port, 0x00, 16, 8);
6995
6996enum mlxsw_reg_mpar_i_e {
6997 MLXSW_REG_MPAR_TYPE_EGRESS,
6998 MLXSW_REG_MPAR_TYPE_INGRESS,
6999};
7000
7001
7002
7003
7004
7005MLXSW_ITEM32(reg, mpar, i_e, 0x00, 0, 4);
7006
7007
7008
7009
7010
7011
7012MLXSW_ITEM32(reg, mpar, enable, 0x04, 31, 1);
7013
7014
7015
7016
7017
7018MLXSW_ITEM32(reg, mpar, pa_id, 0x04, 0, 4);
7019
7020static inline void mlxsw_reg_mpar_pack(char *payload, u8 local_port,
7021 enum mlxsw_reg_mpar_i_e i_e,
7022 bool enable, u8 pa_id)
7023{
7024 MLXSW_REG_ZERO(mpar, payload);
7025 mlxsw_reg_mpar_local_port_set(payload, local_port);
7026 mlxsw_reg_mpar_enable_set(payload, enable);
7027 mlxsw_reg_mpar_i_e_set(payload, i_e);
7028 mlxsw_reg_mpar_pa_id_set(payload, pa_id);
7029}
7030
7031
7032
7033
7034
7035#define MLXSW_REG_MLCR_ID 0x902B
7036#define MLXSW_REG_MLCR_LEN 0x0C
7037
7038MLXSW_REG_DEFINE(mlcr, MLXSW_REG_MLCR_ID, MLXSW_REG_MLCR_LEN);
7039
7040
7041
7042
7043
7044MLXSW_ITEM32(reg, mlcr, local_port, 0x00, 16, 8);
7045
7046#define MLXSW_REG_MLCR_DURATION_MAX 0xFFFF
7047
7048
7049
7050
7051
7052
7053
7054MLXSW_ITEM32(reg, mlcr, beacon_duration, 0x04, 0, 16);
7055
7056
7057
7058
7059
7060
7061MLXSW_ITEM32(reg, mlcr, beacon_remain, 0x08, 0, 16);
7062
7063static inline void mlxsw_reg_mlcr_pack(char *payload, u8 local_port,
7064 bool active)
7065{
7066 MLXSW_REG_ZERO(mlcr, payload);
7067 mlxsw_reg_mlcr_local_port_set(payload, local_port);
7068 mlxsw_reg_mlcr_beacon_duration_set(payload, active ?
7069 MLXSW_REG_MLCR_DURATION_MAX : 0);
7070}
7071
7072
7073
7074
7075
7076#define MLXSW_REG_MCQI_ID 0x9061
7077#define MLXSW_REG_MCQI_BASE_LEN 0x18
7078#define MLXSW_REG_MCQI_CAP_LEN 0x14
7079#define MLXSW_REG_MCQI_LEN (MLXSW_REG_MCQI_BASE_LEN + MLXSW_REG_MCQI_CAP_LEN)
7080
7081MLXSW_REG_DEFINE(mcqi, MLXSW_REG_MCQI_ID, MLXSW_REG_MCQI_LEN);
7082
7083
7084
7085
7086
7087MLXSW_ITEM32(reg, mcqi, component_index, 0x00, 0, 16);
7088
7089enum mlxfw_reg_mcqi_info_type {
7090 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES,
7091};
7092
7093
7094
7095
7096
7097MLXSW_ITEM32(reg, mcqi, info_type, 0x08, 0, 5);
7098
7099
7100
7101
7102
7103
7104MLXSW_ITEM32(reg, mcqi, offset, 0x10, 0, 32);
7105
7106
7107
7108
7109
7110
7111MLXSW_ITEM32(reg, mcqi, data_size, 0x14, 0, 16);
7112
7113
7114
7115
7116
7117MLXSW_ITEM32(reg, mcqi, cap_max_component_size, 0x20, 0, 32);
7118
7119
7120
7121
7122
7123
7124MLXSW_ITEM32(reg, mcqi, cap_log_mcda_word_size, 0x24, 28, 4);
7125
7126
7127
7128
7129
7130MLXSW_ITEM32(reg, mcqi, cap_mcda_max_write_size, 0x24, 0, 16);
7131
7132static inline void mlxsw_reg_mcqi_pack(char *payload, u16 component_index)
7133{
7134 MLXSW_REG_ZERO(mcqi, payload);
7135 mlxsw_reg_mcqi_component_index_set(payload, component_index);
7136 mlxsw_reg_mcqi_info_type_set(payload,
7137 MLXSW_REG_MCQI_INFO_TYPE_CAPABILITIES);
7138 mlxsw_reg_mcqi_offset_set(payload, 0);
7139 mlxsw_reg_mcqi_data_size_set(payload, MLXSW_REG_MCQI_CAP_LEN);
7140}
7141
7142static inline void mlxsw_reg_mcqi_unpack(char *payload,
7143 u32 *p_cap_max_component_size,
7144 u8 *p_cap_log_mcda_word_size,
7145 u16 *p_cap_mcda_max_write_size)
7146{
7147 *p_cap_max_component_size =
7148 mlxsw_reg_mcqi_cap_max_component_size_get(payload);
7149 *p_cap_log_mcda_word_size =
7150 mlxsw_reg_mcqi_cap_log_mcda_word_size_get(payload);
7151 *p_cap_mcda_max_write_size =
7152 mlxsw_reg_mcqi_cap_mcda_max_write_size_get(payload);
7153}
7154
7155
7156
7157
7158
7159#define MLXSW_REG_MCC_ID 0x9062
7160#define MLXSW_REG_MCC_LEN 0x1C
7161
7162MLXSW_REG_DEFINE(mcc, MLXSW_REG_MCC_ID, MLXSW_REG_MCC_LEN);
7163
7164enum mlxsw_reg_mcc_instruction {
7165 MLXSW_REG_MCC_INSTRUCTION_LOCK_UPDATE_HANDLE = 0x01,
7166 MLXSW_REG_MCC_INSTRUCTION_RELEASE_UPDATE_HANDLE = 0x02,
7167 MLXSW_REG_MCC_INSTRUCTION_UPDATE_COMPONENT = 0x03,
7168 MLXSW_REG_MCC_INSTRUCTION_VERIFY_COMPONENT = 0x04,
7169 MLXSW_REG_MCC_INSTRUCTION_ACTIVATE = 0x06,
7170 MLXSW_REG_MCC_INSTRUCTION_CANCEL = 0x08,
7171};
7172
7173
7174
7175
7176
7177
7178MLXSW_ITEM32(reg, mcc, instruction, 0x00, 0, 8);
7179
7180
7181
7182
7183
7184
7185MLXSW_ITEM32(reg, mcc, component_index, 0x04, 0, 16);
7186
7187
7188
7189
7190
7191MLXSW_ITEM32(reg, mcc, update_handle, 0x08, 0, 24);
7192
7193
7194
7195
7196
7197
7198MLXSW_ITEM32(reg, mcc, error_code, 0x0C, 8, 8);
7199
7200
7201
7202
7203
7204MLXSW_ITEM32(reg, mcc, control_state, 0x0C, 0, 4);
7205
7206
7207
7208
7209
7210
7211
7212MLXSW_ITEM32(reg, mcc, component_size, 0x10, 0, 32);
7213
7214static inline void mlxsw_reg_mcc_pack(char *payload,
7215 enum mlxsw_reg_mcc_instruction instr,
7216 u16 component_index, u32 update_handle,
7217 u32 component_size)
7218{
7219 MLXSW_REG_ZERO(mcc, payload);
7220 mlxsw_reg_mcc_instruction_set(payload, instr);
7221 mlxsw_reg_mcc_component_index_set(payload, component_index);
7222 mlxsw_reg_mcc_update_handle_set(payload, update_handle);
7223 mlxsw_reg_mcc_component_size_set(payload, component_size);
7224}
7225
7226static inline void mlxsw_reg_mcc_unpack(char *payload, u32 *p_update_handle,
7227 u8 *p_error_code, u8 *p_control_state)
7228{
7229 if (p_update_handle)
7230 *p_update_handle = mlxsw_reg_mcc_update_handle_get(payload);
7231 if (p_error_code)
7232 *p_error_code = mlxsw_reg_mcc_error_code_get(payload);
7233 if (p_control_state)
7234 *p_control_state = mlxsw_reg_mcc_control_state_get(payload);
7235}
7236
7237
7238
7239
7240
7241#define MLXSW_REG_MCDA_ID 0x9063
7242#define MLXSW_REG_MCDA_BASE_LEN 0x10
7243#define MLXSW_REG_MCDA_MAX_DATA_LEN 0x80
7244#define MLXSW_REG_MCDA_LEN \
7245 (MLXSW_REG_MCDA_BASE_LEN + MLXSW_REG_MCDA_MAX_DATA_LEN)
7246
7247MLXSW_REG_DEFINE(mcda, MLXSW_REG_MCDA_ID, MLXSW_REG_MCDA_LEN);
7248
7249
7250
7251
7252
7253MLXSW_ITEM32(reg, mcda, update_handle, 0x00, 0, 24);
7254
7255
7256
7257
7258
7259
7260MLXSW_ITEM32(reg, mcda, offset, 0x04, 0, 32);
7261
7262
7263
7264
7265
7266MLXSW_ITEM32(reg, mcda, size, 0x08, 0, 16);
7267
7268
7269
7270
7271
7272MLXSW_ITEM32_INDEXED(reg, mcda, data, 0x10, 0, 32, 4, 0, false);
7273
7274static inline void mlxsw_reg_mcda_pack(char *payload, u32 update_handle,
7275 u32 offset, u16 size, u8 *data)
7276{
7277 int i;
7278
7279 MLXSW_REG_ZERO(mcda, payload);
7280 mlxsw_reg_mcda_update_handle_set(payload, update_handle);
7281 mlxsw_reg_mcda_offset_set(payload, offset);
7282 mlxsw_reg_mcda_size_set(payload, size);
7283
7284 for (i = 0; i < size / 4; i++)
7285 mlxsw_reg_mcda_data_set(payload, i, *(u32 *) &data[i * 4]);
7286}
7287
7288
7289
7290
7291
7292#define MLXSW_REG_MPSC_ID 0x9080
7293#define MLXSW_REG_MPSC_LEN 0x1C
7294
7295MLXSW_REG_DEFINE(mpsc, MLXSW_REG_MPSC_ID, MLXSW_REG_MPSC_LEN);
7296
7297
7298
7299
7300
7301
7302MLXSW_ITEM32(reg, mpsc, local_port, 0x00, 16, 8);
7303
7304
7305
7306
7307
7308MLXSW_ITEM32(reg, mpsc, e, 0x04, 30, 1);
7309
7310#define MLXSW_REG_MPSC_RATE_MAX 3500000000UL
7311
7312
7313
7314
7315
7316
7317MLXSW_ITEM32(reg, mpsc, rate, 0x08, 0, 32);
7318
7319static inline void mlxsw_reg_mpsc_pack(char *payload, u8 local_port, bool e,
7320 u32 rate)
7321{
7322 MLXSW_REG_ZERO(mpsc, payload);
7323 mlxsw_reg_mpsc_local_port_set(payload, local_port);
7324 mlxsw_reg_mpsc_e_set(payload, e);
7325 mlxsw_reg_mpsc_rate_set(payload, rate);
7326}
7327
7328
7329
7330
7331#define MLXSW_REG_MGPC_ID 0x9081
7332#define MLXSW_REG_MGPC_LEN 0x18
7333
7334MLXSW_REG_DEFINE(mgpc, MLXSW_REG_MGPC_ID, MLXSW_REG_MGPC_LEN);
7335
7336
7337
7338
7339
7340MLXSW_ITEM32(reg, mgpc, counter_set_type, 0x00, 24, 8);
7341
7342
7343
7344
7345
7346MLXSW_ITEM32(reg, mgpc, counter_index, 0x00, 0, 24);
7347
7348enum mlxsw_reg_mgpc_opcode {
7349
7350 MLXSW_REG_MGPC_OPCODE_NOP = 0x00,
7351
7352 MLXSW_REG_MGPC_OPCODE_CLEAR = 0x08,
7353};
7354
7355
7356
7357
7358
7359MLXSW_ITEM32(reg, mgpc, opcode, 0x04, 28, 4);
7360
7361
7362
7363
7364
7365MLXSW_ITEM64(reg, mgpc, byte_counter, 0x08, 0, 64);
7366
7367
7368
7369
7370
7371MLXSW_ITEM64(reg, mgpc, packet_counter, 0x10, 0, 64);
7372
7373static inline void mlxsw_reg_mgpc_pack(char *payload, u32 counter_index,
7374 enum mlxsw_reg_mgpc_opcode opcode,
7375 enum mlxsw_reg_flow_counter_set_type set_type)
7376{
7377 MLXSW_REG_ZERO(mgpc, payload);
7378 mlxsw_reg_mgpc_counter_index_set(payload, counter_index);
7379 mlxsw_reg_mgpc_counter_set_type_set(payload, set_type);
7380 mlxsw_reg_mgpc_opcode_set(payload, opcode);
7381}
7382
7383
7384
7385
7386
7387#define MLXSW_REG_TIGCR_ID 0xA801
7388#define MLXSW_REG_TIGCR_LEN 0x10
7389
7390MLXSW_REG_DEFINE(tigcr, MLXSW_REG_TIGCR_ID, MLXSW_REG_TIGCR_LEN);
7391
7392
7393
7394
7395
7396
7397MLXSW_ITEM32(reg, tigcr, ttlc, 0x04, 8, 1);
7398
7399
7400
7401
7402
7403
7404MLXSW_ITEM32(reg, tigcr, ttl_uc, 0x04, 0, 8);
7405
7406static inline void mlxsw_reg_tigcr_pack(char *payload, bool ttlc, u8 ttl_uc)
7407{
7408 MLXSW_REG_ZERO(tigcr, payload);
7409 mlxsw_reg_tigcr_ttlc_set(payload, ttlc);
7410 mlxsw_reg_tigcr_ttl_uc_set(payload, ttl_uc);
7411}
7412
7413
7414
7415
7416
7417#define MLXSW_REG_SBPR_ID 0xB001
7418#define MLXSW_REG_SBPR_LEN 0x14
7419
7420MLXSW_REG_DEFINE(sbpr, MLXSW_REG_SBPR_ID, MLXSW_REG_SBPR_LEN);
7421
7422
7423enum mlxsw_reg_sbxx_dir {
7424 MLXSW_REG_SBXX_DIR_INGRESS,
7425 MLXSW_REG_SBXX_DIR_EGRESS,
7426};
7427
7428
7429
7430
7431
7432MLXSW_ITEM32(reg, sbpr, dir, 0x00, 24, 2);
7433
7434
7435
7436
7437
7438MLXSW_ITEM32(reg, sbpr, pool, 0x00, 0, 4);
7439
7440
7441
7442
7443
7444MLXSW_ITEM32(reg, sbpr, size, 0x04, 0, 24);
7445
7446enum mlxsw_reg_sbpr_mode {
7447 MLXSW_REG_SBPR_MODE_STATIC,
7448 MLXSW_REG_SBPR_MODE_DYNAMIC,
7449};
7450
7451
7452
7453
7454
7455MLXSW_ITEM32(reg, sbpr, mode, 0x08, 0, 4);
7456
7457static inline void mlxsw_reg_sbpr_pack(char *payload, u8 pool,
7458 enum mlxsw_reg_sbxx_dir dir,
7459 enum mlxsw_reg_sbpr_mode mode, u32 size)
7460{
7461 MLXSW_REG_ZERO(sbpr, payload);
7462 mlxsw_reg_sbpr_pool_set(payload, pool);
7463 mlxsw_reg_sbpr_dir_set(payload, dir);
7464 mlxsw_reg_sbpr_mode_set(payload, mode);
7465 mlxsw_reg_sbpr_size_set(payload, size);
7466}
7467
7468
7469
7470
7471
7472
7473
7474#define MLXSW_REG_SBCM_ID 0xB002
7475#define MLXSW_REG_SBCM_LEN 0x28
7476
7477MLXSW_REG_DEFINE(sbcm, MLXSW_REG_SBCM_ID, MLXSW_REG_SBCM_LEN);
7478
7479
7480
7481
7482
7483
7484
7485MLXSW_ITEM32(reg, sbcm, local_port, 0x00, 16, 8);
7486
7487
7488
7489
7490
7491
7492
7493
7494
7495MLXSW_ITEM32(reg, sbcm, pg_buff, 0x00, 8, 6);
7496
7497
7498
7499
7500
7501MLXSW_ITEM32(reg, sbcm, dir, 0x00, 0, 2);
7502
7503
7504
7505
7506
7507MLXSW_ITEM32(reg, sbcm, min_buff, 0x18, 0, 24);
7508
7509
7510#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MIN 1
7511#define MLXSW_REG_SBXX_DYN_MAX_BUFF_MAX 14
7512
7513
7514
7515
7516
7517
7518
7519
7520
7521
7522
7523
7524MLXSW_ITEM32(reg, sbcm, max_buff, 0x1C, 0, 24);
7525
7526
7527
7528
7529
7530MLXSW_ITEM32(reg, sbcm, pool, 0x24, 0, 4);
7531
7532static inline void mlxsw_reg_sbcm_pack(char *payload, u8 local_port, u8 pg_buff,
7533 enum mlxsw_reg_sbxx_dir dir,
7534 u32 min_buff, u32 max_buff, u8 pool)
7535{
7536 MLXSW_REG_ZERO(sbcm, payload);
7537 mlxsw_reg_sbcm_local_port_set(payload, local_port);
7538 mlxsw_reg_sbcm_pg_buff_set(payload, pg_buff);
7539 mlxsw_reg_sbcm_dir_set(payload, dir);
7540 mlxsw_reg_sbcm_min_buff_set(payload, min_buff);
7541 mlxsw_reg_sbcm_max_buff_set(payload, max_buff);
7542 mlxsw_reg_sbcm_pool_set(payload, pool);
7543}
7544
7545
7546
7547
7548
7549
7550
7551#define MLXSW_REG_SBPM_ID 0xB003
7552#define MLXSW_REG_SBPM_LEN 0x28
7553
7554MLXSW_REG_DEFINE(sbpm, MLXSW_REG_SBPM_ID, MLXSW_REG_SBPM_LEN);
7555
7556
7557
7558
7559
7560
7561
7562MLXSW_ITEM32(reg, sbpm, local_port, 0x00, 16, 8);
7563
7564
7565
7566
7567
7568MLXSW_ITEM32(reg, sbpm, pool, 0x00, 8, 4);
7569
7570
7571
7572
7573
7574MLXSW_ITEM32(reg, sbpm, dir, 0x00, 0, 2);
7575
7576
7577
7578
7579
7580MLXSW_ITEM32(reg, sbpm, buff_occupancy, 0x10, 0, 24);
7581
7582
7583
7584
7585
7586
7587
7588MLXSW_ITEM32(reg, sbpm, clr, 0x14, 31, 1);
7589
7590
7591
7592
7593
7594
7595MLXSW_ITEM32(reg, sbpm, max_buff_occupancy, 0x14, 0, 24);
7596
7597
7598
7599
7600
7601MLXSW_ITEM32(reg, sbpm, min_buff, 0x18, 0, 24);
7602
7603
7604
7605
7606
7607
7608
7609
7610
7611
7612
7613
7614MLXSW_ITEM32(reg, sbpm, max_buff, 0x1C, 0, 24);
7615
7616static inline void mlxsw_reg_sbpm_pack(char *payload, u8 local_port, u8 pool,
7617 enum mlxsw_reg_sbxx_dir dir, bool clr,
7618 u32 min_buff, u32 max_buff)
7619{
7620 MLXSW_REG_ZERO(sbpm, payload);
7621 mlxsw_reg_sbpm_local_port_set(payload, local_port);
7622 mlxsw_reg_sbpm_pool_set(payload, pool);
7623 mlxsw_reg_sbpm_dir_set(payload, dir);
7624 mlxsw_reg_sbpm_clr_set(payload, clr);
7625 mlxsw_reg_sbpm_min_buff_set(payload, min_buff);
7626 mlxsw_reg_sbpm_max_buff_set(payload, max_buff);
7627}
7628
7629static inline void mlxsw_reg_sbpm_unpack(char *payload, u32 *p_buff_occupancy,
7630 u32 *p_max_buff_occupancy)
7631{
7632 *p_buff_occupancy = mlxsw_reg_sbpm_buff_occupancy_get(payload);
7633 *p_max_buff_occupancy = mlxsw_reg_sbpm_max_buff_occupancy_get(payload);
7634}
7635
7636
7637
7638
7639
7640
7641
7642#define MLXSW_REG_SBMM_ID 0xB004
7643#define MLXSW_REG_SBMM_LEN 0x28
7644
7645MLXSW_REG_DEFINE(sbmm, MLXSW_REG_SBMM_ID, MLXSW_REG_SBMM_LEN);
7646
7647
7648
7649
7650
7651MLXSW_ITEM32(reg, sbmm, prio, 0x00, 8, 4);
7652
7653
7654
7655
7656
7657MLXSW_ITEM32(reg, sbmm, min_buff, 0x18, 0, 24);
7658
7659
7660
7661
7662
7663
7664
7665
7666
7667
7668
7669
7670MLXSW_ITEM32(reg, sbmm, max_buff, 0x1C, 0, 24);
7671
7672
7673
7674
7675
7676MLXSW_ITEM32(reg, sbmm, pool, 0x24, 0, 4);
7677
7678static inline void mlxsw_reg_sbmm_pack(char *payload, u8 prio, u32 min_buff,
7679 u32 max_buff, u8 pool)
7680{
7681 MLXSW_REG_ZERO(sbmm, payload);
7682 mlxsw_reg_sbmm_prio_set(payload, prio);
7683 mlxsw_reg_sbmm_min_buff_set(payload, min_buff);
7684 mlxsw_reg_sbmm_max_buff_set(payload, max_buff);
7685 mlxsw_reg_sbmm_pool_set(payload, pool);
7686}
7687
7688
7689
7690
7691
7692
7693
7694
7695
7696#define MLXSW_REG_SBSR_ID 0xB005
7697#define MLXSW_REG_SBSR_BASE_LEN 0x5C
7698#define MLXSW_REG_SBSR_REC_LEN 0x8
7699#define MLXSW_REG_SBSR_REC_MAX_COUNT 120
7700#define MLXSW_REG_SBSR_LEN (MLXSW_REG_SBSR_BASE_LEN + \
7701 MLXSW_REG_SBSR_REC_LEN * \
7702 MLXSW_REG_SBSR_REC_MAX_COUNT)
7703
7704MLXSW_REG_DEFINE(sbsr, MLXSW_REG_SBSR_ID, MLXSW_REG_SBSR_LEN);
7705
7706
7707
7708
7709
7710
7711
7712MLXSW_ITEM32(reg, sbsr, clr, 0x00, 31, 1);
7713
7714
7715
7716
7717
7718
7719
7720
7721MLXSW_ITEM_BIT_ARRAY(reg, sbsr, ingress_port_mask, 0x10, 0x20, 1);
7722
7723
7724
7725
7726
7727
7728
7729
7730
7731MLXSW_ITEM_BIT_ARRAY(reg, sbsr, pg_buff_mask, 0x30, 0x4, 1);
7732
7733
7734
7735
7736
7737
7738
7739
7740MLXSW_ITEM_BIT_ARRAY(reg, sbsr, egress_port_mask, 0x34, 0x20, 1);
7741
7742
7743
7744
7745
7746
7747
7748
7749
7750MLXSW_ITEM_BIT_ARRAY(reg, sbsr, tclass_mask, 0x54, 0x8, 1);
7751
7752static inline void mlxsw_reg_sbsr_pack(char *payload, bool clr)
7753{
7754 MLXSW_REG_ZERO(sbsr, payload);
7755 mlxsw_reg_sbsr_clr_set(payload, clr);
7756}
7757
7758
7759
7760
7761
7762MLXSW_ITEM32_INDEXED(reg, sbsr, rec_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
7763 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x00, false);
7764
7765
7766
7767
7768
7769
7770MLXSW_ITEM32_INDEXED(reg, sbsr, rec_max_buff_occupancy, MLXSW_REG_SBSR_BASE_LEN,
7771 0, 24, MLXSW_REG_SBSR_REC_LEN, 0x04, false);
7772
7773static inline void mlxsw_reg_sbsr_rec_unpack(char *payload, int rec_index,
7774 u32 *p_buff_occupancy,
7775 u32 *p_max_buff_occupancy)
7776{
7777 *p_buff_occupancy =
7778 mlxsw_reg_sbsr_rec_buff_occupancy_get(payload, rec_index);
7779 *p_max_buff_occupancy =
7780 mlxsw_reg_sbsr_rec_max_buff_occupancy_get(payload, rec_index);
7781}
7782
7783
7784
7785
7786
7787
7788
7789
7790
7791#define MLXSW_REG_SBIB_ID 0xB006
7792#define MLXSW_REG_SBIB_LEN 0x10
7793
7794MLXSW_REG_DEFINE(sbib, MLXSW_REG_SBIB_ID, MLXSW_REG_SBIB_LEN);
7795
7796
7797
7798
7799
7800
7801MLXSW_ITEM32(reg, sbib, local_port, 0x00, 16, 8);
7802
7803
7804
7805
7806
7807
7808
7809MLXSW_ITEM32(reg, sbib, buff_size, 0x08, 0, 24);
7810
7811static inline void mlxsw_reg_sbib_pack(char *payload, u8 local_port,
7812 u32 buff_size)
7813{
7814 MLXSW_REG_ZERO(sbib, payload);
7815 mlxsw_reg_sbib_local_port_set(payload, local_port);
7816 mlxsw_reg_sbib_buff_size_set(payload, buff_size);
7817}
7818
7819static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
7820 MLXSW_REG(sgcr),
7821 MLXSW_REG(spad),
7822 MLXSW_REG(smid),
7823 MLXSW_REG(sspr),
7824 MLXSW_REG(sfdat),
7825 MLXSW_REG(sfd),
7826 MLXSW_REG(sfn),
7827 MLXSW_REG(spms),
7828 MLXSW_REG(spvid),
7829 MLXSW_REG(spvm),
7830 MLXSW_REG(spaft),
7831 MLXSW_REG(sfgc),
7832 MLXSW_REG(sftr),
7833 MLXSW_REG(sfdf),
7834 MLXSW_REG(sldr),
7835 MLXSW_REG(slcr),
7836 MLXSW_REG(slcor),
7837 MLXSW_REG(spmlr),
7838 MLXSW_REG(svfa),
7839 MLXSW_REG(svpe),
7840 MLXSW_REG(sfmr),
7841 MLXSW_REG(spvmlr),
7842 MLXSW_REG(cwtp),
7843 MLXSW_REG(cwtpm),
7844 MLXSW_REG(ppbt),
7845 MLXSW_REG(pacl),
7846 MLXSW_REG(pagt),
7847 MLXSW_REG(ptar),
7848 MLXSW_REG(ppbs),
7849 MLXSW_REG(prcr),
7850 MLXSW_REG(pefa),
7851 MLXSW_REG(ptce2),
7852 MLXSW_REG(qpcr),
7853 MLXSW_REG(qtct),
7854 MLXSW_REG(qeec),
7855 MLXSW_REG(pmlp),
7856 MLXSW_REG(pmtu),
7857 MLXSW_REG(ptys),
7858 MLXSW_REG(ppad),
7859 MLXSW_REG(paos),
7860 MLXSW_REG(pfcc),
7861 MLXSW_REG(ppcnt),
7862 MLXSW_REG(plib),
7863 MLXSW_REG(pptb),
7864 MLXSW_REG(pbmc),
7865 MLXSW_REG(pspa),
7866 MLXSW_REG(htgt),
7867 MLXSW_REG(hpkt),
7868 MLXSW_REG(rgcr),
7869 MLXSW_REG(ritr),
7870 MLXSW_REG(rtar),
7871 MLXSW_REG(ratr),
7872 MLXSW_REG(rtdp),
7873 MLXSW_REG(rdpm),
7874 MLXSW_REG(ricnt),
7875 MLXSW_REG(rrcr),
7876 MLXSW_REG(ralta),
7877 MLXSW_REG(ralst),
7878 MLXSW_REG(raltb),
7879 MLXSW_REG(ralue),
7880 MLXSW_REG(rauht),
7881 MLXSW_REG(raleu),
7882 MLXSW_REG(rauhtd),
7883 MLXSW_REG(rigr2),
7884 MLXSW_REG(recr2),
7885 MLXSW_REG(rmft2),
7886 MLXSW_REG(mfcr),
7887 MLXSW_REG(mfsc),
7888 MLXSW_REG(mfsm),
7889 MLXSW_REG(mfsl),
7890 MLXSW_REG(mtcap),
7891 MLXSW_REG(mtmp),
7892 MLXSW_REG(mcia),
7893 MLXSW_REG(mpat),
7894 MLXSW_REG(mpar),
7895 MLXSW_REG(mlcr),
7896 MLXSW_REG(mpsc),
7897 MLXSW_REG(mcqi),
7898 MLXSW_REG(mcc),
7899 MLXSW_REG(mcda),
7900 MLXSW_REG(mgpc),
7901 MLXSW_REG(tigcr),
7902 MLXSW_REG(sbpr),
7903 MLXSW_REG(sbcm),
7904 MLXSW_REG(sbpm),
7905 MLXSW_REG(sbmm),
7906 MLXSW_REG(sbsr),
7907 MLXSW_REG(sbib),
7908};
7909
7910static inline const char *mlxsw_reg_id_str(u16 reg_id)
7911{
7912 const struct mlxsw_reg_info *reg_info;
7913 int i;
7914
7915 for (i = 0; i < ARRAY_SIZE(mlxsw_reg_infos); i++) {
7916 reg_info = mlxsw_reg_infos[i];
7917 if (reg_info->id == reg_id)
7918 return reg_info->name;
7919 }
7920 return "*UNKNOWN*";
7921}
7922
7923
7924
7925
7926
7927#define MLXSW_REG_PUDE_LEN 0x10
7928
7929
7930
7931
7932
7933MLXSW_ITEM32(reg, pude, swid, 0x00, 24, 8);
7934
7935
7936
7937
7938
7939MLXSW_ITEM32(reg, pude, local_port, 0x00, 16, 8);
7940
7941
7942
7943
7944
7945
7946
7947
7948
7949
7950MLXSW_ITEM32(reg, pude, admin_status, 0x00, 8, 4);
7951
7952
7953
7954
7955
7956
7957
7958
7959
7960MLXSW_ITEM32(reg, pude, oper_status, 0x00, 0, 4);
7961
7962#endif
7963