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33#include <linux/types.h>
34#include <asm/byteorder.h>
35#include <linux/delay.h>
36#include <linux/errno.h>
37#include <linux/kernel.h>
38#include <linux/slab.h>
39#include <linux/spinlock.h>
40#include <linux/string.h>
41#include <linux/etherdevice.h>
42#include "qed.h"
43#include "qed_dcbx.h"
44#include "qed_hsi.h"
45#include "qed_hw.h"
46#include "qed_mcp.h"
47#include "qed_reg_addr.h"
48#include "qed_sriov.h"
49
50#define CHIP_MCP_RESP_ITER_US 10
51
52#define QED_DRV_MB_MAX_RETRIES (500 * 1000)
53#define QED_MCP_RESET_RETRIES (50 * 1000)
54
55#define DRV_INNER_WR(_p_hwfn, _p_ptt, _ptr, _offset, _val) \
56 qed_wr(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset), \
57 _val)
58
59#define DRV_INNER_RD(_p_hwfn, _p_ptt, _ptr, _offset) \
60 qed_rd(_p_hwfn, _p_ptt, (_p_hwfn->mcp_info->_ptr + _offset))
61
62#define DRV_MB_WR(_p_hwfn, _p_ptt, _field, _val) \
63 DRV_INNER_WR(p_hwfn, _p_ptt, drv_mb_addr, \
64 offsetof(struct public_drv_mb, _field), _val)
65
66#define DRV_MB_RD(_p_hwfn, _p_ptt, _field) \
67 DRV_INNER_RD(_p_hwfn, _p_ptt, drv_mb_addr, \
68 offsetof(struct public_drv_mb, _field))
69
70#define PDA_COMP (((FW_MAJOR_VERSION) + (FW_MINOR_VERSION << 8)) << \
71 DRV_ID_PDA_COMP_VER_SHIFT)
72
73#define MCP_BYTES_PER_MBIT_SHIFT 17
74
75bool qed_mcp_is_init(struct qed_hwfn *p_hwfn)
76{
77 if (!p_hwfn->mcp_info || !p_hwfn->mcp_info->public_base)
78 return false;
79 return true;
80}
81
82void qed_mcp_cmd_port_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
83{
84 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
85 PUBLIC_PORT);
86 u32 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt, addr);
87
88 p_hwfn->mcp_info->port_addr = SECTION_ADDR(mfw_mb_offsize,
89 MFW_PORT(p_hwfn));
90 DP_VERBOSE(p_hwfn, QED_MSG_SP,
91 "port_addr = 0x%x, port_id 0x%02x\n",
92 p_hwfn->mcp_info->port_addr, MFW_PORT(p_hwfn));
93}
94
95void qed_mcp_read_mb(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
96{
97 u32 length = MFW_DRV_MSG_MAX_DWORDS(p_hwfn->mcp_info->mfw_mb_length);
98 u32 tmp, i;
99
100 if (!p_hwfn->mcp_info->public_base)
101 return;
102
103 for (i = 0; i < length; i++) {
104 tmp = qed_rd(p_hwfn, p_ptt,
105 p_hwfn->mcp_info->mfw_mb_addr +
106 (i << 2) + sizeof(u32));
107
108
109 ((u32 *)p_hwfn->mcp_info->mfw_mb_cur)[i] =
110 be32_to_cpu((__force __be32)tmp);
111 }
112}
113
114struct qed_mcp_cmd_elem {
115 struct list_head list;
116 struct qed_mcp_mb_params *p_mb_params;
117 u16 expected_seq_num;
118 bool b_is_completed;
119};
120
121
122static struct qed_mcp_cmd_elem *
123qed_mcp_cmd_add_elem(struct qed_hwfn *p_hwfn,
124 struct qed_mcp_mb_params *p_mb_params,
125 u16 expected_seq_num)
126{
127 struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
128
129 p_cmd_elem = kzalloc(sizeof(*p_cmd_elem), GFP_ATOMIC);
130 if (!p_cmd_elem)
131 goto out;
132
133 p_cmd_elem->p_mb_params = p_mb_params;
134 p_cmd_elem->expected_seq_num = expected_seq_num;
135 list_add(&p_cmd_elem->list, &p_hwfn->mcp_info->cmd_list);
136out:
137 return p_cmd_elem;
138}
139
140
141static void qed_mcp_cmd_del_elem(struct qed_hwfn *p_hwfn,
142 struct qed_mcp_cmd_elem *p_cmd_elem)
143{
144 list_del(&p_cmd_elem->list);
145 kfree(p_cmd_elem);
146}
147
148
149static struct qed_mcp_cmd_elem *qed_mcp_cmd_get_elem(struct qed_hwfn *p_hwfn,
150 u16 seq_num)
151{
152 struct qed_mcp_cmd_elem *p_cmd_elem = NULL;
153
154 list_for_each_entry(p_cmd_elem, &p_hwfn->mcp_info->cmd_list, list) {
155 if (p_cmd_elem->expected_seq_num == seq_num)
156 return p_cmd_elem;
157 }
158
159 return NULL;
160}
161
162int qed_mcp_free(struct qed_hwfn *p_hwfn)
163{
164 if (p_hwfn->mcp_info) {
165 struct qed_mcp_cmd_elem *p_cmd_elem, *p_tmp;
166
167 kfree(p_hwfn->mcp_info->mfw_mb_cur);
168 kfree(p_hwfn->mcp_info->mfw_mb_shadow);
169
170 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
171 list_for_each_entry_safe(p_cmd_elem,
172 p_tmp,
173 &p_hwfn->mcp_info->cmd_list, list) {
174 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
175 }
176 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
177 }
178
179 kfree(p_hwfn->mcp_info);
180 p_hwfn->mcp_info = NULL;
181
182 return 0;
183}
184
185static int qed_load_mcp_offsets(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
186{
187 struct qed_mcp_info *p_info = p_hwfn->mcp_info;
188 u32 drv_mb_offsize, mfw_mb_offsize;
189 u32 mcp_pf_id = MCP_PF_ID(p_hwfn);
190
191 p_info->public_base = qed_rd(p_hwfn, p_ptt, MISC_REG_SHARED_MEM_ADDR);
192 if (!p_info->public_base)
193 return 0;
194
195 p_info->public_base |= GRCBASE_MCP;
196
197
198 drv_mb_offsize = qed_rd(p_hwfn, p_ptt,
199 SECTION_OFFSIZE_ADDR(p_info->public_base,
200 PUBLIC_DRV_MB));
201 p_info->drv_mb_addr = SECTION_ADDR(drv_mb_offsize, mcp_pf_id);
202 DP_VERBOSE(p_hwfn, QED_MSG_SP,
203 "drv_mb_offsiz = 0x%x, drv_mb_addr = 0x%x mcp_pf_id = 0x%x\n",
204 drv_mb_offsize, p_info->drv_mb_addr, mcp_pf_id);
205
206
207 mfw_mb_offsize = qed_rd(p_hwfn, p_ptt,
208 SECTION_OFFSIZE_ADDR(p_info->public_base,
209 PUBLIC_MFW_MB));
210 p_info->mfw_mb_addr = SECTION_ADDR(mfw_mb_offsize, mcp_pf_id);
211 p_info->mfw_mb_length = (u16)qed_rd(p_hwfn, p_ptt, p_info->mfw_mb_addr);
212
213
214
215
216 p_info->drv_mb_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_mb_header) &
217 DRV_MSG_SEQ_NUMBER_MASK;
218
219
220 p_info->drv_pulse_seq = DRV_MB_RD(p_hwfn, p_ptt, drv_pulse_mb) &
221 DRV_PULSE_SEQ_MASK;
222
223 p_info->mcp_hist = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
224
225 return 0;
226}
227
228int qed_mcp_cmd_init(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
229{
230 struct qed_mcp_info *p_info;
231 u32 size;
232
233
234 p_hwfn->mcp_info = kzalloc(sizeof(*p_hwfn->mcp_info), GFP_KERNEL);
235 if (!p_hwfn->mcp_info)
236 goto err;
237 p_info = p_hwfn->mcp_info;
238
239
240 spin_lock_init(&p_info->cmd_lock);
241 spin_lock_init(&p_info->link_lock);
242
243 INIT_LIST_HEAD(&p_info->cmd_list);
244
245 if (qed_load_mcp_offsets(p_hwfn, p_ptt) != 0) {
246 DP_NOTICE(p_hwfn, "MCP is not initialized\n");
247
248
249
250 return 0;
251 }
252
253 size = MFW_DRV_MSG_MAX_DWORDS(p_info->mfw_mb_length) * sizeof(u32);
254 p_info->mfw_mb_cur = kzalloc(size, GFP_KERNEL);
255 p_info->mfw_mb_shadow = kzalloc(size, GFP_KERNEL);
256 if (!p_info->mfw_mb_cur || !p_info->mfw_mb_shadow)
257 goto err;
258
259 return 0;
260
261err:
262 qed_mcp_free(p_hwfn);
263 return -ENOMEM;
264}
265
266static void qed_mcp_reread_offsets(struct qed_hwfn *p_hwfn,
267 struct qed_ptt *p_ptt)
268{
269 u32 generic_por_0 = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
270
271
272
273
274 if (p_hwfn->mcp_info->mcp_hist != generic_por_0) {
275 DP_VERBOSE(p_hwfn,
276 QED_MSG_SP,
277 "Rereading MCP offsets [mcp_hist 0x%08x, generic_por_0 0x%08x]\n",
278 p_hwfn->mcp_info->mcp_hist, generic_por_0);
279
280 qed_load_mcp_offsets(p_hwfn, p_ptt);
281 qed_mcp_cmd_port_init(p_hwfn, p_ptt);
282 }
283}
284
285int qed_mcp_reset(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
286{
287 u32 org_mcp_reset_seq, seq, delay = CHIP_MCP_RESP_ITER_US, cnt = 0;
288 int rc = 0;
289
290
291 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
292
293 org_mcp_reset_seq = qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0);
294
295
296 qed_mcp_reread_offsets(p_hwfn, p_ptt);
297 seq = ++p_hwfn->mcp_info->drv_mb_seq;
298 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (DRV_MSG_CODE_MCP_RESET | seq));
299
300 do {
301
302 udelay(delay);
303
304 } while ((org_mcp_reset_seq == qed_rd(p_hwfn, p_ptt,
305 MISCS_REG_GENERIC_POR_0)) &&
306 (cnt++ < QED_MCP_RESET_RETRIES));
307
308 if (org_mcp_reset_seq !=
309 qed_rd(p_hwfn, p_ptt, MISCS_REG_GENERIC_POR_0)) {
310 DP_VERBOSE(p_hwfn, QED_MSG_SP,
311 "MCP was reset after %d usec\n", cnt * delay);
312 } else {
313 DP_ERR(p_hwfn, "Failed to reset MCP\n");
314 rc = -EAGAIN;
315 }
316
317 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
318
319 return rc;
320}
321
322
323static bool qed_mcp_has_pending_cmd(struct qed_hwfn *p_hwfn)
324{
325 struct qed_mcp_cmd_elem *p_cmd_elem;
326
327
328
329
330 if (!list_empty(&p_hwfn->mcp_info->cmd_list)) {
331 p_cmd_elem = list_first_entry(&p_hwfn->mcp_info->cmd_list,
332 struct qed_mcp_cmd_elem, list);
333 return !p_cmd_elem->b_is_completed;
334 }
335
336 return false;
337}
338
339
340static int
341qed_mcp_update_pending_cmd(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
342{
343 struct qed_mcp_mb_params *p_mb_params;
344 struct qed_mcp_cmd_elem *p_cmd_elem;
345 u32 mcp_resp;
346 u16 seq_num;
347
348 mcp_resp = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_header);
349 seq_num = (u16)(mcp_resp & FW_MSG_SEQ_NUMBER_MASK);
350
351
352 if (seq_num != p_hwfn->mcp_info->drv_mb_seq)
353 return -EAGAIN;
354
355 p_cmd_elem = qed_mcp_cmd_get_elem(p_hwfn, seq_num);
356 if (!p_cmd_elem) {
357 DP_ERR(p_hwfn,
358 "Failed to find a pending mailbox cmd that expects sequence number %d\n",
359 seq_num);
360 return -EINVAL;
361 }
362
363 p_mb_params = p_cmd_elem->p_mb_params;
364
365
366 p_mb_params->mcp_resp = mcp_resp;
367
368
369 p_mb_params->mcp_param = DRV_MB_RD(p_hwfn, p_ptt, fw_mb_param);
370
371
372 if (p_mb_params->p_data_dst != NULL && p_mb_params->data_dst_size) {
373 u32 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
374 offsetof(struct public_drv_mb,
375 union_data);
376 qed_memcpy_from(p_hwfn, p_ptt, p_mb_params->p_data_dst,
377 union_data_addr, p_mb_params->data_dst_size);
378 }
379
380 p_cmd_elem->b_is_completed = true;
381
382 return 0;
383}
384
385
386static void __qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
387 struct qed_ptt *p_ptt,
388 struct qed_mcp_mb_params *p_mb_params,
389 u16 seq_num)
390{
391 union drv_union_data union_data;
392 u32 union_data_addr;
393
394
395 union_data_addr = p_hwfn->mcp_info->drv_mb_addr +
396 offsetof(struct public_drv_mb, union_data);
397 memset(&union_data, 0, sizeof(union_data));
398 if (p_mb_params->p_data_src != NULL && p_mb_params->data_src_size)
399 memcpy(&union_data, p_mb_params->p_data_src,
400 p_mb_params->data_src_size);
401 qed_memcpy_to(p_hwfn, p_ptt, union_data_addr, &union_data,
402 sizeof(union_data));
403
404
405 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_param, p_mb_params->param);
406
407
408 DRV_MB_WR(p_hwfn, p_ptt, drv_mb_header, (p_mb_params->cmd | seq_num));
409
410 DP_VERBOSE(p_hwfn, QED_MSG_SP,
411 "MFW mailbox: command 0x%08x param 0x%08x\n",
412 (p_mb_params->cmd | seq_num), p_mb_params->param);
413}
414
415static int
416_qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
417 struct qed_ptt *p_ptt,
418 struct qed_mcp_mb_params *p_mb_params,
419 u32 max_retries, u32 delay)
420{
421 struct qed_mcp_cmd_elem *p_cmd_elem;
422 u32 cnt = 0;
423 u16 seq_num;
424 int rc = 0;
425
426
427 do {
428
429
430
431
432
433 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
434
435 if (!qed_mcp_has_pending_cmd(p_hwfn))
436 break;
437
438 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
439 if (!rc)
440 break;
441 else if (rc != -EAGAIN)
442 goto err;
443
444 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
445 udelay(delay);
446 } while (++cnt < max_retries);
447
448 if (cnt >= max_retries) {
449 DP_NOTICE(p_hwfn,
450 "The MFW mailbox is occupied by an uncompleted command. Failed to send command 0x%08x [param 0x%08x].\n",
451 p_mb_params->cmd, p_mb_params->param);
452 return -EAGAIN;
453 }
454
455
456 qed_mcp_reread_offsets(p_hwfn, p_ptt);
457 seq_num = ++p_hwfn->mcp_info->drv_mb_seq;
458 p_cmd_elem = qed_mcp_cmd_add_elem(p_hwfn, p_mb_params, seq_num);
459 if (!p_cmd_elem) {
460 rc = -ENOMEM;
461 goto err;
462 }
463
464 __qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, seq_num);
465 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
466
467
468 do {
469
470
471
472
473
474 udelay(delay);
475 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
476
477 if (p_cmd_elem->b_is_completed)
478 break;
479
480 rc = qed_mcp_update_pending_cmd(p_hwfn, p_ptt);
481 if (!rc)
482 break;
483 else if (rc != -EAGAIN)
484 goto err;
485
486 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
487 } while (++cnt < max_retries);
488
489 if (cnt >= max_retries) {
490 DP_NOTICE(p_hwfn,
491 "The MFW failed to respond to command 0x%08x [param 0x%08x].\n",
492 p_mb_params->cmd, p_mb_params->param);
493
494 spin_lock_bh(&p_hwfn->mcp_info->cmd_lock);
495 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
496 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
497
498 return -EAGAIN;
499 }
500
501 qed_mcp_cmd_del_elem(p_hwfn, p_cmd_elem);
502 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
503
504 DP_VERBOSE(p_hwfn,
505 QED_MSG_SP,
506 "MFW mailbox: response 0x%08x param 0x%08x [after %d.%03d ms]\n",
507 p_mb_params->mcp_resp,
508 p_mb_params->mcp_param,
509 (cnt * delay) / 1000, (cnt * delay) % 1000);
510
511
512 p_mb_params->mcp_resp &= FW_MSG_CODE_MASK;
513
514 return 0;
515
516err:
517 spin_unlock_bh(&p_hwfn->mcp_info->cmd_lock);
518 return rc;
519}
520
521static int qed_mcp_cmd_and_union(struct qed_hwfn *p_hwfn,
522 struct qed_ptt *p_ptt,
523 struct qed_mcp_mb_params *p_mb_params)
524{
525 size_t union_data_size = sizeof(union drv_union_data);
526 u32 max_retries = QED_DRV_MB_MAX_RETRIES;
527 u32 delay = CHIP_MCP_RESP_ITER_US;
528
529
530 if (!qed_mcp_is_init(p_hwfn)) {
531 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
532 return -EBUSY;
533 }
534
535 if (p_mb_params->data_src_size > union_data_size ||
536 p_mb_params->data_dst_size > union_data_size) {
537 DP_ERR(p_hwfn,
538 "The provided size is larger than the union data size [src_size %u, dst_size %u, union_data_size %zu]\n",
539 p_mb_params->data_src_size,
540 p_mb_params->data_dst_size, union_data_size);
541 return -EINVAL;
542 }
543
544 return _qed_mcp_cmd_and_union(p_hwfn, p_ptt, p_mb_params, max_retries,
545 delay);
546}
547
548int qed_mcp_cmd(struct qed_hwfn *p_hwfn,
549 struct qed_ptt *p_ptt,
550 u32 cmd,
551 u32 param,
552 u32 *o_mcp_resp,
553 u32 *o_mcp_param)
554{
555 struct qed_mcp_mb_params mb_params;
556 int rc;
557
558 memset(&mb_params, 0, sizeof(mb_params));
559 mb_params.cmd = cmd;
560 mb_params.param = param;
561
562 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
563 if (rc)
564 return rc;
565
566 *o_mcp_resp = mb_params.mcp_resp;
567 *o_mcp_param = mb_params.mcp_param;
568
569 return 0;
570}
571
572int qed_mcp_nvm_wr_cmd(struct qed_hwfn *p_hwfn,
573 struct qed_ptt *p_ptt,
574 u32 cmd,
575 u32 param,
576 u32 *o_mcp_resp,
577 u32 *o_mcp_param, u32 i_txn_size, u32 *i_buf)
578{
579 struct qed_mcp_mb_params mb_params;
580 int rc;
581
582 memset(&mb_params, 0, sizeof(mb_params));
583 mb_params.cmd = cmd;
584 mb_params.param = param;
585 mb_params.p_data_src = i_buf;
586 mb_params.data_src_size = (u8)i_txn_size;
587 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
588 if (rc)
589 return rc;
590
591 *o_mcp_resp = mb_params.mcp_resp;
592 *o_mcp_param = mb_params.mcp_param;
593
594 return 0;
595}
596
597int qed_mcp_nvm_rd_cmd(struct qed_hwfn *p_hwfn,
598 struct qed_ptt *p_ptt,
599 u32 cmd,
600 u32 param,
601 u32 *o_mcp_resp,
602 u32 *o_mcp_param, u32 *o_txn_size, u32 *o_buf)
603{
604 struct qed_mcp_mb_params mb_params;
605 u8 raw_data[MCP_DRV_NVM_BUF_LEN];
606 int rc;
607
608 memset(&mb_params, 0, sizeof(mb_params));
609 mb_params.cmd = cmd;
610 mb_params.param = param;
611 mb_params.p_data_dst = raw_data;
612
613
614 mb_params.data_dst_size = MCP_DRV_NVM_BUF_LEN;
615
616 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
617 if (rc)
618 return rc;
619
620 *o_mcp_resp = mb_params.mcp_resp;
621 *o_mcp_param = mb_params.mcp_param;
622
623 *o_txn_size = *o_mcp_param;
624 memcpy(o_buf, raw_data, *o_txn_size);
625
626 return 0;
627}
628
629static bool
630qed_mcp_can_force_load(u8 drv_role,
631 u8 exist_drv_role,
632 enum qed_override_force_load override_force_load)
633{
634 bool can_force_load = false;
635
636 switch (override_force_load) {
637 case QED_OVERRIDE_FORCE_LOAD_ALWAYS:
638 can_force_load = true;
639 break;
640 case QED_OVERRIDE_FORCE_LOAD_NEVER:
641 can_force_load = false;
642 break;
643 default:
644 can_force_load = (drv_role == DRV_ROLE_OS &&
645 exist_drv_role == DRV_ROLE_PREBOOT) ||
646 (drv_role == DRV_ROLE_KDUMP &&
647 exist_drv_role == DRV_ROLE_OS);
648 break;
649 }
650
651 return can_force_load;
652}
653
654static int qed_mcp_cancel_load_req(struct qed_hwfn *p_hwfn,
655 struct qed_ptt *p_ptt)
656{
657 u32 resp = 0, param = 0;
658 int rc;
659
660 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CANCEL_LOAD_REQ, 0,
661 &resp, ¶m);
662 if (rc)
663 DP_NOTICE(p_hwfn,
664 "Failed to send cancel load request, rc = %d\n", rc);
665
666 return rc;
667}
668
669#define CONFIG_QEDE_BITMAP_IDX BIT(0)
670#define CONFIG_QED_SRIOV_BITMAP_IDX BIT(1)
671#define CONFIG_QEDR_BITMAP_IDX BIT(2)
672#define CONFIG_QEDF_BITMAP_IDX BIT(4)
673#define CONFIG_QEDI_BITMAP_IDX BIT(5)
674#define CONFIG_QED_LL2_BITMAP_IDX BIT(6)
675
676static u32 qed_get_config_bitmap(void)
677{
678 u32 config_bitmap = 0x0;
679
680 if (IS_ENABLED(CONFIG_QEDE))
681 config_bitmap |= CONFIG_QEDE_BITMAP_IDX;
682
683 if (IS_ENABLED(CONFIG_QED_SRIOV))
684 config_bitmap |= CONFIG_QED_SRIOV_BITMAP_IDX;
685
686 if (IS_ENABLED(CONFIG_QED_RDMA))
687 config_bitmap |= CONFIG_QEDR_BITMAP_IDX;
688
689 if (IS_ENABLED(CONFIG_QED_FCOE))
690 config_bitmap |= CONFIG_QEDF_BITMAP_IDX;
691
692 if (IS_ENABLED(CONFIG_QED_ISCSI))
693 config_bitmap |= CONFIG_QEDI_BITMAP_IDX;
694
695 if (IS_ENABLED(CONFIG_QED_LL2))
696 config_bitmap |= CONFIG_QED_LL2_BITMAP_IDX;
697
698 return config_bitmap;
699}
700
701struct qed_load_req_in_params {
702 u8 hsi_ver;
703#define QED_LOAD_REQ_HSI_VER_DEFAULT 0
704#define QED_LOAD_REQ_HSI_VER_1 1
705 u32 drv_ver_0;
706 u32 drv_ver_1;
707 u32 fw_ver;
708 u8 drv_role;
709 u8 timeout_val;
710 u8 force_cmd;
711 bool avoid_eng_reset;
712};
713
714struct qed_load_req_out_params {
715 u32 load_code;
716 u32 exist_drv_ver_0;
717 u32 exist_drv_ver_1;
718 u32 exist_fw_ver;
719 u8 exist_drv_role;
720 u8 mfw_hsi_ver;
721 bool drv_exists;
722};
723
724static int
725__qed_mcp_load_req(struct qed_hwfn *p_hwfn,
726 struct qed_ptt *p_ptt,
727 struct qed_load_req_in_params *p_in_params,
728 struct qed_load_req_out_params *p_out_params)
729{
730 struct qed_mcp_mb_params mb_params;
731 struct load_req_stc load_req;
732 struct load_rsp_stc load_rsp;
733 u32 hsi_ver;
734 int rc;
735
736 memset(&load_req, 0, sizeof(load_req));
737 load_req.drv_ver_0 = p_in_params->drv_ver_0;
738 load_req.drv_ver_1 = p_in_params->drv_ver_1;
739 load_req.fw_ver = p_in_params->fw_ver;
740 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_ROLE, p_in_params->drv_role);
741 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_LOCK_TO,
742 p_in_params->timeout_val);
743 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FORCE,
744 p_in_params->force_cmd);
745 QED_MFW_SET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0,
746 p_in_params->avoid_eng_reset);
747
748 hsi_ver = (p_in_params->hsi_ver == QED_LOAD_REQ_HSI_VER_DEFAULT) ?
749 DRV_ID_MCP_HSI_VER_CURRENT :
750 (p_in_params->hsi_ver << DRV_ID_MCP_HSI_VER_SHIFT);
751
752 memset(&mb_params, 0, sizeof(mb_params));
753 mb_params.cmd = DRV_MSG_CODE_LOAD_REQ;
754 mb_params.param = PDA_COMP | hsi_ver | p_hwfn->cdev->drv_type;
755 mb_params.p_data_src = &load_req;
756 mb_params.data_src_size = sizeof(load_req);
757 mb_params.p_data_dst = &load_rsp;
758 mb_params.data_dst_size = sizeof(load_rsp);
759
760 DP_VERBOSE(p_hwfn, QED_MSG_SP,
761 "Load Request: param 0x%08x [init_hw %d, drv_type %d, hsi_ver %d, pda 0x%04x]\n",
762 mb_params.param,
763 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_INIT_HW),
764 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_DRV_TYPE),
765 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_MCP_HSI_VER),
766 QED_MFW_GET_FIELD(mb_params.param, DRV_ID_PDA_COMP_VER));
767
768 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1) {
769 DP_VERBOSE(p_hwfn, QED_MSG_SP,
770 "Load Request: drv_ver 0x%08x_0x%08x, fw_ver 0x%08x, misc0 0x%08x [role %d, timeout %d, force %d, flags0 0x%x]\n",
771 load_req.drv_ver_0,
772 load_req.drv_ver_1,
773 load_req.fw_ver,
774 load_req.misc0,
775 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_ROLE),
776 QED_MFW_GET_FIELD(load_req.misc0,
777 LOAD_REQ_LOCK_TO),
778 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FORCE),
779 QED_MFW_GET_FIELD(load_req.misc0, LOAD_REQ_FLAGS0));
780 }
781
782 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
783 if (rc) {
784 DP_NOTICE(p_hwfn, "Failed to send load request, rc = %d\n", rc);
785 return rc;
786 }
787
788 DP_VERBOSE(p_hwfn, QED_MSG_SP,
789 "Load Response: resp 0x%08x\n", mb_params.mcp_resp);
790 p_out_params->load_code = mb_params.mcp_resp;
791
792 if (p_in_params->hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
793 p_out_params->load_code != FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
794 DP_VERBOSE(p_hwfn,
795 QED_MSG_SP,
796 "Load Response: exist_drv_ver 0x%08x_0x%08x, exist_fw_ver 0x%08x, misc0 0x%08x [exist_role %d, mfw_hsi %d, flags0 0x%x]\n",
797 load_rsp.drv_ver_0,
798 load_rsp.drv_ver_1,
799 load_rsp.fw_ver,
800 load_rsp.misc0,
801 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE),
802 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI),
803 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0));
804
805 p_out_params->exist_drv_ver_0 = load_rsp.drv_ver_0;
806 p_out_params->exist_drv_ver_1 = load_rsp.drv_ver_1;
807 p_out_params->exist_fw_ver = load_rsp.fw_ver;
808 p_out_params->exist_drv_role =
809 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_ROLE);
810 p_out_params->mfw_hsi_ver =
811 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_HSI);
812 p_out_params->drv_exists =
813 QED_MFW_GET_FIELD(load_rsp.misc0, LOAD_RSP_FLAGS0) &
814 LOAD_RSP_FLAGS0_DRV_EXISTS;
815 }
816
817 return 0;
818}
819
820static int eocre_get_mfw_drv_role(struct qed_hwfn *p_hwfn,
821 enum qed_drv_role drv_role,
822 u8 *p_mfw_drv_role)
823{
824 switch (drv_role) {
825 case QED_DRV_ROLE_OS:
826 *p_mfw_drv_role = DRV_ROLE_OS;
827 break;
828 case QED_DRV_ROLE_KDUMP:
829 *p_mfw_drv_role = DRV_ROLE_KDUMP;
830 break;
831 default:
832 DP_ERR(p_hwfn, "Unexpected driver role %d\n", drv_role);
833 return -EINVAL;
834 }
835
836 return 0;
837}
838
839enum qed_load_req_force {
840 QED_LOAD_REQ_FORCE_NONE,
841 QED_LOAD_REQ_FORCE_PF,
842 QED_LOAD_REQ_FORCE_ALL,
843};
844
845static void qed_get_mfw_force_cmd(struct qed_hwfn *p_hwfn,
846
847 enum qed_load_req_force force_cmd,
848 u8 *p_mfw_force_cmd)
849{
850 switch (force_cmd) {
851 case QED_LOAD_REQ_FORCE_NONE:
852 *p_mfw_force_cmd = LOAD_REQ_FORCE_NONE;
853 break;
854 case QED_LOAD_REQ_FORCE_PF:
855 *p_mfw_force_cmd = LOAD_REQ_FORCE_PF;
856 break;
857 case QED_LOAD_REQ_FORCE_ALL:
858 *p_mfw_force_cmd = LOAD_REQ_FORCE_ALL;
859 break;
860 }
861}
862
863int qed_mcp_load_req(struct qed_hwfn *p_hwfn,
864 struct qed_ptt *p_ptt,
865 struct qed_load_req_params *p_params)
866{
867 struct qed_load_req_out_params out_params;
868 struct qed_load_req_in_params in_params;
869 u8 mfw_drv_role, mfw_force_cmd;
870 int rc;
871
872 memset(&in_params, 0, sizeof(in_params));
873 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_DEFAULT;
874 in_params.drv_ver_0 = QED_VERSION;
875 in_params.drv_ver_1 = qed_get_config_bitmap();
876 in_params.fw_ver = STORM_FW_VERSION;
877 rc = eocre_get_mfw_drv_role(p_hwfn, p_params->drv_role, &mfw_drv_role);
878 if (rc)
879 return rc;
880
881 in_params.drv_role = mfw_drv_role;
882 in_params.timeout_val = p_params->timeout_val;
883 qed_get_mfw_force_cmd(p_hwfn,
884 QED_LOAD_REQ_FORCE_NONE, &mfw_force_cmd);
885
886 in_params.force_cmd = mfw_force_cmd;
887 in_params.avoid_eng_reset = p_params->avoid_eng_reset;
888
889 memset(&out_params, 0, sizeof(out_params));
890 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
891 if (rc)
892 return rc;
893
894
895
896
897
898 if (out_params.load_code == FW_MSG_CODE_DRV_LOAD_REFUSED_HSI_1) {
899 DP_INFO(p_hwfn,
900 "MFW refused a load request due to HSI > 1. Resending with HSI = 1\n");
901
902 in_params.hsi_ver = QED_LOAD_REQ_HSI_VER_1;
903 memset(&out_params, 0, sizeof(out_params));
904 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params, &out_params);
905 if (rc)
906 return rc;
907 } else if (out_params.load_code ==
908 FW_MSG_CODE_DRV_LOAD_REFUSED_REQUIRES_FORCE) {
909 if (qed_mcp_can_force_load(in_params.drv_role,
910 out_params.exist_drv_role,
911 p_params->override_force_load)) {
912 DP_INFO(p_hwfn,
913 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}]\n",
914 in_params.drv_role, in_params.fw_ver,
915 in_params.drv_ver_0, in_params.drv_ver_1,
916 out_params.exist_drv_role,
917 out_params.exist_fw_ver,
918 out_params.exist_drv_ver_0,
919 out_params.exist_drv_ver_1);
920
921 qed_get_mfw_force_cmd(p_hwfn,
922 QED_LOAD_REQ_FORCE_ALL,
923 &mfw_force_cmd);
924
925 in_params.force_cmd = mfw_force_cmd;
926 memset(&out_params, 0, sizeof(out_params));
927 rc = __qed_mcp_load_req(p_hwfn, p_ptt, &in_params,
928 &out_params);
929 if (rc)
930 return rc;
931 } else {
932 DP_NOTICE(p_hwfn,
933 "A force load is required [{role, fw_ver, drv_ver}: loading={%d, 0x%08x, x%08x_0x%08x}, existing={%d, 0x%08x, 0x%08x_0x%08x}] - Avoid\n",
934 in_params.drv_role, in_params.fw_ver,
935 in_params.drv_ver_0, in_params.drv_ver_1,
936 out_params.exist_drv_role,
937 out_params.exist_fw_ver,
938 out_params.exist_drv_ver_0,
939 out_params.exist_drv_ver_1);
940 DP_NOTICE(p_hwfn,
941 "Avoid sending a force load request to prevent disruption of active PFs\n");
942
943 qed_mcp_cancel_load_req(p_hwfn, p_ptt);
944 return -EBUSY;
945 }
946 }
947
948
949
950
951
952 switch (out_params.load_code) {
953 case FW_MSG_CODE_DRV_LOAD_ENGINE:
954 case FW_MSG_CODE_DRV_LOAD_PORT:
955 case FW_MSG_CODE_DRV_LOAD_FUNCTION:
956 if (out_params.mfw_hsi_ver != QED_LOAD_REQ_HSI_VER_1 &&
957 out_params.drv_exists) {
958
959
960
961 DP_NOTICE(p_hwfn,
962 "PF is already loaded\n");
963 return -EINVAL;
964 }
965 break;
966 default:
967 DP_NOTICE(p_hwfn,
968 "Unexpected refusal to load request [resp 0x%08x]. Aborting.\n",
969 out_params.load_code);
970 return -EBUSY;
971 }
972
973 p_params->load_code = out_params.load_code;
974
975 return 0;
976}
977
978int qed_mcp_unload_req(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
979{
980 u32 wol_param, mcp_resp, mcp_param;
981
982 switch (p_hwfn->cdev->wol_config) {
983 case QED_OV_WOL_DISABLED:
984 wol_param = DRV_MB_PARAM_UNLOAD_WOL_DISABLED;
985 break;
986 case QED_OV_WOL_ENABLED:
987 wol_param = DRV_MB_PARAM_UNLOAD_WOL_ENABLED;
988 break;
989 default:
990 DP_NOTICE(p_hwfn,
991 "Unknown WoL configuration %02x\n",
992 p_hwfn->cdev->wol_config);
993
994 case QED_OV_WOL_DEFAULT:
995 wol_param = DRV_MB_PARAM_UNLOAD_WOL_MCP;
996 }
997
998 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_UNLOAD_REQ, wol_param,
999 &mcp_resp, &mcp_param);
1000}
1001
1002int qed_mcp_unload_done(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1003{
1004 struct qed_mcp_mb_params mb_params;
1005 struct mcp_mac wol_mac;
1006
1007 memset(&mb_params, 0, sizeof(mb_params));
1008 mb_params.cmd = DRV_MSG_CODE_UNLOAD_DONE;
1009
1010
1011 if (p_hwfn->cdev->wol_config == QED_OV_WOL_ENABLED) {
1012 u8 *p_mac = p_hwfn->cdev->wol_mac;
1013
1014 memset(&wol_mac, 0, sizeof(wol_mac));
1015 wol_mac.mac_upper = p_mac[0] << 8 | p_mac[1];
1016 wol_mac.mac_lower = p_mac[2] << 24 | p_mac[3] << 16 |
1017 p_mac[4] << 8 | p_mac[5];
1018
1019 DP_VERBOSE(p_hwfn,
1020 (QED_MSG_SP | NETIF_MSG_IFDOWN),
1021 "Setting WoL MAC: %pM --> [%08x,%08x]\n",
1022 p_mac, wol_mac.mac_upper, wol_mac.mac_lower);
1023
1024 mb_params.p_data_src = &wol_mac;
1025 mb_params.data_src_size = sizeof(wol_mac);
1026 }
1027
1028 return qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1029}
1030
1031static void qed_mcp_handle_vf_flr(struct qed_hwfn *p_hwfn,
1032 struct qed_ptt *p_ptt)
1033{
1034 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1035 PUBLIC_PATH);
1036 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1037 u32 path_addr = SECTION_ADDR(mfw_path_offsize,
1038 QED_PATH_ID(p_hwfn));
1039 u32 disabled_vfs[VF_MAX_STATIC / 32];
1040 int i;
1041
1042 DP_VERBOSE(p_hwfn,
1043 QED_MSG_SP,
1044 "Reading Disabled VF information from [offset %08x], path_addr %08x\n",
1045 mfw_path_offsize, path_addr);
1046
1047 for (i = 0; i < (VF_MAX_STATIC / 32); i++) {
1048 disabled_vfs[i] = qed_rd(p_hwfn, p_ptt,
1049 path_addr +
1050 offsetof(struct public_path,
1051 mcp_vf_disabled) +
1052 sizeof(u32) * i);
1053 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1054 "FLR-ed VFs [%08x,...,%08x] - %08x\n",
1055 i * 32, (i + 1) * 32 - 1, disabled_vfs[i]);
1056 }
1057
1058 if (qed_iov_mark_vf_flr(p_hwfn, disabled_vfs))
1059 qed_schedule_iov(p_hwfn, QED_IOV_WQ_FLR_FLAG);
1060}
1061
1062int qed_mcp_ack_vf_flr(struct qed_hwfn *p_hwfn,
1063 struct qed_ptt *p_ptt, u32 *vfs_to_ack)
1064{
1065 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1066 PUBLIC_FUNC);
1067 u32 mfw_func_offsize = qed_rd(p_hwfn, p_ptt, addr);
1068 u32 func_addr = SECTION_ADDR(mfw_func_offsize,
1069 MCP_PF_ID(p_hwfn));
1070 struct qed_mcp_mb_params mb_params;
1071 int rc;
1072 int i;
1073
1074 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1075 DP_VERBOSE(p_hwfn, (QED_MSG_SP | QED_MSG_IOV),
1076 "Acking VFs [%08x,...,%08x] - %08x\n",
1077 i * 32, (i + 1) * 32 - 1, vfs_to_ack[i]);
1078
1079 memset(&mb_params, 0, sizeof(mb_params));
1080 mb_params.cmd = DRV_MSG_CODE_VF_DISABLED_DONE;
1081 mb_params.p_data_src = vfs_to_ack;
1082 mb_params.data_src_size = VF_MAX_STATIC / 8;
1083 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1084 if (rc) {
1085 DP_NOTICE(p_hwfn, "Failed to pass ACK for VF flr to MFW\n");
1086 return -EBUSY;
1087 }
1088
1089
1090 for (i = 0; i < (VF_MAX_STATIC / 32); i++)
1091 qed_wr(p_hwfn, p_ptt,
1092 func_addr +
1093 offsetof(struct public_func, drv_ack_vf_disabled) +
1094 i * sizeof(u32), 0);
1095
1096 return rc;
1097}
1098
1099static void qed_mcp_handle_transceiver_change(struct qed_hwfn *p_hwfn,
1100 struct qed_ptt *p_ptt)
1101{
1102 u32 transceiver_state;
1103
1104 transceiver_state = qed_rd(p_hwfn, p_ptt,
1105 p_hwfn->mcp_info->port_addr +
1106 offsetof(struct public_port,
1107 transceiver_data));
1108
1109 DP_VERBOSE(p_hwfn,
1110 (NETIF_MSG_HW | QED_MSG_SP),
1111 "Received transceiver state update [0x%08x] from mfw [Addr 0x%x]\n",
1112 transceiver_state,
1113 (u32)(p_hwfn->mcp_info->port_addr +
1114 offsetof(struct public_port, transceiver_data)));
1115
1116 transceiver_state = GET_FIELD(transceiver_state,
1117 ETH_TRANSCEIVER_STATE);
1118
1119 if (transceiver_state == ETH_TRANSCEIVER_STATE_PRESENT)
1120 DP_NOTICE(p_hwfn, "Transceiver is present.\n");
1121 else
1122 DP_NOTICE(p_hwfn, "Transceiver is unplugged.\n");
1123}
1124
1125static void qed_mcp_read_eee_config(struct qed_hwfn *p_hwfn,
1126 struct qed_ptt *p_ptt,
1127 struct qed_mcp_link_state *p_link)
1128{
1129 u32 eee_status, val;
1130
1131 p_link->eee_adv_caps = 0;
1132 p_link->eee_lp_adv_caps = 0;
1133 eee_status = qed_rd(p_hwfn,
1134 p_ptt,
1135 p_hwfn->mcp_info->port_addr +
1136 offsetof(struct public_port, eee_status));
1137 p_link->eee_active = !!(eee_status & EEE_ACTIVE_BIT);
1138 val = (eee_status & EEE_LD_ADV_STATUS_MASK) >> EEE_LD_ADV_STATUS_OFFSET;
1139 if (val & EEE_1G_ADV)
1140 p_link->eee_adv_caps |= QED_EEE_1G_ADV;
1141 if (val & EEE_10G_ADV)
1142 p_link->eee_adv_caps |= QED_EEE_10G_ADV;
1143 val = (eee_status & EEE_LP_ADV_STATUS_MASK) >> EEE_LP_ADV_STATUS_OFFSET;
1144 if (val & EEE_1G_ADV)
1145 p_link->eee_lp_adv_caps |= QED_EEE_1G_ADV;
1146 if (val & EEE_10G_ADV)
1147 p_link->eee_lp_adv_caps |= QED_EEE_10G_ADV;
1148}
1149
1150static void qed_mcp_handle_link_change(struct qed_hwfn *p_hwfn,
1151 struct qed_ptt *p_ptt, bool b_reset)
1152{
1153 struct qed_mcp_link_state *p_link;
1154 u8 max_bw, min_bw;
1155 u32 status = 0;
1156
1157
1158 spin_lock_bh(&p_hwfn->mcp_info->link_lock);
1159
1160 p_link = &p_hwfn->mcp_info->link_output;
1161 memset(p_link, 0, sizeof(*p_link));
1162 if (!b_reset) {
1163 status = qed_rd(p_hwfn, p_ptt,
1164 p_hwfn->mcp_info->port_addr +
1165 offsetof(struct public_port, link_status));
1166 DP_VERBOSE(p_hwfn, (NETIF_MSG_LINK | QED_MSG_SP),
1167 "Received link update [0x%08x] from mfw [Addr 0x%x]\n",
1168 status,
1169 (u32)(p_hwfn->mcp_info->port_addr +
1170 offsetof(struct public_port, link_status)));
1171 } else {
1172 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1173 "Resetting link indications\n");
1174 goto out;
1175 }
1176
1177 if (p_hwfn->b_drv_link_init)
1178 p_link->link_up = !!(status & LINK_STATUS_LINK_UP);
1179 else
1180 p_link->link_up = false;
1181
1182 p_link->full_duplex = true;
1183 switch ((status & LINK_STATUS_SPEED_AND_DUPLEX_MASK)) {
1184 case LINK_STATUS_SPEED_AND_DUPLEX_100G:
1185 p_link->speed = 100000;
1186 break;
1187 case LINK_STATUS_SPEED_AND_DUPLEX_50G:
1188 p_link->speed = 50000;
1189 break;
1190 case LINK_STATUS_SPEED_AND_DUPLEX_40G:
1191 p_link->speed = 40000;
1192 break;
1193 case LINK_STATUS_SPEED_AND_DUPLEX_25G:
1194 p_link->speed = 25000;
1195 break;
1196 case LINK_STATUS_SPEED_AND_DUPLEX_20G:
1197 p_link->speed = 20000;
1198 break;
1199 case LINK_STATUS_SPEED_AND_DUPLEX_10G:
1200 p_link->speed = 10000;
1201 break;
1202 case LINK_STATUS_SPEED_AND_DUPLEX_1000THD:
1203 p_link->full_duplex = false;
1204
1205 case LINK_STATUS_SPEED_AND_DUPLEX_1000TFD:
1206 p_link->speed = 1000;
1207 break;
1208 default:
1209 p_link->speed = 0;
1210 }
1211
1212 if (p_link->link_up && p_link->speed)
1213 p_link->line_speed = p_link->speed;
1214 else
1215 p_link->line_speed = 0;
1216
1217 max_bw = p_hwfn->mcp_info->func_info.bandwidth_max;
1218 min_bw = p_hwfn->mcp_info->func_info.bandwidth_min;
1219
1220
1221 __qed_configure_pf_max_bandwidth(p_hwfn, p_ptt, p_link, max_bw);
1222
1223
1224 __qed_configure_pf_min_bandwidth(p_hwfn, p_ptt, p_link, min_bw);
1225 qed_configure_vp_wfq_on_link_change(p_hwfn->cdev, p_ptt,
1226 p_link->min_pf_rate);
1227
1228 p_link->an = !!(status & LINK_STATUS_AUTO_NEGOTIATE_ENABLED);
1229 p_link->an_complete = !!(status &
1230 LINK_STATUS_AUTO_NEGOTIATE_COMPLETE);
1231 p_link->parallel_detection = !!(status &
1232 LINK_STATUS_PARALLEL_DETECTION_USED);
1233 p_link->pfc_enabled = !!(status & LINK_STATUS_PFC_ENABLED);
1234
1235 p_link->partner_adv_speed |=
1236 (status & LINK_STATUS_LINK_PARTNER_1000TFD_CAPABLE) ?
1237 QED_LINK_PARTNER_SPEED_1G_FD : 0;
1238 p_link->partner_adv_speed |=
1239 (status & LINK_STATUS_LINK_PARTNER_1000THD_CAPABLE) ?
1240 QED_LINK_PARTNER_SPEED_1G_HD : 0;
1241 p_link->partner_adv_speed |=
1242 (status & LINK_STATUS_LINK_PARTNER_10G_CAPABLE) ?
1243 QED_LINK_PARTNER_SPEED_10G : 0;
1244 p_link->partner_adv_speed |=
1245 (status & LINK_STATUS_LINK_PARTNER_20G_CAPABLE) ?
1246 QED_LINK_PARTNER_SPEED_20G : 0;
1247 p_link->partner_adv_speed |=
1248 (status & LINK_STATUS_LINK_PARTNER_25G_CAPABLE) ?
1249 QED_LINK_PARTNER_SPEED_25G : 0;
1250 p_link->partner_adv_speed |=
1251 (status & LINK_STATUS_LINK_PARTNER_40G_CAPABLE) ?
1252 QED_LINK_PARTNER_SPEED_40G : 0;
1253 p_link->partner_adv_speed |=
1254 (status & LINK_STATUS_LINK_PARTNER_50G_CAPABLE) ?
1255 QED_LINK_PARTNER_SPEED_50G : 0;
1256 p_link->partner_adv_speed |=
1257 (status & LINK_STATUS_LINK_PARTNER_100G_CAPABLE) ?
1258 QED_LINK_PARTNER_SPEED_100G : 0;
1259
1260 p_link->partner_tx_flow_ctrl_en =
1261 !!(status & LINK_STATUS_TX_FLOW_CONTROL_ENABLED);
1262 p_link->partner_rx_flow_ctrl_en =
1263 !!(status & LINK_STATUS_RX_FLOW_CONTROL_ENABLED);
1264
1265 switch (status & LINK_STATUS_LINK_PARTNER_FLOW_CONTROL_MASK) {
1266 case LINK_STATUS_LINK_PARTNER_SYMMETRIC_PAUSE:
1267 p_link->partner_adv_pause = QED_LINK_PARTNER_SYMMETRIC_PAUSE;
1268 break;
1269 case LINK_STATUS_LINK_PARTNER_ASYMMETRIC_PAUSE:
1270 p_link->partner_adv_pause = QED_LINK_PARTNER_ASYMMETRIC_PAUSE;
1271 break;
1272 case LINK_STATUS_LINK_PARTNER_BOTH_PAUSE:
1273 p_link->partner_adv_pause = QED_LINK_PARTNER_BOTH_PAUSE;
1274 break;
1275 default:
1276 p_link->partner_adv_pause = 0;
1277 }
1278
1279 p_link->sfp_tx_fault = !!(status & LINK_STATUS_SFP_TX_FAULT);
1280
1281 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE)
1282 qed_mcp_read_eee_config(p_hwfn, p_ptt, p_link);
1283
1284 qed_link_update(p_hwfn);
1285out:
1286 spin_unlock_bh(&p_hwfn->mcp_info->link_lock);
1287}
1288
1289int qed_mcp_set_link(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt, bool b_up)
1290{
1291 struct qed_mcp_link_params *params = &p_hwfn->mcp_info->link_input;
1292 struct qed_mcp_mb_params mb_params;
1293 struct eth_phy_cfg phy_cfg;
1294 int rc = 0;
1295 u32 cmd;
1296
1297
1298 memset(&phy_cfg, 0, sizeof(phy_cfg));
1299 cmd = b_up ? DRV_MSG_CODE_INIT_PHY : DRV_MSG_CODE_LINK_RESET;
1300 if (!params->speed.autoneg)
1301 phy_cfg.speed = params->speed.forced_speed;
1302 phy_cfg.pause |= (params->pause.autoneg) ? ETH_PAUSE_AUTONEG : 0;
1303 phy_cfg.pause |= (params->pause.forced_rx) ? ETH_PAUSE_RX : 0;
1304 phy_cfg.pause |= (params->pause.forced_tx) ? ETH_PAUSE_TX : 0;
1305 phy_cfg.adv_speed = params->speed.advertised_speeds;
1306 phy_cfg.loopback_mode = params->loopback_mode;
1307 if (p_hwfn->mcp_info->capabilities & FW_MB_PARAM_FEATURE_SUPPORT_EEE) {
1308 if (params->eee.enable)
1309 phy_cfg.eee_cfg |= EEE_CFG_EEE_ENABLED;
1310 if (params->eee.tx_lpi_enable)
1311 phy_cfg.eee_cfg |= EEE_CFG_TX_LPI;
1312 if (params->eee.adv_caps & QED_EEE_1G_ADV)
1313 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_1G;
1314 if (params->eee.adv_caps & QED_EEE_10G_ADV)
1315 phy_cfg.eee_cfg |= EEE_CFG_ADV_SPEED_10G;
1316 phy_cfg.eee_cfg |= (params->eee.tx_lpi_timer <<
1317 EEE_TX_TIMER_USEC_OFFSET) &
1318 EEE_TX_TIMER_USEC_MASK;
1319 }
1320
1321 p_hwfn->b_drv_link_init = b_up;
1322
1323 if (b_up) {
1324 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1325 "Configuring Link: Speed 0x%08x, Pause 0x%08x, adv_speed 0x%08x, loopback 0x%08x, features 0x%08x\n",
1326 phy_cfg.speed,
1327 phy_cfg.pause,
1328 phy_cfg.adv_speed,
1329 phy_cfg.loopback_mode,
1330 phy_cfg.feature_config_flags);
1331 } else {
1332 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1333 "Resetting link\n");
1334 }
1335
1336 memset(&mb_params, 0, sizeof(mb_params));
1337 mb_params.cmd = cmd;
1338 mb_params.p_data_src = &phy_cfg;
1339 mb_params.data_src_size = sizeof(phy_cfg);
1340 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1341
1342
1343 if (rc) {
1344 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1345 return rc;
1346 }
1347
1348
1349
1350
1351
1352
1353
1354 qed_mcp_handle_link_change(p_hwfn, p_ptt, !b_up);
1355
1356 return 0;
1357}
1358
1359static void qed_mcp_send_protocol_stats(struct qed_hwfn *p_hwfn,
1360 struct qed_ptt *p_ptt,
1361 enum MFW_DRV_MSG_TYPE type)
1362{
1363 enum qed_mcp_protocol_type stats_type;
1364 union qed_mcp_protocol_stats stats;
1365 struct qed_mcp_mb_params mb_params;
1366 u32 hsi_param;
1367
1368 switch (type) {
1369 case MFW_DRV_MSG_GET_LAN_STATS:
1370 stats_type = QED_MCP_LAN_STATS;
1371 hsi_param = DRV_MSG_CODE_STATS_TYPE_LAN;
1372 break;
1373 case MFW_DRV_MSG_GET_FCOE_STATS:
1374 stats_type = QED_MCP_FCOE_STATS;
1375 hsi_param = DRV_MSG_CODE_STATS_TYPE_FCOE;
1376 break;
1377 case MFW_DRV_MSG_GET_ISCSI_STATS:
1378 stats_type = QED_MCP_ISCSI_STATS;
1379 hsi_param = DRV_MSG_CODE_STATS_TYPE_ISCSI;
1380 break;
1381 case MFW_DRV_MSG_GET_RDMA_STATS:
1382 stats_type = QED_MCP_RDMA_STATS;
1383 hsi_param = DRV_MSG_CODE_STATS_TYPE_RDMA;
1384 break;
1385 default:
1386 DP_NOTICE(p_hwfn, "Invalid protocol type %d\n", type);
1387 return;
1388 }
1389
1390 qed_get_protocol_stats(p_hwfn->cdev, stats_type, &stats);
1391
1392 memset(&mb_params, 0, sizeof(mb_params));
1393 mb_params.cmd = DRV_MSG_CODE_GET_STATS;
1394 mb_params.param = hsi_param;
1395 mb_params.p_data_src = &stats;
1396 mb_params.data_src_size = sizeof(stats);
1397 qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1398}
1399
1400static void qed_read_pf_bandwidth(struct qed_hwfn *p_hwfn,
1401 struct public_func *p_shmem_info)
1402{
1403 struct qed_mcp_function_info *p_info;
1404
1405 p_info = &p_hwfn->mcp_info->func_info;
1406
1407 p_info->bandwidth_min = (p_shmem_info->config &
1408 FUNC_MF_CFG_MIN_BW_MASK) >>
1409 FUNC_MF_CFG_MIN_BW_SHIFT;
1410 if (p_info->bandwidth_min < 1 || p_info->bandwidth_min > 100) {
1411 DP_INFO(p_hwfn,
1412 "bandwidth minimum out of bounds [%02x]. Set to 1\n",
1413 p_info->bandwidth_min);
1414 p_info->bandwidth_min = 1;
1415 }
1416
1417 p_info->bandwidth_max = (p_shmem_info->config &
1418 FUNC_MF_CFG_MAX_BW_MASK) >>
1419 FUNC_MF_CFG_MAX_BW_SHIFT;
1420 if (p_info->bandwidth_max < 1 || p_info->bandwidth_max > 100) {
1421 DP_INFO(p_hwfn,
1422 "bandwidth maximum out of bounds [%02x]. Set to 100\n",
1423 p_info->bandwidth_max);
1424 p_info->bandwidth_max = 100;
1425 }
1426}
1427
1428static u32 qed_mcp_get_shmem_func(struct qed_hwfn *p_hwfn,
1429 struct qed_ptt *p_ptt,
1430 struct public_func *p_data, int pfid)
1431{
1432 u32 addr = SECTION_OFFSIZE_ADDR(p_hwfn->mcp_info->public_base,
1433 PUBLIC_FUNC);
1434 u32 mfw_path_offsize = qed_rd(p_hwfn, p_ptt, addr);
1435 u32 func_addr = SECTION_ADDR(mfw_path_offsize, pfid);
1436 u32 i, size;
1437
1438 memset(p_data, 0, sizeof(*p_data));
1439
1440 size = min_t(u32, sizeof(*p_data), QED_SECTION_SIZE(mfw_path_offsize));
1441 for (i = 0; i < size / sizeof(u32); i++)
1442 ((u32 *)p_data)[i] = qed_rd(p_hwfn, p_ptt,
1443 func_addr + (i << 2));
1444 return size;
1445}
1446
1447static void qed_mcp_update_bw(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1448{
1449 struct qed_mcp_function_info *p_info;
1450 struct public_func shmem_info;
1451 u32 resp = 0, param = 0;
1452
1453 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1454
1455 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1456
1457 p_info = &p_hwfn->mcp_info->func_info;
1458
1459 qed_configure_pf_min_bandwidth(p_hwfn->cdev, p_info->bandwidth_min);
1460 qed_configure_pf_max_bandwidth(p_hwfn->cdev, p_info->bandwidth_max);
1461
1462
1463 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BW_UPDATE_ACK, 0, &resp,
1464 ¶m);
1465}
1466
1467static void qed_mcp_update_stag(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1468{
1469 struct public_func shmem_info;
1470 u32 resp = 0, param = 0;
1471
1472 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1473
1474 p_hwfn->mcp_info->func_info.ovlan = (u16)shmem_info.ovlan_stag &
1475 FUNC_MF_CFG_OV_STAG_MASK;
1476 p_hwfn->hw_info.ovlan = p_hwfn->mcp_info->func_info.ovlan;
1477 if ((p_hwfn->hw_info.hw_mode & BIT(MODE_MF_SD)) &&
1478 (p_hwfn->hw_info.ovlan != QED_MCP_VLAN_UNSET)) {
1479 qed_wr(p_hwfn, p_ptt,
1480 NIG_REG_LLH_FUNC_TAG_VALUE, p_hwfn->hw_info.ovlan);
1481 qed_sp_pf_update_stag(p_hwfn);
1482 }
1483
1484
1485 qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_S_TAG_UPDATE_ACK, 0,
1486 &resp, ¶m);
1487}
1488
1489int qed_mcp_handle_events(struct qed_hwfn *p_hwfn,
1490 struct qed_ptt *p_ptt)
1491{
1492 struct qed_mcp_info *info = p_hwfn->mcp_info;
1493 int rc = 0;
1494 bool found = false;
1495 u16 i;
1496
1497 DP_VERBOSE(p_hwfn, QED_MSG_SP, "Received message from MFW\n");
1498
1499
1500 qed_mcp_read_mb(p_hwfn, p_ptt);
1501
1502
1503 for (i = 0; i < info->mfw_mb_length; i++) {
1504 if (info->mfw_mb_cur[i] == info->mfw_mb_shadow[i])
1505 continue;
1506
1507 found = true;
1508
1509 DP_VERBOSE(p_hwfn, NETIF_MSG_LINK,
1510 "Msg [%d] - old CMD 0x%02x, new CMD 0x%02x\n",
1511 i, info->mfw_mb_shadow[i], info->mfw_mb_cur[i]);
1512
1513 switch (i) {
1514 case MFW_DRV_MSG_LINK_CHANGE:
1515 qed_mcp_handle_link_change(p_hwfn, p_ptt, false);
1516 break;
1517 case MFW_DRV_MSG_VF_DISABLED:
1518 qed_mcp_handle_vf_flr(p_hwfn, p_ptt);
1519 break;
1520 case MFW_DRV_MSG_LLDP_DATA_UPDATED:
1521 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1522 QED_DCBX_REMOTE_LLDP_MIB);
1523 break;
1524 case MFW_DRV_MSG_DCBX_REMOTE_MIB_UPDATED:
1525 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1526 QED_DCBX_REMOTE_MIB);
1527 break;
1528 case MFW_DRV_MSG_DCBX_OPERATIONAL_MIB_UPDATED:
1529 qed_dcbx_mib_update_event(p_hwfn, p_ptt,
1530 QED_DCBX_OPERATIONAL_MIB);
1531 break;
1532 case MFW_DRV_MSG_TRANSCEIVER_STATE_CHANGE:
1533 qed_mcp_handle_transceiver_change(p_hwfn, p_ptt);
1534 break;
1535 case MFW_DRV_MSG_GET_LAN_STATS:
1536 case MFW_DRV_MSG_GET_FCOE_STATS:
1537 case MFW_DRV_MSG_GET_ISCSI_STATS:
1538 case MFW_DRV_MSG_GET_RDMA_STATS:
1539 qed_mcp_send_protocol_stats(p_hwfn, p_ptt, i);
1540 break;
1541 case MFW_DRV_MSG_BW_UPDATE:
1542 qed_mcp_update_bw(p_hwfn, p_ptt);
1543 break;
1544 case MFW_DRV_MSG_S_TAG_UPDATE:
1545 qed_mcp_update_stag(p_hwfn, p_ptt);
1546 break;
1547 break;
1548 default:
1549 DP_INFO(p_hwfn, "Unimplemented MFW message %d\n", i);
1550 rc = -EINVAL;
1551 }
1552 }
1553
1554
1555 for (i = 0; i < MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length); i++) {
1556 __be32 val = cpu_to_be32(((u32 *)info->mfw_mb_cur)[i]);
1557
1558
1559 qed_wr(p_hwfn, p_ptt,
1560 info->mfw_mb_addr + sizeof(u32) +
1561 MFW_DRV_MSG_MAX_DWORDS(info->mfw_mb_length) *
1562 sizeof(u32) + i * sizeof(u32),
1563 (__force u32)val);
1564 }
1565
1566 if (!found) {
1567 DP_NOTICE(p_hwfn,
1568 "Received an MFW message indication but no new message!\n");
1569 rc = -EINVAL;
1570 }
1571
1572
1573 memcpy(info->mfw_mb_shadow, info->mfw_mb_cur, info->mfw_mb_length);
1574
1575 return rc;
1576}
1577
1578int qed_mcp_get_mfw_ver(struct qed_hwfn *p_hwfn,
1579 struct qed_ptt *p_ptt,
1580 u32 *p_mfw_ver, u32 *p_running_bundle_id)
1581{
1582 u32 global_offsize;
1583
1584 if (IS_VF(p_hwfn->cdev)) {
1585 if (p_hwfn->vf_iov_info) {
1586 struct pfvf_acquire_resp_tlv *p_resp;
1587
1588 p_resp = &p_hwfn->vf_iov_info->acquire_resp;
1589 *p_mfw_ver = p_resp->pfdev_info.mfw_ver;
1590 return 0;
1591 } else {
1592 DP_VERBOSE(p_hwfn,
1593 QED_MSG_IOV,
1594 "VF requested MFW version prior to ACQUIRE\n");
1595 return -EINVAL;
1596 }
1597 }
1598
1599 global_offsize = qed_rd(p_hwfn, p_ptt,
1600 SECTION_OFFSIZE_ADDR(p_hwfn->
1601 mcp_info->public_base,
1602 PUBLIC_GLOBAL));
1603 *p_mfw_ver =
1604 qed_rd(p_hwfn, p_ptt,
1605 SECTION_ADDR(global_offsize,
1606 0) + offsetof(struct public_global, mfw_ver));
1607
1608 if (p_running_bundle_id != NULL) {
1609 *p_running_bundle_id = qed_rd(p_hwfn, p_ptt,
1610 SECTION_ADDR(global_offsize, 0) +
1611 offsetof(struct public_global,
1612 running_bundle_id));
1613 }
1614
1615 return 0;
1616}
1617
1618int qed_mcp_get_mbi_ver(struct qed_hwfn *p_hwfn,
1619 struct qed_ptt *p_ptt, u32 *p_mbi_ver)
1620{
1621 u32 nvm_cfg_addr, nvm_cfg1_offset, mbi_ver_addr;
1622
1623 if (IS_VF(p_hwfn->cdev))
1624 return -EINVAL;
1625
1626
1627 nvm_cfg_addr = qed_rd(p_hwfn, p_ptt, MISC_REG_GEN_PURP_CR0);
1628 if (!nvm_cfg_addr) {
1629 DP_NOTICE(p_hwfn, "Shared memory not initialized\n");
1630 return -EINVAL;
1631 }
1632
1633
1634 nvm_cfg1_offset = qed_rd(p_hwfn, p_ptt, nvm_cfg_addr + 4);
1635
1636 mbi_ver_addr = MCP_REG_SCRATCH + nvm_cfg1_offset +
1637 offsetof(struct nvm_cfg1, glob) +
1638 offsetof(struct nvm_cfg1_glob, mbi_version);
1639 *p_mbi_ver = qed_rd(p_hwfn, p_ptt,
1640 mbi_ver_addr) &
1641 (NVM_CFG1_GLOB_MBI_VERSION_0_MASK |
1642 NVM_CFG1_GLOB_MBI_VERSION_1_MASK |
1643 NVM_CFG1_GLOB_MBI_VERSION_2_MASK);
1644
1645 return 0;
1646}
1647
1648int qed_mcp_get_media_type(struct qed_dev *cdev, u32 *p_media_type)
1649{
1650 struct qed_hwfn *p_hwfn = &cdev->hwfns[0];
1651 struct qed_ptt *p_ptt;
1652
1653 if (IS_VF(cdev))
1654 return -EINVAL;
1655
1656 if (!qed_mcp_is_init(p_hwfn)) {
1657 DP_NOTICE(p_hwfn, "MFW is not initialized!\n");
1658 return -EBUSY;
1659 }
1660
1661 *p_media_type = MEDIA_UNSPECIFIED;
1662
1663 p_ptt = qed_ptt_acquire(p_hwfn);
1664 if (!p_ptt)
1665 return -EBUSY;
1666
1667 *p_media_type = qed_rd(p_hwfn, p_ptt, p_hwfn->mcp_info->port_addr +
1668 offsetof(struct public_port, media_type));
1669
1670 qed_ptt_release(p_hwfn, p_ptt);
1671
1672 return 0;
1673}
1674
1675
1676static void
1677qed_mcp_get_shmem_proto_legacy(struct qed_hwfn *p_hwfn,
1678 enum qed_pci_personality *p_proto)
1679{
1680
1681
1682
1683 if (test_bit(QED_DEV_CAP_ROCE, &p_hwfn->hw_info.device_capabilities))
1684 *p_proto = QED_PCI_ETH_ROCE;
1685 else
1686 *p_proto = QED_PCI_ETH;
1687
1688 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1689 "According to Legacy capabilities, L2 personality is %08x\n",
1690 (u32) *p_proto);
1691}
1692
1693static int
1694qed_mcp_get_shmem_proto_mfw(struct qed_hwfn *p_hwfn,
1695 struct qed_ptt *p_ptt,
1696 enum qed_pci_personality *p_proto)
1697{
1698 u32 resp = 0, param = 0;
1699 int rc;
1700
1701 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1702 DRV_MSG_CODE_GET_PF_RDMA_PROTOCOL, 0, &resp, ¶m);
1703 if (rc)
1704 return rc;
1705 if (resp != FW_MSG_CODE_OK) {
1706 DP_VERBOSE(p_hwfn, NETIF_MSG_IFUP,
1707 "MFW lacks support for command; Returns %08x\n",
1708 resp);
1709 return -EINVAL;
1710 }
1711
1712 switch (param) {
1713 case FW_MB_PARAM_GET_PF_RDMA_NONE:
1714 *p_proto = QED_PCI_ETH;
1715 break;
1716 case FW_MB_PARAM_GET_PF_RDMA_ROCE:
1717 *p_proto = QED_PCI_ETH_ROCE;
1718 break;
1719 case FW_MB_PARAM_GET_PF_RDMA_IWARP:
1720 *p_proto = QED_PCI_ETH_IWARP;
1721 break;
1722 case FW_MB_PARAM_GET_PF_RDMA_BOTH:
1723 *p_proto = QED_PCI_ETH_RDMA;
1724 break;
1725 default:
1726 DP_NOTICE(p_hwfn,
1727 "MFW answers GET_PF_RDMA_PROTOCOL but param is %08x\n",
1728 param);
1729 return -EINVAL;
1730 }
1731
1732 DP_VERBOSE(p_hwfn,
1733 NETIF_MSG_IFUP,
1734 "According to capabilities, L2 personality is %08x [resp %08x param %08x]\n",
1735 (u32) *p_proto, resp, param);
1736 return 0;
1737}
1738
1739static int
1740qed_mcp_get_shmem_proto(struct qed_hwfn *p_hwfn,
1741 struct public_func *p_info,
1742 struct qed_ptt *p_ptt,
1743 enum qed_pci_personality *p_proto)
1744{
1745 int rc = 0;
1746
1747 switch (p_info->config & FUNC_MF_CFG_PROTOCOL_MASK) {
1748 case FUNC_MF_CFG_PROTOCOL_ETHERNET:
1749 if (!IS_ENABLED(CONFIG_QED_RDMA))
1750 *p_proto = QED_PCI_ETH;
1751 else if (qed_mcp_get_shmem_proto_mfw(p_hwfn, p_ptt, p_proto))
1752 qed_mcp_get_shmem_proto_legacy(p_hwfn, p_proto);
1753 break;
1754 case FUNC_MF_CFG_PROTOCOL_ISCSI:
1755 *p_proto = QED_PCI_ISCSI;
1756 break;
1757 case FUNC_MF_CFG_PROTOCOL_FCOE:
1758 *p_proto = QED_PCI_FCOE;
1759 break;
1760 case FUNC_MF_CFG_PROTOCOL_ROCE:
1761 DP_NOTICE(p_hwfn, "RoCE personality is not a valid value!\n");
1762
1763 default:
1764 rc = -EINVAL;
1765 }
1766
1767 return rc;
1768}
1769
1770int qed_mcp_fill_shmem_func_info(struct qed_hwfn *p_hwfn,
1771 struct qed_ptt *p_ptt)
1772{
1773 struct qed_mcp_function_info *info;
1774 struct public_func shmem_info;
1775
1776 qed_mcp_get_shmem_func(p_hwfn, p_ptt, &shmem_info, MCP_PF_ID(p_hwfn));
1777 info = &p_hwfn->mcp_info->func_info;
1778
1779 info->pause_on_host = (shmem_info.config &
1780 FUNC_MF_CFG_PAUSE_ON_HOST_RING) ? 1 : 0;
1781
1782 if (qed_mcp_get_shmem_proto(p_hwfn, &shmem_info, p_ptt,
1783 &info->protocol)) {
1784 DP_ERR(p_hwfn, "Unknown personality %08x\n",
1785 (u32)(shmem_info.config & FUNC_MF_CFG_PROTOCOL_MASK));
1786 return -EINVAL;
1787 }
1788
1789 qed_read_pf_bandwidth(p_hwfn, &shmem_info);
1790
1791 if (shmem_info.mac_upper || shmem_info.mac_lower) {
1792 info->mac[0] = (u8)(shmem_info.mac_upper >> 8);
1793 info->mac[1] = (u8)(shmem_info.mac_upper);
1794 info->mac[2] = (u8)(shmem_info.mac_lower >> 24);
1795 info->mac[3] = (u8)(shmem_info.mac_lower >> 16);
1796 info->mac[4] = (u8)(shmem_info.mac_lower >> 8);
1797 info->mac[5] = (u8)(shmem_info.mac_lower);
1798
1799
1800 memcpy(&p_hwfn->cdev->wol_mac, info->mac, ETH_ALEN);
1801 } else {
1802 DP_NOTICE(p_hwfn, "MAC is 0 in shmem\n");
1803 }
1804
1805 info->wwn_port = (u64)shmem_info.fcoe_wwn_port_name_lower |
1806 (((u64)shmem_info.fcoe_wwn_port_name_upper) << 32);
1807 info->wwn_node = (u64)shmem_info.fcoe_wwn_node_name_lower |
1808 (((u64)shmem_info.fcoe_wwn_node_name_upper) << 32);
1809
1810 info->ovlan = (u16)(shmem_info.ovlan_stag & FUNC_MF_CFG_OV_STAG_MASK);
1811
1812 info->mtu = (u16)shmem_info.mtu_size;
1813
1814 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_NONE;
1815 p_hwfn->cdev->wol_config = (u8)QED_OV_WOL_DEFAULT;
1816 if (qed_mcp_is_init(p_hwfn)) {
1817 u32 resp = 0, param = 0;
1818 int rc;
1819
1820 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1821 DRV_MSG_CODE_OS_WOL, 0, &resp, ¶m);
1822 if (rc)
1823 return rc;
1824 if (resp == FW_MSG_CODE_OS_WOL_SUPPORTED)
1825 p_hwfn->hw_info.b_wol_support = QED_WOL_SUPPORT_PME;
1826 }
1827
1828 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_IFUP),
1829 "Read configuration from shmem: pause_on_host %02x protocol %02x BW [%02x - %02x] MAC %02x:%02x:%02x:%02x:%02x:%02x wwn port %llx node %llx ovlan %04x wol %02x\n",
1830 info->pause_on_host, info->protocol,
1831 info->bandwidth_min, info->bandwidth_max,
1832 info->mac[0], info->mac[1], info->mac[2],
1833 info->mac[3], info->mac[4], info->mac[5],
1834 info->wwn_port, info->wwn_node,
1835 info->ovlan, (u8)p_hwfn->hw_info.b_wol_support);
1836
1837 return 0;
1838}
1839
1840struct qed_mcp_link_params
1841*qed_mcp_get_link_params(struct qed_hwfn *p_hwfn)
1842{
1843 if (!p_hwfn || !p_hwfn->mcp_info)
1844 return NULL;
1845 return &p_hwfn->mcp_info->link_input;
1846}
1847
1848struct qed_mcp_link_state
1849*qed_mcp_get_link_state(struct qed_hwfn *p_hwfn)
1850{
1851 if (!p_hwfn || !p_hwfn->mcp_info)
1852 return NULL;
1853 return &p_hwfn->mcp_info->link_output;
1854}
1855
1856struct qed_mcp_link_capabilities
1857*qed_mcp_get_link_capabilities(struct qed_hwfn *p_hwfn)
1858{
1859 if (!p_hwfn || !p_hwfn->mcp_info)
1860 return NULL;
1861 return &p_hwfn->mcp_info->link_capabilities;
1862}
1863
1864int qed_mcp_drain(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1865{
1866 u32 resp = 0, param = 0;
1867 int rc;
1868
1869 rc = qed_mcp_cmd(p_hwfn, p_ptt,
1870 DRV_MSG_CODE_NIG_DRAIN, 1000, &resp, ¶m);
1871
1872
1873 msleep(1020);
1874
1875 return rc;
1876}
1877
1878int qed_mcp_get_flash_size(struct qed_hwfn *p_hwfn,
1879 struct qed_ptt *p_ptt, u32 *p_flash_size)
1880{
1881 u32 flash_size;
1882
1883 if (IS_VF(p_hwfn->cdev))
1884 return -EINVAL;
1885
1886 flash_size = qed_rd(p_hwfn, p_ptt, MCP_REG_NVM_CFG4);
1887 flash_size = (flash_size & MCP_REG_NVM_CFG4_FLASH_SIZE) >>
1888 MCP_REG_NVM_CFG4_FLASH_SIZE_SHIFT;
1889 flash_size = (1 << (flash_size + MCP_BYTES_PER_MBIT_SHIFT));
1890
1891 *p_flash_size = flash_size;
1892
1893 return 0;
1894}
1895
1896static int
1897qed_mcp_config_vf_msix_bb(struct qed_hwfn *p_hwfn,
1898 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1899{
1900 u32 resp = 0, param = 0, rc_param = 0;
1901 int rc;
1902
1903
1904 if (!IS_LEAD_HWFN(p_hwfn))
1905 return 0;
1906 num *= p_hwfn->cdev->num_hwfns;
1907
1908 param |= (vf_id << DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_SHIFT) &
1909 DRV_MB_PARAM_CFG_VF_MSIX_VF_ID_MASK;
1910 param |= (num << DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_SHIFT) &
1911 DRV_MB_PARAM_CFG_VF_MSIX_SB_NUM_MASK;
1912
1913 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_VF_MSIX, param,
1914 &resp, &rc_param);
1915
1916 if (resp != FW_MSG_CODE_DRV_CFG_VF_MSIX_DONE) {
1917 DP_NOTICE(p_hwfn, "VF[%d]: MFW failed to set MSI-X\n", vf_id);
1918 rc = -EINVAL;
1919 } else {
1920 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1921 "Requested 0x%02x MSI-x interrupts from VF 0x%02x\n",
1922 num, vf_id);
1923 }
1924
1925 return rc;
1926}
1927
1928static int
1929qed_mcp_config_vf_msix_ah(struct qed_hwfn *p_hwfn,
1930 struct qed_ptt *p_ptt, u8 num)
1931{
1932 u32 resp = 0, param = num, rc_param = 0;
1933 int rc;
1934
1935 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_CFG_PF_VFS_MSIX,
1936 param, &resp, &rc_param);
1937
1938 if (resp != FW_MSG_CODE_DRV_CFG_PF_VFS_MSIX_DONE) {
1939 DP_NOTICE(p_hwfn, "MFW failed to set MSI-X for VFs\n");
1940 rc = -EINVAL;
1941 } else {
1942 DP_VERBOSE(p_hwfn, QED_MSG_IOV,
1943 "Requested 0x%02x MSI-x interrupts for VFs\n", num);
1944 }
1945
1946 return rc;
1947}
1948
1949int qed_mcp_config_vf_msix(struct qed_hwfn *p_hwfn,
1950 struct qed_ptt *p_ptt, u8 vf_id, u8 num)
1951{
1952 if (QED_IS_BB(p_hwfn->cdev))
1953 return qed_mcp_config_vf_msix_bb(p_hwfn, p_ptt, vf_id, num);
1954 else
1955 return qed_mcp_config_vf_msix_ah(p_hwfn, p_ptt, num);
1956}
1957
1958int
1959qed_mcp_send_drv_version(struct qed_hwfn *p_hwfn,
1960 struct qed_ptt *p_ptt,
1961 struct qed_mcp_drv_version *p_ver)
1962{
1963 struct qed_mcp_mb_params mb_params;
1964 struct drv_version_stc drv_version;
1965 __be32 val;
1966 u32 i;
1967 int rc;
1968
1969 memset(&drv_version, 0, sizeof(drv_version));
1970 drv_version.version = p_ver->version;
1971 for (i = 0; i < (MCP_DRV_VER_STR_SIZE - 4) / sizeof(u32); i++) {
1972 val = cpu_to_be32(*((u32 *)&p_ver->name[i * sizeof(u32)]));
1973 *(__be32 *)&drv_version.name[i * sizeof(u32)] = val;
1974 }
1975
1976 memset(&mb_params, 0, sizeof(mb_params));
1977 mb_params.cmd = DRV_MSG_CODE_SET_VERSION;
1978 mb_params.p_data_src = &drv_version;
1979 mb_params.data_src_size = sizeof(drv_version);
1980 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
1981 if (rc)
1982 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1983
1984 return rc;
1985}
1986
1987int qed_mcp_halt(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
1988{
1989 u32 resp = 0, param = 0;
1990 int rc;
1991
1992 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MCP_HALT, 0, &resp,
1993 ¶m);
1994 if (rc)
1995 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
1996
1997 return rc;
1998}
1999
2000int qed_mcp_resume(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2001{
2002 u32 value, cpu_mode;
2003
2004 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_STATE, 0xffffffff);
2005
2006 value = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2007 value &= ~MCP_REG_CPU_MODE_SOFT_HALT;
2008 qed_wr(p_hwfn, p_ptt, MCP_REG_CPU_MODE, value);
2009 cpu_mode = qed_rd(p_hwfn, p_ptt, MCP_REG_CPU_MODE);
2010
2011 return (cpu_mode & MCP_REG_CPU_MODE_SOFT_HALT) ? -EAGAIN : 0;
2012}
2013
2014int qed_mcp_ov_update_current_config(struct qed_hwfn *p_hwfn,
2015 struct qed_ptt *p_ptt,
2016 enum qed_ov_client client)
2017{
2018 u32 resp = 0, param = 0;
2019 u32 drv_mb_param;
2020 int rc;
2021
2022 switch (client) {
2023 case QED_OV_CLIENT_DRV:
2024 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OS;
2025 break;
2026 case QED_OV_CLIENT_USER:
2027 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_OTHER;
2028 break;
2029 case QED_OV_CLIENT_VENDOR_SPEC:
2030 drv_mb_param = DRV_MB_PARAM_OV_CURR_CFG_VENDOR_SPEC;
2031 break;
2032 default:
2033 DP_NOTICE(p_hwfn, "Invalid client type %d\n", client);
2034 return -EINVAL;
2035 }
2036
2037 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_CURR_CFG,
2038 drv_mb_param, &resp, ¶m);
2039 if (rc)
2040 DP_ERR(p_hwfn, "MCP response failure, aborting\n");
2041
2042 return rc;
2043}
2044
2045int qed_mcp_ov_update_driver_state(struct qed_hwfn *p_hwfn,
2046 struct qed_ptt *p_ptt,
2047 enum qed_ov_driver_state drv_state)
2048{
2049 u32 resp = 0, param = 0;
2050 u32 drv_mb_param;
2051 int rc;
2052
2053 switch (drv_state) {
2054 case QED_OV_DRIVER_STATE_NOT_LOADED:
2055 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_NOT_LOADED;
2056 break;
2057 case QED_OV_DRIVER_STATE_DISABLED:
2058 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_DISABLED;
2059 break;
2060 case QED_OV_DRIVER_STATE_ACTIVE:
2061 drv_mb_param = DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE_ACTIVE;
2062 break;
2063 default:
2064 DP_NOTICE(p_hwfn, "Invalid driver state %d\n", drv_state);
2065 return -EINVAL;
2066 }
2067
2068 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_DRIVER_STATE,
2069 drv_mb_param, &resp, ¶m);
2070 if (rc)
2071 DP_ERR(p_hwfn, "Failed to send driver state\n");
2072
2073 return rc;
2074}
2075
2076int qed_mcp_ov_update_mtu(struct qed_hwfn *p_hwfn,
2077 struct qed_ptt *p_ptt, u16 mtu)
2078{
2079 u32 resp = 0, param = 0;
2080 u32 drv_mb_param;
2081 int rc;
2082
2083 drv_mb_param = (u32)mtu << DRV_MB_PARAM_OV_MTU_SIZE_SHIFT;
2084 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_MTU,
2085 drv_mb_param, &resp, ¶m);
2086 if (rc)
2087 DP_ERR(p_hwfn, "Failed to send mtu value, rc = %d\n", rc);
2088
2089 return rc;
2090}
2091
2092int qed_mcp_ov_update_mac(struct qed_hwfn *p_hwfn,
2093 struct qed_ptt *p_ptt, u8 *mac)
2094{
2095 struct qed_mcp_mb_params mb_params;
2096 u32 mfw_mac[2];
2097 int rc;
2098
2099 memset(&mb_params, 0, sizeof(mb_params));
2100 mb_params.cmd = DRV_MSG_CODE_SET_VMAC;
2101 mb_params.param = DRV_MSG_CODE_VMAC_TYPE_MAC <<
2102 DRV_MSG_CODE_VMAC_TYPE_SHIFT;
2103 mb_params.param |= MCP_PF_ID(p_hwfn);
2104
2105
2106
2107
2108
2109
2110 mfw_mac[0] = mac[0] << 24 | mac[1] << 16 | mac[2] << 8 | mac[3];
2111 mfw_mac[1] = mac[4] << 24 | mac[5] << 16;
2112
2113 mb_params.p_data_src = (u8 *)mfw_mac;
2114 mb_params.data_src_size = 8;
2115 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2116 if (rc)
2117 DP_ERR(p_hwfn, "Failed to send mac address, rc = %d\n", rc);
2118
2119
2120 memcpy(p_hwfn->cdev->wol_mac, mac, ETH_ALEN);
2121
2122 return rc;
2123}
2124
2125int qed_mcp_ov_update_wol(struct qed_hwfn *p_hwfn,
2126 struct qed_ptt *p_ptt, enum qed_ov_wol wol)
2127{
2128 u32 resp = 0, param = 0;
2129 u32 drv_mb_param;
2130 int rc;
2131
2132 if (p_hwfn->hw_info.b_wol_support == QED_WOL_SUPPORT_NONE) {
2133 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2134 "Can't change WoL configuration when WoL isn't supported\n");
2135 return -EINVAL;
2136 }
2137
2138 switch (wol) {
2139 case QED_OV_WOL_DEFAULT:
2140 drv_mb_param = DRV_MB_PARAM_WOL_DEFAULT;
2141 break;
2142 case QED_OV_WOL_DISABLED:
2143 drv_mb_param = DRV_MB_PARAM_WOL_DISABLED;
2144 break;
2145 case QED_OV_WOL_ENABLED:
2146 drv_mb_param = DRV_MB_PARAM_WOL_ENABLED;
2147 break;
2148 default:
2149 DP_ERR(p_hwfn, "Invalid wol state %d\n", wol);
2150 return -EINVAL;
2151 }
2152
2153 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_WOL,
2154 drv_mb_param, &resp, ¶m);
2155 if (rc)
2156 DP_ERR(p_hwfn, "Failed to send wol mode, rc = %d\n", rc);
2157
2158
2159 p_hwfn->cdev->wol_config = (u8)wol;
2160
2161 return rc;
2162}
2163
2164int qed_mcp_ov_update_eswitch(struct qed_hwfn *p_hwfn,
2165 struct qed_ptt *p_ptt,
2166 enum qed_ov_eswitch eswitch)
2167{
2168 u32 resp = 0, param = 0;
2169 u32 drv_mb_param;
2170 int rc;
2171
2172 switch (eswitch) {
2173 case QED_OV_ESWITCH_NONE:
2174 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_NONE;
2175 break;
2176 case QED_OV_ESWITCH_VEB:
2177 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEB;
2178 break;
2179 case QED_OV_ESWITCH_VEPA:
2180 drv_mb_param = DRV_MB_PARAM_ESWITCH_MODE_VEPA;
2181 break;
2182 default:
2183 DP_ERR(p_hwfn, "Invalid eswitch mode %d\n", eswitch);
2184 return -EINVAL;
2185 }
2186
2187 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_OV_UPDATE_ESWITCH_MODE,
2188 drv_mb_param, &resp, ¶m);
2189 if (rc)
2190 DP_ERR(p_hwfn, "Failed to send eswitch mode, rc = %d\n", rc);
2191
2192 return rc;
2193}
2194
2195int qed_mcp_set_led(struct qed_hwfn *p_hwfn,
2196 struct qed_ptt *p_ptt, enum qed_led_mode mode)
2197{
2198 u32 resp = 0, param = 0, drv_mb_param;
2199 int rc;
2200
2201 switch (mode) {
2202 case QED_LED_MODE_ON:
2203 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_ON;
2204 break;
2205 case QED_LED_MODE_OFF:
2206 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OFF;
2207 break;
2208 case QED_LED_MODE_RESTORE:
2209 drv_mb_param = DRV_MB_PARAM_SET_LED_MODE_OPER;
2210 break;
2211 default:
2212 DP_NOTICE(p_hwfn, "Invalid LED mode %d\n", mode);
2213 return -EINVAL;
2214 }
2215
2216 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_SET_LED_MODE,
2217 drv_mb_param, &resp, ¶m);
2218
2219 return rc;
2220}
2221
2222int qed_mcp_mask_parities(struct qed_hwfn *p_hwfn,
2223 struct qed_ptt *p_ptt, u32 mask_parities)
2224{
2225 u32 resp = 0, param = 0;
2226 int rc;
2227
2228 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_MASK_PARITIES,
2229 mask_parities, &resp, ¶m);
2230
2231 if (rc) {
2232 DP_ERR(p_hwfn,
2233 "MCP response failure for mask parities, aborting\n");
2234 } else if (resp != FW_MSG_CODE_OK) {
2235 DP_ERR(p_hwfn,
2236 "MCP did not acknowledge mask parity request. Old MFW?\n");
2237 rc = -EINVAL;
2238 }
2239
2240 return rc;
2241}
2242
2243int qed_mcp_nvm_read(struct qed_dev *cdev, u32 addr, u8 *p_buf, u32 len)
2244{
2245 u32 bytes_left = len, offset = 0, bytes_to_copy, read_len = 0;
2246 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2247 u32 resp = 0, resp_param = 0;
2248 struct qed_ptt *p_ptt;
2249 int rc = 0;
2250
2251 p_ptt = qed_ptt_acquire(p_hwfn);
2252 if (!p_ptt)
2253 return -EBUSY;
2254
2255 while (bytes_left > 0) {
2256 bytes_to_copy = min_t(u32, bytes_left, MCP_DRV_NVM_BUF_LEN);
2257
2258 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2259 DRV_MSG_CODE_NVM_READ_NVRAM,
2260 addr + offset +
2261 (bytes_to_copy <<
2262 DRV_MB_PARAM_NVM_LEN_OFFSET),
2263 &resp, &resp_param,
2264 &read_len,
2265 (u32 *)(p_buf + offset));
2266
2267 if (rc || (resp != FW_MSG_CODE_NVM_OK)) {
2268 DP_NOTICE(cdev, "MCP command rc = %d\n", rc);
2269 break;
2270 }
2271
2272
2273
2274
2275 if (bytes_left % 0x1000 <
2276 (bytes_left - read_len) % 0x1000)
2277 usleep_range(1000, 2000);
2278
2279 offset += read_len;
2280 bytes_left -= read_len;
2281 }
2282
2283 cdev->mcp_nvm_resp = resp;
2284 qed_ptt_release(p_hwfn, p_ptt);
2285
2286 return rc;
2287}
2288
2289int qed_mcp_nvm_resp(struct qed_dev *cdev, u8 *p_buf)
2290{
2291 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2292 struct qed_ptt *p_ptt;
2293
2294 p_ptt = qed_ptt_acquire(p_hwfn);
2295 if (!p_ptt)
2296 return -EBUSY;
2297
2298 memcpy(p_buf, &cdev->mcp_nvm_resp, sizeof(cdev->mcp_nvm_resp));
2299 qed_ptt_release(p_hwfn, p_ptt);
2300
2301 return 0;
2302}
2303
2304int qed_mcp_nvm_put_file_begin(struct qed_dev *cdev, u32 addr)
2305{
2306 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2307 struct qed_ptt *p_ptt;
2308 u32 resp, param;
2309 int rc;
2310
2311 p_ptt = qed_ptt_acquire(p_hwfn);
2312 if (!p_ptt)
2313 return -EBUSY;
2314 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_NVM_PUT_FILE_BEGIN, addr,
2315 &resp, ¶m);
2316 cdev->mcp_nvm_resp = resp;
2317 qed_ptt_release(p_hwfn, p_ptt);
2318
2319 return rc;
2320}
2321
2322int qed_mcp_nvm_write(struct qed_dev *cdev,
2323 u32 cmd, u32 addr, u8 *p_buf, u32 len)
2324{
2325 u32 buf_idx = 0, buf_size, nvm_cmd, nvm_offset, resp = 0, param;
2326 struct qed_hwfn *p_hwfn = QED_LEADING_HWFN(cdev);
2327 struct qed_ptt *p_ptt;
2328 int rc = -EINVAL;
2329
2330 p_ptt = qed_ptt_acquire(p_hwfn);
2331 if (!p_ptt)
2332 return -EBUSY;
2333
2334 switch (cmd) {
2335 case QED_PUT_FILE_DATA:
2336 nvm_cmd = DRV_MSG_CODE_NVM_PUT_FILE_DATA;
2337 break;
2338 case QED_NVM_WRITE_NVRAM:
2339 nvm_cmd = DRV_MSG_CODE_NVM_WRITE_NVRAM;
2340 break;
2341 default:
2342 DP_NOTICE(p_hwfn, "Invalid nvm write command 0x%x\n", cmd);
2343 rc = -EINVAL;
2344 goto out;
2345 }
2346
2347 while (buf_idx < len) {
2348 buf_size = min_t(u32, (len - buf_idx), MCP_DRV_NVM_BUF_LEN);
2349 nvm_offset = ((buf_size << DRV_MB_PARAM_NVM_LEN_OFFSET) |
2350 addr) + buf_idx;
2351 rc = qed_mcp_nvm_wr_cmd(p_hwfn, p_ptt, nvm_cmd, nvm_offset,
2352 &resp, ¶m, buf_size,
2353 (u32 *)&p_buf[buf_idx]);
2354 if (rc) {
2355 DP_NOTICE(cdev, "nvm write failed, rc = %d\n", rc);
2356 resp = FW_MSG_CODE_ERROR;
2357 break;
2358 }
2359
2360 if (resp != FW_MSG_CODE_OK &&
2361 resp != FW_MSG_CODE_NVM_OK &&
2362 resp != FW_MSG_CODE_NVM_PUT_FILE_FINISH_OK) {
2363 DP_NOTICE(cdev,
2364 "nvm write failed, resp = 0x%08x\n", resp);
2365 rc = -EINVAL;
2366 break;
2367 }
2368
2369
2370
2371
2372 if (buf_idx % 0x1000 > (buf_idx + buf_size) % 0x1000)
2373 usleep_range(1000, 2000);
2374
2375 buf_idx += buf_size;
2376 }
2377
2378 cdev->mcp_nvm_resp = resp;
2379out:
2380 qed_ptt_release(p_hwfn, p_ptt);
2381
2382 return rc;
2383}
2384
2385int qed_mcp_bist_register_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2386{
2387 u32 drv_mb_param = 0, rsp, param;
2388 int rc = 0;
2389
2390 drv_mb_param = (DRV_MB_PARAM_BIST_REGISTER_TEST <<
2391 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2392
2393 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2394 drv_mb_param, &rsp, ¶m);
2395
2396 if (rc)
2397 return rc;
2398
2399 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2400 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2401 rc = -EAGAIN;
2402
2403 return rc;
2404}
2405
2406int qed_mcp_bist_clock_test(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2407{
2408 u32 drv_mb_param, rsp, param;
2409 int rc = 0;
2410
2411 drv_mb_param = (DRV_MB_PARAM_BIST_CLOCK_TEST <<
2412 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2413
2414 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2415 drv_mb_param, &rsp, ¶m);
2416
2417 if (rc)
2418 return rc;
2419
2420 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2421 (param != DRV_MB_PARAM_BIST_RC_PASSED))
2422 rc = -EAGAIN;
2423
2424 return rc;
2425}
2426
2427int qed_mcp_bist_nvm_get_num_images(struct qed_hwfn *p_hwfn,
2428 struct qed_ptt *p_ptt,
2429 u32 *num_images)
2430{
2431 u32 drv_mb_param = 0, rsp;
2432 int rc = 0;
2433
2434 drv_mb_param = (DRV_MB_PARAM_BIST_NVM_TEST_NUM_IMAGES <<
2435 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT);
2436
2437 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_BIST_TEST,
2438 drv_mb_param, &rsp, num_images);
2439 if (rc)
2440 return rc;
2441
2442 if (((rsp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK))
2443 rc = -EINVAL;
2444
2445 return rc;
2446}
2447
2448int qed_mcp_bist_nvm_get_image_att(struct qed_hwfn *p_hwfn,
2449 struct qed_ptt *p_ptt,
2450 struct bist_nvm_image_att *p_image_att,
2451 u32 image_index)
2452{
2453 u32 buf_size = 0, param, resp = 0, resp_param = 0;
2454 int rc;
2455
2456 param = DRV_MB_PARAM_BIST_NVM_TEST_IMAGE_BY_INDEX <<
2457 DRV_MB_PARAM_BIST_TEST_INDEX_SHIFT;
2458 param |= image_index << DRV_MB_PARAM_BIST_TEST_IMAGE_INDEX_SHIFT;
2459
2460 rc = qed_mcp_nvm_rd_cmd(p_hwfn, p_ptt,
2461 DRV_MSG_CODE_BIST_TEST, param,
2462 &resp, &resp_param,
2463 &buf_size,
2464 (u32 *)p_image_att);
2465 if (rc)
2466 return rc;
2467
2468 if (((resp & FW_MSG_CODE_MASK) != FW_MSG_CODE_OK) ||
2469 (p_image_att->return_code != 1))
2470 rc = -EINVAL;
2471
2472 return rc;
2473}
2474
2475int qed_mcp_nvm_info_populate(struct qed_hwfn *p_hwfn)
2476{
2477 struct qed_nvm_image_info *nvm_info = &p_hwfn->nvm_info;
2478 struct qed_ptt *p_ptt;
2479 int rc;
2480 u32 i;
2481
2482 p_ptt = qed_ptt_acquire(p_hwfn);
2483 if (!p_ptt) {
2484 DP_ERR(p_hwfn, "failed to acquire ptt\n");
2485 return -EBUSY;
2486 }
2487
2488
2489 nvm_info->num_images = 0;
2490 rc = qed_mcp_bist_nvm_get_num_images(p_hwfn,
2491 p_ptt, &nvm_info->num_images);
2492 if (rc == -EOPNOTSUPP) {
2493 DP_INFO(p_hwfn, "DRV_MSG_CODE_BIST_TEST is not supported\n");
2494 goto out;
2495 } else if (rc || !nvm_info->num_images) {
2496 DP_ERR(p_hwfn, "Failed getting number of images\n");
2497 goto err0;
2498 }
2499
2500 nvm_info->image_att = kmalloc(nvm_info->num_images *
2501 sizeof(struct bist_nvm_image_att),
2502 GFP_KERNEL);
2503 if (!nvm_info->image_att) {
2504 rc = -ENOMEM;
2505 goto err0;
2506 }
2507
2508
2509 for (i = 0; i < nvm_info->num_images; i++) {
2510 rc = qed_mcp_bist_nvm_get_image_att(p_hwfn, p_ptt,
2511 &nvm_info->image_att[i], i);
2512 if (rc) {
2513 DP_ERR(p_hwfn,
2514 "Failed getting image index %d attributes\n", i);
2515 goto err1;
2516 }
2517
2518 DP_VERBOSE(p_hwfn, QED_MSG_SP, "image index %d, size %x\n", i,
2519 nvm_info->image_att[i].len);
2520 }
2521out:
2522 qed_ptt_release(p_hwfn, p_ptt);
2523 return 0;
2524
2525err1:
2526 kfree(nvm_info->image_att);
2527err0:
2528 qed_ptt_release(p_hwfn, p_ptt);
2529 return rc;
2530}
2531
2532static int
2533qed_mcp_get_nvm_image_att(struct qed_hwfn *p_hwfn,
2534 struct qed_ptt *p_ptt,
2535 enum qed_nvm_images image_id,
2536 struct qed_nvm_image_att *p_image_att)
2537{
2538 enum nvm_image_type type;
2539 u32 i;
2540
2541
2542 switch (image_id) {
2543 case QED_NVM_IMAGE_ISCSI_CFG:
2544 type = NVM_TYPE_ISCSI_CFG;
2545 break;
2546 case QED_NVM_IMAGE_FCOE_CFG:
2547 type = NVM_TYPE_FCOE_CFG;
2548 break;
2549 default:
2550 DP_NOTICE(p_hwfn, "Unknown request of image_id %08x\n",
2551 image_id);
2552 return -EINVAL;
2553 }
2554
2555 for (i = 0; i < p_hwfn->nvm_info.num_images; i++)
2556 if (type == p_hwfn->nvm_info.image_att[i].image_type)
2557 break;
2558 if (i == p_hwfn->nvm_info.num_images) {
2559 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2560 "Failed to find nvram image of type %08x\n",
2561 image_id);
2562 return -ENOENT;
2563 }
2564
2565 p_image_att->start_addr = p_hwfn->nvm_info.image_att[i].nvm_start_addr;
2566 p_image_att->length = p_hwfn->nvm_info.image_att[i].len;
2567
2568 return 0;
2569}
2570
2571int qed_mcp_get_nvm_image(struct qed_hwfn *p_hwfn,
2572 struct qed_ptt *p_ptt,
2573 enum qed_nvm_images image_id,
2574 u8 *p_buffer, u32 buffer_len)
2575{
2576 struct qed_nvm_image_att image_att;
2577 int rc;
2578
2579 memset(p_buffer, 0, buffer_len);
2580
2581 rc = qed_mcp_get_nvm_image_att(p_hwfn, p_ptt, image_id, &image_att);
2582 if (rc)
2583 return rc;
2584
2585
2586 if (image_att.length <= 4) {
2587 DP_VERBOSE(p_hwfn, QED_MSG_STORAGE,
2588 "Image [%d] is too small - only %d bytes\n",
2589 image_id, image_att.length);
2590 return -EINVAL;
2591 }
2592
2593
2594 image_att.length -= 4;
2595
2596 if (image_att.length > buffer_len) {
2597 DP_VERBOSE(p_hwfn,
2598 QED_MSG_STORAGE,
2599 "Image [%d] is too big - %08x bytes where only %08x are available\n",
2600 image_id, image_att.length, buffer_len);
2601 return -ENOMEM;
2602 }
2603
2604 return qed_mcp_nvm_read(p_hwfn->cdev, image_att.start_addr,
2605 p_buffer, image_att.length);
2606}
2607
2608static enum resource_id_enum qed_mcp_get_mfw_res_id(enum qed_resources res_id)
2609{
2610 enum resource_id_enum mfw_res_id = RESOURCE_NUM_INVALID;
2611
2612 switch (res_id) {
2613 case QED_SB:
2614 mfw_res_id = RESOURCE_NUM_SB_E;
2615 break;
2616 case QED_L2_QUEUE:
2617 mfw_res_id = RESOURCE_NUM_L2_QUEUE_E;
2618 break;
2619 case QED_VPORT:
2620 mfw_res_id = RESOURCE_NUM_VPORT_E;
2621 break;
2622 case QED_RSS_ENG:
2623 mfw_res_id = RESOURCE_NUM_RSS_ENGINES_E;
2624 break;
2625 case QED_PQ:
2626 mfw_res_id = RESOURCE_NUM_PQ_E;
2627 break;
2628 case QED_RL:
2629 mfw_res_id = RESOURCE_NUM_RL_E;
2630 break;
2631 case QED_MAC:
2632 case QED_VLAN:
2633
2634 mfw_res_id = RESOURCE_VFC_FILTER_E;
2635 break;
2636 case QED_ILT:
2637 mfw_res_id = RESOURCE_ILT_E;
2638 break;
2639 case QED_LL2_QUEUE:
2640 mfw_res_id = RESOURCE_LL2_QUEUE_E;
2641 break;
2642 case QED_RDMA_CNQ_RAM:
2643 case QED_CMDQS_CQS:
2644
2645 mfw_res_id = RESOURCE_CQS_E;
2646 break;
2647 case QED_RDMA_STATS_QUEUE:
2648 mfw_res_id = RESOURCE_RDMA_STATS_QUEUE_E;
2649 break;
2650 case QED_BDQ:
2651 mfw_res_id = RESOURCE_BDQ_E;
2652 break;
2653 default:
2654 break;
2655 }
2656
2657 return mfw_res_id;
2658}
2659
2660#define QED_RESC_ALLOC_VERSION_MAJOR 2
2661#define QED_RESC_ALLOC_VERSION_MINOR 0
2662#define QED_RESC_ALLOC_VERSION \
2663 ((QED_RESC_ALLOC_VERSION_MAJOR << \
2664 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR_SHIFT) | \
2665 (QED_RESC_ALLOC_VERSION_MINOR << \
2666 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR_SHIFT))
2667
2668struct qed_resc_alloc_in_params {
2669 u32 cmd;
2670 enum qed_resources res_id;
2671 u32 resc_max_val;
2672};
2673
2674struct qed_resc_alloc_out_params {
2675 u32 mcp_resp;
2676 u32 mcp_param;
2677 u32 resc_num;
2678 u32 resc_start;
2679 u32 vf_resc_num;
2680 u32 vf_resc_start;
2681 u32 flags;
2682};
2683
2684static int
2685qed_mcp_resc_allocation_msg(struct qed_hwfn *p_hwfn,
2686 struct qed_ptt *p_ptt,
2687 struct qed_resc_alloc_in_params *p_in_params,
2688 struct qed_resc_alloc_out_params *p_out_params)
2689{
2690 struct qed_mcp_mb_params mb_params;
2691 struct resource_info mfw_resc_info;
2692 int rc;
2693
2694 memset(&mfw_resc_info, 0, sizeof(mfw_resc_info));
2695
2696 mfw_resc_info.res_id = qed_mcp_get_mfw_res_id(p_in_params->res_id);
2697 if (mfw_resc_info.res_id == RESOURCE_NUM_INVALID) {
2698 DP_ERR(p_hwfn,
2699 "Failed to match resource %d [%s] with the MFW resources\n",
2700 p_in_params->res_id,
2701 qed_hw_get_resc_name(p_in_params->res_id));
2702 return -EINVAL;
2703 }
2704
2705 switch (p_in_params->cmd) {
2706 case DRV_MSG_SET_RESOURCE_VALUE_MSG:
2707 mfw_resc_info.size = p_in_params->resc_max_val;
2708
2709 case DRV_MSG_GET_RESOURCE_ALLOC_MSG:
2710 break;
2711 default:
2712 DP_ERR(p_hwfn, "Unexpected resource alloc command [0x%08x]\n",
2713 p_in_params->cmd);
2714 return -EINVAL;
2715 }
2716
2717 memset(&mb_params, 0, sizeof(mb_params));
2718 mb_params.cmd = p_in_params->cmd;
2719 mb_params.param = QED_RESC_ALLOC_VERSION;
2720 mb_params.p_data_src = &mfw_resc_info;
2721 mb_params.data_src_size = sizeof(mfw_resc_info);
2722 mb_params.p_data_dst = mb_params.p_data_src;
2723 mb_params.data_dst_size = mb_params.data_src_size;
2724
2725 DP_VERBOSE(p_hwfn,
2726 QED_MSG_SP,
2727 "Resource message request: cmd 0x%08x, res_id %d [%s], hsi_version %d.%d, val 0x%x\n",
2728 p_in_params->cmd,
2729 p_in_params->res_id,
2730 qed_hw_get_resc_name(p_in_params->res_id),
2731 QED_MFW_GET_FIELD(mb_params.param,
2732 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2733 QED_MFW_GET_FIELD(mb_params.param,
2734 DRV_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2735 p_in_params->resc_max_val);
2736
2737 rc = qed_mcp_cmd_and_union(p_hwfn, p_ptt, &mb_params);
2738 if (rc)
2739 return rc;
2740
2741 p_out_params->mcp_resp = mb_params.mcp_resp;
2742 p_out_params->mcp_param = mb_params.mcp_param;
2743 p_out_params->resc_num = mfw_resc_info.size;
2744 p_out_params->resc_start = mfw_resc_info.offset;
2745 p_out_params->vf_resc_num = mfw_resc_info.vf_size;
2746 p_out_params->vf_resc_start = mfw_resc_info.vf_offset;
2747 p_out_params->flags = mfw_resc_info.flags;
2748
2749 DP_VERBOSE(p_hwfn,
2750 QED_MSG_SP,
2751 "Resource message response: mfw_hsi_version %d.%d, num 0x%x, start 0x%x, vf_num 0x%x, vf_start 0x%x, flags 0x%08x\n",
2752 QED_MFW_GET_FIELD(p_out_params->mcp_param,
2753 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MAJOR),
2754 QED_MFW_GET_FIELD(p_out_params->mcp_param,
2755 FW_MB_PARAM_RESOURCE_ALLOC_VERSION_MINOR),
2756 p_out_params->resc_num,
2757 p_out_params->resc_start,
2758 p_out_params->vf_resc_num,
2759 p_out_params->vf_resc_start, p_out_params->flags);
2760
2761 return 0;
2762}
2763
2764int
2765qed_mcp_set_resc_max_val(struct qed_hwfn *p_hwfn,
2766 struct qed_ptt *p_ptt,
2767 enum qed_resources res_id,
2768 u32 resc_max_val, u32 *p_mcp_resp)
2769{
2770 struct qed_resc_alloc_out_params out_params;
2771 struct qed_resc_alloc_in_params in_params;
2772 int rc;
2773
2774 memset(&in_params, 0, sizeof(in_params));
2775 in_params.cmd = DRV_MSG_SET_RESOURCE_VALUE_MSG;
2776 in_params.res_id = res_id;
2777 in_params.resc_max_val = resc_max_val;
2778 memset(&out_params, 0, sizeof(out_params));
2779 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2780 &out_params);
2781 if (rc)
2782 return rc;
2783
2784 *p_mcp_resp = out_params.mcp_resp;
2785
2786 return 0;
2787}
2788
2789int
2790qed_mcp_get_resc_info(struct qed_hwfn *p_hwfn,
2791 struct qed_ptt *p_ptt,
2792 enum qed_resources res_id,
2793 u32 *p_mcp_resp, u32 *p_resc_num, u32 *p_resc_start)
2794{
2795 struct qed_resc_alloc_out_params out_params;
2796 struct qed_resc_alloc_in_params in_params;
2797 int rc;
2798
2799 memset(&in_params, 0, sizeof(in_params));
2800 in_params.cmd = DRV_MSG_GET_RESOURCE_ALLOC_MSG;
2801 in_params.res_id = res_id;
2802 memset(&out_params, 0, sizeof(out_params));
2803 rc = qed_mcp_resc_allocation_msg(p_hwfn, p_ptt, &in_params,
2804 &out_params);
2805 if (rc)
2806 return rc;
2807
2808 *p_mcp_resp = out_params.mcp_resp;
2809
2810 if (*p_mcp_resp == FW_MSG_CODE_RESOURCE_ALLOC_OK) {
2811 *p_resc_num = out_params.resc_num;
2812 *p_resc_start = out_params.resc_start;
2813 }
2814
2815 return 0;
2816}
2817
2818int qed_mcp_initiate_pf_flr(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
2819{
2820 u32 mcp_resp, mcp_param;
2821
2822 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_INITIATE_PF_FLR, 0,
2823 &mcp_resp, &mcp_param);
2824}
2825
2826static int qed_mcp_resource_cmd(struct qed_hwfn *p_hwfn,
2827 struct qed_ptt *p_ptt,
2828 u32 param, u32 *p_mcp_resp, u32 *p_mcp_param)
2829{
2830 int rc;
2831
2832 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_RESOURCE_CMD, param,
2833 p_mcp_resp, p_mcp_param);
2834 if (rc)
2835 return rc;
2836
2837 if (*p_mcp_resp == FW_MSG_CODE_UNSUPPORTED) {
2838 DP_INFO(p_hwfn,
2839 "The resource command is unsupported by the MFW\n");
2840 return -EINVAL;
2841 }
2842
2843 if (*p_mcp_param == RESOURCE_OPCODE_UNKNOWN_CMD) {
2844 u8 opcode = QED_MFW_GET_FIELD(param, RESOURCE_CMD_REQ_OPCODE);
2845
2846 DP_NOTICE(p_hwfn,
2847 "The resource command is unknown to the MFW [param 0x%08x, opcode %d]\n",
2848 param, opcode);
2849 return -EINVAL;
2850 }
2851
2852 return rc;
2853}
2854
2855int
2856__qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2857 struct qed_ptt *p_ptt,
2858 struct qed_resc_lock_params *p_params)
2859{
2860 u32 param = 0, mcp_resp, mcp_param;
2861 u8 opcode;
2862 int rc;
2863
2864 switch (p_params->timeout) {
2865 case QED_MCP_RESC_LOCK_TO_DEFAULT:
2866 opcode = RESOURCE_OPCODE_REQ;
2867 p_params->timeout = 0;
2868 break;
2869 case QED_MCP_RESC_LOCK_TO_NONE:
2870 opcode = RESOURCE_OPCODE_REQ_WO_AGING;
2871 p_params->timeout = 0;
2872 break;
2873 default:
2874 opcode = RESOURCE_OPCODE_REQ_W_AGING;
2875 break;
2876 }
2877
2878 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2879 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2880 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_AGE, p_params->timeout);
2881
2882 DP_VERBOSE(p_hwfn,
2883 QED_MSG_SP,
2884 "Resource lock request: param 0x%08x [age %d, opcode %d, resource %d]\n",
2885 param, p_params->timeout, opcode, p_params->resource);
2886
2887
2888 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2889 if (rc)
2890 return rc;
2891
2892
2893 p_params->owner = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OWNER);
2894 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2895
2896 DP_VERBOSE(p_hwfn,
2897 QED_MSG_SP,
2898 "Resource lock response: mcp_param 0x%08x [opcode %d, owner %d]\n",
2899 mcp_param, opcode, p_params->owner);
2900
2901 switch (opcode) {
2902 case RESOURCE_OPCODE_GNT:
2903 p_params->b_granted = true;
2904 break;
2905 case RESOURCE_OPCODE_BUSY:
2906 p_params->b_granted = false;
2907 break;
2908 default:
2909 DP_NOTICE(p_hwfn,
2910 "Unexpected opcode in resource lock response [mcp_param 0x%08x, opcode %d]\n",
2911 mcp_param, opcode);
2912 return -EINVAL;
2913 }
2914
2915 return 0;
2916}
2917
2918int
2919qed_mcp_resc_lock(struct qed_hwfn *p_hwfn,
2920 struct qed_ptt *p_ptt, struct qed_resc_lock_params *p_params)
2921{
2922 u32 retry_cnt = 0;
2923 int rc;
2924
2925 do {
2926
2927 if (retry_cnt) {
2928 if (p_params->sleep_b4_retry) {
2929 u16 retry_interval_in_ms =
2930 DIV_ROUND_UP(p_params->retry_interval,
2931 1000);
2932
2933 msleep(retry_interval_in_ms);
2934 } else {
2935 udelay(p_params->retry_interval);
2936 }
2937 }
2938
2939 rc = __qed_mcp_resc_lock(p_hwfn, p_ptt, p_params);
2940 if (rc)
2941 return rc;
2942
2943 if (p_params->b_granted)
2944 break;
2945 } while (retry_cnt++ < p_params->retry_num);
2946
2947 return 0;
2948}
2949
2950int
2951qed_mcp_resc_unlock(struct qed_hwfn *p_hwfn,
2952 struct qed_ptt *p_ptt,
2953 struct qed_resc_unlock_params *p_params)
2954{
2955 u32 param = 0, mcp_resp, mcp_param;
2956 u8 opcode;
2957 int rc;
2958
2959 opcode = p_params->b_force ? RESOURCE_OPCODE_FORCE_RELEASE
2960 : RESOURCE_OPCODE_RELEASE;
2961 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_RESC, p_params->resource);
2962 QED_MFW_SET_FIELD(param, RESOURCE_CMD_REQ_OPCODE, opcode);
2963
2964 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2965 "Resource unlock request: param 0x%08x [opcode %d, resource %d]\n",
2966 param, opcode, p_params->resource);
2967
2968
2969 rc = qed_mcp_resource_cmd(p_hwfn, p_ptt, param, &mcp_resp, &mcp_param);
2970 if (rc)
2971 return rc;
2972
2973
2974 opcode = QED_MFW_GET_FIELD(mcp_param, RESOURCE_CMD_RSP_OPCODE);
2975
2976 DP_VERBOSE(p_hwfn, QED_MSG_SP,
2977 "Resource unlock response: mcp_param 0x%08x [opcode %d]\n",
2978 mcp_param, opcode);
2979
2980 switch (opcode) {
2981 case RESOURCE_OPCODE_RELEASED_PREVIOUS:
2982 DP_INFO(p_hwfn,
2983 "Resource unlock request for an already released resource [%d]\n",
2984 p_params->resource);
2985
2986 case RESOURCE_OPCODE_RELEASED:
2987 p_params->b_released = true;
2988 break;
2989 case RESOURCE_OPCODE_WRONG_OWNER:
2990 p_params->b_released = false;
2991 break;
2992 default:
2993 DP_NOTICE(p_hwfn,
2994 "Unexpected opcode in resource unlock response [mcp_param 0x%08x, opcode %d]\n",
2995 mcp_param, opcode);
2996 return -EINVAL;
2997 }
2998
2999 return 0;
3000}
3001
3002void qed_mcp_resc_lock_default_init(struct qed_resc_lock_params *p_lock,
3003 struct qed_resc_unlock_params *p_unlock,
3004 enum qed_resc_lock
3005 resource, bool b_is_permanent)
3006{
3007 if (p_lock) {
3008 memset(p_lock, 0, sizeof(*p_lock));
3009
3010
3011
3012
3013
3014 if (b_is_permanent) {
3015 p_lock->timeout = QED_MCP_RESC_LOCK_TO_NONE;
3016 } else {
3017 p_lock->retry_num = QED_MCP_RESC_LOCK_RETRY_CNT_DFLT;
3018 p_lock->retry_interval =
3019 QED_MCP_RESC_LOCK_RETRY_VAL_DFLT;
3020 p_lock->sleep_b4_retry = true;
3021 }
3022
3023 p_lock->resource = resource;
3024 }
3025
3026 if (p_unlock) {
3027 memset(p_unlock, 0, sizeof(*p_unlock));
3028 p_unlock->resource = resource;
3029 }
3030}
3031
3032int qed_mcp_get_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3033{
3034 u32 mcp_resp;
3035 int rc;
3036
3037 rc = qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_GET_MFW_FEATURE_SUPPORT,
3038 0, &mcp_resp, &p_hwfn->mcp_info->capabilities);
3039 if (!rc)
3040 DP_VERBOSE(p_hwfn, (QED_MSG_SP | NETIF_MSG_PROBE),
3041 "MFW supported features: %08x\n",
3042 p_hwfn->mcp_info->capabilities);
3043
3044 return rc;
3045}
3046
3047int qed_mcp_set_capabilities(struct qed_hwfn *p_hwfn, struct qed_ptt *p_ptt)
3048{
3049 u32 mcp_resp, mcp_param, features;
3050
3051 features = DRV_MB_PARAM_FEATURE_SUPPORT_PORT_EEE;
3052
3053 return qed_mcp_cmd(p_hwfn, p_ptt, DRV_MSG_CODE_FEATURE_SUPPORT,
3054 features, &mcp_resp, &mcp_param);
3055}
3056