LXR linux/drivers/net/wan/pc300too.c

   1/*
   2 * Cyclades PC300 synchronous serial card driver for Linux
   3 *
   4 * Copyright (C) 2000-2008 Krzysztof Halasa <khc@pm.waw.pl>
   5 *
   6 * This program is free software; you can redistribute it and/or modify it
   7 * under the terms of version 2 of the GNU General Public License
   8 * as published by the Free Software Foundation.
   9 *
  10 * For information see <http://www.kernel.org/pub/linux/utils/net/hdlc/>.
  11 *
  12 * Sources of information:
  13 *    Hitachi HD64572 SCA-II User's Manual
  14 *    Original Cyclades PC300 Linux driver
  15 *
  16 * This driver currently supports only PC300/RSV (V.24/V.35) and
  17 * PC300/X21 cards.
  18 */
  19
  20#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  21
  22#include <linux/module.h>
  23#include <linux/kernel.h>
  24#include <linux/slab.h>
  25#include <linux/sched.h>
  26#include <linux/types.h>
  27#include <linux/fcntl.h>
  28#include <linux/in.h>
  29#include <linux/string.h>
  30#include <linux/errno.h>
  31#include <linux/init.h>
  32#include <linux/ioport.h>
  33#include <linux/moduleparam.h>
  34#include <linux/netdevice.h>
  35#include <linux/hdlc.h>
  36#include <linux/pci.h>
  37#include <linux/delay.h>
  38#include <asm/io.h>
  39
  40#include "hd64572.h"
  41
  42#undef DEBUG_PKT
  43#define DEBUG_RINGS
  44
  45#define PC300_PLX_SIZE          0x80    /* PLX control window size (128 B) */
  46#define PC300_SCA_SIZE          0x400   /* SCA window size (1 KB) */
  47#define MAX_TX_BUFFERS          10
  48
  49static int pci_clock_freq = 33000000;
  50static int use_crystal_clock = 0;
  51static unsigned int CLOCK_BASE;
  52
  53/* Masks to access the init_ctrl PLX register */
  54#define PC300_CLKSEL_MASK        (0x00000004UL)
  55#define PC300_CHMEDIA_MASK(port) (0x00000020UL << ((port) * 3))
  56#define PC300_CTYPE_MASK         (0x00000800UL)
  57
  58
  59enum { PC300_RSV = 1, PC300_X21, PC300_TE }; /* card types */
  60
  61/*
  62 *      PLX PCI9050-1 local configuration and shared runtime registers.
  63 *      This structure can be used to access 9050 registers (memory mapped).
  64 */
  65typedef struct {
  66        u32 loc_addr_range[4];  /* 00-0Ch : Local Address Ranges */
  67        u32 loc_rom_range;      /* 10h : Local ROM Range */
  68        u32 loc_addr_base[4];   /* 14-20h : Local Address Base Addrs */
  69        u32 loc_rom_base;       /* 24h : Local ROM Base */
  70        u32 loc_bus_descr[4];   /* 28-34h : Local Bus Descriptors */
  71        u32 rom_bus_descr;      /* 38h : ROM Bus Descriptor */
  72        u32 cs_base[4];         /* 3C-48h : Chip Select Base Addrs */
  73        u32 intr_ctrl_stat;     /* 4Ch : Interrupt Control/Status */
  74        u32 init_ctrl;          /* 50h : EEPROM ctrl, Init Ctrl, etc */
  75}plx9050;
  76
  77
  78
  79typedef struct port_s {
  80        struct napi_struct napi;
  81        struct net_device *netdev;
  82        struct card_s *card;
  83        spinlock_t lock;        /* TX lock */
  84        sync_serial_settings settings;
  85        int rxpart;             /* partial frame received, next frame invalid*/
  86        unsigned short encoding;
  87        unsigned short parity;
  88        unsigned int iface;
  89        u16 rxin;               /* rx ring buffer 'in' pointer */
  90        u16 txin;               /* tx ring buffer 'in' and 'last' pointers */
  91        u16 txlast;
  92        u8 rxs, txs, tmc;       /* SCA registers */
  93        u8 chan;                /* physical port # - 0 or 1 */
  94}port_t;
  95
  96
  97
  98typedef struct card_s {
  99        int type;               /* RSV, X21, etc. */
 100        int n_ports;            /* 1 or 2 ports */
 101        u8 __iomem *rambase;    /* buffer memory base (virtual) */
 102        u8 __iomem *scabase;    /* SCA memory base (virtual) */
 103        plx9050 __iomem *plxbase; /* PLX registers memory base (virtual) */
 104        u32 init_ctrl_value;    /* Saved value - 9050 bug workaround */
 105        u16 rx_ring_buffers;    /* number of buffers in a ring */
 106        u16 tx_ring_buffers;
 107        u16 buff_offset;        /* offset of first buffer of first channel */
 108        u8 irq;                 /* interrupt request level */
 109
 110        port_t ports[2];
 111}card_t;
 112
 113
 114#define get_port(card, port)         ((port) < (card)->n_ports ? \
 115                                         (&(card)->ports[port]) : (NULL))
 116
 117#include "hd64572.c"
 118
 119
 120static void pc300_set_iface(port_t *port)
 121{
 122        card_t *card = port->card;
 123        u32 __iomem * init_ctrl = &card->plxbase->init_ctrl;
 124        u16 msci = get_msci(port);
 125        u8 rxs = port->rxs & CLK_BRG_MASK;
 126        u8 txs = port->txs & CLK_BRG_MASK;
 127
 128        sca_out(EXS_TES1, (port->chan ? MSCI1_OFFSET : MSCI0_OFFSET) + EXS,
 129                port->card);
 130        switch(port->settings.clock_type) {
 131        case CLOCK_INT:
 132                rxs |= CLK_BRG; /* BRG output */
 133                txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
 134                break;
 135
 136        case CLOCK_TXINT:
 137                rxs |= CLK_LINE; /* RXC input */
 138                txs |= CLK_PIN_OUT | CLK_BRG; /* BRG output */
 139                break;
 140
 141        case CLOCK_TXFROMRX:
 142                rxs |= CLK_LINE; /* RXC input */
 143                txs |= CLK_PIN_OUT | CLK_TX_RXCLK; /* RX clock */
 144                break;
 145
 146        default:                /* EXTernal clock */
 147                rxs |= CLK_LINE; /* RXC input */
 148                txs |= CLK_PIN_OUT | CLK_LINE; /* TXC input */
 149                break;
 150        }
 151
 152        port->rxs = rxs;
 153        port->txs = txs;
 154        sca_out(rxs, msci + RXS, card);
 155        sca_out(txs, msci + TXS, card);
 156        sca_set_port(port);
 157
 158        if (port->card->type == PC300_RSV) {
 159                if (port->iface == IF_IFACE_V35)
 160                        writel(card->init_ctrl_value |
 161                               PC300_CHMEDIA_MASK(port->chan), init_ctrl);
 162                else
 163                        writel(card->init_ctrl_value &
 164                               ~PC300_CHMEDIA_MASK(port->chan), init_ctrl);
 165        }
 166}
 167
 168
 169
 170static int pc300_open(struct net_device *dev)
 171{
 172        port_t *port = dev_to_port(dev);
 173
 174        int result = hdlc_open(dev);
 175        if (result)
 176                return result;
 177
 178        sca_open(dev);
 179        pc300_set_iface(port);
 180        return 0;
 181}
 182
 183
 184
 185static int pc300_close(struct net_device *dev)
 186{
 187        sca_close(dev);
 188        hdlc_close(dev);
 189        return 0;
 190}
 191
 192
 193
 194static int pc300_ioctl(struct net_device *dev, struct ifreq *ifr, int cmd)
 195{
 196        const size_t size = sizeof(sync_serial_settings);
 197        sync_serial_settings new_line;
 198        sync_serial_settings __user *line = ifr->ifr_settings.ifs_ifsu.sync;
 199        int new_type;
 200        port_t *port = dev_to_port(dev);
 201
 202#ifdef DEBUG_RINGS
 203        if (cmd == SIOCDEVPRIVATE) {
 204                sca_dump_rings(dev);
 205                return 0;
 206        }
 207#endif
 208        if (cmd != SIOCWANDEV)
 209                return hdlc_ioctl(dev, ifr, cmd);
 210
 211        if (ifr->ifr_settings.type == IF_GET_IFACE) {
 212                ifr->ifr_settings.type = port->iface;
 213                if (ifr->ifr_settings.size < size) {
 214                        ifr->ifr_settings.size = size; /* data size wanted */
 215                        return -ENOBUFS;
 216                }
 217                if (copy_to_user(line, &port->settings, size))
 218                        return -EFAULT;
 219                return 0;
 220
 221        }
 222
 223        if (port->card->type == PC300_X21 &&
 224            (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
 225             ifr->ifr_settings.type == IF_IFACE_X21))
 226                new_type = IF_IFACE_X21;
 227
 228        else if (port->card->type == PC300_RSV &&
 229                 (ifr->ifr_settings.type == IF_IFACE_SYNC_SERIAL ||
 230                  ifr->ifr_settings.type == IF_IFACE_V35))
 231                new_type = IF_IFACE_V35;
 232
 233        else if (port->card->type == PC300_RSV &&
 234                 ifr->ifr_settings.type == IF_IFACE_V24)
 235                new_type = IF_IFACE_V24;
 236
 237        else
 238                return hdlc_ioctl(dev, ifr, cmd);
 239
 240        if (!capable(CAP_NET_ADMIN))
 241                return -EPERM;
 242
 243        if (copy_from_user(&new_line, line, size))
 244                return -EFAULT;
 245
 246        if (new_line.clock_type != CLOCK_EXT &&
 247            new_line.clock_type != CLOCK_TXFROMRX &&
 248            new_line.clock_type != CLOCK_INT &&
 249            new_line.clock_type != CLOCK_TXINT)
 250                return -EINVAL; /* No such clock setting */
 251
 252        if (new_line.loopback != 0 && new_line.loopback != 1)
 253                return -EINVAL;
 254
 255        memcpy(&port->settings, &new_line, size); /* Update settings */
 256        port->iface = new_type;
 257        pc300_set_iface(port);
 258        return 0;
 259}
 260
 261
 262
 263static void pc300_pci_remove_one(struct pci_dev *pdev)
 264{
 265        int i;
 266        card_t *card = pci_get_drvdata(pdev);
 267
 268        for (i = 0; i < 2; i++)
 269                if (card->ports[i].card)
 270                        unregister_hdlc_device(card->ports[i].netdev);
 271
 272        if (card->irq)
 273                free_irq(card->irq, card);
 274
 275        if (card->rambase)
 276                iounmap(card->rambase);
 277        if (card->scabase)
 278                iounmap(card->scabase);
 279        if (card->plxbase)
 280                iounmap(card->plxbase);
 281
 282        pci_release_regions(pdev);
 283        pci_disable_device(pdev);
 284        if (card->ports[0].netdev)
 285                free_netdev(card->ports[0].netdev);
 286        if (card->ports[1].netdev)
 287                free_netdev(card->ports[1].netdev);
 288        kfree(card);
 289}
 290
 291static const struct net_device_ops pc300_ops = {
 292        .ndo_open       = pc300_open,
 293        .ndo_stop       = pc300_close,
 294        .ndo_start_xmit = hdlc_start_xmit,
 295        .ndo_do_ioctl   = pc300_ioctl,
 296};
 297
 298static int pc300_pci_init_one(struct pci_dev *pdev,
 299                              const struct pci_device_id *ent)
 300{
 301        card_t *card;
 302        u32 __iomem *p;
 303        int i;
 304        u32 ramsize;
 305        u32 ramphys;            /* buffer memory base */
 306        u32 scaphys;            /* SCA memory base */
 307        u32 plxphys;            /* PLX registers memory base */
 308
 309        i = pci_enable_device(pdev);
 310        if (i)
 311                return i;
 312
 313        i = pci_request_regions(pdev, "PC300");
 314        if (i) {
 315                pci_disable_device(pdev);
 316                return i;
 317        }
 318
 319        card = kzalloc(sizeof(card_t), GFP_KERNEL);
 320        if (card == NULL) {
 321                pci_release_regions(pdev);
 322                pci_disable_device(pdev);
 323                return -ENOBUFS;
 324        }
 325        pci_set_drvdata(pdev, card);
 326
 327        if (pci_resource_len(pdev, 0) != PC300_PLX_SIZE ||
 328            pci_resource_len(pdev, 2) != PC300_SCA_SIZE ||
 329            pci_resource_len(pdev, 3) < 16384) {
 330                pr_err("invalid card EEPROM parameters\n");
 331                pc300_pci_remove_one(pdev);
 332                return -EFAULT;
 333        }
 334
 335        plxphys = pci_resource_start(pdev, 0) & PCI_BASE_ADDRESS_MEM_MASK;
 336        card->plxbase = ioremap(plxphys, PC300_PLX_SIZE);
 337
 338        scaphys = pci_resource_start(pdev, 2) & PCI_BASE_ADDRESS_MEM_MASK;
 339        card->scabase = ioremap(scaphys, PC300_SCA_SIZE);
 340
 341        ramphys = pci_resource_start(pdev, 3) & PCI_BASE_ADDRESS_MEM_MASK;
 342        card->rambase = pci_ioremap_bar(pdev, 3);
 343
 344        if (card->plxbase == NULL ||
 345            card->scabase == NULL ||
 346            card->rambase == NULL) {
 347                pr_err("ioremap() failed\n");
 348                pc300_pci_remove_one(pdev);
 349                return -ENOMEM;
 350        }
 351
 352        /* PLX PCI 9050 workaround for local configuration register read bug */
 353        pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, scaphys);
 354        card->init_ctrl_value = readl(&((plx9050 __iomem *)card->scabase)->init_ctrl);
 355        pci_write_config_dword(pdev, PCI_BASE_ADDRESS_0, plxphys);
 356
 357        if (pdev->device == PCI_DEVICE_ID_PC300_TE_1 ||
 358            pdev->device == PCI_DEVICE_ID_PC300_TE_2)
 359                card->type = PC300_TE; /* not fully supported */
 360        else if (card->init_ctrl_value & PC300_CTYPE_MASK)
 361                card->type = PC300_X21;
 362        else
 363                card->type = PC300_RSV;
 364
 365        if (pdev->device == PCI_DEVICE_ID_PC300_RX_1 ||
 366            pdev->device == PCI_DEVICE_ID_PC300_TE_1)
 367                card->n_ports = 1;
 368        else
 369                card->n_ports = 2;
 370
 371        for (i = 0; i < card->n_ports; i++)
 372                if (!(card->ports[i].netdev = alloc_hdlcdev(&card->ports[i]))) {
 373                        pr_err("unable to allocate memory\n");
 374                        pc300_pci_remove_one(pdev);
 375                        return -ENOMEM;
 376                }
 377
 378        /* Reset PLX */
 379        p = &card->plxbase->init_ctrl;
 380        writel(card->init_ctrl_value | 0x40000000, p);
 381        readl(p);               /* Flush the write - do not use sca_flush */
 382        udelay(1);
 383
 384        writel(card->init_ctrl_value, p);
 385        readl(p);               /* Flush the write - do not use sca_flush */
 386        udelay(1);
 387
 388        /* Reload Config. Registers from EEPROM */
 389        writel(card->init_ctrl_value | 0x20000000, p);
 390        readl(p);               /* Flush the write - do not use sca_flush */
 391        udelay(1);
 392
 393        writel(card->init_ctrl_value, p);
 394        readl(p);               /* Flush the write - do not use sca_flush */
 395        udelay(1);
 396
 397        ramsize = sca_detect_ram(card, card->rambase,
 398                                 pci_resource_len(pdev, 3));
 399
 400        if (use_crystal_clock)
 401                card->init_ctrl_value &= ~PC300_CLKSEL_MASK;
 402        else
 403                card->init_ctrl_value |= PC300_CLKSEL_MASK;
 404
 405        writel(card->init_ctrl_value, &card->plxbase->init_ctrl);
 406        /* number of TX + RX buffers for one port */
 407        i = ramsize / (card->n_ports * (sizeof(pkt_desc) + HDLC_MAX_MRU));
 408        card->tx_ring_buffers = min(i / 2, MAX_TX_BUFFERS);
 409        card->rx_ring_buffers = i - card->tx_ring_buffers;
 410
 411        card->buff_offset = card->n_ports * sizeof(pkt_desc) *
 412                (card->tx_ring_buffers + card->rx_ring_buffers);
 413
 414        pr_info("PC300/%s, %u KB RAM at 0x%x, IRQ%u, using %u TX + %u RX packets rings\n",
 415                card->type == PC300_X21 ? "X21" :
 416                card->type == PC300_TE ? "TE" : "RSV",
 417                ramsize / 1024, ramphys, pdev->irq,
 418                card->tx_ring_buffers, card->rx_ring_buffers);
 419
 420        if (card->tx_ring_buffers < 1) {
 421                pr_err("RAM test failed\n");
 422                pc300_pci_remove_one(pdev);
 423                return -EFAULT;
 424        }
 425
 426        /* Enable interrupts on the PCI bridge, LINTi1 active low */
 427        writew(0x0041, &card->plxbase->intr_ctrl_stat);
 428
 429        /* Allocate IRQ */
 430        if (request_irq(pdev->irq, sca_intr, IRQF_SHARED, "pc300", card)) {
 431                pr_warn("could not allocate IRQ%d\n", pdev->irq);
 432                pc300_pci_remove_one(pdev);
 433                return -EBUSY;
 434        }
 435        card->irq = pdev->irq;
 436
 437        sca_init(card, 0);
 438
 439        // COTE not set - allows better TX DMA settings
 440        // sca_out(sca_in(PCR, card) | PCR_COTE, PCR, card);
 441
 442        sca_out(0x10, BTCR, card);
 443
 444        for (i = 0; i < card->n_ports; i++) {
 445                port_t *port = &card->ports[i];
 446                struct net_device *dev = port->netdev;
 447                hdlc_device *hdlc = dev_to_hdlc(dev);
 448                port->chan = i;
 449
 450                spin_lock_init(&port->lock);
 451                dev->irq = card->irq;
 452                dev->mem_start = ramphys;
 453                dev->mem_end = ramphys + ramsize - 1;
 454                dev->tx_queue_len = 50;
 455                dev->netdev_ops = &pc300_ops;
 456                hdlc->attach = sca_attach;
 457                hdlc->xmit = sca_xmit;
 458                port->settings.clock_type = CLOCK_EXT;
 459                port->card = card;
 460                if (card->type == PC300_X21)
 461                        port->iface = IF_IFACE_X21;
 462                else
 463                        port->iface = IF_IFACE_V35;
 464
 465                sca_init_port(port);
 466                if (register_hdlc_device(dev)) {
 467                        pr_err("unable to register hdlc device\n");
 468                        port->card = NULL;
 469                        pc300_pci_remove_one(pdev);
 470                        return -ENOBUFS;
 471                }
 472
 473                netdev_info(dev, "PC300 channel %d\n", port->chan);
 474        }
 475        return 0;
 476}
 477
 478
 479
 480static const struct pci_device_id pc300_pci_tbl[] = {
 481        { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_1, PCI_ANY_ID,
 482          PCI_ANY_ID, 0, 0, 0 },
 483        { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_RX_2, PCI_ANY_ID,
 484          PCI_ANY_ID, 0, 0, 0 },
 485        { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_1, PCI_ANY_ID,
 486          PCI_ANY_ID, 0, 0, 0 },
 487        { PCI_VENDOR_ID_CYCLADES, PCI_DEVICE_ID_PC300_TE_2, PCI_ANY_ID,
 488          PCI_ANY_ID, 0, 0, 0 },
 489        { 0, }
 490};
 491
 492
 493static struct pci_driver pc300_pci_driver = {
 494        .name =          "PC300",
 495        .id_table =      pc300_pci_tbl,
 496        .probe =         pc300_pci_init_one,
 497        .remove =        pc300_pci_remove_one,
 498};
 499
 500
 501static int __init pc300_init_module(void)
 502{
 503        if (pci_clock_freq < 1000000 || pci_clock_freq > 80000000) {
 504                pr_err("Invalid PCI clock frequency\n");
 505                return -EINVAL;
 506        }
 507        if (use_crystal_clock != 0 && use_crystal_clock != 1) {
 508                pr_err("Invalid 'use_crystal_clock' value\n");
 509                return -EINVAL;
 510        }
 511
 512        CLOCK_BASE = use_crystal_clock ? 24576000 : pci_clock_freq;
 513
 514        return pci_register_driver(&pc300_pci_driver);
 515}
 516
 517
 518
 519static void __exit pc300_cleanup_module(void)
 520{
 521        pci_unregister_driver(&pc300_pci_driver);
 522}
 523
 524MODULE_AUTHOR("Krzysztof Halasa <khc@pm.waw.pl>");
 525MODULE_DESCRIPTION("Cyclades PC300 serial port driver");
 526MODULE_LICENSE("GPL v2");
 527MODULE_DEVICE_TABLE(pci, pc300_pci_tbl);
 528module_param(pci_clock_freq, int, 0444);
 529MODULE_PARM_DESC(pci_clock_freq, "System PCI clock frequency in Hz");
 530module_param(use_crystal_clock, int, 0444);
 531MODULE_PARM_DESC(use_crystal_clock,
 532                 "Use 24.576 MHz clock instead of PCI clock");
 533module_init(pc300_init_module);
 534module_exit(pc300_cleanup_module);
 535