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69#ifndef __iwl_commands_h__
70#define __iwl_commands_h__
71
72#include <linux/ieee80211.h>
73#include <linux/types.h>
74
75
76enum {
77 REPLY_ALIVE = 0x1,
78 REPLY_ERROR = 0x2,
79 REPLY_ECHO = 0x3,
80
81
82 REPLY_RXON = 0x10,
83 REPLY_RXON_ASSOC = 0x11,
84 REPLY_QOS_PARAM = 0x13,
85 REPLY_RXON_TIMING = 0x14,
86
87
88 REPLY_ADD_STA = 0x18,
89 REPLY_REMOVE_STA = 0x19,
90 REPLY_REMOVE_ALL_STA = 0x1a,
91 REPLY_TXFIFO_FLUSH = 0x1e,
92
93
94 REPLY_WEPKEY = 0x20,
95
96
97 REPLY_TX = 0x1c,
98 REPLY_LEDS_CMD = 0x48,
99 REPLY_TX_LINK_QUALITY_CMD = 0x4e,
100
101
102 COEX_PRIORITY_TABLE_CMD = 0x5a,
103 COEX_MEDIUM_NOTIFICATION = 0x5b,
104 COEX_EVENT_CMD = 0x5c,
105
106
107 TEMPERATURE_NOTIFICATION = 0x62,
108 CALIBRATION_CFG_CMD = 0x65,
109 CALIBRATION_RES_NOTIFICATION = 0x66,
110 CALIBRATION_COMPLETE_NOTIFICATION = 0x67,
111
112
113 REPLY_QUIET_CMD = 0x71,
114 REPLY_CHANNEL_SWITCH = 0x72,
115 CHANNEL_SWITCH_NOTIFICATION = 0x73,
116 REPLY_SPECTRUM_MEASUREMENT_CMD = 0x74,
117 SPECTRUM_MEASURE_NOTIFICATION = 0x75,
118
119
120 POWER_TABLE_CMD = 0x77,
121 PM_SLEEP_NOTIFICATION = 0x7A,
122 PM_DEBUG_STATISTIC_NOTIFIC = 0x7B,
123
124
125 REPLY_SCAN_CMD = 0x80,
126 REPLY_SCAN_ABORT_CMD = 0x81,
127 SCAN_START_NOTIFICATION = 0x82,
128 SCAN_RESULTS_NOTIFICATION = 0x83,
129 SCAN_COMPLETE_NOTIFICATION = 0x84,
130
131
132 BEACON_NOTIFICATION = 0x90,
133 REPLY_TX_BEACON = 0x91,
134 WHO_IS_AWAKE_NOTIFICATION = 0x94,
135
136
137 REPLY_TX_POWER_DBM_CMD = 0x95,
138 QUIET_NOTIFICATION = 0x96,
139 REPLY_TX_PWR_TABLE_CMD = 0x97,
140 REPLY_TX_POWER_DBM_CMD_V1 = 0x98,
141 TX_ANT_CONFIGURATION_CMD = 0x98,
142 MEASURE_ABORT_NOTIFICATION = 0x99,
143
144
145 REPLY_BT_CONFIG = 0x9b,
146
147
148 REPLY_STATISTICS_CMD = 0x9c,
149 STATISTICS_NOTIFICATION = 0x9d,
150
151
152 REPLY_CARD_STATE_CMD = 0xa0,
153 CARD_STATE_NOTIFICATION = 0xa1,
154
155
156 MISSED_BEACONS_NOTIFICATION = 0xa2,
157
158 REPLY_CT_KILL_CONFIG_CMD = 0xa4,
159 SENSITIVITY_CMD = 0xa8,
160 REPLY_PHY_CALIBRATION_CMD = 0xb0,
161 REPLY_RX_PHY_CMD = 0xc0,
162 REPLY_RX_MPDU_CMD = 0xc1,
163 REPLY_RX = 0xc3,
164 REPLY_COMPRESSED_BA = 0xc5,
165
166
167 REPLY_BT_COEX_PRIO_TABLE = 0xcc,
168 REPLY_BT_COEX_PROT_ENV = 0xcd,
169 REPLY_BT_COEX_PROFILE_NOTIF = 0xce,
170
171
172 REPLY_WIPAN_PARAMS = 0xb2,
173 REPLY_WIPAN_RXON = 0xb3,
174 REPLY_WIPAN_RXON_TIMING = 0xb4,
175 REPLY_WIPAN_RXON_ASSOC = 0xb6,
176 REPLY_WIPAN_QOS_PARAM = 0xb7,
177 REPLY_WIPAN_WEPKEY = 0xb8,
178 REPLY_WIPAN_P2P_CHANNEL_SWITCH = 0xb9,
179 REPLY_WIPAN_NOA_NOTIFICATION = 0xbc,
180 REPLY_WIPAN_DEACTIVATION_COMPLETE = 0xbd,
181
182 REPLY_WOWLAN_PATTERNS = 0xe0,
183 REPLY_WOWLAN_WAKEUP_FILTER = 0xe1,
184 REPLY_WOWLAN_TSC_RSC_PARAMS = 0xe2,
185 REPLY_WOWLAN_TKIP_PARAMS = 0xe3,
186 REPLY_WOWLAN_KEK_KCK_MATERIAL = 0xe4,
187 REPLY_WOWLAN_GET_STATUS = 0xe5,
188 REPLY_D3_CONFIG = 0xd3,
189
190 REPLY_MAX = 0xff
191};
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200
201
202#define IWL_MIN_NUM_QUEUES 11
203
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206
207#define IWL_DEFAULT_CMD_QUEUE_NUM 4
208#define IWL_IPAN_CMD_QUEUE_NUM 9
209
210#define IWL_TX_FIFO_BK 0
211#define IWL_TX_FIFO_BE 1
212#define IWL_TX_FIFO_VI 2
213#define IWL_TX_FIFO_VO 3
214#define IWL_TX_FIFO_BK_IPAN IWL_TX_FIFO_BK
215#define IWL_TX_FIFO_BE_IPAN 4
216#define IWL_TX_FIFO_VI_IPAN IWL_TX_FIFO_VI
217#define IWL_TX_FIFO_VO_IPAN 5
218
219#define IWL_TX_FIFO_AUX 5
220#define IWL_TX_FIFO_UNUSED 255
221
222#define IWLAGN_CMD_FIFO_NUM 7
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228
229#define IWL_IPAN_MCAST_QUEUE 8
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279#define RATE_MCS_CODE_MSK 0x7
280#define RATE_MCS_SPATIAL_POS 3
281#define RATE_MCS_SPATIAL_MSK 0x18
282#define RATE_MCS_HT_DUP_POS 5
283#define RATE_MCS_HT_DUP_MSK 0x20
284
285#define RATE_MCS_RATE_MSK 0xff
286
287
288#define RATE_MCS_FLAGS_POS 8
289#define RATE_MCS_HT_POS 8
290#define RATE_MCS_HT_MSK 0x100
291
292
293#define RATE_MCS_CCK_POS 9
294#define RATE_MCS_CCK_MSK 0x200
295
296
297#define RATE_MCS_GF_POS 10
298#define RATE_MCS_GF_MSK 0x400
299
300
301#define RATE_MCS_HT40_POS 11
302#define RATE_MCS_HT40_MSK 0x800
303
304
305#define RATE_MCS_DUP_POS 12
306#define RATE_MCS_DUP_MSK 0x1000
307
308
309#define RATE_MCS_SGI_POS 13
310#define RATE_MCS_SGI_MSK 0x2000
311
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315
316#define RATE_MCS_ANT_POS 14
317#define RATE_MCS_ANT_A_MSK 0x04000
318#define RATE_MCS_ANT_B_MSK 0x08000
319#define RATE_MCS_ANT_C_MSK 0x10000
320#define RATE_MCS_ANT_AB_MSK (RATE_MCS_ANT_A_MSK | RATE_MCS_ANT_B_MSK)
321#define RATE_MCS_ANT_ABC_MSK (RATE_MCS_ANT_AB_MSK | RATE_MCS_ANT_C_MSK)
322#define RATE_ANT_NUM 3
323
324#define POWER_TABLE_NUM_ENTRIES 33
325#define POWER_TABLE_NUM_HT_OFDM_ENTRIES 32
326#define POWER_TABLE_CCK_ENTRY 32
327
328#define IWL_PWR_NUM_HT_OFDM_ENTRIES 24
329#define IWL_PWR_CCK_ENTRIES 2
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337
338struct tx_power_dual_stream {
339 __le32 dw;
340} __packed;
341
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345
346#define IWLAGN_TX_POWER_AUTO 0x7f
347#define IWLAGN_TX_POWER_NO_CLOSED (0x1 << 6)
348
349struct iwlagn_tx_power_dbm_cmd {
350 s8 global_lmt;
351 u8 flags;
352 s8 srv_chan_lmt;
353 u8 reserved;
354} __packed;
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362struct iwl_tx_ant_config_cmd {
363 __le32 valid;
364} __packed;
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371
372#define UCODE_VALID_OK cpu_to_le32(0x1)
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420struct iwl_error_event_table {
421 u32 valid;
422 u32 error_id;
423 u32 pc;
424 u32 blink1;
425 u32 blink2;
426 u32 ilink1;
427 u32 ilink2;
428 u32 data1;
429 u32 data2;
430 u32 line;
431 u32 bcon_time;
432 u32 tsf_low;
433 u32 tsf_hi;
434 u32 gp1;
435 u32 gp2;
436 u32 gp3;
437 u32 ucode_ver;
438 u32 hw_ver;
439 u32 brd_ver;
440 u32 log_pc;
441 u32 frame_ptr;
442 u32 stack_ptr;
443 u32 hcmd;
444 u32 isr0;
445
446 u32 isr1;
447
448 u32 isr2;
449
450 u32 isr3;
451
452 u32 isr4;
453
454 u32 isr_pref;
455 u32 wait_event;
456 u32 l2p_control;
457 u32 l2p_duration;
458 u32 l2p_mhvalid;
459 u32 l2p_addr_match;
460 u32 lmpm_pmg_sel;
461
462 u32 u_timestamp;
463
464 u32 flow_handler;
465} __packed;
466
467struct iwl_alive_resp {
468 u8 ucode_minor;
469 u8 ucode_major;
470 __le16 reserved1;
471 u8 sw_rev[8];
472 u8 ver_type;
473 u8 ver_subtype;
474 __le16 reserved2;
475 __le32 log_event_table_ptr;
476 __le32 error_event_table_ptr;
477 __le32 timestamp;
478 __le32 is_valid;
479} __packed;
480
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483
484struct iwl_error_resp {
485 __le32 error_type;
486 u8 cmd_id;
487 u8 reserved1;
488 __le16 bad_cmd_seq_num;
489 __le32 error_info;
490 __le64 timestamp;
491} __packed;
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502
503enum {
504 RXON_DEV_TYPE_AP = 1,
505 RXON_DEV_TYPE_ESS = 3,
506 RXON_DEV_TYPE_IBSS = 4,
507 RXON_DEV_TYPE_SNIFFER = 6,
508 RXON_DEV_TYPE_CP = 7,
509 RXON_DEV_TYPE_2STA = 8,
510 RXON_DEV_TYPE_P2P = 9,
511};
512
513
514#define RXON_RX_CHAIN_DRIVER_FORCE_MSK cpu_to_le16(0x1 << 0)
515#define RXON_RX_CHAIN_DRIVER_FORCE_POS (0)
516#define RXON_RX_CHAIN_VALID_MSK cpu_to_le16(0x7 << 1)
517#define RXON_RX_CHAIN_VALID_POS (1)
518#define RXON_RX_CHAIN_FORCE_SEL_MSK cpu_to_le16(0x7 << 4)
519#define RXON_RX_CHAIN_FORCE_SEL_POS (4)
520#define RXON_RX_CHAIN_FORCE_MIMO_SEL_MSK cpu_to_le16(0x7 << 7)
521#define RXON_RX_CHAIN_FORCE_MIMO_SEL_POS (7)
522#define RXON_RX_CHAIN_CNT_MSK cpu_to_le16(0x3 << 10)
523#define RXON_RX_CHAIN_CNT_POS (10)
524#define RXON_RX_CHAIN_MIMO_CNT_MSK cpu_to_le16(0x3 << 12)
525#define RXON_RX_CHAIN_MIMO_CNT_POS (12)
526#define RXON_RX_CHAIN_MIMO_FORCE_MSK cpu_to_le16(0x1 << 14)
527#define RXON_RX_CHAIN_MIMO_FORCE_POS (14)
528
529
530
531#define RXON_FLG_BAND_24G_MSK cpu_to_le32(1 << 0)
532#define RXON_FLG_CCK_MSK cpu_to_le32(1 << 1)
533
534#define RXON_FLG_AUTO_DETECT_MSK cpu_to_le32(1 << 2)
535
536#define RXON_FLG_TGG_PROTECT_MSK cpu_to_le32(1 << 3)
537
538#define RXON_FLG_SHORT_SLOT_MSK cpu_to_le32(1 << 4)
539#define RXON_FLG_SHORT_PREAMBLE_MSK cpu_to_le32(1 << 5)
540
541#define RXON_FLG_DIS_DIV_MSK cpu_to_le32(1 << 7)
542#define RXON_FLG_ANT_SEL_MSK cpu_to_le32(0x0f00)
543#define RXON_FLG_ANT_A_MSK cpu_to_le32(1 << 8)
544#define RXON_FLG_ANT_B_MSK cpu_to_le32(1 << 9)
545
546#define RXON_FLG_RADAR_DETECT_MSK cpu_to_le32(1 << 12)
547#define RXON_FLG_TGJ_NARROW_BAND_MSK cpu_to_le32(1 << 13)
548
549
550#define RXON_FLG_TSF2HOST_MSK cpu_to_le32(1 << 15)
551
552
553
554#define RXON_FLG_CTRL_CHANNEL_LOC_POS (22)
555#define RXON_FLG_CTRL_CHANNEL_LOC_HI_MSK cpu_to_le32(0x1 << 22)
556
557#define RXON_FLG_HT_OPERATING_MODE_POS (23)
558
559#define RXON_FLG_HT_PROT_MSK cpu_to_le32(0x1 << 23)
560#define RXON_FLG_HT40_PROT_MSK cpu_to_le32(0x2 << 23)
561
562#define RXON_FLG_CHANNEL_MODE_POS (25)
563#define RXON_FLG_CHANNEL_MODE_MSK cpu_to_le32(0x3 << 25)
564
565
566enum {
567 CHANNEL_MODE_LEGACY = 0,
568 CHANNEL_MODE_PURE_40 = 1,
569 CHANNEL_MODE_MIXED = 2,
570 CHANNEL_MODE_RESERVED = 3,
571};
572#define RXON_FLG_CHANNEL_MODE_LEGACY cpu_to_le32(CHANNEL_MODE_LEGACY << RXON_FLG_CHANNEL_MODE_POS)
573#define RXON_FLG_CHANNEL_MODE_PURE_40 cpu_to_le32(CHANNEL_MODE_PURE_40 << RXON_FLG_CHANNEL_MODE_POS)
574#define RXON_FLG_CHANNEL_MODE_MIXED cpu_to_le32(CHANNEL_MODE_MIXED << RXON_FLG_CHANNEL_MODE_POS)
575
576
577#define RXON_FLG_SELF_CTS_EN cpu_to_le32(0x1<<30)
578
579
580
581#define RXON_FILTER_PROMISC_MSK cpu_to_le32(1 << 0)
582
583#define RXON_FILTER_CTL2HOST_MSK cpu_to_le32(1 << 1)
584
585#define RXON_FILTER_ACCEPT_GRP_MSK cpu_to_le32(1 << 2)
586
587#define RXON_FILTER_DIS_DECRYPT_MSK cpu_to_le32(1 << 3)
588
589#define RXON_FILTER_DIS_GRP_DECRYPT_MSK cpu_to_le32(1 << 4)
590
591#define RXON_FILTER_ASSOC_MSK cpu_to_le32(1 << 5)
592
593#define RXON_FILTER_BCON_AWARE_MSK cpu_to_le32(1 << 6)
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613struct iwl_rxon_cmd {
614 u8 node_addr[6];
615 __le16 reserved1;
616 u8 bssid_addr[6];
617 __le16 reserved2;
618 u8 wlap_bssid_addr[6];
619 __le16 reserved3;
620 u8 dev_type;
621 u8 air_propagation;
622 __le16 rx_chain;
623 u8 ofdm_basic_rates;
624 u8 cck_basic_rates;
625 __le16 assoc_id;
626 __le32 flags;
627 __le32 filter_flags;
628 __le16 channel;
629 u8 ofdm_ht_single_stream_basic_rates;
630 u8 ofdm_ht_dual_stream_basic_rates;
631 u8 ofdm_ht_triple_stream_basic_rates;
632 u8 reserved5;
633 __le16 acquisition_data;
634 __le16 reserved6;
635} __packed;
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638
639
640struct iwl_rxon_assoc_cmd {
641 __le32 flags;
642 __le32 filter_flags;
643 u8 ofdm_basic_rates;
644 u8 cck_basic_rates;
645 __le16 reserved1;
646 u8 ofdm_ht_single_stream_basic_rates;
647 u8 ofdm_ht_dual_stream_basic_rates;
648 u8 ofdm_ht_triple_stream_basic_rates;
649 u8 reserved2;
650 __le16 rx_chain_select_flags;
651 __le16 acquisition_data;
652 __le32 reserved3;
653} __packed;
654
655#define IWL_CONN_MAX_LISTEN_INTERVAL 10
656#define IWL_MAX_UCODE_BEACON_INTERVAL 4
657
658
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660
661struct iwl_rxon_time_cmd {
662 __le64 timestamp;
663 __le16 beacon_interval;
664 __le16 atim_window;
665 __le32 beacon_init_val;
666 __le16 listen_interval;
667 u8 dtim_period;
668 u8 delta_cp_bss_tbtts;
669} __packed;
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685struct iwl5000_channel_switch_cmd {
686 u8 band;
687 u8 expect_beacon;
688 __le16 channel;
689 __le32 rxon_flags;
690 __le32 rxon_filter_flags;
691 __le32 switch_time;
692 __le32 reserved[2][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
693} __packed;
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706struct iwl6000_channel_switch_cmd {
707 u8 band;
708 u8 expect_beacon;
709 __le16 channel;
710 __le32 rxon_flags;
711 __le32 rxon_filter_flags;
712 __le32 switch_time;
713 __le32 reserved[3][IWL_PWR_NUM_HT_OFDM_ENTRIES + IWL_PWR_CCK_ENTRIES];
714} __packed;
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719struct iwl_csa_notification {
720 __le16 band;
721 __le16 channel;
722 __le32 status;
723} __packed;
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747struct iwl_ac_qos {
748 __le16 cw_min;
749 __le16 cw_max;
750 u8 aifsn;
751 u8 reserved1;
752 __le16 edca_txop;
753} __packed;
754
755
756#define QOS_PARAM_FLG_UPDATE_EDCA_MSK cpu_to_le32(0x01)
757#define QOS_PARAM_FLG_TGN_MSK cpu_to_le32(0x02)
758#define QOS_PARAM_FLG_TXOP_TYPE_MSK cpu_to_le32(0x10)
759
760
761#define AC_NUM 4
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769struct iwl_qosparam_cmd {
770 __le32 qos_flags;
771 struct iwl_ac_qos ac[AC_NUM];
772} __packed;
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784#define IWL_AP_ID 0
785#define IWL_AP_ID_PAN 1
786#define IWL_STA_ID 2
787#define IWLAGN_PAN_BCAST_ID 14
788#define IWLAGN_BROADCAST_ID 15
789#define IWLAGN_STATION_COUNT 16
790
791#define IWL_TID_NON_QOS IWL_MAX_TID_COUNT
792
793#define STA_FLG_TX_RATE_MSK cpu_to_le32(1 << 2)
794#define STA_FLG_PWR_SAVE_MSK cpu_to_le32(1 << 8)
795#define STA_FLG_PAN_STATION cpu_to_le32(1 << 13)
796#define STA_FLG_RTS_MIMO_PROT_MSK cpu_to_le32(1 << 17)
797#define STA_FLG_AGG_MPDU_8US_MSK cpu_to_le32(1 << 18)
798#define STA_FLG_MAX_AGG_SIZE_POS (19)
799#define STA_FLG_MAX_AGG_SIZE_MSK cpu_to_le32(3 << 19)
800#define STA_FLG_HT40_EN_MSK cpu_to_le32(1 << 21)
801#define STA_FLG_MIMO_DIS_MSK cpu_to_le32(1 << 22)
802#define STA_FLG_AGG_MPDU_DENSITY_POS (23)
803#define STA_FLG_AGG_MPDU_DENSITY_MSK cpu_to_le32(7 << 23)
804
805
806#define STA_CONTROL_MODIFY_MSK 0x01
807
808
809#define STA_KEY_FLG_ENCRYPT_MSK cpu_to_le16(0x0007)
810#define STA_KEY_FLG_NO_ENC cpu_to_le16(0x0000)
811#define STA_KEY_FLG_WEP cpu_to_le16(0x0001)
812#define STA_KEY_FLG_CCMP cpu_to_le16(0x0002)
813#define STA_KEY_FLG_TKIP cpu_to_le16(0x0003)
814
815#define STA_KEY_FLG_KEYID_POS 8
816#define STA_KEY_FLG_INVALID cpu_to_le16(0x0800)
817
818#define STA_KEY_FLG_MAP_KEY_MSK cpu_to_le16(0x0008)
819
820
821#define STA_KEY_FLG_KEY_SIZE_MSK cpu_to_le16(0x1000)
822#define STA_KEY_MULTICAST_MSK cpu_to_le16(0x4000)
823#define STA_KEY_MAX_NUM 8
824#define STA_KEY_MAX_NUM_PAN 16
825
826#define IWLAGN_HW_KEY_DEFAULT 0xfe
827
828
829#define STA_MODIFY_KEY_MASK 0x01
830#define STA_MODIFY_TID_DISABLE_TX 0x02
831#define STA_MODIFY_TX_RATE_MSK 0x04
832#define STA_MODIFY_ADDBA_TID_MSK 0x08
833#define STA_MODIFY_DELBA_TID_MSK 0x10
834#define STA_MODIFY_SLEEP_TX_COUNT_MSK 0x20
835
836
837struct iwl_keyinfo {
838 __le16 key_flags;
839 u8 tkip_rx_tsc_byte2;
840 u8 reserved1;
841 __le16 tkip_rx_ttak[5];
842 u8 key_offset;
843 u8 reserved2;
844 u8 key[16];
845 __le64 tx_secur_seq_cnt;
846 __le64 hw_tkip_mic_rx_key;
847 __le64 hw_tkip_mic_tx_key;
848} __packed;
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862struct sta_id_modify {
863 u8 addr[ETH_ALEN];
864 __le16 reserved1;
865 u8 sta_id;
866 u8 modify_mask;
867 __le16 reserved2;
868} __packed;
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872
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880
881
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890
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893
894
895
896struct iwl_addsta_cmd {
897 u8 mode;
898 u8 reserved[3];
899 struct sta_id_modify sta;
900 struct iwl_keyinfo key;
901 __le32 station_flags;
902 __le32 station_flags_msk;
903
904
905
906
907 __le16 tid_disable_tx;
908 __le16 legacy_reserved;
909
910
911
912 u8 add_immediate_ba_tid;
913
914
915
916 u8 remove_immediate_ba_tid;
917
918
919
920 __le16 add_immediate_ba_ssn;
921
922
923
924
925
926
927 __le16 sleep_tx_count;
928
929 __le16 reserved2;
930} __packed;
931
932
933#define ADD_STA_SUCCESS_MSK 0x1
934#define ADD_STA_NO_ROOM_IN_TABLE 0x2
935#define ADD_STA_NO_BLOCK_ACK_RESOURCE 0x4
936#define ADD_STA_MODIFY_NON_EXIST_STA 0x8
937
938
939
940struct iwl_add_sta_resp {
941 u8 status;
942} __packed;
943
944#define REM_STA_SUCCESS_MSK 0x1
945
946
947
948struct iwl_rem_sta_resp {
949 u8 status;
950} __packed;
951
952
953
954
955struct iwl_rem_sta_cmd {
956 u8 num_sta;
957 u8 reserved[3];
958 u8 addr[ETH_ALEN];
959 u8 reserved2[2];
960} __packed;
961
962
963
964#define IWL_SCD_BK_MSK BIT(0)
965#define IWL_SCD_BE_MSK BIT(1)
966#define IWL_SCD_VI_MSK BIT(2)
967#define IWL_SCD_VO_MSK BIT(3)
968#define IWL_SCD_MGMT_MSK BIT(3)
969
970
971#define IWL_PAN_SCD_BK_MSK BIT(4)
972#define IWL_PAN_SCD_BE_MSK BIT(5)
973#define IWL_PAN_SCD_VI_MSK BIT(6)
974#define IWL_PAN_SCD_VO_MSK BIT(7)
975#define IWL_PAN_SCD_MGMT_MSK BIT(7)
976#define IWL_PAN_SCD_MULTICAST_MSK BIT(8)
977
978#define IWL_AGG_TX_QUEUE_MSK 0xffc00
979
980#define IWL_DROP_ALL BIT(1)
981
982
983
984
985
986
987
988
989
990
991
992
993
994
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1000
1001
1002
1003struct iwl_txfifo_flush_cmd_v3 {
1004 __le32 queue_control;
1005 __le16 flush_control;
1006 __le16 reserved;
1007} __packed;
1008
1009struct iwl_txfifo_flush_cmd_v2 {
1010 __le16 queue_control;
1011 __le16 flush_control;
1012} __packed;
1013
1014
1015
1016
1017struct iwl_wep_key {
1018 u8 key_index;
1019 u8 key_offset;
1020 u8 reserved1[2];
1021 u8 key_size;
1022 u8 reserved2[3];
1023 u8 key[16];
1024} __packed;
1025
1026struct iwl_wep_cmd {
1027 u8 num_keys;
1028 u8 global_key_type;
1029 u8 flags;
1030 u8 reserved;
1031 struct iwl_wep_key key[0];
1032} __packed;
1033
1034#define WEP_KEY_WEP_TYPE 1
1035#define WEP_KEYS_MAX 4
1036#define WEP_INVALID_OFFSET 0xff
1037#define WEP_KEY_LEN_64 5
1038#define WEP_KEY_LEN_128 13
1039
1040
1041
1042
1043
1044
1045
1046#define RX_RES_STATUS_NO_CRC32_ERROR cpu_to_le32(1 << 0)
1047#define RX_RES_STATUS_NO_RXE_OVERFLOW cpu_to_le32(1 << 1)
1048
1049#define RX_RES_PHY_FLAGS_BAND_24_MSK cpu_to_le16(1 << 0)
1050#define RX_RES_PHY_FLAGS_MOD_CCK_MSK cpu_to_le16(1 << 1)
1051#define RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK cpu_to_le16(1 << 2)
1052#define RX_RES_PHY_FLAGS_NARROW_BAND_MSK cpu_to_le16(1 << 3)
1053#define RX_RES_PHY_FLAGS_ANTENNA_MSK 0x70
1054#define RX_RES_PHY_FLAGS_ANTENNA_POS 4
1055#define RX_RES_PHY_FLAGS_AGG_MSK cpu_to_le16(1 << 7)
1056
1057#define RX_RES_STATUS_SEC_TYPE_MSK (0x7 << 8)
1058#define RX_RES_STATUS_SEC_TYPE_NONE (0x0 << 8)
1059#define RX_RES_STATUS_SEC_TYPE_WEP (0x1 << 8)
1060#define RX_RES_STATUS_SEC_TYPE_CCMP (0x2 << 8)
1061#define RX_RES_STATUS_SEC_TYPE_TKIP (0x3 << 8)
1062#define RX_RES_STATUS_SEC_TYPE_ERR (0x7 << 8)
1063
1064#define RX_RES_STATUS_STATION_FOUND (1<<6)
1065#define RX_RES_STATUS_NO_STATION_INFO_MISMATCH (1<<7)
1066
1067#define RX_RES_STATUS_DECRYPT_TYPE_MSK (0x3 << 11)
1068#define RX_RES_STATUS_NOT_DECRYPT (0x0 << 11)
1069#define RX_RES_STATUS_DECRYPT_OK (0x3 << 11)
1070#define RX_RES_STATUS_BAD_ICV_MIC (0x1 << 11)
1071#define RX_RES_STATUS_BAD_KEY_TTAK (0x2 << 11)
1072
1073#define RX_MPDU_RES_STATUS_ICV_OK (0x20)
1074#define RX_MPDU_RES_STATUS_MIC_OK (0x40)
1075#define RX_MPDU_RES_STATUS_TTAK_OK (1 << 7)
1076#define RX_MPDU_RES_STATUS_DEC_DONE_MSK (0x800)
1077
1078
1079#define IWLAGN_RX_RES_PHY_CNT 8
1080#define IWLAGN_RX_RES_AGC_IDX 1
1081#define IWLAGN_RX_RES_RSSI_AB_IDX 2
1082#define IWLAGN_RX_RES_RSSI_C_IDX 3
1083#define IWLAGN_OFDM_AGC_MSK 0xfe00
1084#define IWLAGN_OFDM_AGC_BIT_POS 9
1085#define IWLAGN_OFDM_RSSI_INBAND_A_BITMSK 0x00ff
1086#define IWLAGN_OFDM_RSSI_ALLBAND_A_BITMSK 0xff00
1087#define IWLAGN_OFDM_RSSI_A_BIT_POS 0
1088#define IWLAGN_OFDM_RSSI_INBAND_B_BITMSK 0xff0000
1089#define IWLAGN_OFDM_RSSI_ALLBAND_B_BITMSK 0xff000000
1090#define IWLAGN_OFDM_RSSI_B_BIT_POS 16
1091#define IWLAGN_OFDM_RSSI_INBAND_C_BITMSK 0x00ff
1092#define IWLAGN_OFDM_RSSI_ALLBAND_C_BITMSK 0xff00
1093#define IWLAGN_OFDM_RSSI_C_BIT_POS 0
1094
1095struct iwlagn_non_cfg_phy {
1096 __le32 non_cfg_phy[IWLAGN_RX_RES_PHY_CNT];
1097} __packed;
1098
1099
1100
1101
1102
1103
1104struct iwl_rx_phy_res {
1105 u8 non_cfg_phy_cnt;
1106 u8 cfg_phy_cnt;
1107 u8 stat_id;
1108 u8 reserved1;
1109 __le64 timestamp;
1110 __le32 beacon_time_stamp;
1111 __le16 phy_flags;
1112 __le16 channel;
1113 u8 non_cfg_phy_buf[32];
1114 __le32 rate_n_flags;
1115 __le16 byte_count;
1116 __le16 frame_time;
1117} __packed;
1118
1119struct iwl_rx_mpdu_res_start {
1120 __le16 byte_count;
1121 __le16 reserved;
1122} __packed;
1123
1124
1125
1126
1127
1128
1129
1130
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1154
1155
1156#define TX_CMD_FLG_PROT_REQUIRE_MSK cpu_to_le32(1 << 0)
1157
1158
1159
1160
1161#define TX_CMD_FLG_ACK_MSK cpu_to_le32(1 << 3)
1162
1163
1164
1165
1166
1167
1168
1169#define TX_CMD_FLG_STA_RATE_MSK cpu_to_le32(1 << 4)
1170
1171
1172
1173#define TX_CMD_FLG_IMM_BA_RSP_MASK cpu_to_le32(1 << 6)
1174
1175
1176#define TX_CMD_FLG_ANT_SEL_MSK cpu_to_le32(0xf00)
1177
1178
1179
1180#define TX_CMD_FLG_IGNORE_BT cpu_to_le32(1 << 12)
1181
1182
1183
1184
1185
1186#define TX_CMD_FLG_SEQ_CTL_MSK cpu_to_le32(1 << 13)
1187
1188
1189
1190#define TX_CMD_FLG_MORE_FRAG_MSK cpu_to_le32(1 << 14)
1191
1192
1193
1194
1195#define TX_CMD_FLG_TSF_MSK cpu_to_le32(1 << 16)
1196
1197
1198
1199
1200
1201
1202
1203#define TX_CMD_FLG_MH_PAD_MSK cpu_to_le32(1 << 20)
1204
1205
1206
1207#define TX_CMD_FLG_AGG_CCMP_MSK cpu_to_le32(1 << 22)
1208
1209
1210#define TX_CMD_FLG_DUR_MSK cpu_to_le32(1 << 25)
1211
1212
1213
1214
1215
1216#define TX_CMD_SEC_WEP 0x01
1217#define TX_CMD_SEC_CCM 0x02
1218#define TX_CMD_SEC_TKIP 0x03
1219#define TX_CMD_SEC_MSK 0x03
1220#define TX_CMD_SEC_SHIFT 6
1221#define TX_CMD_SEC_KEY128 0x08
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231struct iwl_dram_scratch {
1232 u8 try_cnt;
1233 u8 bt_kill_cnt;
1234 __le16 reserved;
1235} __packed;
1236
1237struct iwl_tx_cmd {
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248 __le16 len;
1249
1250
1251
1252
1253
1254
1255 __le16 next_frame_len;
1256
1257 __le32 tx_flags;
1258
1259
1260
1261 struct iwl_dram_scratch scratch;
1262
1263
1264 __le32 rate_n_flags;
1265
1266
1267 u8 sta_id;
1268
1269
1270 u8 sec_ctl;
1271
1272
1273
1274
1275
1276
1277
1278
1279 u8 initial_rate_index;
1280 u8 reserved;
1281 u8 key[16];
1282 __le16 next_frame_flags;
1283 __le16 reserved2;
1284 union {
1285 __le32 life_time;
1286 __le32 attempt;
1287 } stop_time;
1288
1289
1290
1291 __le32 dram_lsb_ptr;
1292 u8 dram_msb_ptr;
1293
1294 u8 rts_retry_limit;
1295 u8 data_retry_limit;
1296 u8 tid_tspec;
1297 union {
1298 __le16 pm_frame_timeout;
1299 __le16 attempt_duration;
1300 } timeout;
1301
1302
1303
1304
1305
1306 __le16 driver_txop;
1307
1308
1309
1310
1311
1312 u8 payload[0];
1313 struct ieee80211_hdr hdr[0];
1314} __packed;
1315
1316
1317
1318
1319
1320
1321
1322
1323enum {
1324 TX_STATUS_SUCCESS = 0x01,
1325 TX_STATUS_DIRECT_DONE = 0x02,
1326
1327 TX_STATUS_POSTPONE_DELAY = 0x40,
1328 TX_STATUS_POSTPONE_FEW_BYTES = 0x41,
1329 TX_STATUS_POSTPONE_BT_PRIO = 0x42,
1330 TX_STATUS_POSTPONE_QUIET_PERIOD = 0x43,
1331 TX_STATUS_POSTPONE_CALC_TTAK = 0x44,
1332
1333 TX_STATUS_FAIL_INTERNAL_CROSSED_RETRY = 0x81,
1334 TX_STATUS_FAIL_SHORT_LIMIT = 0x82,
1335 TX_STATUS_FAIL_LONG_LIMIT = 0x83,
1336 TX_STATUS_FAIL_FIFO_UNDERRUN = 0x84,
1337 TX_STATUS_FAIL_DRAIN_FLOW = 0x85,
1338 TX_STATUS_FAIL_RFKILL_FLUSH = 0x86,
1339 TX_STATUS_FAIL_LIFE_EXPIRE = 0x87,
1340 TX_STATUS_FAIL_DEST_PS = 0x88,
1341 TX_STATUS_FAIL_HOST_ABORTED = 0x89,
1342 TX_STATUS_FAIL_BT_RETRY = 0x8a,
1343 TX_STATUS_FAIL_STA_INVALID = 0x8b,
1344 TX_STATUS_FAIL_FRAG_DROPPED = 0x8c,
1345 TX_STATUS_FAIL_TID_DISABLE = 0x8d,
1346 TX_STATUS_FAIL_FIFO_FLUSHED = 0x8e,
1347 TX_STATUS_FAIL_INSUFFICIENT_CF_POLL = 0x8f,
1348 TX_STATUS_FAIL_PASSIVE_NO_RX = 0x90,
1349 TX_STATUS_FAIL_NO_BEACON_ON_RADAR = 0x91,
1350};
1351
1352#define TX_PACKET_MODE_REGULAR 0x0000
1353#define TX_PACKET_MODE_BURST_SEQ 0x0100
1354#define TX_PACKET_MODE_BURST_FIRST 0x0200
1355
1356enum {
1357 TX_POWER_PA_NOT_ACTIVE = 0x0,
1358};
1359
1360enum {
1361 TX_STATUS_MSK = 0x000000ff,
1362 TX_STATUS_DELAY_MSK = 0x00000040,
1363 TX_STATUS_ABORT_MSK = 0x00000080,
1364 TX_PACKET_MODE_MSK = 0x0000ff00,
1365 TX_FIFO_NUMBER_MSK = 0x00070000,
1366 TX_RESERVED = 0x00780000,
1367 TX_POWER_PA_DETECT_MSK = 0x7f800000,
1368 TX_ABORT_REQUIRED_MSK = 0x80000000,
1369};
1370
1371
1372
1373
1374
1375enum {
1376 AGG_TX_STATE_TRANSMITTED = 0x00,
1377 AGG_TX_STATE_UNDERRUN_MSK = 0x01,
1378 AGG_TX_STATE_BT_PRIO_MSK = 0x02,
1379 AGG_TX_STATE_FEW_BYTES_MSK = 0x04,
1380 AGG_TX_STATE_ABORT_MSK = 0x08,
1381 AGG_TX_STATE_LAST_SENT_TTL_MSK = 0x10,
1382 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK = 0x20,
1383 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK = 0x40,
1384 AGG_TX_STATE_SCD_QUERY_MSK = 0x80,
1385 AGG_TX_STATE_TEST_BAD_CRC32_MSK = 0x100,
1386 AGG_TX_STATE_RESPONSE_MSK = 0x1ff,
1387 AGG_TX_STATE_DUMP_TX_MSK = 0x200,
1388 AGG_TX_STATE_DELAY_TX_MSK = 0x400
1389};
1390
1391#define AGG_TX_STATUS_MSK 0x00000fff
1392#define AGG_TX_TRY_MSK 0x0000f000
1393#define AGG_TX_TRY_POS 12
1394
1395#define AGG_TX_STATE_LAST_SENT_MSK (AGG_TX_STATE_LAST_SENT_TTL_MSK | \
1396 AGG_TX_STATE_LAST_SENT_TRY_CNT_MSK | \
1397 AGG_TX_STATE_LAST_SENT_BT_KILL_MSK)
1398
1399
1400#define AGG_TX_STATE_TRY_CNT_POS 12
1401#define AGG_TX_STATE_TRY_CNT_MSK 0xf000
1402
1403
1404#define AGG_TX_STATE_SEQ_NUM_POS 16
1405#define AGG_TX_STATE_SEQ_NUM_MSK 0xffff0000
1406
1407
1408
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1410
1411
1412
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1425
1426
1427
1428
1429struct agg_tx_status {
1430 __le16 status;
1431 __le16 sequence;
1432} __packed;
1433
1434
1435#define IWLAGN_TX_RES_TID_POS 0
1436#define IWLAGN_TX_RES_TID_MSK 0x0f
1437#define IWLAGN_TX_RES_RA_POS 4
1438#define IWLAGN_TX_RES_RA_MSK 0xf0
1439
1440struct iwlagn_tx_resp {
1441 u8 frame_count;
1442 u8 bt_kill_count;
1443 u8 failure_rts;
1444 u8 failure_frame;
1445
1446
1447
1448 __le32 rate_n_flags;
1449
1450
1451
1452 __le16 wireless_media_time;
1453
1454 u8 pa_status;
1455 u8 pa_integ_res_a[3];
1456 u8 pa_integ_res_b[3];
1457 u8 pa_integ_res_C[3];
1458
1459 __le32 tfd_info;
1460 __le16 seq_ctl;
1461 __le16 byte_cnt;
1462 u8 tlc_info;
1463 u8 ra_tid;
1464 __le16 frame_ctrl;
1465
1466
1467
1468
1469
1470
1471
1472
1473
1474
1475
1476
1477
1478 struct agg_tx_status status;
1479
1480} __packed;
1481
1482
1483
1484
1485
1486struct iwl_compressed_ba_resp {
1487 __le32 sta_addr_lo32;
1488 __le16 sta_addr_hi16;
1489 __le16 reserved;
1490
1491
1492 u8 sta_id;
1493 u8 tid;
1494 __le16 seq_ctl;
1495 __le64 bitmap;
1496 __le16 scd_flow;
1497 __le16 scd_ssn;
1498 u8 txed;
1499 u8 txed_2_done;
1500 __le16 reserved1;
1501} __packed;
1502
1503
1504
1505
1506
1507
1508
1509#define LINK_QUAL_FLAGS_SET_STA_TLC_RTS_MSK (1 << 0)
1510
1511
1512#define LINK_QUAL_AC_NUM AC_NUM
1513
1514
1515#define LINK_QUAL_MAX_RETRY_NUM 16
1516
1517
1518#define LINK_QUAL_ANT_A_MSK (1 << 0)
1519#define LINK_QUAL_ANT_B_MSK (1 << 1)
1520#define LINK_QUAL_ANT_MSK (LINK_QUAL_ANT_A_MSK|LINK_QUAL_ANT_B_MSK)
1521
1522
1523
1524
1525
1526
1527
1528struct iwl_link_qual_general_params {
1529 u8 flags;
1530
1531
1532 u8 mimo_delimiter;
1533
1534
1535 u8 single_stream_ant_msk;
1536
1537
1538 u8 dual_stream_ant_msk;
1539
1540
1541
1542
1543
1544
1545
1546
1547
1548
1549
1550
1551 u8 start_rate_index[LINK_QUAL_AC_NUM];
1552} __packed;
1553
1554#define LINK_QUAL_AGG_TIME_LIMIT_DEF (4000)
1555#define LINK_QUAL_AGG_TIME_LIMIT_MAX (8000)
1556#define LINK_QUAL_AGG_TIME_LIMIT_MIN (100)
1557
1558#define LINK_QUAL_AGG_DISABLE_START_DEF (3)
1559#define LINK_QUAL_AGG_DISABLE_START_MAX (255)
1560#define LINK_QUAL_AGG_DISABLE_START_MIN (0)
1561
1562#define LINK_QUAL_AGG_FRAME_LIMIT_DEF (63)
1563#define LINK_QUAL_AGG_FRAME_LIMIT_MAX (63)
1564#define LINK_QUAL_AGG_FRAME_LIMIT_MIN (0)
1565
1566
1567
1568
1569
1570
1571struct iwl_link_qual_agg_params {
1572
1573
1574
1575
1576
1577 __le16 agg_time_limit;
1578
1579
1580
1581
1582
1583
1584
1585 u8 agg_dis_start_th;
1586
1587
1588
1589
1590
1591
1592 u8 agg_frame_cnt_limit;
1593
1594 __le32 reserved;
1595} __packed;
1596
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1781
1782
1783
1784
1785struct iwl_link_quality_cmd {
1786
1787
1788 u8 sta_id;
1789 u8 reserved1;
1790 __le16 control;
1791 struct iwl_link_qual_general_params general_params;
1792 struct iwl_link_qual_agg_params agg_params;
1793
1794
1795
1796
1797
1798
1799 struct {
1800 __le32 rate_n_flags;
1801 } rs_table[LINK_QUAL_MAX_RETRY_NUM];
1802 __le32 reserved2;
1803} __packed;
1804
1805
1806
1807
1808
1809
1810
1811
1812
1813
1814#define BT_COEX_DISABLE (0x0)
1815#define BT_ENABLE_CHANNEL_ANNOUNCE BIT(0)
1816#define BT_ENABLE_PRIORITY BIT(1)
1817#define BT_ENABLE_2_WIRE BIT(2)
1818
1819#define BT_COEX_DISABLE (0x0)
1820#define BT_COEX_ENABLE (BT_ENABLE_CHANNEL_ANNOUNCE | BT_ENABLE_PRIORITY)
1821
1822#define BT_LEAD_TIME_MIN (0x0)
1823#define BT_LEAD_TIME_DEF (0x1E)
1824#define BT_LEAD_TIME_MAX (0xFF)
1825
1826#define BT_MAX_KILL_MIN (0x1)
1827#define BT_MAX_KILL_DEF (0x5)
1828#define BT_MAX_KILL_MAX (0xFF)
1829
1830#define BT_DURATION_LIMIT_DEF 625
1831#define BT_DURATION_LIMIT_MAX 1250
1832#define BT_DURATION_LIMIT_MIN 625
1833
1834#define BT_ON_THRESHOLD_DEF 4
1835#define BT_ON_THRESHOLD_MAX 1000
1836#define BT_ON_THRESHOLD_MIN 1
1837
1838#define BT_FRAG_THRESHOLD_DEF 0
1839#define BT_FRAG_THRESHOLD_MAX 0
1840#define BT_FRAG_THRESHOLD_MIN 0
1841
1842#define BT_AGG_THRESHOLD_DEF 1200
1843#define BT_AGG_THRESHOLD_MAX 8000
1844#define BT_AGG_THRESHOLD_MIN 400
1845
1846
1847
1848
1849
1850
1851
1852
1853struct iwl_bt_cmd {
1854 u8 flags;
1855 u8 lead_time;
1856 u8 max_kill;
1857 u8 reserved;
1858 __le32 kill_ack_mask;
1859 __le32 kill_cts_mask;
1860} __packed;
1861
1862#define IWLAGN_BT_FLAG_CHANNEL_INHIBITION BIT(0)
1863
1864#define IWLAGN_BT_FLAG_COEX_MODE_MASK (BIT(3)|BIT(4)|BIT(5))
1865#define IWLAGN_BT_FLAG_COEX_MODE_SHIFT 3
1866#define IWLAGN_BT_FLAG_COEX_MODE_DISABLED 0
1867#define IWLAGN_BT_FLAG_COEX_MODE_LEGACY_2W 1
1868#define IWLAGN_BT_FLAG_COEX_MODE_3W 2
1869#define IWLAGN_BT_FLAG_COEX_MODE_4W 3
1870
1871#define IWLAGN_BT_FLAG_UCODE_DEFAULT BIT(6)
1872
1873#define IWLAGN_BT_FLAG_SYNC_2_BT_DISABLE BIT(7)
1874
1875#define IWLAGN_BT_PSP_MIN_RSSI_THRESHOLD -75
1876#define IWLAGN_BT_PSP_MAX_RSSI_THRESHOLD -65
1877
1878#define IWLAGN_BT_PRIO_BOOST_MAX 0xFF
1879#define IWLAGN_BT_PRIO_BOOST_MIN 0x00
1880#define IWLAGN_BT_PRIO_BOOST_DEFAULT 0xF0
1881#define IWLAGN_BT_PRIO_BOOST_DEFAULT32 0xF0F0F0F0
1882
1883#define IWLAGN_BT_MAX_KILL_DEFAULT 5
1884
1885#define IWLAGN_BT3_T7_DEFAULT 1
1886
1887enum iwl_bt_kill_idx {
1888 IWL_BT_KILL_DEFAULT = 0,
1889 IWL_BT_KILL_OVERRIDE = 1,
1890 IWL_BT_KILL_REDUCE = 2,
1891};
1892
1893#define IWLAGN_BT_KILL_ACK_MASK_DEFAULT cpu_to_le32(0xffff0000)
1894#define IWLAGN_BT_KILL_CTS_MASK_DEFAULT cpu_to_le32(0xffff0000)
1895#define IWLAGN_BT_KILL_ACK_CTS_MASK_SCO cpu_to_le32(0xffffffff)
1896#define IWLAGN_BT_KILL_ACK_CTS_MASK_REDUCE cpu_to_le32(0)
1897
1898#define IWLAGN_BT3_PRIO_SAMPLE_DEFAULT 2
1899
1900#define IWLAGN_BT3_T2_DEFAULT 0xc
1901
1902#define IWLAGN_BT_VALID_ENABLE_FLAGS cpu_to_le16(BIT(0))
1903#define IWLAGN_BT_VALID_BOOST cpu_to_le16(BIT(1))
1904#define IWLAGN_BT_VALID_MAX_KILL cpu_to_le16(BIT(2))
1905#define IWLAGN_BT_VALID_3W_TIMERS cpu_to_le16(BIT(3))
1906#define IWLAGN_BT_VALID_KILL_ACK_MASK cpu_to_le16(BIT(4))
1907#define IWLAGN_BT_VALID_KILL_CTS_MASK cpu_to_le16(BIT(5))
1908#define IWLAGN_BT_VALID_REDUCED_TX_PWR cpu_to_le16(BIT(6))
1909#define IWLAGN_BT_VALID_3W_LUT cpu_to_le16(BIT(7))
1910
1911#define IWLAGN_BT_ALL_VALID_MSK (IWLAGN_BT_VALID_ENABLE_FLAGS | \
1912 IWLAGN_BT_VALID_BOOST | \
1913 IWLAGN_BT_VALID_MAX_KILL | \
1914 IWLAGN_BT_VALID_3W_TIMERS | \
1915 IWLAGN_BT_VALID_KILL_ACK_MASK | \
1916 IWLAGN_BT_VALID_KILL_CTS_MASK | \
1917 IWLAGN_BT_VALID_REDUCED_TX_PWR | \
1918 IWLAGN_BT_VALID_3W_LUT)
1919
1920#define IWLAGN_BT_REDUCED_TX_PWR BIT(0)
1921
1922#define IWLAGN_BT_DECISION_LUT_SIZE 12
1923
1924struct iwl_basic_bt_cmd {
1925 u8 flags;
1926 u8 ledtime;
1927 u8 max_kill;
1928 u8 bt3_timer_t7_value;
1929 __le32 kill_ack_mask;
1930 __le32 kill_cts_mask;
1931 u8 bt3_prio_sample_time;
1932 u8 bt3_timer_t2_value;
1933 __le16 bt4_reaction_time;
1934 __le32 bt3_lookup_table[IWLAGN_BT_DECISION_LUT_SIZE];
1935
1936
1937
1938
1939 u8 reduce_txpower;
1940 u8 reserved;
1941 __le16 valid;
1942};
1943
1944struct iwl_bt_cmd_v1 {
1945 struct iwl_basic_bt_cmd basic;
1946 u8 prio_boost;
1947
1948
1949
1950
1951 u8 tx_prio_boost;
1952 __le16 rx_prio_boost;
1953};
1954
1955struct iwl_bt_cmd_v2 {
1956 struct iwl_basic_bt_cmd basic;
1957 __le32 prio_boost;
1958
1959
1960
1961
1962 u8 reserved;
1963 u8 tx_prio_boost;
1964 __le16 rx_prio_boost;
1965};
1966
1967#define IWLAGN_BT_SCO_ACTIVE cpu_to_le32(BIT(0))
1968
1969struct iwlagn_bt_sco_cmd {
1970 __le32 flags;
1971};
1972
1973
1974
1975
1976
1977
1978
1979
1980
1981
1982#define MEASUREMENT_FILTER_FLAG (RXON_FILTER_PROMISC_MSK | \
1983 RXON_FILTER_CTL2HOST_MSK | \
1984 RXON_FILTER_ACCEPT_GRP_MSK | \
1985 RXON_FILTER_DIS_DECRYPT_MSK | \
1986 RXON_FILTER_DIS_GRP_DECRYPT_MSK | \
1987 RXON_FILTER_ASSOC_MSK | \
1988 RXON_FILTER_BCON_AWARE_MSK)
1989
1990struct iwl_measure_channel {
1991 __le32 duration;
1992
1993 u8 channel;
1994 u8 type;
1995 __le16 reserved;
1996} __packed;
1997
1998
1999
2000
2001struct iwl_spectrum_cmd {
2002 __le16 len;
2003 u8 token;
2004 u8 id;
2005 u8 origin;
2006 u8 periodic;
2007 __le16 path_loss_timeout;
2008 __le32 start_time;
2009 __le32 reserved2;
2010 __le32 flags;
2011 __le32 filter_flags;
2012 __le16 channel_count;
2013 __le16 reserved3;
2014 struct iwl_measure_channel channels[10];
2015} __packed;
2016
2017
2018
2019
2020struct iwl_spectrum_resp {
2021 u8 token;
2022 u8 id;
2023 __le16 status;
2024
2025
2026} __packed;
2027
2028enum iwl_measurement_state {
2029 IWL_MEASUREMENT_START = 0,
2030 IWL_MEASUREMENT_STOP = 1,
2031};
2032
2033enum iwl_measurement_status {
2034 IWL_MEASUREMENT_OK = 0,
2035 IWL_MEASUREMENT_CONCURRENT = 1,
2036 IWL_MEASUREMENT_CSA_CONFLICT = 2,
2037 IWL_MEASUREMENT_TGH_CONFLICT = 3,
2038
2039 IWL_MEASUREMENT_STOPPED = 6,
2040 IWL_MEASUREMENT_TIMEOUT = 7,
2041 IWL_MEASUREMENT_PERIODIC_FAILED = 8,
2042};
2043
2044#define NUM_ELEMENTS_IN_HISTOGRAM 8
2045
2046struct iwl_measurement_histogram {
2047 __le32 ofdm[NUM_ELEMENTS_IN_HISTOGRAM];
2048 __le32 cck[NUM_ELEMENTS_IN_HISTOGRAM];
2049} __packed;
2050
2051
2052struct iwl_measurement_cca_counters {
2053 __le32 ofdm;
2054 __le32 cck;
2055} __packed;
2056
2057enum iwl_measure_type {
2058 IWL_MEASURE_BASIC = (1 << 0),
2059 IWL_MEASURE_CHANNEL_LOAD = (1 << 1),
2060 IWL_MEASURE_HISTOGRAM_RPI = (1 << 2),
2061 IWL_MEASURE_HISTOGRAM_NOISE = (1 << 3),
2062 IWL_MEASURE_FRAME = (1 << 4),
2063
2064 IWL_MEASURE_IDLE = (1 << 7),
2065};
2066
2067
2068
2069
2070struct iwl_spectrum_notification {
2071 u8 id;
2072 u8 token;
2073 u8 channel_index;
2074 u8 state;
2075 __le32 start_time;
2076 u8 band;
2077 u8 channel;
2078 u8 type;
2079 u8 reserved1;
2080
2081
2082 __le32 cca_ofdm;
2083 __le32 cca_cck;
2084 __le32 cca_time;
2085 u8 basic_type;
2086
2087 u8 reserved2[3];
2088 struct iwl_measurement_histogram histogram;
2089 __le32 stop_time;
2090 __le32 status;
2091} __packed;
2092
2093
2094
2095
2096
2097
2098
2099
2100
2101
2102
2103
2104
2105
2106
2107
2108
2109
2110
2111
2112
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124
2125
2126
2127
2128
2129
2130
2131
2132
2133
2134#define IWL_POWER_VEC_SIZE 5
2135
2136#define IWL_POWER_DRIVER_ALLOW_SLEEP_MSK cpu_to_le16(BIT(0))
2137#define IWL_POWER_POWER_SAVE_ENA_MSK cpu_to_le16(BIT(0))
2138#define IWL_POWER_POWER_MANAGEMENT_ENA_MSK cpu_to_le16(BIT(1))
2139#define IWL_POWER_SLEEP_OVER_DTIM_MSK cpu_to_le16(BIT(2))
2140#define IWL_POWER_PCI_PM_MSK cpu_to_le16(BIT(3))
2141#define IWL_POWER_FAST_PD cpu_to_le16(BIT(4))
2142#define IWL_POWER_BEACON_FILTERING cpu_to_le16(BIT(5))
2143#define IWL_POWER_SHADOW_REG_ENA cpu_to_le16(BIT(6))
2144#define IWL_POWER_CT_KILL_SET cpu_to_le16(BIT(7))
2145#define IWL_POWER_BT_SCO_ENA cpu_to_le16(BIT(8))
2146#define IWL_POWER_ADVANCE_PM_ENA_MSK cpu_to_le16(BIT(9))
2147
2148struct iwl_powertable_cmd {
2149 __le16 flags;
2150 u8 keep_alive_seconds;
2151 u8 debug_flags;
2152 __le32 rx_data_timeout;
2153 __le32 tx_data_timeout;
2154 __le32 sleep_interval[IWL_POWER_VEC_SIZE];
2155 __le32 keep_alive_beacons;
2156} __packed;
2157
2158
2159
2160
2161
2162struct iwl_sleep_notification {
2163 u8 pm_sleep_mode;
2164 u8 pm_wakeup_src;
2165 __le16 reserved;
2166 __le32 sleep_time;
2167 __le32 tsf_low;
2168 __le32 bcon_timer;
2169} __packed;
2170
2171
2172enum {
2173 IWL_PM_NO_SLEEP = 0,
2174 IWL_PM_SLP_MAC = 1,
2175 IWL_PM_SLP_FULL_MAC_UNASSOCIATE = 2,
2176 IWL_PM_SLP_FULL_MAC_CARD_STATE = 3,
2177 IWL_PM_SLP_PHY = 4,
2178 IWL_PM_SLP_REPENT = 5,
2179 IWL_PM_WAKEUP_BY_TIMER = 6,
2180 IWL_PM_WAKEUP_BY_DRIVER = 7,
2181 IWL_PM_WAKEUP_BY_RFKILL = 8,
2182
2183 IWL_PM_NUM_OF_MODES = 12,
2184};
2185
2186
2187
2188
2189#define CARD_STATE_CMD_DISABLE 0x00
2190#define CARD_STATE_CMD_ENABLE 0x01
2191#define CARD_STATE_CMD_HALT 0x02
2192struct iwl_card_state_cmd {
2193 __le32 status;
2194} __packed;
2195
2196
2197
2198
2199struct iwl_card_state_notif {
2200 __le32 flags;
2201} __packed;
2202
2203#define HW_CARD_DISABLED 0x01
2204#define SW_CARD_DISABLED 0x02
2205#define CT_CARD_DISABLED 0x04
2206#define RXON_CARD_DISABLED 0x10
2207
2208struct iwl_ct_kill_config {
2209 __le32 reserved;
2210 __le32 critical_temperature_M;
2211 __le32 critical_temperature_R;
2212} __packed;
2213
2214
2215struct iwl_ct_kill_throttling_config {
2216 __le32 critical_temperature_exit;
2217 __le32 reserved;
2218 __le32 critical_temperature_enter;
2219} __packed;
2220
2221
2222
2223
2224
2225
2226
2227#define SCAN_CHANNEL_TYPE_PASSIVE cpu_to_le32(0)
2228#define SCAN_CHANNEL_TYPE_ACTIVE cpu_to_le32(1)
2229
2230
2231
2232
2233
2234
2235
2236
2237
2238
2239
2240
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250struct iwl_scan_channel {
2251
2252
2253
2254
2255
2256
2257
2258 __le32 type;
2259 __le16 channel;
2260 u8 tx_gain;
2261 u8 dsp_atten;
2262 __le16 active_dwell;
2263 __le16 passive_dwell;
2264} __packed;
2265
2266
2267#define IWL_SCAN_PROBE_MASK(n) cpu_to_le32((BIT(n) | (BIT(n) - BIT(1))))
2268
2269
2270
2271
2272
2273
2274
2275
2276
2277struct iwl_ssid_ie {
2278 u8 id;
2279 u8 len;
2280 u8 ssid[32];
2281} __packed;
2282
2283#define PROBE_OPTION_MAX 20
2284#define TX_CMD_LIFE_TIME_INFINITE cpu_to_le32(0xFFFFFFFF)
2285#define IWL_GOOD_CRC_TH_DISABLED 0
2286#define IWL_GOOD_CRC_TH_DEFAULT cpu_to_le16(1)
2287#define IWL_GOOD_CRC_TH_NEVER cpu_to_le16(0xffff)
2288#define IWL_MAX_CMD_SIZE 4096
2289
2290
2291
2292
2293
2294
2295
2296
2297
2298
2299
2300
2301
2302
2303
2304
2305
2306
2307
2308
2309
2310
2311
2312
2313
2314
2315
2316
2317
2318
2319
2320
2321
2322
2323
2324
2325
2326
2327
2328
2329
2330
2331
2332
2333
2334
2335
2336
2337
2338
2339
2340
2341
2342
2343enum iwl_scan_flags {
2344
2345 IWL_SCAN_FLAGS_ACTION_FRAME_TX = BIT(1),
2346
2347};
2348
2349struct iwl_scan_cmd {
2350 __le16 len;
2351 u8 scan_flags;
2352 u8 channel_count;
2353 __le16 quiet_time;
2354
2355 __le16 quiet_plcp_th;
2356 __le16 good_CRC_th;
2357 __le16 rx_chain;
2358 __le32 max_out_time;
2359
2360 __le32 suspend_time;
2361
2362
2363 __le32 flags;
2364 __le32 filter_flags;
2365
2366
2367
2368 struct iwl_tx_cmd tx_cmd;
2369
2370
2371 struct iwl_ssid_ie direct_scan[PROBE_OPTION_MAX];
2372
2373
2374
2375
2376
2377
2378
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388 u8 data[0];
2389} __packed;
2390
2391
2392#define CAN_ABORT_STATUS cpu_to_le32(0x1)
2393
2394#define ABORT_STATUS 0x2
2395
2396
2397
2398
2399struct iwl_scanreq_notification {
2400 __le32 status;
2401} __packed;
2402
2403
2404
2405
2406struct iwl_scanstart_notification {
2407 __le32 tsf_low;
2408 __le32 tsf_high;
2409 __le32 beacon_timer;
2410 u8 channel;
2411 u8 band;
2412 u8 reserved[2];
2413 __le32 status;
2414} __packed;
2415
2416#define SCAN_OWNER_STATUS 0x1
2417#define MEASURE_OWNER_STATUS 0x2
2418
2419#define IWL_PROBE_STATUS_OK 0
2420#define IWL_PROBE_STATUS_TX_FAILED BIT(0)
2421
2422#define IWL_PROBE_STATUS_FAIL_TTL BIT(1)
2423#define IWL_PROBE_STATUS_FAIL_BT BIT(2)
2424
2425#define NUMBER_OF_STATISTICS 1
2426
2427
2428
2429struct iwl_scanresults_notification {
2430 u8 channel;
2431 u8 band;
2432 u8 probe_status;
2433 u8 num_probe_not_sent;
2434 __le32 tsf_low;
2435 __le32 tsf_high;
2436 __le32 statistics[NUMBER_OF_STATISTICS];
2437} __packed;
2438
2439
2440
2441
2442struct iwl_scancomplete_notification {
2443 u8 scanned_channels;
2444 u8 status;
2445 u8 bt_status;
2446 u8 last_channel;
2447 __le32 tsf_low;
2448 __le32 tsf_high;
2449} __packed;
2450
2451
2452
2453
2454
2455
2456
2457
2458enum iwl_ibss_manager {
2459 IWL_NOT_IBSS_MANAGER = 0,
2460 IWL_IBSS_MANAGER = 1,
2461};
2462
2463
2464
2465
2466
2467struct iwlagn_beacon_notif {
2468 struct iwlagn_tx_resp beacon_notify_hdr;
2469 __le32 low_tsf;
2470 __le32 high_tsf;
2471 __le32 ibss_mgr_status;
2472} __packed;
2473
2474
2475
2476
2477
2478struct iwl_tx_beacon_cmd {
2479 struct iwl_tx_cmd tx;
2480 __le16 tim_idx;
2481 u8 tim_size;
2482 u8 reserved1;
2483 struct ieee80211_hdr frame[0];
2484} __packed;
2485
2486
2487
2488
2489
2490
2491
2492#define IWL_TEMP_CONVERT 260
2493
2494#define SUP_RATE_11A_MAX_NUM_CHANNELS 8
2495#define SUP_RATE_11B_MAX_NUM_CHANNELS 4
2496#define SUP_RATE_11G_MAX_NUM_CHANNELS 12
2497
2498
2499struct rate_histogram {
2500 union {
2501 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2502 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2503 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2504 } success;
2505 union {
2506 __le32 a[SUP_RATE_11A_MAX_NUM_CHANNELS];
2507 __le32 b[SUP_RATE_11B_MAX_NUM_CHANNELS];
2508 __le32 g[SUP_RATE_11G_MAX_NUM_CHANNELS];
2509 } failed;
2510} __packed;
2511
2512
2513
2514struct statistics_dbg {
2515 __le32 burst_check;
2516 __le32 burst_count;
2517 __le32 wait_for_silence_timeout_cnt;
2518 __le32 reserved[3];
2519} __packed;
2520
2521struct statistics_rx_phy {
2522 __le32 ina_cnt;
2523 __le32 fina_cnt;
2524 __le32 plcp_err;
2525 __le32 crc32_err;
2526 __le32 overrun_err;
2527 __le32 early_overrun_err;
2528 __le32 crc32_good;
2529 __le32 false_alarm_cnt;
2530 __le32 fina_sync_err_cnt;
2531 __le32 sfd_timeout;
2532 __le32 fina_timeout;
2533 __le32 unresponded_rts;
2534 __le32 rxe_frame_limit_overrun;
2535 __le32 sent_ack_cnt;
2536 __le32 sent_cts_cnt;
2537 __le32 sent_ba_rsp_cnt;
2538 __le32 dsp_self_kill;
2539 __le32 mh_format_err;
2540 __le32 re_acq_main_rssi_sum;
2541 __le32 reserved3;
2542} __packed;
2543
2544struct statistics_rx_ht_phy {
2545 __le32 plcp_err;
2546 __le32 overrun_err;
2547 __le32 early_overrun_err;
2548 __le32 crc32_good;
2549 __le32 crc32_err;
2550 __le32 mh_format_err;
2551 __le32 agg_crc32_good;
2552 __le32 agg_mpdu_cnt;
2553 __le32 agg_cnt;
2554 __le32 unsupport_mcs;
2555} __packed;
2556
2557#define INTERFERENCE_DATA_AVAILABLE cpu_to_le32(1)
2558
2559struct statistics_rx_non_phy {
2560 __le32 bogus_cts;
2561 __le32 bogus_ack;
2562 __le32 non_bssid_frames;
2563
2564 __le32 filtered_frames;
2565
2566 __le32 non_channel_beacons;
2567
2568 __le32 channel_beacons;
2569
2570 __le32 num_missed_bcon;
2571 __le32 adc_rx_saturation_time;
2572
2573 __le32 ina_detection_search_time;
2574
2575 __le32 beacon_silence_rssi_a;
2576 __le32 beacon_silence_rssi_b;
2577 __le32 beacon_silence_rssi_c;
2578 __le32 interference_data_flag;
2579
2580
2581 __le32 channel_load;
2582 __le32 dsp_false_alarms;
2583
2584 __le32 beacon_rssi_a;
2585 __le32 beacon_rssi_b;
2586 __le32 beacon_rssi_c;
2587 __le32 beacon_energy_a;
2588 __le32 beacon_energy_b;
2589 __le32 beacon_energy_c;
2590} __packed;
2591
2592struct statistics_rx_non_phy_bt {
2593 struct statistics_rx_non_phy common;
2594
2595 __le32 num_bt_kills;
2596 __le32 reserved[2];
2597} __packed;
2598
2599struct statistics_rx {
2600 struct statistics_rx_phy ofdm;
2601 struct statistics_rx_phy cck;
2602 struct statistics_rx_non_phy general;
2603 struct statistics_rx_ht_phy ofdm_ht;
2604} __packed;
2605
2606struct statistics_rx_bt {
2607 struct statistics_rx_phy ofdm;
2608 struct statistics_rx_phy cck;
2609 struct statistics_rx_non_phy_bt general;
2610 struct statistics_rx_ht_phy ofdm_ht;
2611} __packed;
2612
2613
2614
2615
2616
2617
2618
2619
2620struct statistics_tx_power {
2621 u8 ant_a;
2622 u8 ant_b;
2623 u8 ant_c;
2624 u8 reserved;
2625} __packed;
2626
2627struct statistics_tx_non_phy_agg {
2628 __le32 ba_timeout;
2629 __le32 ba_reschedule_frames;
2630 __le32 scd_query_agg_frame_cnt;
2631 __le32 scd_query_no_agg;
2632 __le32 scd_query_agg;
2633 __le32 scd_query_mismatch;
2634 __le32 frame_not_ready;
2635 __le32 underrun;
2636 __le32 bt_prio_kill;
2637 __le32 rx_ba_rsp_cnt;
2638} __packed;
2639
2640struct statistics_tx {
2641 __le32 preamble_cnt;
2642 __le32 rx_detected_cnt;
2643 __le32 bt_prio_defer_cnt;
2644 __le32 bt_prio_kill_cnt;
2645 __le32 few_bytes_cnt;
2646 __le32 cts_timeout;
2647 __le32 ack_timeout;
2648 __le32 expected_ack_cnt;
2649 __le32 actual_ack_cnt;
2650 __le32 dump_msdu_cnt;
2651 __le32 burst_abort_next_frame_mismatch_cnt;
2652 __le32 burst_abort_missing_next_frame_cnt;
2653 __le32 cts_timeout_collision;
2654 __le32 ack_or_ba_timeout_collision;
2655 struct statistics_tx_non_phy_agg agg;
2656
2657
2658
2659
2660
2661 struct statistics_tx_power tx_power;
2662 __le32 reserved1;
2663} __packed;
2664
2665
2666struct statistics_div {
2667 __le32 tx_on_a;
2668 __le32 tx_on_b;
2669 __le32 exec_time;
2670 __le32 probe_time;
2671 __le32 reserved1;
2672 __le32 reserved2;
2673} __packed;
2674
2675struct statistics_general_common {
2676 __le32 temperature;
2677 __le32 temperature_m;
2678 struct statistics_dbg dbg;
2679 __le32 sleep_time;
2680 __le32 slots_out;
2681 __le32 slots_idle;
2682 __le32 ttl_timestamp;
2683 struct statistics_div div;
2684 __le32 rx_enable_counter;
2685
2686
2687
2688
2689
2690 __le32 num_of_sos_states;
2691} __packed;
2692
2693struct statistics_bt_activity {
2694
2695 __le32 hi_priority_tx_req_cnt;
2696 __le32 hi_priority_tx_denied_cnt;
2697 __le32 lo_priority_tx_req_cnt;
2698 __le32 lo_priority_tx_denied_cnt;
2699
2700 __le32 hi_priority_rx_req_cnt;
2701 __le32 hi_priority_rx_denied_cnt;
2702 __le32 lo_priority_rx_req_cnt;
2703 __le32 lo_priority_rx_denied_cnt;
2704} __packed;
2705
2706struct statistics_general {
2707 struct statistics_general_common common;
2708 __le32 reserved2;
2709 __le32 reserved3;
2710} __packed;
2711
2712struct statistics_general_bt {
2713 struct statistics_general_common common;
2714 struct statistics_bt_activity activity;
2715 __le32 reserved2;
2716 __le32 reserved3;
2717} __packed;
2718
2719#define UCODE_STATISTICS_CLEAR_MSK (0x1 << 0)
2720#define UCODE_STATISTICS_FREQUENCY_MSK (0x1 << 1)
2721#define UCODE_STATISTICS_NARROW_BAND_MSK (0x1 << 2)
2722
2723
2724
2725
2726
2727
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738#define IWL_STATS_CONF_CLEAR_STATS cpu_to_le32(0x1)
2739#define IWL_STATS_CONF_DISABLE_NOTIF cpu_to_le32(0x2)
2740struct iwl_statistics_cmd {
2741 __le32 configuration_flags;
2742} __packed;
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756
2757
2758
2759#define STATISTICS_REPLY_FLG_BAND_24G_MSK cpu_to_le32(0x2)
2760#define STATISTICS_REPLY_FLG_HT40_MODE_MSK cpu_to_le32(0x8)
2761
2762struct iwl_notif_statistics {
2763 __le32 flag;
2764 struct statistics_rx rx;
2765 struct statistics_tx tx;
2766 struct statistics_general general;
2767} __packed;
2768
2769struct iwl_bt_notif_statistics {
2770 __le32 flag;
2771 struct statistics_rx_bt rx;
2772 struct statistics_tx tx;
2773 struct statistics_general_bt general;
2774} __packed;
2775
2776
2777
2778
2779
2780
2781
2782
2783
2784
2785
2786
2787
2788
2789
2790
2791
2792
2793
2794
2795
2796#define IWL_MISSED_BEACON_THRESHOLD_MIN (1)
2797#define IWL_MISSED_BEACON_THRESHOLD_DEF (5)
2798#define IWL_MISSED_BEACON_THRESHOLD_MAX IWL_MISSED_BEACON_THRESHOLD_DEF
2799
2800struct iwl_missed_beacon_notif {
2801 __le32 consecutive_missed_beacons;
2802 __le32 total_missed_becons;
2803 __le32 num_expected_beacons;
2804 __le32 num_recvd_beacons;
2805} __packed;
2806
2807
2808
2809
2810
2811
2812
2813
2814
2815
2816
2817
2818
2819
2820
2821
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2900
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2962
2963
2964
2965
2966
2967
2968
2969
2970
2971
2972
2973
2974
2975
2976
2977
2978
2979
2980#define HD_TABLE_SIZE (11)
2981#define HD_MIN_ENERGY_CCK_DET_INDEX (0)
2982#define HD_MIN_ENERGY_OFDM_DET_INDEX (1)
2983#define HD_AUTO_CORR32_X1_TH_ADD_MIN_INDEX (2)
2984#define HD_AUTO_CORR32_X1_TH_ADD_MIN_MRC_INDEX (3)
2985#define HD_AUTO_CORR40_X4_TH_ADD_MIN_MRC_INDEX (4)
2986#define HD_AUTO_CORR32_X4_TH_ADD_MIN_INDEX (5)
2987#define HD_AUTO_CORR32_X4_TH_ADD_MIN_MRC_INDEX (6)
2988#define HD_BARKER_CORR_TH_ADD_MIN_INDEX (7)
2989#define HD_BARKER_CORR_TH_ADD_MIN_MRC_INDEX (8)
2990#define HD_AUTO_CORR40_X4_TH_ADD_MIN_INDEX (9)
2991#define HD_OFDM_ENERGY_TH_IN_INDEX (10)
2992
2993
2994
2995
2996#define HD_INA_NON_SQUARE_DET_OFDM_INDEX (11)
2997#define HD_INA_NON_SQUARE_DET_CCK_INDEX (12)
2998#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_INDEX (13)
2999#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_INDEX (14)
3000#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (15)
3001#define HD_OFDM_NON_SQUARE_DET_SLOPE_INDEX (16)
3002#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_INDEX (17)
3003#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_INDEX (18)
3004#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_INDEX (19)
3005#define HD_CCK_NON_SQUARE_DET_SLOPE_INDEX (20)
3006#define HD_CCK_NON_SQUARE_DET_INTERCEPT_INDEX (21)
3007#define HD_RESERVED (22)
3008
3009
3010#define ENHANCE_HD_TABLE_SIZE (23)
3011
3012
3013#define ENHANCE_HD_TABLE_ENTRIES (ENHANCE_HD_TABLE_SIZE - HD_TABLE_SIZE)
3014
3015#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V1 cpu_to_le16(0)
3016#define HD_INA_NON_SQUARE_DET_CCK_DATA_V1 cpu_to_le16(0)
3017#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V1 cpu_to_le16(0)
3018#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(668)
3019#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3020#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(486)
3021#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(37)
3022#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V1 cpu_to_le16(853)
3023#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V1 cpu_to_le16(4)
3024#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V1 cpu_to_le16(476)
3025#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V1 cpu_to_le16(99)
3026
3027#define HD_INA_NON_SQUARE_DET_OFDM_DATA_V2 cpu_to_le16(1)
3028#define HD_INA_NON_SQUARE_DET_CCK_DATA_V2 cpu_to_le16(1)
3029#define HD_CORR_11_INSTEAD_OF_CORR_9_EN_DATA_V2 cpu_to_le16(1)
3030#define HD_OFDM_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(600)
3031#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(40)
3032#define HD_OFDM_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(486)
3033#define HD_OFDM_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(45)
3034#define HD_CCK_NON_SQUARE_DET_SLOPE_MRC_DATA_V2 cpu_to_le16(853)
3035#define HD_CCK_NON_SQUARE_DET_INTERCEPT_MRC_DATA_V2 cpu_to_le16(60)
3036#define HD_CCK_NON_SQUARE_DET_SLOPE_DATA_V2 cpu_to_le16(476)
3037#define HD_CCK_NON_SQUARE_DET_INTERCEPT_DATA_V2 cpu_to_le16(99)
3038
3039
3040
3041#define SENSITIVITY_CMD_CONTROL_DEFAULT_TABLE cpu_to_le16(0)
3042#define SENSITIVITY_CMD_CONTROL_WORK_TABLE cpu_to_le16(1)
3043
3044
3045
3046
3047
3048
3049
3050
3051struct iwl_sensitivity_cmd {
3052 __le16 control;
3053 __le16 table[HD_TABLE_SIZE];
3054} __packed;
3055
3056
3057
3058
3059struct iwl_enhance_sensitivity_cmd {
3060 __le16 control;
3061 __le16 enhance_table[ENHANCE_HD_TABLE_SIZE];
3062} __packed;
3063
3064
3065
3066
3067
3068
3069
3070
3071
3072
3073
3074
3075
3076
3077
3078
3079
3080
3081
3082
3083
3084
3085
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3087
3088
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3090
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3093
3094
3095
3096
3097
3098
3099
3100
3101
3102
3103
3104
3105
3106
3107
3108
3109
3110
3111
3112
3113
3114
3115
3116
3117
3118
3119
3120
3121enum {
3122 IWL_PHY_CALIBRATE_DC_CMD = 8,
3123 IWL_PHY_CALIBRATE_LO_CMD = 9,
3124 IWL_PHY_CALIBRATE_TX_IQ_CMD = 11,
3125 IWL_PHY_CALIBRATE_CRYSTAL_FRQ_CMD = 15,
3126 IWL_PHY_CALIBRATE_BASE_BAND_CMD = 16,
3127 IWL_PHY_CALIBRATE_TX_IQ_PERD_CMD = 17,
3128 IWL_PHY_CALIBRATE_TEMP_OFFSET_CMD = 18,
3129};
3130
3131
3132
3133
3134enum iwl_ucode_calib_cfg {
3135 IWL_CALIB_CFG_RX_BB_IDX = BIT(0),
3136 IWL_CALIB_CFG_DC_IDX = BIT(1),
3137 IWL_CALIB_CFG_LO_IDX = BIT(2),
3138 IWL_CALIB_CFG_TX_IQ_IDX = BIT(3),
3139 IWL_CALIB_CFG_RX_IQ_IDX = BIT(4),
3140 IWL_CALIB_CFG_NOISE_IDX = BIT(5),
3141 IWL_CALIB_CFG_CRYSTAL_IDX = BIT(6),
3142 IWL_CALIB_CFG_TEMPERATURE_IDX = BIT(7),
3143 IWL_CALIB_CFG_PAPD_IDX = BIT(8),
3144 IWL_CALIB_CFG_SENSITIVITY_IDX = BIT(9),
3145 IWL_CALIB_CFG_TX_PWR_IDX = BIT(10),
3146};
3147
3148#define IWL_CALIB_INIT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3149 IWL_CALIB_CFG_DC_IDX | \
3150 IWL_CALIB_CFG_LO_IDX | \
3151 IWL_CALIB_CFG_TX_IQ_IDX | \
3152 IWL_CALIB_CFG_RX_IQ_IDX | \
3153 IWL_CALIB_CFG_CRYSTAL_IDX)
3154
3155#define IWL_CALIB_RT_CFG_ALL cpu_to_le32(IWL_CALIB_CFG_RX_BB_IDX | \
3156 IWL_CALIB_CFG_DC_IDX | \
3157 IWL_CALIB_CFG_LO_IDX | \
3158 IWL_CALIB_CFG_TX_IQ_IDX | \
3159 IWL_CALIB_CFG_RX_IQ_IDX | \
3160 IWL_CALIB_CFG_TEMPERATURE_IDX | \
3161 IWL_CALIB_CFG_PAPD_IDX | \
3162 IWL_CALIB_CFG_TX_PWR_IDX | \
3163 IWL_CALIB_CFG_CRYSTAL_IDX)
3164
3165#define IWL_CALIB_CFG_FLAG_SEND_COMPLETE_NTFY_MSK cpu_to_le32(BIT(0))
3166
3167struct iwl_calib_cfg_elmnt_s {
3168 __le32 is_enable;
3169 __le32 start;
3170 __le32 send_res;
3171 __le32 apply_res;
3172 __le32 reserved;
3173} __packed;
3174
3175struct iwl_calib_cfg_status_s {
3176 struct iwl_calib_cfg_elmnt_s once;
3177 struct iwl_calib_cfg_elmnt_s perd;
3178 __le32 flags;
3179} __packed;
3180
3181struct iwl_calib_cfg_cmd {
3182 struct iwl_calib_cfg_status_s ucd_calib_cfg;
3183 struct iwl_calib_cfg_status_s drv_calib_cfg;
3184 __le32 reserved1;
3185} __packed;
3186
3187struct iwl_calib_hdr {
3188 u8 op_code;
3189 u8 first_group;
3190 u8 groups_num;
3191 u8 data_valid;
3192} __packed;
3193
3194struct iwl_calib_cmd {
3195 struct iwl_calib_hdr hdr;
3196 u8 data[0];
3197} __packed;
3198
3199struct iwl_calib_xtal_freq_cmd {
3200 struct iwl_calib_hdr hdr;
3201 u8 cap_pin1;
3202 u8 cap_pin2;
3203 u8 pad[2];
3204} __packed;
3205
3206#define DEFAULT_RADIO_SENSOR_OFFSET cpu_to_le16(2700)
3207struct iwl_calib_temperature_offset_cmd {
3208 struct iwl_calib_hdr hdr;
3209 __le16 radio_sensor_offset;
3210 __le16 reserved;
3211} __packed;
3212
3213struct iwl_calib_temperature_offset_v2_cmd {
3214 struct iwl_calib_hdr hdr;
3215 __le16 radio_sensor_offset_high;
3216 __le16 radio_sensor_offset_low;
3217 __le16 burntVoltageRef;
3218 __le16 reserved;
3219} __packed;
3220
3221
3222struct iwl_calib_chain_noise_reset_cmd {
3223 struct iwl_calib_hdr hdr;
3224 u8 data[0];
3225};
3226
3227
3228struct iwl_calib_chain_noise_gain_cmd {
3229 struct iwl_calib_hdr hdr;
3230 u8 delta_gain_1;
3231 u8 delta_gain_2;
3232 u8 pad[2];
3233} __packed;
3234
3235
3236
3237
3238
3239
3240
3241
3242
3243
3244
3245
3246
3247
3248struct iwl_led_cmd {
3249 __le32 interval;
3250 u8 id;
3251 u8 off;
3252
3253 u8 on;
3254
3255 u8 reserved;
3256} __packed;
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266
3267
3268
3269#define COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG (0x1)
3270#define COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG (0x2)
3271#define COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG (0x4)
3272
3273#define COEX_CU_UNASSOC_IDLE_RP 4
3274#define COEX_CU_UNASSOC_MANUAL_SCAN_RP 4
3275#define COEX_CU_UNASSOC_AUTO_SCAN_RP 4
3276#define COEX_CU_CALIBRATION_RP 4
3277#define COEX_CU_PERIODIC_CALIBRATION_RP 4
3278#define COEX_CU_CONNECTION_ESTAB_RP 4
3279#define COEX_CU_ASSOCIATED_IDLE_RP 4
3280#define COEX_CU_ASSOC_MANUAL_SCAN_RP 4
3281#define COEX_CU_ASSOC_AUTO_SCAN_RP 4
3282#define COEX_CU_ASSOC_ACTIVE_LEVEL_RP 4
3283#define COEX_CU_RF_ON_RP 6
3284#define COEX_CU_RF_OFF_RP 4
3285#define COEX_CU_STAND_ALONE_DEBUG_RP 6
3286#define COEX_CU_IPAN_ASSOC_LEVEL_RP 4
3287#define COEX_CU_RSRVD1_RP 4
3288#define COEX_CU_RSRVD2_RP 4
3289
3290#define COEX_CU_UNASSOC_IDLE_WP 3
3291#define COEX_CU_UNASSOC_MANUAL_SCAN_WP 3
3292#define COEX_CU_UNASSOC_AUTO_SCAN_WP 3
3293#define COEX_CU_CALIBRATION_WP 3
3294#define COEX_CU_PERIODIC_CALIBRATION_WP 3
3295#define COEX_CU_CONNECTION_ESTAB_WP 3
3296#define COEX_CU_ASSOCIATED_IDLE_WP 3
3297#define COEX_CU_ASSOC_MANUAL_SCAN_WP 3
3298#define COEX_CU_ASSOC_AUTO_SCAN_WP 3
3299#define COEX_CU_ASSOC_ACTIVE_LEVEL_WP 3
3300#define COEX_CU_RF_ON_WP 3
3301#define COEX_CU_RF_OFF_WP 3
3302#define COEX_CU_STAND_ALONE_DEBUG_WP 6
3303#define COEX_CU_IPAN_ASSOC_LEVEL_WP 3
3304#define COEX_CU_RSRVD1_WP 3
3305#define COEX_CU_RSRVD2_WP 3
3306
3307#define COEX_UNASSOC_IDLE_FLAGS 0
3308#define COEX_UNASSOC_MANUAL_SCAN_FLAGS \
3309 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3310 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3311#define COEX_UNASSOC_AUTO_SCAN_FLAGS \
3312 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3313 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3314#define COEX_CALIBRATION_FLAGS \
3315 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3316 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3317#define COEX_PERIODIC_CALIBRATION_FLAGS 0
3318
3319
3320
3321
3322#define COEX_CONNECTION_ESTAB_FLAGS \
3323 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3324 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3325 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3326#define COEX_ASSOCIATED_IDLE_FLAGS 0
3327#define COEX_ASSOC_MANUAL_SCAN_FLAGS \
3328 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3329 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3330#define COEX_ASSOC_AUTO_SCAN_FLAGS \
3331 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3332 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3333#define COEX_ASSOC_ACTIVE_LEVEL_FLAGS 0
3334#define COEX_RF_ON_FLAGS 0
3335#define COEX_RF_OFF_FLAGS 0
3336#define COEX_STAND_ALONE_DEBUG_FLAGS \
3337 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3338 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG)
3339#define COEX_IPAN_ASSOC_LEVEL_FLAGS \
3340 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3341 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3342 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3343#define COEX_RSRVD1_FLAGS 0
3344#define COEX_RSRVD2_FLAGS 0
3345
3346
3347
3348
3349#define COEX_CU_RF_ON_FLAGS \
3350 (COEX_EVT_FLAG_MEDIUM_FREE_NTFY_FLG | \
3351 COEX_EVT_FLAG_MEDIUM_ACTV_NTFY_FLG | \
3352 COEX_EVT_FLAG_DELAY_MEDIUM_FREE_NTFY_FLG)
3353
3354
3355enum {
3356
3357 COEX_UNASSOC_IDLE = 0,
3358 COEX_UNASSOC_MANUAL_SCAN = 1,
3359 COEX_UNASSOC_AUTO_SCAN = 2,
3360
3361 COEX_CALIBRATION = 3,
3362 COEX_PERIODIC_CALIBRATION = 4,
3363
3364 COEX_CONNECTION_ESTAB = 5,
3365
3366 COEX_ASSOCIATED_IDLE = 6,
3367 COEX_ASSOC_MANUAL_SCAN = 7,
3368 COEX_ASSOC_AUTO_SCAN = 8,
3369 COEX_ASSOC_ACTIVE_LEVEL = 9,
3370
3371 COEX_RF_ON = 10,
3372 COEX_RF_OFF = 11,
3373 COEX_STAND_ALONE_DEBUG = 12,
3374
3375 COEX_IPAN_ASSOC_LEVEL = 13,
3376
3377 COEX_RSRVD1 = 14,
3378 COEX_RSRVD2 = 15,
3379 COEX_NUM_OF_EVENTS = 16
3380};
3381
3382
3383
3384
3385
3386
3387struct iwl_wimax_coex_event_entry {
3388 u8 request_prio;
3389 u8 win_medium_prio;
3390 u8 reserved;
3391 u8 flags;
3392} __packed;
3393
3394
3395
3396
3397#define COEX_FLAGS_STA_TABLE_VALID_MSK (0x1)
3398
3399#define COEX_FLAGS_UNASSOC_WA_UNMASK_MSK (0x4)
3400
3401#define COEX_FLAGS_ASSOC_WA_UNMASK_MSK (0x8)
3402
3403#define COEX_FLAGS_COEX_ENABLE_MSK (0x80)
3404
3405struct iwl_wimax_coex_cmd {
3406 u8 flags;
3407 u8 reserved[3];
3408 struct iwl_wimax_coex_event_entry sta_prio[COEX_NUM_OF_EVENTS];
3409} __packed;
3410
3411
3412
3413
3414
3415
3416
3417
3418
3419
3420
3421
3422
3423
3424
3425#define COEX_MEDIUM_BUSY (0x0)
3426#define COEX_MEDIUM_ACTIVE (0x1)
3427#define COEX_MEDIUM_PRE_RELEASE (0x2)
3428#define COEX_MEDIUM_MSK (0x7)
3429
3430
3431#define COEX_MEDIUM_CHANGED (0x8)
3432#define COEX_MEDIUM_CHANGED_MSK (0x8)
3433#define COEX_MEDIUM_SHIFT (3)
3434
3435struct iwl_coex_medium_notification {
3436 __le32 status;
3437 __le32 events;
3438} __packed;
3439
3440
3441
3442
3443
3444
3445
3446
3447#define COEX_EVENT_REQUEST_MSK (0x1)
3448
3449struct iwl_coex_event_cmd {
3450 u8 flags;
3451 u8 event;
3452 __le16 reserved;
3453} __packed;
3454
3455struct iwl_coex_event_resp {
3456 __le32 status;
3457} __packed;
3458
3459
3460
3461
3462
3463
3464
3465
3466
3467
3468
3469enum iwl_bt_coex_profile_traffic_load {
3470 IWL_BT_COEX_TRAFFIC_LOAD_NONE = 0,
3471 IWL_BT_COEX_TRAFFIC_LOAD_LOW = 1,
3472 IWL_BT_COEX_TRAFFIC_LOAD_HIGH = 2,
3473 IWL_BT_COEX_TRAFFIC_LOAD_CONTINUOUS = 3,
3474
3475
3476
3477
3478};
3479
3480#define BT_SESSION_ACTIVITY_1_UART_MSG 0x1
3481#define BT_SESSION_ACTIVITY_2_UART_MSG 0x2
3482
3483
3484#define BT_UART_MSG_FRAME1MSGTYPE_POS (0)
3485#define BT_UART_MSG_FRAME1MSGTYPE_MSK \
3486 (0x7 << BT_UART_MSG_FRAME1MSGTYPE_POS)
3487#define BT_UART_MSG_FRAME1SSN_POS (3)
3488#define BT_UART_MSG_FRAME1SSN_MSK \
3489 (0x3 << BT_UART_MSG_FRAME1SSN_POS)
3490#define BT_UART_MSG_FRAME1UPDATEREQ_POS (5)
3491#define BT_UART_MSG_FRAME1UPDATEREQ_MSK \
3492 (0x1 << BT_UART_MSG_FRAME1UPDATEREQ_POS)
3493#define BT_UART_MSG_FRAME1RESERVED_POS (6)
3494#define BT_UART_MSG_FRAME1RESERVED_MSK \
3495 (0x3 << BT_UART_MSG_FRAME1RESERVED_POS)
3496
3497#define BT_UART_MSG_FRAME2OPENCONNECTIONS_POS (0)
3498#define BT_UART_MSG_FRAME2OPENCONNECTIONS_MSK \
3499 (0x3 << BT_UART_MSG_FRAME2OPENCONNECTIONS_POS)
3500#define BT_UART_MSG_FRAME2TRAFFICLOAD_POS (2)
3501#define BT_UART_MSG_FRAME2TRAFFICLOAD_MSK \
3502 (0x3 << BT_UART_MSG_FRAME2TRAFFICLOAD_POS)
3503#define BT_UART_MSG_FRAME2CHLSEQN_POS (4)
3504#define BT_UART_MSG_FRAME2CHLSEQN_MSK \
3505 (0x1 << BT_UART_MSG_FRAME2CHLSEQN_POS)
3506#define BT_UART_MSG_FRAME2INBAND_POS (5)
3507#define BT_UART_MSG_FRAME2INBAND_MSK \
3508 (0x1 << BT_UART_MSG_FRAME2INBAND_POS)
3509#define BT_UART_MSG_FRAME2RESERVED_POS (6)
3510#define BT_UART_MSG_FRAME2RESERVED_MSK \
3511 (0x3 << BT_UART_MSG_FRAME2RESERVED_POS)
3512
3513#define BT_UART_MSG_FRAME3SCOESCO_POS (0)
3514#define BT_UART_MSG_FRAME3SCOESCO_MSK \
3515 (0x1 << BT_UART_MSG_FRAME3SCOESCO_POS)
3516#define BT_UART_MSG_FRAME3SNIFF_POS (1)
3517#define BT_UART_MSG_FRAME3SNIFF_MSK \
3518 (0x1 << BT_UART_MSG_FRAME3SNIFF_POS)
3519#define BT_UART_MSG_FRAME3A2DP_POS (2)
3520#define BT_UART_MSG_FRAME3A2DP_MSK \
3521 (0x1 << BT_UART_MSG_FRAME3A2DP_POS)
3522#define BT_UART_MSG_FRAME3ACL_POS (3)
3523#define BT_UART_MSG_FRAME3ACL_MSK \
3524 (0x1 << BT_UART_MSG_FRAME3ACL_POS)
3525#define BT_UART_MSG_FRAME3MASTER_POS (4)
3526#define BT_UART_MSG_FRAME3MASTER_MSK \
3527 (0x1 << BT_UART_MSG_FRAME3MASTER_POS)
3528#define BT_UART_MSG_FRAME3OBEX_POS (5)
3529#define BT_UART_MSG_FRAME3OBEX_MSK \
3530 (0x1 << BT_UART_MSG_FRAME3OBEX_POS)
3531#define BT_UART_MSG_FRAME3RESERVED_POS (6)
3532#define BT_UART_MSG_FRAME3RESERVED_MSK \
3533 (0x3 << BT_UART_MSG_FRAME3RESERVED_POS)
3534
3535#define BT_UART_MSG_FRAME4IDLEDURATION_POS (0)
3536#define BT_UART_MSG_FRAME4IDLEDURATION_MSK \
3537 (0x3F << BT_UART_MSG_FRAME4IDLEDURATION_POS)
3538#define BT_UART_MSG_FRAME4RESERVED_POS (6)
3539#define BT_UART_MSG_FRAME4RESERVED_MSK \
3540 (0x3 << BT_UART_MSG_FRAME4RESERVED_POS)
3541
3542#define BT_UART_MSG_FRAME5TXACTIVITY_POS (0)
3543#define BT_UART_MSG_FRAME5TXACTIVITY_MSK \
3544 (0x3 << BT_UART_MSG_FRAME5TXACTIVITY_POS)
3545#define BT_UART_MSG_FRAME5RXACTIVITY_POS (2)
3546#define BT_UART_MSG_FRAME5RXACTIVITY_MSK \
3547 (0x3 << BT_UART_MSG_FRAME5RXACTIVITY_POS)
3548#define BT_UART_MSG_FRAME5ESCORETRANSMIT_POS (4)
3549#define BT_UART_MSG_FRAME5ESCORETRANSMIT_MSK \
3550 (0x3 << BT_UART_MSG_FRAME5ESCORETRANSMIT_POS)
3551#define BT_UART_MSG_FRAME5RESERVED_POS (6)
3552#define BT_UART_MSG_FRAME5RESERVED_MSK \
3553 (0x3 << BT_UART_MSG_FRAME5RESERVED_POS)
3554
3555#define BT_UART_MSG_FRAME6SNIFFINTERVAL_POS (0)
3556#define BT_UART_MSG_FRAME6SNIFFINTERVAL_MSK \
3557 (0x1F << BT_UART_MSG_FRAME6SNIFFINTERVAL_POS)
3558#define BT_UART_MSG_FRAME6DISCOVERABLE_POS (5)
3559#define BT_UART_MSG_FRAME6DISCOVERABLE_MSK \
3560 (0x1 << BT_UART_MSG_FRAME6DISCOVERABLE_POS)
3561#define BT_UART_MSG_FRAME6RESERVED_POS (6)
3562#define BT_UART_MSG_FRAME6RESERVED_MSK \
3563 (0x3 << BT_UART_MSG_FRAME6RESERVED_POS)
3564
3565#define BT_UART_MSG_FRAME7SNIFFACTIVITY_POS (0)
3566#define BT_UART_MSG_FRAME7SNIFFACTIVITY_MSK \
3567 (0x7 << BT_UART_MSG_FRAME7SNIFFACTIVITY_POS)
3568#define BT_UART_MSG_FRAME7PAGE_POS (3)
3569#define BT_UART_MSG_FRAME7PAGE_MSK \
3570 (0x1 << BT_UART_MSG_FRAME7PAGE_POS)
3571#define BT_UART_MSG_FRAME7INQUIRY_POS (4)
3572#define BT_UART_MSG_FRAME7INQUIRY_MSK \
3573 (0x1 << BT_UART_MSG_FRAME7INQUIRY_POS)
3574#define BT_UART_MSG_FRAME7CONNECTABLE_POS (5)
3575#define BT_UART_MSG_FRAME7CONNECTABLE_MSK \
3576 (0x1 << BT_UART_MSG_FRAME7CONNECTABLE_POS)
3577#define BT_UART_MSG_FRAME7RESERVED_POS (6)
3578#define BT_UART_MSG_FRAME7RESERVED_MSK \
3579 (0x3 << BT_UART_MSG_FRAME7RESERVED_POS)
3580
3581
3582#define BT_UART_MSG_2_FRAME1RESERVED1_POS (5)
3583#define BT_UART_MSG_2_FRAME1RESERVED1_MSK \
3584 (0x1<<BT_UART_MSG_2_FRAME1RESERVED1_POS)
3585#define BT_UART_MSG_2_FRAME1RESERVED2_POS (6)
3586#define BT_UART_MSG_2_FRAME1RESERVED2_MSK \
3587 (0x3<<BT_UART_MSG_2_FRAME1RESERVED2_POS)
3588
3589#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS (0)
3590#define BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_MSK \
3591 (0x3F<<BT_UART_MSG_2_FRAME2AGGTRAFFICLOAD_POS)
3592#define BT_UART_MSG_2_FRAME2RESERVED_POS (6)
3593#define BT_UART_MSG_2_FRAME2RESERVED_MSK \
3594 (0x3<<BT_UART_MSG_2_FRAME2RESERVED_POS)
3595
3596#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS (0)
3597#define BT_UART_MSG_2_FRAME3BRLASTTXPOWER_MSK \
3598 (0xF<<BT_UART_MSG_2_FRAME3BRLASTTXPOWER_POS)
3599#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS (4)
3600#define BT_UART_MSG_2_FRAME3INQPAGESRMODE_MSK \
3601 (0x1<<BT_UART_MSG_2_FRAME3INQPAGESRMODE_POS)
3602#define BT_UART_MSG_2_FRAME3LEMASTER_POS (5)
3603#define BT_UART_MSG_2_FRAME3LEMASTER_MSK \
3604 (0x1<<BT_UART_MSG_2_FRAME3LEMASTER_POS)
3605#define BT_UART_MSG_2_FRAME3RESERVED_POS (6)
3606#define BT_UART_MSG_2_FRAME3RESERVED_MSK \
3607 (0x3<<BT_UART_MSG_2_FRAME3RESERVED_POS)
3608
3609#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS (0)
3610#define BT_UART_MSG_2_FRAME4LELASTTXPOWER_MSK \
3611 (0xF<<BT_UART_MSG_2_FRAME4LELASTTXPOWER_POS)
3612#define BT_UART_MSG_2_FRAME4NUMLECONN_POS (4)
3613#define BT_UART_MSG_2_FRAME4NUMLECONN_MSK \
3614 (0x3<<BT_UART_MSG_2_FRAME4NUMLECONN_POS)
3615#define BT_UART_MSG_2_FRAME4RESERVED_POS (6)
3616#define BT_UART_MSG_2_FRAME4RESERVED_MSK \
3617 (0x3<<BT_UART_MSG_2_FRAME4RESERVED_POS)
3618
3619#define BT_UART_MSG_2_FRAME5BTMINRSSI_POS (0)
3620#define BT_UART_MSG_2_FRAME5BTMINRSSI_MSK \
3621 (0xF<<BT_UART_MSG_2_FRAME5BTMINRSSI_POS)
3622#define BT_UART_MSG_2_FRAME5LESCANINITMODE_POS (4)
3623#define BT_UART_MSG_2_FRAME5LESCANINITMODE_MSK \
3624 (0x1<<BT_UART_MSG_2_FRAME5LESCANINITMODE_POS)
3625#define BT_UART_MSG_2_FRAME5LEADVERMODE_POS (5)
3626#define BT_UART_MSG_2_FRAME5LEADVERMODE_MSK \
3627 (0x1<<BT_UART_MSG_2_FRAME5LEADVERMODE_POS)
3628#define BT_UART_MSG_2_FRAME5RESERVED_POS (6)
3629#define BT_UART_MSG_2_FRAME5RESERVED_MSK \
3630 (0x3<<BT_UART_MSG_2_FRAME5RESERVED_POS)
3631
3632#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS (0)
3633#define BT_UART_MSG_2_FRAME6LECONNINTERVAL_MSK \
3634 (0x1F<<BT_UART_MSG_2_FRAME6LECONNINTERVAL_POS)
3635#define BT_UART_MSG_2_FRAME6RFU_POS (5)
3636#define BT_UART_MSG_2_FRAME6RFU_MSK \
3637 (0x1<<BT_UART_MSG_2_FRAME6RFU_POS)
3638#define BT_UART_MSG_2_FRAME6RESERVED_POS (6)
3639#define BT_UART_MSG_2_FRAME6RESERVED_MSK \
3640 (0x3<<BT_UART_MSG_2_FRAME6RESERVED_POS)
3641
3642#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS (0)
3643#define BT_UART_MSG_2_FRAME7LECONNSLAVELAT_MSK \
3644 (0x7<<BT_UART_MSG_2_FRAME7LECONNSLAVELAT_POS)
3645#define BT_UART_MSG_2_FRAME7LEPROFILE1_POS (3)
3646#define BT_UART_MSG_2_FRAME7LEPROFILE1_MSK \
3647 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE1_POS)
3648#define BT_UART_MSG_2_FRAME7LEPROFILE2_POS (4)
3649#define BT_UART_MSG_2_FRAME7LEPROFILE2_MSK \
3650 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILE2_POS)
3651#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS (5)
3652#define BT_UART_MSG_2_FRAME7LEPROFILEOTHER_MSK \
3653 (0x1<<BT_UART_MSG_2_FRAME7LEPROFILEOTHER_POS)
3654#define BT_UART_MSG_2_FRAME7RESERVED_POS (6)
3655#define BT_UART_MSG_2_FRAME7RESERVED_MSK \
3656 (0x3<<BT_UART_MSG_2_FRAME7RESERVED_POS)
3657
3658
3659#define BT_ENABLE_REDUCED_TXPOWER_THRESHOLD (-62)
3660#define BT_DISABLE_REDUCED_TXPOWER_THRESHOLD (-65)
3661
3662struct iwl_bt_uart_msg {
3663 u8 header;
3664 u8 frame1;
3665 u8 frame2;
3666 u8 frame3;
3667 u8 frame4;
3668 u8 frame5;
3669 u8 frame6;
3670 u8 frame7;
3671} __packed;
3672
3673struct iwl_bt_coex_profile_notif {
3674 struct iwl_bt_uart_msg last_bt_uart_msg;
3675 u8 bt_status;
3676 u8 bt_traffic_load;
3677 u8 bt_ci_compliance;
3678 u8 reserved;
3679} __packed;
3680
3681#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_POS 0
3682#define IWL_BT_COEX_PRIO_TBL_SHARED_ANTENNA_MSK 0x1
3683#define IWL_BT_COEX_PRIO_TBL_PRIO_POS 1
3684#define IWL_BT_COEX_PRIO_TBL_PRIO_MASK 0x0e
3685#define IWL_BT_COEX_PRIO_TBL_RESERVED_POS 4
3686#define IWL_BT_COEX_PRIO_TBL_RESERVED_MASK 0xf0
3687#define IWL_BT_COEX_PRIO_TBL_PRIO_SHIFT 1
3688
3689
3690
3691
3692
3693enum bt_coex_prio_table_events {
3694 BT_COEX_PRIO_TBL_EVT_INIT_CALIB1 = 0,
3695 BT_COEX_PRIO_TBL_EVT_INIT_CALIB2 = 1,
3696 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW1 = 2,
3697 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_LOW2 = 3,
3698 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH1 = 4,
3699 BT_COEX_PRIO_TBL_EVT_PERIODIC_CALIB_HIGH2 = 5,
3700 BT_COEX_PRIO_TBL_EVT_DTIM = 6,
3701 BT_COEX_PRIO_TBL_EVT_SCAN52 = 7,
3702 BT_COEX_PRIO_TBL_EVT_SCAN24 = 8,
3703 BT_COEX_PRIO_TBL_EVT_RESERVED0 = 9,
3704 BT_COEX_PRIO_TBL_EVT_RESERVED1 = 10,
3705 BT_COEX_PRIO_TBL_EVT_RESERVED2 = 11,
3706 BT_COEX_PRIO_TBL_EVT_RESERVED3 = 12,
3707 BT_COEX_PRIO_TBL_EVT_RESERVED4 = 13,
3708 BT_COEX_PRIO_TBL_EVT_RESERVED5 = 14,
3709 BT_COEX_PRIO_TBL_EVT_RESERVED6 = 15,
3710
3711 BT_COEX_PRIO_TBL_EVT_MAX,
3712};
3713
3714enum bt_coex_prio_table_priorities {
3715 BT_COEX_PRIO_TBL_DISABLED = 0,
3716 BT_COEX_PRIO_TBL_PRIO_LOW = 1,
3717 BT_COEX_PRIO_TBL_PRIO_HIGH = 2,
3718 BT_COEX_PRIO_TBL_PRIO_BYPASS = 3,
3719 BT_COEX_PRIO_TBL_PRIO_COEX_OFF = 4,
3720 BT_COEX_PRIO_TBL_PRIO_COEX_ON = 5,
3721 BT_COEX_PRIO_TBL_PRIO_RSRVD1 = 6,
3722 BT_COEX_PRIO_TBL_PRIO_RSRVD2 = 7,
3723 BT_COEX_PRIO_TBL_MAX,
3724};
3725
3726struct iwl_bt_coex_prio_table_cmd {
3727 u8 prio_tbl[BT_COEX_PRIO_TBL_EVT_MAX];
3728} __packed;
3729
3730#define IWL_BT_COEX_ENV_CLOSE 0
3731#define IWL_BT_COEX_ENV_OPEN 1
3732
3733
3734
3735
3736struct iwl_bt_coex_prot_env_cmd {
3737 u8 action;
3738 u8 type;
3739 u8 reserved[2];
3740} __packed;
3741
3742
3743
3744
3745enum iwlagn_d3_wakeup_filters {
3746 IWLAGN_D3_WAKEUP_RFKILL = BIT(0),
3747 IWLAGN_D3_WAKEUP_SYSASSERT = BIT(1),
3748};
3749
3750struct iwlagn_d3_config_cmd {
3751 __le32 min_sleep_time;
3752 __le32 wakeup_flags;
3753} __packed;
3754
3755
3756
3757
3758#define IWLAGN_WOWLAN_MIN_PATTERN_LEN 16
3759#define IWLAGN_WOWLAN_MAX_PATTERN_LEN 128
3760
3761struct iwlagn_wowlan_pattern {
3762 u8 mask[IWLAGN_WOWLAN_MAX_PATTERN_LEN / 8];
3763 u8 pattern[IWLAGN_WOWLAN_MAX_PATTERN_LEN];
3764 u8 mask_size;
3765 u8 pattern_size;
3766 __le16 reserved;
3767} __packed;
3768
3769#define IWLAGN_WOWLAN_MAX_PATTERNS 20
3770
3771struct iwlagn_wowlan_patterns_cmd {
3772 __le32 n_patterns;
3773 struct iwlagn_wowlan_pattern patterns[];
3774} __packed;
3775
3776
3777
3778
3779enum iwlagn_wowlan_wakeup_filters {
3780 IWLAGN_WOWLAN_WAKEUP_MAGIC_PACKET = BIT(0),
3781 IWLAGN_WOWLAN_WAKEUP_PATTERN_MATCH = BIT(1),
3782 IWLAGN_WOWLAN_WAKEUP_BEACON_MISS = BIT(2),
3783 IWLAGN_WOWLAN_WAKEUP_LINK_CHANGE = BIT(3),
3784 IWLAGN_WOWLAN_WAKEUP_GTK_REKEY_FAIL = BIT(4),
3785 IWLAGN_WOWLAN_WAKEUP_EAP_IDENT_REQ = BIT(5),
3786 IWLAGN_WOWLAN_WAKEUP_4WAY_HANDSHAKE = BIT(6),
3787 IWLAGN_WOWLAN_WAKEUP_ALWAYS = BIT(7),
3788 IWLAGN_WOWLAN_WAKEUP_ENABLE_NET_DETECT = BIT(8),
3789};
3790
3791struct iwlagn_wowlan_wakeup_filter_cmd {
3792 __le32 enabled;
3793 __le16 non_qos_seq;
3794 __le16 reserved;
3795 __le16 qos_seq[8];
3796};
3797
3798
3799
3800
3801#define IWLAGN_NUM_RSC 16
3802
3803struct tkip_sc {
3804 __le16 iv16;
3805 __le16 pad;
3806 __le32 iv32;
3807} __packed;
3808
3809struct iwlagn_tkip_rsc_tsc {
3810 struct tkip_sc unicast_rsc[IWLAGN_NUM_RSC];
3811 struct tkip_sc multicast_rsc[IWLAGN_NUM_RSC];
3812 struct tkip_sc tsc;
3813} __packed;
3814
3815struct aes_sc {
3816 __le64 pn;
3817} __packed;
3818
3819struct iwlagn_aes_rsc_tsc {
3820 struct aes_sc unicast_rsc[IWLAGN_NUM_RSC];
3821 struct aes_sc multicast_rsc[IWLAGN_NUM_RSC];
3822 struct aes_sc tsc;
3823} __packed;
3824
3825union iwlagn_all_tsc_rsc {
3826 struct iwlagn_tkip_rsc_tsc tkip;
3827 struct iwlagn_aes_rsc_tsc aes;
3828};
3829
3830struct iwlagn_wowlan_rsc_tsc_params_cmd {
3831 union iwlagn_all_tsc_rsc all_tsc_rsc;
3832} __packed;
3833
3834
3835
3836
3837#define IWLAGN_MIC_KEY_SIZE 8
3838#define IWLAGN_P1K_SIZE 5
3839struct iwlagn_mic_keys {
3840 u8 tx[IWLAGN_MIC_KEY_SIZE];
3841 u8 rx_unicast[IWLAGN_MIC_KEY_SIZE];
3842 u8 rx_mcast[IWLAGN_MIC_KEY_SIZE];
3843} __packed;
3844
3845struct iwlagn_p1k_cache {
3846 __le16 p1k[IWLAGN_P1K_SIZE];
3847} __packed;
3848
3849#define IWLAGN_NUM_RX_P1K_CACHE 2
3850
3851struct iwlagn_wowlan_tkip_params_cmd {
3852 struct iwlagn_mic_keys mic_keys;
3853 struct iwlagn_p1k_cache tx;
3854 struct iwlagn_p1k_cache rx_uni[IWLAGN_NUM_RX_P1K_CACHE];
3855 struct iwlagn_p1k_cache rx_multi[IWLAGN_NUM_RX_P1K_CACHE];
3856} __packed;
3857
3858
3859
3860
3861
3862#define IWLAGN_KCK_MAX_SIZE 32
3863#define IWLAGN_KEK_MAX_SIZE 32
3864
3865struct iwlagn_wowlan_kek_kck_material_cmd {
3866 u8 kck[IWLAGN_KCK_MAX_SIZE];
3867 u8 kek[IWLAGN_KEK_MAX_SIZE];
3868 __le16 kck_len;
3869 __le16 kek_len;
3870 __le64 replay_ctr;
3871} __packed;
3872
3873#define RF_KILL_INDICATOR_FOR_WOWLAN 0x87
3874
3875
3876
3877
3878struct iwlagn_wowlan_status {
3879 __le64 replay_ctr;
3880 __le32 rekey_status;
3881 __le32 wakeup_reason;
3882 u8 pattern_number;
3883 u8 reserved1;
3884 __le16 qos_seq_ctr[8];
3885 __le16 non_qos_seq_ctr;
3886 __le16 reserved2;
3887 union iwlagn_all_tsc_rsc tsc_rsc;
3888 __le16 reserved3;
3889} __packed;
3890
3891
3892
3893
3894
3895
3896
3897
3898#define IWL_MIN_SLOT_TIME 20
3899
3900
3901
3902
3903
3904
3905
3906
3907struct iwl_wipan_slot {
3908 __le16 width;
3909 u8 type;
3910 u8 reserved;
3911} __packed;
3912
3913#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_CTS BIT(1)
3914#define IWL_WIPAN_PARAMS_FLG_LEAVE_CHANNEL_QUIET BIT(2)
3915#define IWL_WIPAN_PARAMS_FLG_SLOTTED_MODE BIT(3)
3916#define IWL_WIPAN_PARAMS_FLG_FILTER_BEACON_NOTIF BIT(4)
3917#define IWL_WIPAN_PARAMS_FLG_FULL_SLOTTED_MODE BIT(5)
3918
3919
3920
3921
3922
3923
3924
3925
3926
3927
3928
3929
3930
3931
3932
3933
3934struct iwl_wipan_params_cmd {
3935 __le16 flags;
3936 u8 reserved;
3937 u8 num_slots;
3938 struct iwl_wipan_slot slots[10];
3939} __packed;
3940
3941
3942
3943
3944
3945
3946
3947
3948
3949struct iwl_wipan_p2p_channel_switch_cmd {
3950 __le16 channel;
3951 __le16 reserved;
3952};
3953
3954
3955
3956
3957
3958
3959
3960
3961
3962
3963
3964
3965struct iwl_wipan_noa_descriptor {
3966 u8 count;
3967 __le32 duration;
3968 __le32 interval;
3969 __le32 starttime;
3970} __packed;
3971
3972struct iwl_wipan_noa_attribute {
3973 u8 id;
3974 __le16 length;
3975 u8 index;
3976 u8 ct_window;
3977 struct iwl_wipan_noa_descriptor descr0, descr1;
3978 u8 reserved;
3979} __packed;
3980
3981struct iwl_wipan_noa_notification {
3982 u32 noa_active;
3983 struct iwl_wipan_noa_attribute noa_attribute;
3984} __packed;
3985
3986#endif
3987