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16#include <linux/pci.h>
17#include <linux/slab.h>
18#include <linux/firmware.h>
19#include <linux/etherdevice.h>
20#include <linux/delay.h>
21#include <linux/completion.h>
22#include <linux/module.h>
23#include <net/mac80211.h>
24
25#include "p54.h"
26#include "lmac.h"
27#include "p54pci.h"
28
29MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
30MODULE_DESCRIPTION("Prism54 PCI wireless driver");
31MODULE_LICENSE("GPL");
32MODULE_ALIAS("prism54pci");
33MODULE_FIRMWARE("isl3886pci");
34
35static const struct pci_device_id p54p_table[] = {
36
37 { PCI_DEVICE(0x1260, 0x3890) },
38
39 { PCI_DEVICE(0x10b7, 0x6001) },
40
41 { PCI_DEVICE(0x1260, 0x3877) },
42
43 { PCI_DEVICE(0x1260, 0x3886) },
44
45 { PCI_DEVICE(0x1260, 0xffff) },
46 { },
47};
48
49MODULE_DEVICE_TABLE(pci, p54p_table);
50
51static int p54p_upload_firmware(struct ieee80211_hw *dev)
52{
53 struct p54p_priv *priv = dev->priv;
54 __le32 reg;
55 int err;
56 __le32 *data;
57 u32 remains, left, device_addr;
58
59 P54P_WRITE(int_enable, cpu_to_le32(0));
60 P54P_READ(int_enable);
61 udelay(10);
62
63 reg = P54P_READ(ctrl_stat);
64 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
65 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RAMBOOT);
66 P54P_WRITE(ctrl_stat, reg);
67 P54P_READ(ctrl_stat);
68 udelay(10);
69
70 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
71 P54P_WRITE(ctrl_stat, reg);
72 wmb();
73 udelay(10);
74
75 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
76 P54P_WRITE(ctrl_stat, reg);
77 wmb();
78
79
80 mdelay(10);
81
82 err = p54_parse_firmware(dev, priv->firmware);
83 if (err)
84 return err;
85
86 if (priv->common.fw_interface != FW_LM86) {
87 dev_err(&priv->pdev->dev, "wrong firmware, "
88 "please get a LM86(PCI) firmware a try again.\n");
89 return -EINVAL;
90 }
91
92 data = (__le32 *) priv->firmware->data;
93 remains = priv->firmware->size;
94 device_addr = ISL38XX_DEV_FIRMWARE_ADDR;
95 while (remains) {
96 u32 i = 0;
97 left = min((u32)0x1000, remains);
98 P54P_WRITE(direct_mem_base, cpu_to_le32(device_addr));
99 P54P_READ(int_enable);
100
101 device_addr += 0x1000;
102 while (i < left) {
103 P54P_WRITE(direct_mem_win[i], *data++);
104 i += sizeof(u32);
105 }
106
107 remains -= left;
108 P54P_READ(int_enable);
109 }
110
111 reg = P54P_READ(ctrl_stat);
112 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_CLKRUN);
113 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
114 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RAMBOOT);
115 P54P_WRITE(ctrl_stat, reg);
116 P54P_READ(ctrl_stat);
117 udelay(10);
118
119 reg |= cpu_to_le32(ISL38XX_CTRL_STAT_RESET);
120 P54P_WRITE(ctrl_stat, reg);
121 wmb();
122 udelay(10);
123
124 reg &= cpu_to_le32(~ISL38XX_CTRL_STAT_RESET);
125 P54P_WRITE(ctrl_stat, reg);
126 wmb();
127 udelay(10);
128
129
130 mdelay(100);
131
132 return 0;
133}
134
135static void p54p_refill_rx_ring(struct ieee80211_hw *dev,
136 int ring_index, struct p54p_desc *ring, u32 ring_limit,
137 struct sk_buff **rx_buf, u32 index)
138{
139 struct p54p_priv *priv = dev->priv;
140 struct p54p_ring_control *ring_control = priv->ring_control;
141 u32 limit, idx, i;
142
143 idx = le32_to_cpu(ring_control->host_idx[ring_index]);
144 limit = idx;
145 limit -= index;
146 limit = ring_limit - limit;
147
148 i = idx % ring_limit;
149 while (limit-- > 1) {
150 struct p54p_desc *desc = &ring[i];
151
152 if (!desc->host_addr) {
153 struct sk_buff *skb;
154 dma_addr_t mapping;
155 skb = dev_alloc_skb(priv->common.rx_mtu + 32);
156 if (!skb)
157 break;
158
159 mapping = pci_map_single(priv->pdev,
160 skb_tail_pointer(skb),
161 priv->common.rx_mtu + 32,
162 PCI_DMA_FROMDEVICE);
163
164 if (pci_dma_mapping_error(priv->pdev, mapping)) {
165 dev_kfree_skb_any(skb);
166 dev_err(&priv->pdev->dev,
167 "RX DMA Mapping error\n");
168 break;
169 }
170
171 desc->host_addr = cpu_to_le32(mapping);
172 desc->device_addr = 0;
173 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
174 desc->flags = 0;
175 rx_buf[i] = skb;
176 }
177
178 i++;
179 idx++;
180 i %= ring_limit;
181 }
182
183 wmb();
184 ring_control->host_idx[ring_index] = cpu_to_le32(idx);
185}
186
187static void p54p_check_rx_ring(struct ieee80211_hw *dev, u32 *index,
188 int ring_index, struct p54p_desc *ring, u32 ring_limit,
189 struct sk_buff **rx_buf)
190{
191 struct p54p_priv *priv = dev->priv;
192 struct p54p_ring_control *ring_control = priv->ring_control;
193 struct p54p_desc *desc;
194 u32 idx, i;
195
196 i = (*index) % ring_limit;
197 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
198 idx %= ring_limit;
199 while (i != idx) {
200 u16 len;
201 struct sk_buff *skb;
202 dma_addr_t dma_addr;
203 desc = &ring[i];
204 len = le16_to_cpu(desc->len);
205 skb = rx_buf[i];
206
207 if (!skb) {
208 i++;
209 i %= ring_limit;
210 continue;
211 }
212
213 if (unlikely(len > priv->common.rx_mtu)) {
214 if (net_ratelimit())
215 dev_err(&priv->pdev->dev, "rx'd frame size "
216 "exceeds length threshold.\n");
217
218 len = priv->common.rx_mtu;
219 }
220 dma_addr = le32_to_cpu(desc->host_addr);
221 pci_dma_sync_single_for_cpu(priv->pdev, dma_addr,
222 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
223 skb_put(skb, len);
224
225 if (p54_rx(dev, skb)) {
226 pci_unmap_single(priv->pdev, dma_addr,
227 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
228 rx_buf[i] = NULL;
229 desc->host_addr = cpu_to_le32(0);
230 } else {
231 skb_trim(skb, 0);
232 pci_dma_sync_single_for_device(priv->pdev, dma_addr,
233 priv->common.rx_mtu + 32, PCI_DMA_FROMDEVICE);
234 desc->len = cpu_to_le16(priv->common.rx_mtu + 32);
235 }
236
237 i++;
238 i %= ring_limit;
239 }
240
241 p54p_refill_rx_ring(dev, ring_index, ring, ring_limit, rx_buf, *index);
242}
243
244static void p54p_check_tx_ring(struct ieee80211_hw *dev, u32 *index,
245 int ring_index, struct p54p_desc *ring, u32 ring_limit,
246 struct sk_buff **tx_buf)
247{
248 struct p54p_priv *priv = dev->priv;
249 struct p54p_ring_control *ring_control = priv->ring_control;
250 struct p54p_desc *desc;
251 struct sk_buff *skb;
252 u32 idx, i;
253
254 i = (*index) % ring_limit;
255 (*index) = idx = le32_to_cpu(ring_control->device_idx[ring_index]);
256 idx %= ring_limit;
257
258 while (i != idx) {
259 desc = &ring[i];
260
261 skb = tx_buf[i];
262 tx_buf[i] = NULL;
263
264 pci_unmap_single(priv->pdev, le32_to_cpu(desc->host_addr),
265 le16_to_cpu(desc->len), PCI_DMA_TODEVICE);
266
267 desc->host_addr = 0;
268 desc->device_addr = 0;
269 desc->len = 0;
270 desc->flags = 0;
271
272 if (skb && FREE_AFTER_TX(skb))
273 p54_free_skb(dev, skb);
274
275 i++;
276 i %= ring_limit;
277 }
278}
279
280static void p54p_tasklet(unsigned long dev_id)
281{
282 struct ieee80211_hw *dev = (struct ieee80211_hw *)dev_id;
283 struct p54p_priv *priv = dev->priv;
284 struct p54p_ring_control *ring_control = priv->ring_control;
285
286 p54p_check_tx_ring(dev, &priv->tx_idx_mgmt, 3, ring_control->tx_mgmt,
287 ARRAY_SIZE(ring_control->tx_mgmt),
288 priv->tx_buf_mgmt);
289
290 p54p_check_tx_ring(dev, &priv->tx_idx_data, 1, ring_control->tx_data,
291 ARRAY_SIZE(ring_control->tx_data),
292 priv->tx_buf_data);
293
294 p54p_check_rx_ring(dev, &priv->rx_idx_mgmt, 2, ring_control->rx_mgmt,
295 ARRAY_SIZE(ring_control->rx_mgmt), priv->rx_buf_mgmt);
296
297 p54p_check_rx_ring(dev, &priv->rx_idx_data, 0, ring_control->rx_data,
298 ARRAY_SIZE(ring_control->rx_data), priv->rx_buf_data);
299
300 wmb();
301 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
302}
303
304static irqreturn_t p54p_interrupt(int irq, void *dev_id)
305{
306 struct ieee80211_hw *dev = dev_id;
307 struct p54p_priv *priv = dev->priv;
308 __le32 reg;
309
310 reg = P54P_READ(int_ident);
311 if (unlikely(reg == cpu_to_le32(0xFFFFFFFF))) {
312 goto out;
313 }
314 P54P_WRITE(int_ack, reg);
315
316 reg &= P54P_READ(int_enable);
317
318 if (reg & cpu_to_le32(ISL38XX_INT_IDENT_UPDATE))
319 tasklet_schedule(&priv->tasklet);
320 else if (reg & cpu_to_le32(ISL38XX_INT_IDENT_INIT))
321 complete(&priv->boot_comp);
322
323out:
324 return reg ? IRQ_HANDLED : IRQ_NONE;
325}
326
327static void p54p_tx(struct ieee80211_hw *dev, struct sk_buff *skb)
328{
329 unsigned long flags;
330 struct p54p_priv *priv = dev->priv;
331 struct p54p_ring_control *ring_control = priv->ring_control;
332 struct p54p_desc *desc;
333 dma_addr_t mapping;
334 u32 idx, i;
335
336 spin_lock_irqsave(&priv->lock, flags);
337 idx = le32_to_cpu(ring_control->host_idx[1]);
338 i = idx % ARRAY_SIZE(ring_control->tx_data);
339
340 mapping = pci_map_single(priv->pdev, skb->data, skb->len,
341 PCI_DMA_TODEVICE);
342 if (pci_dma_mapping_error(priv->pdev, mapping)) {
343 spin_unlock_irqrestore(&priv->lock, flags);
344 p54_free_skb(dev, skb);
345 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
346 return ;
347 }
348 priv->tx_buf_data[i] = skb;
349
350 desc = &ring_control->tx_data[i];
351 desc->host_addr = cpu_to_le32(mapping);
352 desc->device_addr = ((struct p54_hdr *)skb->data)->req_id;
353 desc->len = cpu_to_le16(skb->len);
354 desc->flags = 0;
355
356 wmb();
357 ring_control->host_idx[1] = cpu_to_le32(idx + 1);
358 spin_unlock_irqrestore(&priv->lock, flags);
359
360 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
361 P54P_READ(dev_int);
362}
363
364static void p54p_stop(struct ieee80211_hw *dev)
365{
366 struct p54p_priv *priv = dev->priv;
367 struct p54p_ring_control *ring_control = priv->ring_control;
368 unsigned int i;
369 struct p54p_desc *desc;
370
371 P54P_WRITE(int_enable, cpu_to_le32(0));
372 P54P_READ(int_enable);
373 udelay(10);
374
375 free_irq(priv->pdev->irq, dev);
376
377 tasklet_kill(&priv->tasklet);
378
379 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
380
381 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_data); i++) {
382 desc = &ring_control->rx_data[i];
383 if (desc->host_addr)
384 pci_unmap_single(priv->pdev,
385 le32_to_cpu(desc->host_addr),
386 priv->common.rx_mtu + 32,
387 PCI_DMA_FROMDEVICE);
388 kfree_skb(priv->rx_buf_data[i]);
389 priv->rx_buf_data[i] = NULL;
390 }
391
392 for (i = 0; i < ARRAY_SIZE(priv->rx_buf_mgmt); i++) {
393 desc = &ring_control->rx_mgmt[i];
394 if (desc->host_addr)
395 pci_unmap_single(priv->pdev,
396 le32_to_cpu(desc->host_addr),
397 priv->common.rx_mtu + 32,
398 PCI_DMA_FROMDEVICE);
399 kfree_skb(priv->rx_buf_mgmt[i]);
400 priv->rx_buf_mgmt[i] = NULL;
401 }
402
403 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_data); i++) {
404 desc = &ring_control->tx_data[i];
405 if (desc->host_addr)
406 pci_unmap_single(priv->pdev,
407 le32_to_cpu(desc->host_addr),
408 le16_to_cpu(desc->len),
409 PCI_DMA_TODEVICE);
410
411 p54_free_skb(dev, priv->tx_buf_data[i]);
412 priv->tx_buf_data[i] = NULL;
413 }
414
415 for (i = 0; i < ARRAY_SIZE(priv->tx_buf_mgmt); i++) {
416 desc = &ring_control->tx_mgmt[i];
417 if (desc->host_addr)
418 pci_unmap_single(priv->pdev,
419 le32_to_cpu(desc->host_addr),
420 le16_to_cpu(desc->len),
421 PCI_DMA_TODEVICE);
422
423 p54_free_skb(dev, priv->tx_buf_mgmt[i]);
424 priv->tx_buf_mgmt[i] = NULL;
425 }
426
427 memset(ring_control, 0, sizeof(*ring_control));
428}
429
430static int p54p_open(struct ieee80211_hw *dev)
431{
432 struct p54p_priv *priv = dev->priv;
433 int err;
434 long timeout;
435
436 init_completion(&priv->boot_comp);
437 err = request_irq(priv->pdev->irq, p54p_interrupt,
438 IRQF_SHARED, "p54pci", dev);
439 if (err) {
440 dev_err(&priv->pdev->dev, "failed to register IRQ handler\n");
441 return err;
442 }
443
444 memset(priv->ring_control, 0, sizeof(*priv->ring_control));
445 err = p54p_upload_firmware(dev);
446 if (err) {
447 free_irq(priv->pdev->irq, dev);
448 return err;
449 }
450 priv->rx_idx_data = priv->tx_idx_data = 0;
451 priv->rx_idx_mgmt = priv->tx_idx_mgmt = 0;
452
453 p54p_refill_rx_ring(dev, 0, priv->ring_control->rx_data,
454 ARRAY_SIZE(priv->ring_control->rx_data), priv->rx_buf_data, 0);
455
456 p54p_refill_rx_ring(dev, 2, priv->ring_control->rx_mgmt,
457 ARRAY_SIZE(priv->ring_control->rx_mgmt), priv->rx_buf_mgmt, 0);
458
459 P54P_WRITE(ring_control_base, cpu_to_le32(priv->ring_control_dma));
460 P54P_READ(ring_control_base);
461 wmb();
462 udelay(10);
463
464 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_INIT));
465 P54P_READ(int_enable);
466 wmb();
467 udelay(10);
468
469 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_RESET));
470 P54P_READ(dev_int);
471
472 timeout = wait_for_completion_interruptible_timeout(
473 &priv->boot_comp, HZ);
474 if (timeout <= 0) {
475 wiphy_err(dev->wiphy, "Cannot boot firmware!\n");
476 p54p_stop(dev);
477 return timeout ? -ERESTARTSYS : -ETIMEDOUT;
478 }
479
480 P54P_WRITE(int_enable, cpu_to_le32(ISL38XX_INT_IDENT_UPDATE));
481 P54P_READ(int_enable);
482 wmb();
483 udelay(10);
484
485 P54P_WRITE(dev_int, cpu_to_le32(ISL38XX_DEV_INT_UPDATE));
486 P54P_READ(dev_int);
487 wmb();
488 udelay(10);
489
490 return 0;
491}
492
493static void p54p_firmware_step2(const struct firmware *fw,
494 void *context)
495{
496 struct p54p_priv *priv = context;
497 struct ieee80211_hw *dev = priv->common.hw;
498 struct pci_dev *pdev = priv->pdev;
499 int err;
500
501 if (!fw) {
502 dev_err(&pdev->dev, "Cannot find firmware (isl3886pci)\n");
503 err = -ENOENT;
504 goto out;
505 }
506
507 priv->firmware = fw;
508
509 err = p54p_open(dev);
510 if (err)
511 goto out;
512 err = p54_read_eeprom(dev);
513 p54p_stop(dev);
514 if (err)
515 goto out;
516
517 err = p54_register_common(dev, &pdev->dev);
518 if (err)
519 goto out;
520
521out:
522
523 complete(&priv->fw_loaded);
524
525 if (err) {
526 struct device *parent = pdev->dev.parent;
527
528 if (parent)
529 device_lock(parent);
530
531
532
533
534
535
536 device_release_driver(&pdev->dev);
537
538 if (parent)
539 device_unlock(parent);
540 }
541
542 pci_dev_put(pdev);
543}
544
545static int p54p_probe(struct pci_dev *pdev,
546 const struct pci_device_id *id)
547{
548 struct p54p_priv *priv;
549 struct ieee80211_hw *dev;
550 unsigned long mem_addr, mem_len;
551 int err;
552
553 pci_dev_get(pdev);
554 err = pci_enable_device(pdev);
555 if (err) {
556 dev_err(&pdev->dev, "Cannot enable new PCI device\n");
557 return err;
558 }
559
560 mem_addr = pci_resource_start(pdev, 0);
561 mem_len = pci_resource_len(pdev, 0);
562 if (mem_len < sizeof(struct p54p_csr)) {
563 dev_err(&pdev->dev, "Too short PCI resources\n");
564 err = -ENODEV;
565 goto err_disable_dev;
566 }
567
568 err = pci_request_regions(pdev, "p54pci");
569 if (err) {
570 dev_err(&pdev->dev, "Cannot obtain PCI resources\n");
571 goto err_disable_dev;
572 }
573
574 err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
575 if (!err)
576 err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
577 if (err) {
578 dev_err(&pdev->dev, "No suitable DMA available\n");
579 goto err_free_reg;
580 }
581
582 pci_set_master(pdev);
583 pci_try_set_mwi(pdev);
584
585 pci_write_config_byte(pdev, 0x40, 0);
586 pci_write_config_byte(pdev, 0x41, 0);
587
588 dev = p54_init_common(sizeof(*priv));
589 if (!dev) {
590 dev_err(&pdev->dev, "ieee80211 alloc failed\n");
591 err = -ENOMEM;
592 goto err_free_reg;
593 }
594
595 priv = dev->priv;
596 priv->pdev = pdev;
597
598 init_completion(&priv->fw_loaded);
599 SET_IEEE80211_DEV(dev, &pdev->dev);
600 pci_set_drvdata(pdev, dev);
601
602 priv->map = ioremap(mem_addr, mem_len);
603 if (!priv->map) {
604 dev_err(&pdev->dev, "Cannot map device memory\n");
605 err = -ENOMEM;
606 goto err_free_dev;
607 }
608
609 priv->ring_control = pci_alloc_consistent(pdev, sizeof(*priv->ring_control),
610 &priv->ring_control_dma);
611 if (!priv->ring_control) {
612 dev_err(&pdev->dev, "Cannot allocate rings\n");
613 err = -ENOMEM;
614 goto err_iounmap;
615 }
616 priv->common.open = p54p_open;
617 priv->common.stop = p54p_stop;
618 priv->common.tx = p54p_tx;
619
620 spin_lock_init(&priv->lock);
621 tasklet_init(&priv->tasklet, p54p_tasklet, (unsigned long)dev);
622
623 err = request_firmware_nowait(THIS_MODULE, 1, "isl3886pci",
624 &priv->pdev->dev, GFP_KERNEL,
625 priv, p54p_firmware_step2);
626 if (!err)
627 return 0;
628
629 pci_free_consistent(pdev, sizeof(*priv->ring_control),
630 priv->ring_control, priv->ring_control_dma);
631
632 err_iounmap:
633 iounmap(priv->map);
634
635 err_free_dev:
636 p54_free_common(dev);
637
638 err_free_reg:
639 pci_release_regions(pdev);
640 err_disable_dev:
641 pci_disable_device(pdev);
642 pci_dev_put(pdev);
643 return err;
644}
645
646static void p54p_remove(struct pci_dev *pdev)
647{
648 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
649 struct p54p_priv *priv;
650
651 if (!dev)
652 return;
653
654 priv = dev->priv;
655 wait_for_completion(&priv->fw_loaded);
656 p54_unregister_common(dev);
657 release_firmware(priv->firmware);
658 pci_free_consistent(pdev, sizeof(*priv->ring_control),
659 priv->ring_control, priv->ring_control_dma);
660 iounmap(priv->map);
661 pci_release_regions(pdev);
662 pci_disable_device(pdev);
663 p54_free_common(dev);
664}
665
666#ifdef CONFIG_PM_SLEEP
667static int p54p_suspend(struct device *device)
668{
669 struct pci_dev *pdev = to_pci_dev(device);
670
671 pci_save_state(pdev);
672 pci_set_power_state(pdev, PCI_D3hot);
673 pci_disable_device(pdev);
674 return 0;
675}
676
677static int p54p_resume(struct device *device)
678{
679 struct pci_dev *pdev = to_pci_dev(device);
680 int err;
681
682 err = pci_reenable_device(pdev);
683 if (err)
684 return err;
685 return pci_set_power_state(pdev, PCI_D0);
686}
687
688static SIMPLE_DEV_PM_OPS(p54pci_pm_ops, p54p_suspend, p54p_resume);
689
690#define P54P_PM_OPS (&p54pci_pm_ops)
691#else
692#define P54P_PM_OPS (NULL)
693#endif
694
695static struct pci_driver p54p_driver = {
696 .name = "p54pci",
697 .id_table = p54p_table,
698 .probe = p54p_probe,
699 .remove = p54p_remove,
700 .driver.pm = P54P_PM_OPS,
701};
702
703module_pci_driver(p54p_driver);
704
