1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32#include <linux/delay.h>
33#include <linux/etherdevice.h>
34#include <linux/init.h>
35#include <linux/kernel.h>
36#include <linux/module.h>
37#include <linux/pci.h>
38#include <linux/eeprom_93cx6.h>
39
40#include "rt2x00.h"
41#include "rt2x00mmio.h"
42#include "rt2x00pci.h"
43#include "rt2800lib.h"
44#include "rt2800mmio.h"
45#include "rt2800.h"
46#include "rt2800pci.h"
47
48
49
50
51static bool modparam_nohwcrypt = false;
52module_param_named(nohwcrypt, modparam_nohwcrypt, bool, 0444);
53MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
54
55static bool rt2800pci_hwcrypt_disabled(struct rt2x00_dev *rt2x00dev)
56{
57 return modparam_nohwcrypt;
58}
59
60static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
61{
62 unsigned int i;
63 u32 reg;
64
65
66
67
68 if (rt2x00_is_soc(rt2x00dev))
69 return;
70
71 for (i = 0; i < 200; i++) {
72 reg = rt2x00mmio_register_read(rt2x00dev, H2M_MAILBOX_CID);
73
74 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
75 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
76 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
77 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
78 break;
79
80 udelay(REGISTER_BUSY_DELAY);
81 }
82
83 if (i == 200)
84 rt2x00_err(rt2x00dev, "MCU request failed, no response from hardware\n");
85
86 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
87 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
88}
89
90static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
91{
92 struct rt2x00_dev *rt2x00dev = eeprom->data;
93 u32 reg;
94
95 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
96
97 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
98 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
99 eeprom->reg_data_clock =
100 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
101 eeprom->reg_chip_select =
102 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
103}
104
105static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
106{
107 struct rt2x00_dev *rt2x00dev = eeprom->data;
108 u32 reg = 0;
109
110 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
111 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
112 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
113 !!eeprom->reg_data_clock);
114 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
115 !!eeprom->reg_chip_select);
116
117 rt2x00mmio_register_write(rt2x00dev, E2PROM_CSR, reg);
118}
119
120static int rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
121{
122 struct eeprom_93cx6 eeprom;
123 u32 reg;
124
125 reg = rt2x00mmio_register_read(rt2x00dev, E2PROM_CSR);
126
127 eeprom.data = rt2x00dev;
128 eeprom.register_read = rt2800pci_eepromregister_read;
129 eeprom.register_write = rt2800pci_eepromregister_write;
130 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
131 {
132 case 0:
133 eeprom.width = PCI_EEPROM_WIDTH_93C46;
134 break;
135 case 1:
136 eeprom.width = PCI_EEPROM_WIDTH_93C66;
137 break;
138 default:
139 eeprom.width = PCI_EEPROM_WIDTH_93C86;
140 break;
141 }
142 eeprom.reg_data_in = 0;
143 eeprom.reg_data_out = 0;
144 eeprom.reg_data_clock = 0;
145 eeprom.reg_chip_select = 0;
146
147 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
148 EEPROM_SIZE / sizeof(u16));
149
150 return 0;
151}
152
153static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
154{
155 return rt2800_efuse_detect(rt2x00dev);
156}
157
158static inline int rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
159{
160 return rt2800_read_eeprom_efuse(rt2x00dev);
161}
162
163
164
165
166static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
167{
168
169
170
171 if (rt2x00_rt(rt2x00dev, RT3290))
172 return FIRMWARE_RT3290;
173 else
174 return FIRMWARE_RT2860;
175}
176
177static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
178 const u8 *data, const size_t len)
179{
180 u32 reg;
181
182
183
184
185 reg = 0;
186 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
187 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
188
189
190
191
192 rt2x00mmio_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
193 data, len);
194
195 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
196 rt2x00mmio_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
197
198 rt2x00mmio_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
199 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
200
201 return 0;
202}
203
204
205
206
207static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
208{
209 int retval;
210
211 retval = rt2800mmio_enable_radio(rt2x00dev);
212 if (retval)
213 return retval;
214
215
216 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
217 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
218
219 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_RADIO_OFF, 0xff, 0x02);
220 rt2800pci_mcu_status(rt2x00dev, TOKEN_RADIO_OFF);
221
222 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP, 0, 0);
223 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
224
225 return retval;
226}
227
228static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
229 enum dev_state state)
230{
231 if (state == STATE_AWAKE) {
232 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKEUP,
233 0, 0x02);
234 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKEUP);
235 } else if (state == STATE_SLEEP) {
236 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
237 0xffffffff);
238 rt2x00mmio_register_write(rt2x00dev, H2M_MAILBOX_CID,
239 0xffffffff);
240 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, TOKEN_SLEEP,
241 0xff, 0x01);
242 }
243
244 return 0;
245}
246
247static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
248 enum dev_state state)
249{
250 int retval = 0;
251
252 switch (state) {
253 case STATE_RADIO_ON:
254 retval = rt2800pci_enable_radio(rt2x00dev);
255 break;
256 case STATE_RADIO_OFF:
257
258
259
260
261 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
262 break;
263 case STATE_RADIO_IRQ_ON:
264 case STATE_RADIO_IRQ_OFF:
265 rt2800mmio_toggle_irq(rt2x00dev, state);
266 break;
267 case STATE_DEEP_SLEEP:
268 case STATE_SLEEP:
269 case STATE_STANDBY:
270 case STATE_AWAKE:
271 retval = rt2800pci_set_state(rt2x00dev, state);
272 break;
273 default:
274 retval = -ENOTSUPP;
275 break;
276 }
277
278 if (unlikely(retval))
279 rt2x00_err(rt2x00dev, "Device failed to enter state %d (%d)\n",
280 state, retval);
281
282 return retval;
283}
284
285
286
287
288static int rt2800pci_read_eeprom(struct rt2x00_dev *rt2x00dev)
289{
290 int retval;
291
292 if (rt2800pci_efuse_detect(rt2x00dev))
293 retval = rt2800pci_read_eeprom_efuse(rt2x00dev);
294 else
295 retval = rt2800pci_read_eeprom_pci(rt2x00dev);
296
297 return retval;
298}
299
300static const struct ieee80211_ops rt2800pci_mac80211_ops = {
301 .tx = rt2x00mac_tx,
302 .start = rt2x00mac_start,
303 .stop = rt2x00mac_stop,
304 .add_interface = rt2x00mac_add_interface,
305 .remove_interface = rt2x00mac_remove_interface,
306 .config = rt2x00mac_config,
307 .configure_filter = rt2x00mac_configure_filter,
308 .set_key = rt2x00mac_set_key,
309 .sw_scan_start = rt2x00mac_sw_scan_start,
310 .sw_scan_complete = rt2x00mac_sw_scan_complete,
311 .get_stats = rt2x00mac_get_stats,
312 .get_key_seq = rt2800_get_key_seq,
313 .set_rts_threshold = rt2800_set_rts_threshold,
314 .sta_add = rt2x00mac_sta_add,
315 .sta_remove = rt2x00mac_sta_remove,
316 .bss_info_changed = rt2x00mac_bss_info_changed,
317 .conf_tx = rt2800_conf_tx,
318 .get_tsf = rt2800_get_tsf,
319 .rfkill_poll = rt2x00mac_rfkill_poll,
320 .ampdu_action = rt2800_ampdu_action,
321 .flush = rt2x00mac_flush,
322 .get_survey = rt2800_get_survey,
323 .get_ringparam = rt2x00mac_get_ringparam,
324 .tx_frames_pending = rt2x00mac_tx_frames_pending,
325};
326
327static const struct rt2800_ops rt2800pci_rt2800_ops = {
328 .register_read = rt2x00mmio_register_read,
329 .register_read_lock = rt2x00mmio_register_read,
330 .register_write = rt2x00mmio_register_write,
331 .register_write_lock = rt2x00mmio_register_write,
332 .register_multiread = rt2x00mmio_register_multiread,
333 .register_multiwrite = rt2x00mmio_register_multiwrite,
334 .regbusy_read = rt2x00mmio_regbusy_read,
335 .read_eeprom = rt2800pci_read_eeprom,
336 .hwcrypt_disabled = rt2800pci_hwcrypt_disabled,
337 .drv_write_firmware = rt2800pci_write_firmware,
338 .drv_init_registers = rt2800mmio_init_registers,
339 .drv_get_txwi = rt2800mmio_get_txwi,
340};
341
342static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
343 .irq_handler = rt2800mmio_interrupt,
344 .txstatus_tasklet = rt2800mmio_txstatus_tasklet,
345 .pretbtt_tasklet = rt2800mmio_pretbtt_tasklet,
346 .tbtt_tasklet = rt2800mmio_tbtt_tasklet,
347 .rxdone_tasklet = rt2800mmio_rxdone_tasklet,
348 .autowake_tasklet = rt2800mmio_autowake_tasklet,
349 .probe_hw = rt2800_probe_hw,
350 .get_firmware_name = rt2800pci_get_firmware_name,
351 .check_firmware = rt2800_check_firmware,
352 .load_firmware = rt2800_load_firmware,
353 .initialize = rt2x00mmio_initialize,
354 .uninitialize = rt2x00mmio_uninitialize,
355 .get_entry_state = rt2800mmio_get_entry_state,
356 .clear_entry = rt2800mmio_clear_entry,
357 .set_device_state = rt2800pci_set_device_state,
358 .rfkill_poll = rt2800_rfkill_poll,
359 .link_stats = rt2800_link_stats,
360 .reset_tuner = rt2800_reset_tuner,
361 .link_tuner = rt2800_link_tuner,
362 .gain_calibration = rt2800_gain_calibration,
363 .vco_calibration = rt2800_vco_calibration,
364 .start_queue = rt2800mmio_start_queue,
365 .kick_queue = rt2800mmio_kick_queue,
366 .stop_queue = rt2800mmio_stop_queue,
367 .flush_queue = rt2x00mmio_flush_queue,
368 .write_tx_desc = rt2800mmio_write_tx_desc,
369 .write_tx_data = rt2800_write_tx_data,
370 .write_beacon = rt2800_write_beacon,
371 .clear_beacon = rt2800_clear_beacon,
372 .fill_rxdone = rt2800mmio_fill_rxdone,
373 .config_shared_key = rt2800_config_shared_key,
374 .config_pairwise_key = rt2800_config_pairwise_key,
375 .config_filter = rt2800_config_filter,
376 .config_intf = rt2800_config_intf,
377 .config_erp = rt2800_config_erp,
378 .config_ant = rt2800_config_ant,
379 .config = rt2800_config,
380 .sta_add = rt2800_sta_add,
381 .sta_remove = rt2800_sta_remove,
382};
383
384static const struct rt2x00_ops rt2800pci_ops = {
385 .name = KBUILD_MODNAME,
386 .drv_data_size = sizeof(struct rt2800_drv_data),
387 .max_ap_intf = 8,
388 .eeprom_size = EEPROM_SIZE,
389 .rf_size = RF_SIZE,
390 .tx_queues = NUM_TX_QUEUES,
391 .queue_init = rt2800mmio_queue_init,
392 .lib = &rt2800pci_rt2x00_ops,
393 .drv = &rt2800pci_rt2800_ops,
394 .hw = &rt2800pci_mac80211_ops,
395#ifdef CONFIG_RT2X00_LIB_DEBUGFS
396 .debugfs = &rt2800_rt2x00debug,
397#endif
398};
399
400
401
402
403static const struct pci_device_id rt2800pci_device_table[] = {
404 { PCI_DEVICE(0x1814, 0x0601) },
405 { PCI_DEVICE(0x1814, 0x0681) },
406 { PCI_DEVICE(0x1814, 0x0701) },
407 { PCI_DEVICE(0x1814, 0x0781) },
408 { PCI_DEVICE(0x1814, 0x3090) },
409 { PCI_DEVICE(0x1814, 0x3091) },
410 { PCI_DEVICE(0x1814, 0x3092) },
411 { PCI_DEVICE(0x1432, 0x7708) },
412 { PCI_DEVICE(0x1432, 0x7727) },
413 { PCI_DEVICE(0x1432, 0x7728) },
414 { PCI_DEVICE(0x1432, 0x7738) },
415 { PCI_DEVICE(0x1432, 0x7748) },
416 { PCI_DEVICE(0x1432, 0x7758) },
417 { PCI_DEVICE(0x1432, 0x7768) },
418 { PCI_DEVICE(0x1462, 0x891a) },
419 { PCI_DEVICE(0x1a3b, 0x1059) },
420#ifdef CONFIG_RT2800PCI_RT3290
421 { PCI_DEVICE(0x1814, 0x3290) },
422#endif
423#ifdef CONFIG_RT2800PCI_RT33XX
424 { PCI_DEVICE(0x1814, 0x3390) },
425#endif
426#ifdef CONFIG_RT2800PCI_RT35XX
427 { PCI_DEVICE(0x1432, 0x7711) },
428 { PCI_DEVICE(0x1432, 0x7722) },
429 { PCI_DEVICE(0x1814, 0x3060) },
430 { PCI_DEVICE(0x1814, 0x3062) },
431 { PCI_DEVICE(0x1814, 0x3562) },
432 { PCI_DEVICE(0x1814, 0x3592) },
433 { PCI_DEVICE(0x1814, 0x3593) },
434 { PCI_DEVICE(0x1814, 0x359f) },
435#endif
436#ifdef CONFIG_RT2800PCI_RT53XX
437 { PCI_DEVICE(0x1814, 0x5360) },
438 { PCI_DEVICE(0x1814, 0x5362) },
439 { PCI_DEVICE(0x1814, 0x5390) },
440 { PCI_DEVICE(0x1814, 0x5392) },
441 { PCI_DEVICE(0x1814, 0x539a) },
442 { PCI_DEVICE(0x1814, 0x539b) },
443 { PCI_DEVICE(0x1814, 0x539f) },
444#endif
445 { 0, }
446};
447
448MODULE_AUTHOR(DRV_PROJECT);
449MODULE_VERSION(DRV_VERSION);
450MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
451MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
452MODULE_FIRMWARE(FIRMWARE_RT2860);
453MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
454MODULE_LICENSE("GPL");
455
456static int rt2800pci_probe(struct pci_dev *pci_dev,
457 const struct pci_device_id *id)
458{
459 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
460}
461
462static struct pci_driver rt2800pci_driver = {
463 .name = KBUILD_MODNAME,
464 .id_table = rt2800pci_device_table,
465 .probe = rt2800pci_probe,
466 .remove = rt2x00pci_remove,
467 .suspend = rt2x00pci_suspend,
468 .resume = rt2x00pci_resume,
469};
470
471module_pci_driver(rt2800pci_driver);
472
