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24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
45int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
46static bool rtl8xxxu_ht40_2g;
47static bool rtl8xxxu_dma_aggregation;
48static int rtl8xxxu_dma_agg_timeout = -1;
49static int rtl8xxxu_dma_agg_pages = -1;
50
51MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@gmail.com>");
52MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
53MODULE_LICENSE("GPL");
54MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
57MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
58MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
59MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
60MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
61MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin");
62MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin");
63
64module_param_named(debug, rtl8xxxu_debug, int, 0600);
65MODULE_PARM_DESC(debug, "Set debug mask");
66module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
67MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
68module_param_named(dma_aggregation, rtl8xxxu_dma_aggregation, bool, 0600);
69MODULE_PARM_DESC(dma_aggregation, "Enable DMA packet aggregation");
70module_param_named(dma_agg_timeout, rtl8xxxu_dma_agg_timeout, int, 0600);
71MODULE_PARM_DESC(dma_agg_timeout, "Set DMA aggregation timeout (range 1-127)");
72module_param_named(dma_agg_pages, rtl8xxxu_dma_agg_pages, int, 0600);
73MODULE_PARM_DESC(dma_agg_pages, "Set DMA aggregation pages (range 1-127, 0 to disable)");
74
75#define USB_VENDOR_ID_REALTEK 0x0bda
76#define RTL8XXXU_RX_URBS 32
77#define RTL8XXXU_RX_URB_PENDING_WATER 8
78#define RTL8XXXU_TX_URBS 64
79#define RTL8XXXU_TX_URB_LOW_WATER 25
80#define RTL8XXXU_TX_URB_HIGH_WATER 32
81
82static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
83 struct rtl8xxxu_rx_urb *rx_urb);
84
85static struct ieee80211_rate rtl8xxxu_rates[] = {
86 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
87 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
88 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
89 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
90 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
91 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
92 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
93 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
94 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
95 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
96 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
97 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
98};
99
100static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
101 { .band = NL80211_BAND_2GHZ, .center_freq = 2412,
102 .hw_value = 1, .max_power = 30 },
103 { .band = NL80211_BAND_2GHZ, .center_freq = 2417,
104 .hw_value = 2, .max_power = 30 },
105 { .band = NL80211_BAND_2GHZ, .center_freq = 2422,
106 .hw_value = 3, .max_power = 30 },
107 { .band = NL80211_BAND_2GHZ, .center_freq = 2427,
108 .hw_value = 4, .max_power = 30 },
109 { .band = NL80211_BAND_2GHZ, .center_freq = 2432,
110 .hw_value = 5, .max_power = 30 },
111 { .band = NL80211_BAND_2GHZ, .center_freq = 2437,
112 .hw_value = 6, .max_power = 30 },
113 { .band = NL80211_BAND_2GHZ, .center_freq = 2442,
114 .hw_value = 7, .max_power = 30 },
115 { .band = NL80211_BAND_2GHZ, .center_freq = 2447,
116 .hw_value = 8, .max_power = 30 },
117 { .band = NL80211_BAND_2GHZ, .center_freq = 2452,
118 .hw_value = 9, .max_power = 30 },
119 { .band = NL80211_BAND_2GHZ, .center_freq = 2457,
120 .hw_value = 10, .max_power = 30 },
121 { .band = NL80211_BAND_2GHZ, .center_freq = 2462,
122 .hw_value = 11, .max_power = 30 },
123 { .band = NL80211_BAND_2GHZ, .center_freq = 2467,
124 .hw_value = 12, .max_power = 30 },
125 { .band = NL80211_BAND_2GHZ, .center_freq = 2472,
126 .hw_value = 13, .max_power = 30 },
127 { .band = NL80211_BAND_2GHZ, .center_freq = 2484,
128 .hw_value = 14, .max_power = 30 }
129};
130
131static struct ieee80211_supported_band rtl8xxxu_supported_band = {
132 .channels = rtl8xxxu_channels_2g,
133 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
134 .bitrates = rtl8xxxu_rates,
135 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
136};
137
138struct rtl8xxxu_reg8val rtl8xxxu_gen1_mac_init_table[] = {
139 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
140 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
141 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
142 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
143 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
144 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
145 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
146 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
147 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
148 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
149 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
150 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
151 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
152 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
153 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
154 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
155 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
156 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
157 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
158 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
159 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
160 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
161};
162
163static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
164 {0x800, 0x80040000}, {0x804, 0x00000003},
165 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
166 {0x810, 0x10001331}, {0x814, 0x020c3d10},
167 {0x818, 0x02200385}, {0x81c, 0x00000000},
168 {0x820, 0x01000100}, {0x824, 0x00390004},
169 {0x828, 0x00000000}, {0x82c, 0x00000000},
170 {0x830, 0x00000000}, {0x834, 0x00000000},
171 {0x838, 0x00000000}, {0x83c, 0x00000000},
172 {0x840, 0x00010000}, {0x844, 0x00000000},
173 {0x848, 0x00000000}, {0x84c, 0x00000000},
174 {0x850, 0x00000000}, {0x854, 0x00000000},
175 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
176 {0x860, 0x66f60110}, {0x864, 0x061f0130},
177 {0x868, 0x00000000}, {0x86c, 0x32323200},
178 {0x870, 0x07000760}, {0x874, 0x22004000},
179 {0x878, 0x00000808}, {0x87c, 0x00000000},
180 {0x880, 0xc0083070}, {0x884, 0x000004d5},
181 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
182 {0x890, 0x00000800}, {0x894, 0xfffffffe},
183 {0x898, 0x40302010}, {0x89c, 0x00706050},
184 {0x900, 0x00000000}, {0x904, 0x00000023},
185 {0x908, 0x00000000}, {0x90c, 0x81121111},
186 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
187 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
188 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
189 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
190 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
191 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
192 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
193 {0xa78, 0x00000900},
194 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
195 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
196 {0xc10, 0x08800000}, {0xc14, 0x40000100},
197 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
198 {0xc20, 0x00000000}, {0xc24, 0x00000000},
199 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
200 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
201 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
202 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
203 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
204 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
205 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
206 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
207 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
208 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
209 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
210 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
211 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
212 {0xc90, 0x00121820}, {0xc94, 0x00000000},
213 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
214 {0xca0, 0x00000000}, {0xca4, 0x00000080},
215 {0xca8, 0x00000000}, {0xcac, 0x00000000},
216 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
217 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
218 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
219 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
220 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
221 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
222 {0xce0, 0x00222222}, {0xce4, 0x00000000},
223 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
224 {0xd00, 0x00080740}, {0xd04, 0x00020401},
225 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
226 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
227 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
228 {0xd30, 0x00000000}, {0xd34, 0x80608000},
229 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
230 {0xd40, 0x00000000}, {0xd44, 0x00000000},
231 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
232 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
233 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
234 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
235 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
236 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
237 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
238 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
239 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
240 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
241 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
242 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
243 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
244 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
245 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
246 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
247 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
248 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
249 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
250 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
251 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
252 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
253 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
254 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
255 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
256 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
257 {0xf00, 0x00000300},
258 {0xffff, 0xffffffff},
259};
260
261static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
262 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
263 {0x800, 0x80040002}, {0x804, 0x00000003},
264 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
265 {0x810, 0x10000330}, {0x814, 0x020c3d10},
266 {0x818, 0x02200385}, {0x81c, 0x00000000},
267 {0x820, 0x01000100}, {0x824, 0x00390004},
268 {0x828, 0x01000100}, {0x82c, 0x00390004},
269 {0x830, 0x27272727}, {0x834, 0x27272727},
270 {0x838, 0x27272727}, {0x83c, 0x27272727},
271 {0x840, 0x00010000}, {0x844, 0x00010000},
272 {0x848, 0x27272727}, {0x84c, 0x27272727},
273 {0x850, 0x00000000}, {0x854, 0x00000000},
274 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
275 {0x860, 0x66e60230}, {0x864, 0x061f0130},
276 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
277 {0x870, 0x07000700}, {0x874, 0x22184000},
278 {0x878, 0x08080808}, {0x87c, 0x00000000},
279 {0x880, 0xc0083070}, {0x884, 0x000004d5},
280 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
281 {0x890, 0x00000800}, {0x894, 0xfffffffe},
282 {0x898, 0x40302010}, {0x89c, 0x00706050},
283 {0x900, 0x00000000}, {0x904, 0x00000023},
284 {0x908, 0x00000000}, {0x90c, 0x81121313},
285 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
286 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
287 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
288 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
289 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
290 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
291 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
292 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
293 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
294 {0xc10, 0x08800000}, {0xc14, 0x40000100},
295 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
296 {0xc20, 0x00000000}, {0xc24, 0x00000000},
297 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
298 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
299 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
300 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
301 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
302 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
303 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
304 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
305 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
306 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
307 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
308 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
309 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
310 {0xc90, 0x00121820}, {0xc94, 0x00000000},
311 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
312 {0xca0, 0x00000000}, {0xca4, 0x00000080},
313 {0xca8, 0x00000000}, {0xcac, 0x00000000},
314 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
315 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
316 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
317 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
318 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
319 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
320 {0xce0, 0x00222222}, {0xce4, 0x00000000},
321 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
322 {0xd00, 0x00080740}, {0xd04, 0x00020403},
323 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
324 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
325 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
326 {0xd30, 0x00000000}, {0xd34, 0x80608000},
327 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
328 {0xd40, 0x00000000}, {0xd44, 0x00000000},
329 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
330 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
331 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
332 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
333 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
334 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
335 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
336 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
337 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
338 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
339 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
340 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
341 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
342 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
343 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
344 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
345 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
346 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
347 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
348 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
349 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
350 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
351 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
352 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
353 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
354 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
355 {0xf00, 0x00000300},
356 {0xffff, 0xffffffff},
357};
358
359static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
360 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
361 {0x040, 0x000c0004}, {0x800, 0x80040000},
362 {0x804, 0x00000001}, {0x808, 0x0000fc00},
363 {0x80c, 0x0000000a}, {0x810, 0x10005388},
364 {0x814, 0x020c3d10}, {0x818, 0x02200385},
365 {0x81c, 0x00000000}, {0x820, 0x01000100},
366 {0x824, 0x00390204}, {0x828, 0x00000000},
367 {0x82c, 0x00000000}, {0x830, 0x00000000},
368 {0x834, 0x00000000}, {0x838, 0x00000000},
369 {0x83c, 0x00000000}, {0x840, 0x00010000},
370 {0x844, 0x00000000}, {0x848, 0x00000000},
371 {0x84c, 0x00000000}, {0x850, 0x00000000},
372 {0x854, 0x00000000}, {0x858, 0x569a569a},
373 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
374 {0x864, 0x061f0130}, {0x868, 0x00000000},
375 {0x86c, 0x20202000}, {0x870, 0x03000300},
376 {0x874, 0x22004000}, {0x878, 0x00000808},
377 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
378 {0x884, 0x000004d5}, {0x888, 0x00000000},
379 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
380 {0x894, 0xfffffffe}, {0x898, 0x40302010},
381 {0x89c, 0x00706050}, {0x900, 0x00000000},
382 {0x904, 0x00000023}, {0x908, 0x00000000},
383 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
384 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
385 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
386 {0xa14, 0x11144028}, {0xa18, 0x00881117},
387 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
388 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
389 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
390 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
391 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
392 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
393 {0xc14, 0x40000100}, {0xc18, 0x08800000},
394 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
395 {0xc24, 0x00000000}, {0xc28, 0x00000000},
396 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
397 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
398 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
399 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
400 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
401 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
402 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
403 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
404 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
405 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
406 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
407 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
408 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
409 {0xc94, 0x00000000}, {0xc98, 0x00121820},
410 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
411 {0xca4, 0x00000080}, {0xca8, 0x00000000},
412 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
413 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
414 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
415 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
416 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
417 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
418 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
419 {0xce4, 0x00000000}, {0xce8, 0x37644302},
420 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
421 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
422 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
423 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
424 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
425 {0xd34, 0x80608000}, {0xd38, 0x00000000},
426 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
427 {0xd44, 0x00000000}, {0xd48, 0x00000000},
428 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
429 {0xd54, 0x00000000}, {0xd58, 0x00000000},
430 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
431 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
432 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
433 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
434 {0xe00, 0x24242424}, {0xe04, 0x24242424},
435 {0xe08, 0x03902024}, {0xe10, 0x24242424},
436 {0xe14, 0x24242424}, {0xe18, 0x24242424},
437 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
438 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
439 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
440 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
441 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
442 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
443 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
444 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
445 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
446 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
447 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
448 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
449 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
450 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
451 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
452 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
453 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
454 {0xf00, 0x00000300},
455 {0xffff, 0xffffffff},
456};
457
458static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
459 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
460 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
461 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
462 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
463 {0xc78, 0x78080001}, {0xc78, 0x77090001},
464 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
465 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
466 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
467 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
468 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
469 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
470 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
471 {0xc78, 0x68180001}, {0xc78, 0x67190001},
472 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
473 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
474 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
475 {0xc78, 0x60200001}, {0xc78, 0x49210001},
476 {0xc78, 0x48220001}, {0xc78, 0x47230001},
477 {0xc78, 0x46240001}, {0xc78, 0x45250001},
478 {0xc78, 0x44260001}, {0xc78, 0x43270001},
479 {0xc78, 0x42280001}, {0xc78, 0x41290001},
480 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
481 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
482 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
483 {0xc78, 0x21300001}, {0xc78, 0x20310001},
484 {0xc78, 0x06320001}, {0xc78, 0x05330001},
485 {0xc78, 0x04340001}, {0xc78, 0x03350001},
486 {0xc78, 0x02360001}, {0xc78, 0x01370001},
487 {0xc78, 0x00380001}, {0xc78, 0x00390001},
488 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
489 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
490 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
491 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
492 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
493 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
494 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
495 {0xc78, 0x78480001}, {0xc78, 0x77490001},
496 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
497 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
498 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
499 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
500 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
501 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
502 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
503 {0xc78, 0x68580001}, {0xc78, 0x67590001},
504 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
505 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
506 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
507 {0xc78, 0x60600001}, {0xc78, 0x49610001},
508 {0xc78, 0x48620001}, {0xc78, 0x47630001},
509 {0xc78, 0x46640001}, {0xc78, 0x45650001},
510 {0xc78, 0x44660001}, {0xc78, 0x43670001},
511 {0xc78, 0x42680001}, {0xc78, 0x41690001},
512 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
513 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
514 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
515 {0xc78, 0x21700001}, {0xc78, 0x20710001},
516 {0xc78, 0x06720001}, {0xc78, 0x05730001},
517 {0xc78, 0x04740001}, {0xc78, 0x03750001},
518 {0xc78, 0x02760001}, {0xc78, 0x01770001},
519 {0xc78, 0x00780001}, {0xc78, 0x00790001},
520 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
521 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
522 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
523 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
524 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
525 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
526 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
527 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
528 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
529 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
530 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
531 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
532 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
533 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
534 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
535 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
536 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
537 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
538 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
539 {0xffff, 0xffffffff}
540};
541
542static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
543 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
544 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
545 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
546 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
547 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
548 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
549 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
550 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
551 {0xc78, 0x73100001}, {0xc78, 0x72110001},
552 {0xc78, 0x71120001}, {0xc78, 0x70130001},
553 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
554 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
555 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
556 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
557 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
558 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
559 {0xc78, 0x63200001}, {0xc78, 0x62210001},
560 {0xc78, 0x61220001}, {0xc78, 0x60230001},
561 {0xc78, 0x46240001}, {0xc78, 0x45250001},
562 {0xc78, 0x44260001}, {0xc78, 0x43270001},
563 {0xc78, 0x42280001}, {0xc78, 0x41290001},
564 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
565 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
566 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
567 {0xc78, 0x21300001}, {0xc78, 0x20310001},
568 {0xc78, 0x06320001}, {0xc78, 0x05330001},
569 {0xc78, 0x04340001}, {0xc78, 0x03350001},
570 {0xc78, 0x02360001}, {0xc78, 0x01370001},
571 {0xc78, 0x00380001}, {0xc78, 0x00390001},
572 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
573 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
574 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
575 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
576 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
577 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
578 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
579 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
580 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
581 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
582 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
583 {0xc78, 0x73500001}, {0xc78, 0x72510001},
584 {0xc78, 0x71520001}, {0xc78, 0x70530001},
585 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
586 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
587 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
588 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
589 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
590 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
591 {0xc78, 0x63600001}, {0xc78, 0x62610001},
592 {0xc78, 0x61620001}, {0xc78, 0x60630001},
593 {0xc78, 0x46640001}, {0xc78, 0x45650001},
594 {0xc78, 0x44660001}, {0xc78, 0x43670001},
595 {0xc78, 0x42680001}, {0xc78, 0x41690001},
596 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
597 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
598 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
599 {0xc78, 0x21700001}, {0xc78, 0x20710001},
600 {0xc78, 0x06720001}, {0xc78, 0x05730001},
601 {0xc78, 0x04740001}, {0xc78, 0x03750001},
602 {0xc78, 0x02760001}, {0xc78, 0x01770001},
603 {0xc78, 0x00780001}, {0xc78, 0x00790001},
604 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
605 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
606 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
607 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
608 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
609 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
610 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
611 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
612 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
613 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
614 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
615 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
616 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
617 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
618 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
619 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
620 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
621 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
622 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
623 {0xffff, 0xffffffff}
624};
625
626static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
627 {
628 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
629 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
630 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
631 .hspiread = REG_HSPI_XA_READBACK,
632 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
633 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
634 },
635 {
636 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
637 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
638 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
639 .hspiread = REG_HSPI_XB_READBACK,
640 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
641 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
642 },
643};
644
645const u32 rtl8xxxu_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
646 REG_OFDM0_XA_RX_IQ_IMBALANCE,
647 REG_OFDM0_XB_RX_IQ_IMBALANCE,
648 REG_OFDM0_ENERGY_CCA_THRES,
649 REG_OFDM0_AGCR_SSI_TABLE,
650 REG_OFDM0_XA_TX_IQ_IMBALANCE,
651 REG_OFDM0_XB_TX_IQ_IMBALANCE,
652 REG_OFDM0_XC_TX_AFE,
653 REG_OFDM0_XD_TX_AFE,
654 REG_OFDM0_RX_IQ_EXT_ANTA
655};
656
657u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
658{
659 struct usb_device *udev = priv->udev;
660 int len;
661 u8 data;
662
663 mutex_lock(&priv->usb_buf_mutex);
664 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
665 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
666 addr, 0, &priv->usb_buf.val8, sizeof(u8),
667 RTW_USB_CONTROL_MSG_TIMEOUT);
668 data = priv->usb_buf.val8;
669 mutex_unlock(&priv->usb_buf_mutex);
670
671 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
672 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
673 __func__, addr, data, len);
674 return data;
675}
676
677u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
678{
679 struct usb_device *udev = priv->udev;
680 int len;
681 u16 data;
682
683 mutex_lock(&priv->usb_buf_mutex);
684 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
685 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
686 addr, 0, &priv->usb_buf.val16, sizeof(u16),
687 RTW_USB_CONTROL_MSG_TIMEOUT);
688 data = le16_to_cpu(priv->usb_buf.val16);
689 mutex_unlock(&priv->usb_buf_mutex);
690
691 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
692 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
693 __func__, addr, data, len);
694 return data;
695}
696
697u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
698{
699 struct usb_device *udev = priv->udev;
700 int len;
701 u32 data;
702
703 mutex_lock(&priv->usb_buf_mutex);
704 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
705 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
706 addr, 0, &priv->usb_buf.val32, sizeof(u32),
707 RTW_USB_CONTROL_MSG_TIMEOUT);
708 data = le32_to_cpu(priv->usb_buf.val32);
709 mutex_unlock(&priv->usb_buf_mutex);
710
711 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
712 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
713 __func__, addr, data, len);
714 return data;
715}
716
717int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
718{
719 struct usb_device *udev = priv->udev;
720 int ret;
721
722 mutex_lock(&priv->usb_buf_mutex);
723 priv->usb_buf.val8 = val;
724 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
725 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
726 addr, 0, &priv->usb_buf.val8, sizeof(u8),
727 RTW_USB_CONTROL_MSG_TIMEOUT);
728
729 mutex_unlock(&priv->usb_buf_mutex);
730
731 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
732 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
733 __func__, addr, val);
734 return ret;
735}
736
737int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
738{
739 struct usb_device *udev = priv->udev;
740 int ret;
741
742 mutex_lock(&priv->usb_buf_mutex);
743 priv->usb_buf.val16 = cpu_to_le16(val);
744 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
745 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
746 addr, 0, &priv->usb_buf.val16, sizeof(u16),
747 RTW_USB_CONTROL_MSG_TIMEOUT);
748 mutex_unlock(&priv->usb_buf_mutex);
749
750 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
751 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
752 __func__, addr, val);
753 return ret;
754}
755
756int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
757{
758 struct usb_device *udev = priv->udev;
759 int ret;
760
761 mutex_lock(&priv->usb_buf_mutex);
762 priv->usb_buf.val32 = cpu_to_le32(val);
763 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
764 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
765 addr, 0, &priv->usb_buf.val32, sizeof(u32),
766 RTW_USB_CONTROL_MSG_TIMEOUT);
767 mutex_unlock(&priv->usb_buf_mutex);
768
769 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
770 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
771 __func__, addr, val);
772 return ret;
773}
774
775static int
776rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
777{
778 struct usb_device *udev = priv->udev;
779 int blocksize = priv->fops->writeN_block_size;
780 int ret, i, count, remainder;
781
782 count = len / blocksize;
783 remainder = len % blocksize;
784
785 for (i = 0; i < count; i++) {
786 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
787 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
788 addr, 0, buf, blocksize,
789 RTW_USB_CONTROL_MSG_TIMEOUT);
790 if (ret != blocksize)
791 goto write_error;
792
793 addr += blocksize;
794 buf += blocksize;
795 }
796
797 if (remainder) {
798 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
799 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
800 addr, 0, buf, remainder,
801 RTW_USB_CONTROL_MSG_TIMEOUT);
802 if (ret != remainder)
803 goto write_error;
804 }
805
806 return len;
807
808write_error:
809 dev_info(&udev->dev,
810 "%s: Failed to write block at addr: %04x size: %04x\n",
811 __func__, addr, blocksize);
812 return -EAGAIN;
813}
814
815u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
816 enum rtl8xxxu_rfpath path, u8 reg)
817{
818 u32 hssia, val32, retval;
819
820 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
821 if (path != RF_A)
822 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
823 else
824 val32 = hssia;
825
826 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
827 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
828 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
829 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
830 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
831
832 udelay(10);
833
834 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
835 udelay(100);
836
837 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
838 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
839 udelay(10);
840
841 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
842 if (val32 & FPGA0_HSSI_PARM1_PI)
843 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
844 else
845 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
846
847 retval &= 0xfffff;
848
849 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
850 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
851 __func__, reg, retval);
852 return retval;
853}
854
855
856
857
858
859
860int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
861 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
862{
863 int ret, retval;
864 u32 dataaddr, val32;
865
866 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
867 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
868 __func__, reg, data);
869
870 data &= FPGA0_LSSI_PARM_DATA_MASK;
871 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
872
873 if (priv->rtl_chip == RTL8192E) {
874 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
875 val32 &= ~0x20000;
876 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
877 }
878
879
880 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
881 if (ret != sizeof(dataaddr))
882 retval = -EIO;
883 else
884 retval = 0;
885
886 udelay(1);
887
888 if (priv->rtl_chip == RTL8192E) {
889 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
890 val32 |= 0x20000;
891 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
892 }
893
894 return retval;
895}
896
897static int
898rtl8xxxu_gen1_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
899{
900 struct device *dev = &priv->udev->dev;
901 int mbox_nr, retry, retval = 0;
902 int mbox_reg, mbox_ext_reg;
903 u8 val8;
904
905 mutex_lock(&priv->h2c_mutex);
906
907 mbox_nr = priv->next_mbox;
908 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
909 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
910
911
912
913
914 retry = 100;
915 do {
916 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
917 if (!(val8 & BIT(mbox_nr)))
918 break;
919 } while (retry--);
920
921 if (!retry) {
922 dev_info(dev, "%s: Mailbox busy\n", __func__);
923 retval = -EBUSY;
924 goto error;
925 }
926
927
928
929
930 if (len > sizeof(u32)) {
931 rtl8xxxu_write16(priv, mbox_ext_reg, le16_to_cpu(h2c->raw.ext));
932 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
933 dev_info(dev, "H2C_EXT %04x\n",
934 le16_to_cpu(h2c->raw.ext));
935 }
936 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
937 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
938 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
939
940 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
941
942error:
943 mutex_unlock(&priv->h2c_mutex);
944 return retval;
945}
946
947int
948rtl8xxxu_gen2_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c, int len)
949{
950 struct device *dev = &priv->udev->dev;
951 int mbox_nr, retry, retval = 0;
952 int mbox_reg, mbox_ext_reg;
953 u8 val8;
954
955 mutex_lock(&priv->h2c_mutex);
956
957 mbox_nr = priv->next_mbox;
958 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
959 mbox_ext_reg = REG_HMBOX_EXT0_8723B + (mbox_nr * 4);
960
961
962
963
964 retry = 100;
965 do {
966 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
967 if (!(val8 & BIT(mbox_nr)))
968 break;
969 } while (retry--);
970
971 if (!retry) {
972 dev_info(dev, "%s: Mailbox busy\n", __func__);
973 retval = -EBUSY;
974 goto error;
975 }
976
977
978
979
980 if (len > sizeof(u32)) {
981 rtl8xxxu_write32(priv, mbox_ext_reg,
982 le32_to_cpu(h2c->raw_wide.ext));
983 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
984 dev_info(dev, "H2C_EXT %08x\n",
985 le32_to_cpu(h2c->raw_wide.ext));
986 }
987 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
988 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
989 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
990
991 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
992
993error:
994 mutex_unlock(&priv->h2c_mutex);
995 return retval;
996}
997
998void rtl8xxxu_gen1_enable_rf(struct rtl8xxxu_priv *priv)
999{
1000 u8 val8;
1001 u32 val32;
1002
1003 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1004 val8 |= BIT(0) | BIT(3);
1005 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1006
1007 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1008 val32 &= ~(BIT(4) | BIT(5));
1009 val32 |= BIT(3);
1010 if (priv->rf_paths == 2) {
1011 val32 &= ~(BIT(20) | BIT(21));
1012 val32 |= BIT(19);
1013 }
1014 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1015
1016 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1017 val32 &= ~OFDM_RF_PATH_TX_MASK;
1018 if (priv->tx_paths == 2)
1019 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1020 else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C)
1021 val32 |= OFDM_RF_PATH_TX_B;
1022 else
1023 val32 |= OFDM_RF_PATH_TX_A;
1024 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1025
1026 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1027 val32 &= ~FPGA_RF_MODE_JAPAN;
1028 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1029
1030 if (priv->rf_paths == 2)
1031 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1032 else
1033 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1034
1035 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1036 if (priv->rf_paths == 2)
1037 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1038
1039 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1040}
1041
1042void rtl8xxxu_gen1_disable_rf(struct rtl8xxxu_priv *priv)
1043{
1044 u8 sps0;
1045 u32 val32;
1046
1047 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1048
1049
1050 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1051 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1052 if (priv->rf_paths == 2)
1053 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1054 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1055
1056
1057 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1058 val32 &= ~OFDM_RF_PATH_TX_MASK;
1059 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1060
1061
1062 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1063 val32 |= FPGA_RF_MODE_JAPAN;
1064 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1065
1066
1067 if (priv->rf_paths == 2)
1068 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1069 else
1070 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1071
1072
1073 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1074 if (priv->rf_paths == 2)
1075 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1076
1077 sps0 &= ~(BIT(0) | BIT(3));
1078 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1079}
1080
1081static void rtl8xxxu_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1082{
1083 u8 val8;
1084
1085 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1086 val8 &= ~BIT(6);
1087 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1088
1089 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1090 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1091 val8 &= ~BIT(0);
1092 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1093}
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105static int rtl8xxxu_gen1_channel_to_group(int channel)
1106{
1107 int group;
1108
1109 if (channel < 4)
1110 group = 0;
1111 else if (channel < 10)
1112 group = 1;
1113 else
1114 group = 2;
1115
1116 return group;
1117}
1118
1119
1120
1121
1122int rtl8xxxu_gen2_channel_to_group(int channel)
1123{
1124 int group;
1125
1126 if (channel < 3)
1127 group = 0;
1128 else if (channel < 6)
1129 group = 1;
1130 else if (channel < 9)
1131 group = 2;
1132 else if (channel < 12)
1133 group = 3;
1134 else
1135 group = 4;
1136
1137 return group;
1138}
1139
1140void rtl8xxxu_gen1_config_channel(struct ieee80211_hw *hw)
1141{
1142 struct rtl8xxxu_priv *priv = hw->priv;
1143 u32 val32, rsr;
1144 u8 val8, opmode;
1145 bool ht = true;
1146 int sec_ch_above, channel;
1147 int i;
1148
1149 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1150 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1151 channel = hw->conf.chandef.chan->hw_value;
1152
1153 switch (hw->conf.chandef.width) {
1154 case NL80211_CHAN_WIDTH_20_NOHT:
1155 ht = false;
1156 case NL80211_CHAN_WIDTH_20:
1157 opmode |= BW_OPMODE_20MHZ;
1158 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1159
1160 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1161 val32 &= ~FPGA_RF_MODE;
1162 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1163
1164 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1165 val32 &= ~FPGA_RF_MODE;
1166 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1167
1168 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1169 val32 |= FPGA0_ANALOG2_20MHZ;
1170 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1171 break;
1172 case NL80211_CHAN_WIDTH_40:
1173 if (hw->conf.chandef.center_freq1 >
1174 hw->conf.chandef.chan->center_freq) {
1175 sec_ch_above = 1;
1176 channel += 2;
1177 } else {
1178 sec_ch_above = 0;
1179 channel -= 2;
1180 }
1181
1182 opmode &= ~BW_OPMODE_20MHZ;
1183 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1184 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1185 if (sec_ch_above)
1186 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1187 else
1188 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1189 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1190
1191 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1192 val32 |= FPGA_RF_MODE;
1193 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1194
1195 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1196 val32 |= FPGA_RF_MODE;
1197 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1198
1199
1200
1201
1202
1203 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1204 val32 &= ~CCK0_SIDEBAND;
1205 if (!sec_ch_above)
1206 val32 |= CCK0_SIDEBAND;
1207 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1208
1209 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1210 val32 &= ~OFDM_LSTF_PRIME_CH_MASK;
1211 if (sec_ch_above)
1212 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1213 else
1214 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1215 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1216
1217 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1218 val32 &= ~FPGA0_ANALOG2_20MHZ;
1219 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1220
1221 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1222 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1223 if (sec_ch_above)
1224 val32 |= FPGA0_PS_UPPER_CHANNEL;
1225 else
1226 val32 |= FPGA0_PS_LOWER_CHANNEL;
1227 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1228 break;
1229
1230 default:
1231 break;
1232 }
1233
1234 for (i = RF_A; i < priv->rf_paths; i++) {
1235 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1236 val32 &= ~MODE_AG_CHANNEL_MASK;
1237 val32 |= channel;
1238 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1239 }
1240
1241 if (ht)
1242 val8 = 0x0e;
1243 else
1244 val8 = 0x0a;
1245
1246 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1247 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1248
1249 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1250 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1251
1252 for (i = RF_A; i < priv->rf_paths; i++) {
1253 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1254 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1255 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1256 else
1257 val32 |= MODE_AG_CHANNEL_20MHZ;
1258 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1259 }
1260}
1261
1262void rtl8xxxu_gen2_config_channel(struct ieee80211_hw *hw)
1263{
1264 struct rtl8xxxu_priv *priv = hw->priv;
1265 u32 val32, rsr;
1266 u8 val8, subchannel;
1267 u16 rf_mode_bw;
1268 bool ht = true;
1269 int sec_ch_above, channel;
1270 int i;
1271
1272 rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL);
1273 rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK;
1274 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1275 channel = hw->conf.chandef.chan->hw_value;
1276
1277
1278 subchannel = 0;
1279
1280 switch (hw->conf.chandef.width) {
1281 case NL80211_CHAN_WIDTH_20_NOHT:
1282 ht = false;
1283 case NL80211_CHAN_WIDTH_20:
1284 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20;
1285 subchannel = 0;
1286
1287 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1288 val32 &= ~FPGA_RF_MODE;
1289 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1290
1291 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1292 val32 &= ~FPGA_RF_MODE;
1293 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1294
1295 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT);
1296 val32 &= ~(BIT(30) | BIT(31));
1297 rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32);
1298
1299 break;
1300 case NL80211_CHAN_WIDTH_40:
1301 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40;
1302
1303 if (hw->conf.chandef.center_freq1 >
1304 hw->conf.chandef.chan->center_freq) {
1305 sec_ch_above = 1;
1306 channel += 2;
1307 } else {
1308 sec_ch_above = 0;
1309 channel -= 2;
1310 }
1311
1312 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1313 val32 |= FPGA_RF_MODE;
1314 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1315
1316 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1317 val32 |= FPGA_RF_MODE;
1318 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1319
1320
1321
1322
1323
1324 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1325 val32 &= ~CCK0_SIDEBAND;
1326 if (!sec_ch_above)
1327 val32 |= CCK0_SIDEBAND;
1328 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1329
1330 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1331 val32 &= ~OFDM_LSTF_PRIME_CH_MASK;
1332 if (sec_ch_above)
1333 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1334 else
1335 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1336 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1337
1338 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1339 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1340 if (sec_ch_above)
1341 val32 |= FPGA0_PS_UPPER_CHANNEL;
1342 else
1343 val32 |= FPGA0_PS_LOWER_CHANNEL;
1344 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1345 break;
1346 case NL80211_CHAN_WIDTH_80:
1347 rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80;
1348 break;
1349 default:
1350 break;
1351 }
1352
1353 for (i = RF_A; i < priv->rf_paths; i++) {
1354 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1355 val32 &= ~MODE_AG_CHANNEL_MASK;
1356 val32 |= channel;
1357 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1358 }
1359
1360 rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw);
1361 rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel);
1362
1363 if (ht)
1364 val8 = 0x0e;
1365 else
1366 val8 = 0x0a;
1367
1368 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1369 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1370
1371 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1372 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1373
1374 for (i = RF_A; i < priv->rf_paths; i++) {
1375 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1376 val32 &= ~MODE_AG_BW_MASK;
1377 switch(hw->conf.chandef.width) {
1378 case NL80211_CHAN_WIDTH_80:
1379 val32 |= MODE_AG_BW_80MHZ_8723B;
1380 break;
1381 case NL80211_CHAN_WIDTH_40:
1382 val32 |= MODE_AG_BW_40MHZ_8723B;
1383 break;
1384 default:
1385 val32 |= MODE_AG_BW_20MHZ_8723B;
1386 break;
1387 }
1388 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1389 }
1390}
1391
1392void
1393rtl8xxxu_gen1_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1394{
1395 struct rtl8xxxu_power_base *power_base = priv->power_base;
1396 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1397 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1398 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1399 u8 val8;
1400 int group, i;
1401
1402 group = rtl8xxxu_gen1_channel_to_group(channel);
1403
1404 cck[0] = priv->cck_tx_power_index_A[group] - 1;
1405 cck[1] = priv->cck_tx_power_index_B[group] - 1;
1406
1407 if (priv->hi_pa) {
1408 if (cck[0] > 0x20)
1409 cck[0] = 0x20;
1410 if (cck[1] > 0x20)
1411 cck[1] = 0x20;
1412 }
1413
1414 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1415 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1416 if (ofdm[0])
1417 ofdm[0] -= 1;
1418 if (ofdm[1])
1419 ofdm[1] -= 1;
1420
1421 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1422 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1423
1424 mcsbase[0] = ofdm[0];
1425 mcsbase[1] = ofdm[1];
1426 if (!ht40) {
1427 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1428 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1429 }
1430
1431 if (priv->tx_paths > 1) {
1432 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1433 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1434 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1435 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1436 }
1437
1438 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1439 dev_info(&priv->udev->dev,
1440 "%s: Setting TX power CCK A: %02x, "
1441 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1442 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1443
1444 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1445 if (cck[i] > RF6052_MAX_TX_PWR)
1446 cck[i] = RF6052_MAX_TX_PWR;
1447 if (ofdm[i] > RF6052_MAX_TX_PWR)
1448 ofdm[i] = RF6052_MAX_TX_PWR;
1449 }
1450
1451 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1452 val32 &= 0xffff00ff;
1453 val32 |= (cck[0] << 8);
1454 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1455
1456 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1457 val32 &= 0xff;
1458 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1459 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1460
1461 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1462 val32 &= 0xffffff00;
1463 val32 |= cck[1];
1464 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1465
1466 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1467 val32 &= 0xff;
1468 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1469 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1470
1471 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1472 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1473 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1474 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1475
1476 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06,
1477 ofdm_a + power_base->reg_0e00);
1478 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06,
1479 ofdm_b + power_base->reg_0830);
1480
1481 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24,
1482 ofdm_a + power_base->reg_0e04);
1483 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24,
1484 ofdm_b + power_base->reg_0834);
1485
1486 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1487 mcsbase[0] << 16 | mcsbase[0] << 24;
1488 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1489 mcsbase[1] << 16 | mcsbase[1] << 24;
1490
1491 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00,
1492 mcs_a + power_base->reg_0e10);
1493 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00,
1494 mcs_b + power_base->reg_083c);
1495
1496 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04,
1497 mcs_a + power_base->reg_0e14);
1498 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04,
1499 mcs_b + power_base->reg_0848);
1500
1501 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08,
1502 mcs_a + power_base->reg_0e18);
1503 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08,
1504 mcs_b + power_base->reg_084c);
1505
1506 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12,
1507 mcs_a + power_base->reg_0e1c);
1508 for (i = 0; i < 3; i++) {
1509 if (i != 2)
1510 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1511 else
1512 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1513 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1514 }
1515 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12,
1516 mcs_b + power_base->reg_0868);
1517 for (i = 0; i < 3; i++) {
1518 if (i != 2)
1519 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1520 else
1521 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1522 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1523 }
1524}
1525
1526static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1527 enum nl80211_iftype linktype)
1528{
1529 u8 val8;
1530
1531 val8 = rtl8xxxu_read8(priv, REG_MSR);
1532 val8 &= ~MSR_LINKTYPE_MASK;
1533
1534 switch (linktype) {
1535 case NL80211_IFTYPE_UNSPECIFIED:
1536 val8 |= MSR_LINKTYPE_NONE;
1537 break;
1538 case NL80211_IFTYPE_ADHOC:
1539 val8 |= MSR_LINKTYPE_ADHOC;
1540 break;
1541 case NL80211_IFTYPE_STATION:
1542 val8 |= MSR_LINKTYPE_STATION;
1543 break;
1544 case NL80211_IFTYPE_AP:
1545 val8 |= MSR_LINKTYPE_AP;
1546 break;
1547 default:
1548 goto out;
1549 }
1550
1551 rtl8xxxu_write8(priv, REG_MSR, val8);
1552out:
1553 return;
1554}
1555
1556static void
1557rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1558{
1559 u16 val16;
1560
1561 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1562 RETRY_LIMIT_SHORT_MASK) |
1563 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1564 RETRY_LIMIT_LONG_MASK);
1565
1566 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1567}
1568
1569static void
1570rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1571{
1572 u16 val16;
1573
1574 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1575 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1576
1577 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1578}
1579
1580static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1581{
1582 struct device *dev = &priv->udev->dev;
1583 char *cut;
1584
1585 switch (priv->chip_cut) {
1586 case 0:
1587 cut = "A";
1588 break;
1589 case 1:
1590 cut = "B";
1591 break;
1592 case 2:
1593 cut = "C";
1594 break;
1595 case 3:
1596 cut = "D";
1597 break;
1598 case 4:
1599 cut = "E";
1600 break;
1601 default:
1602 cut = "unknown";
1603 }
1604
1605 dev_info(dev,
1606 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
1607 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1608 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1609 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
1610
1611 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1612}
1613
1614static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1615{
1616 struct device *dev = &priv->udev->dev;
1617 u32 val32, bonding;
1618 u16 val16;
1619
1620 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1621 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1622 SYS_CFG_CHIP_VERSION_SHIFT;
1623 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1624 dev_info(dev, "Unsupported test chip\n");
1625 return -ENOTSUPP;
1626 }
1627
1628 if (val32 & SYS_CFG_BT_FUNC) {
1629 if (priv->chip_cut >= 3) {
1630 sprintf(priv->chip_name, "8723BU");
1631 priv->rtl_chip = RTL8723B;
1632 } else {
1633 sprintf(priv->chip_name, "8723AU");
1634 priv->usb_interrupts = 1;
1635 priv->rtl_chip = RTL8723A;
1636 }
1637
1638 priv->rf_paths = 1;
1639 priv->rx_paths = 1;
1640 priv->tx_paths = 1;
1641
1642 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1643 if (val32 & MULTI_WIFI_FUNC_EN)
1644 priv->has_wifi = 1;
1645 if (val32 & MULTI_BT_FUNC_EN)
1646 priv->has_bluetooth = 1;
1647 if (val32 & MULTI_GPS_FUNC_EN)
1648 priv->has_gps = 1;
1649 priv->is_multi_func = 1;
1650 } else if (val32 & SYS_CFG_TYPE_ID) {
1651 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1652 bonding &= HPON_FSM_BONDING_MASK;
1653 if (priv->fops->tx_desc_size ==
1654 sizeof(struct rtl8xxxu_txdesc40)) {
1655 if (bonding == HPON_FSM_BONDING_1T2R) {
1656 sprintf(priv->chip_name, "8191EU");
1657 priv->rf_paths = 2;
1658 priv->rx_paths = 2;
1659 priv->tx_paths = 1;
1660 priv->rtl_chip = RTL8191E;
1661 } else {
1662 sprintf(priv->chip_name, "8192EU");
1663 priv->rf_paths = 2;
1664 priv->rx_paths = 2;
1665 priv->tx_paths = 2;
1666 priv->rtl_chip = RTL8192E;
1667 }
1668 } else if (bonding == HPON_FSM_BONDING_1T2R) {
1669 sprintf(priv->chip_name, "8191CU");
1670 priv->rf_paths = 2;
1671 priv->rx_paths = 2;
1672 priv->tx_paths = 1;
1673 priv->usb_interrupts = 1;
1674 priv->rtl_chip = RTL8191C;
1675 } else {
1676 sprintf(priv->chip_name, "8192CU");
1677 priv->rf_paths = 2;
1678 priv->rx_paths = 2;
1679 priv->tx_paths = 2;
1680 priv->usb_interrupts = 1;
1681 priv->rtl_chip = RTL8192C;
1682 }
1683 priv->has_wifi = 1;
1684 } else {
1685 sprintf(priv->chip_name, "8188CU");
1686 priv->rf_paths = 1;
1687 priv->rx_paths = 1;
1688 priv->tx_paths = 1;
1689 priv->rtl_chip = RTL8188C;
1690 priv->usb_interrupts = 1;
1691 priv->has_wifi = 1;
1692 }
1693
1694 switch (priv->rtl_chip) {
1695 case RTL8188E:
1696 case RTL8192E:
1697 case RTL8723B:
1698 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1699 case SYS_CFG_VENDOR_ID_TSMC:
1700 sprintf(priv->chip_vendor, "TSMC");
1701 break;
1702 case SYS_CFG_VENDOR_ID_SMIC:
1703 sprintf(priv->chip_vendor, "SMIC");
1704 priv->vendor_smic = 1;
1705 break;
1706 case SYS_CFG_VENDOR_ID_UMC:
1707 sprintf(priv->chip_vendor, "UMC");
1708 priv->vendor_umc = 1;
1709 break;
1710 default:
1711 sprintf(priv->chip_vendor, "unknown");
1712 }
1713 break;
1714 default:
1715 if (val32 & SYS_CFG_VENDOR_ID) {
1716 sprintf(priv->chip_vendor, "UMC");
1717 priv->vendor_umc = 1;
1718 } else {
1719 sprintf(priv->chip_vendor, "TSMC");
1720 }
1721 }
1722
1723 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1724 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1725
1726 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1727 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1728 priv->ep_tx_high_queue = 1;
1729 priv->ep_tx_count++;
1730 }
1731
1732 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1733 priv->ep_tx_normal_queue = 1;
1734 priv->ep_tx_count++;
1735 }
1736
1737 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1738 priv->ep_tx_low_queue = 1;
1739 priv->ep_tx_count++;
1740 }
1741
1742
1743
1744
1745 if (!priv->ep_tx_count) {
1746 switch (priv->nr_out_eps) {
1747 case 4:
1748 case 3:
1749 priv->ep_tx_low_queue = 1;
1750 priv->ep_tx_count++;
1751 case 2:
1752 priv->ep_tx_normal_queue = 1;
1753 priv->ep_tx_count++;
1754 case 1:
1755 priv->ep_tx_high_queue = 1;
1756 priv->ep_tx_count++;
1757 break;
1758 default:
1759 dev_info(dev, "Unsupported USB TX end-points\n");
1760 return -ENOTSUPP;
1761 }
1762 }
1763
1764 return 0;
1765}
1766
1767static int
1768rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1769{
1770 int i;
1771 u8 val8;
1772 u32 val32;
1773
1774
1775 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1776 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1777 val8 &= 0xfc;
1778 val8 |= (offset >> 8) & 0x03;
1779 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
1780
1781 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
1782 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
1783
1784
1785 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1786 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
1787 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1788 if (val32 & BIT(31))
1789 break;
1790 }
1791
1792 if (i == RTL8XXXU_MAX_REG_POLL)
1793 return -EIO;
1794
1795 udelay(50);
1796 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
1797
1798 *data = val32 & 0xff;
1799 return 0;
1800}
1801
1802static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
1803{
1804 struct device *dev = &priv->udev->dev;
1805 int i, ret = 0;
1806 u8 val8, word_mask, header, extheader;
1807 u16 val16, efuse_addr, offset;
1808 u32 val32;
1809
1810 val16 = rtl8xxxu_read16(priv, REG_9346CR);
1811 if (val16 & EEPROM_ENABLE)
1812 priv->has_eeprom = 1;
1813 if (val16 & EEPROM_BOOT)
1814 priv->boot_eeprom = 1;
1815
1816 if (priv->is_multi_func) {
1817 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
1818 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
1819 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
1820 }
1821
1822 dev_dbg(dev, "Booting from %s\n",
1823 priv->boot_eeprom ? "EEPROM" : "EFUSE");
1824
1825 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
1826
1827
1828 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
1829 if (!(val16 & SYS_ISO_PWC_EV12V)) {
1830 val16 |= SYS_ISO_PWC_EV12V;
1831 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
1832 }
1833
1834 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1835 if (!(val16 & SYS_FUNC_ELDR)) {
1836 val16 |= SYS_FUNC_ELDR;
1837 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
1838 }
1839
1840
1841
1842
1843 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
1844 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
1845 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
1846 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
1847 }
1848
1849
1850 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
1851
1852 efuse_addr = 0;
1853 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
1854 u16 map_addr;
1855
1856 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
1857 if (ret || header == 0xff)
1858 goto exit;
1859
1860 if ((header & 0x1f) == 0x0f) {
1861 offset = (header & 0xe0) >> 5;
1862
1863 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
1864 &extheader);
1865 if (ret)
1866 goto exit;
1867
1868 if ((extheader & 0x0f) == 0x0f)
1869 continue;
1870
1871 offset |= ((extheader & 0xf0) >> 1);
1872 word_mask = extheader & 0x0f;
1873 } else {
1874 offset = (header >> 4) & 0x0f;
1875 word_mask = header & 0x0f;
1876 }
1877
1878
1879
1880
1881 map_addr = offset * 8;
1882 if (map_addr >= EFUSE_MAP_LEN) {
1883 dev_warn(dev, "%s: Illegal map_addr (%04x), "
1884 "efuse corrupt!\n",
1885 __func__, map_addr);
1886 ret = -EINVAL;
1887 goto exit;
1888 }
1889 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
1890
1891 if (word_mask & BIT(i)) {
1892 map_addr += 2;
1893 continue;
1894 }
1895
1896 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1897 if (ret)
1898 goto exit;
1899 priv->efuse_wifi.raw[map_addr++] = val8;
1900
1901 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8);
1902 if (ret)
1903 goto exit;
1904 priv->efuse_wifi.raw[map_addr++] = val8;
1905 }
1906 }
1907
1908exit:
1909 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
1910
1911 return ret;
1912}
1913
1914void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
1915{
1916 u8 val8;
1917 u16 sys_func;
1918
1919 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1920 val8 &= ~BIT(0);
1921 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1922
1923 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
1924 sys_func &= ~SYS_FUNC_CPU_ENABLE;
1925 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1926
1927 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
1928 val8 |= BIT(0);
1929 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
1930
1931 sys_func |= SYS_FUNC_CPU_ENABLE;
1932 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
1933}
1934
1935static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
1936{
1937 struct device *dev = &priv->udev->dev;
1938 int ret = 0, i;
1939 u32 val32;
1940
1941
1942 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1943 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1944 if (val32 & MCU_FW_DL_CSUM_REPORT)
1945 break;
1946 }
1947
1948 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1949 dev_warn(dev, "Firmware checksum poll timed out\n");
1950 ret = -EAGAIN;
1951 goto exit;
1952 }
1953
1954 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1955 val32 |= MCU_FW_DL_READY;
1956 val32 &= ~MCU_WINT_INIT_READY;
1957 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
1958
1959
1960
1961
1962
1963 priv->fops->reset_8051(priv);
1964
1965
1966 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
1967 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
1968 if (val32 & MCU_WINT_INIT_READY)
1969 break;
1970
1971 udelay(100);
1972 }
1973
1974 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
1975 dev_warn(dev, "Firmware failed to start\n");
1976 ret = -EAGAIN;
1977 goto exit;
1978 }
1979
1980
1981
1982
1983 if (priv->rtl_chip == RTL8723B)
1984 rtl8xxxu_write8(priv, REG_HMTFR, 0x0f);
1985exit:
1986 return ret;
1987}
1988
1989static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
1990{
1991 int pages, remainder, i, ret;
1992 u8 val8;
1993 u16 val16;
1994 u32 val32;
1995 u8 *fwptr;
1996
1997 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
1998 val8 |= 4;
1999 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2000
2001
2002 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2003 val16 |= SYS_FUNC_CPU_ENABLE;
2004 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2005
2006 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2007 if (val8 & MCU_FW_RAM_SEL) {
2008 pr_info("do the RAM reset\n");
2009 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
2010 priv->fops->reset_8051(priv);
2011 }
2012
2013
2014 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2015 val8 |= MCU_FW_DL_ENABLE;
2016 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2017
2018
2019 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2020 val32 &= ~BIT(19);
2021 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2022
2023
2024 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2025 val8 |= MCU_FW_DL_CSUM_REPORT;
2026 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
2027
2028 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2029 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2030
2031 fwptr = priv->fw_data->data;
2032
2033 for (i = 0; i < pages; i++) {
2034 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2035 val8 |= i;
2036 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2037
2038 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2039 fwptr, RTL_FW_PAGE_SIZE);
2040 if (ret != RTL_FW_PAGE_SIZE) {
2041 ret = -EAGAIN;
2042 goto fw_abort;
2043 }
2044
2045 fwptr += RTL_FW_PAGE_SIZE;
2046 }
2047
2048 if (remainder) {
2049 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
2050 val8 |= i;
2051 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
2052 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2053 fwptr, remainder);
2054 if (ret != remainder) {
2055 ret = -EAGAIN;
2056 goto fw_abort;
2057 }
2058 }
2059
2060 ret = 0;
2061fw_abort:
2062
2063 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
2064 val16 &= ~MCU_FW_DL_ENABLE;
2065 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
2066
2067 return ret;
2068}
2069
2070int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2071{
2072 struct device *dev = &priv->udev->dev;
2073 const struct firmware *fw;
2074 int ret = 0;
2075 u16 signature;
2076
2077 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2078 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2079 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2080 ret = -EAGAIN;
2081 goto exit;
2082 }
2083 if (!fw) {
2084 dev_warn(dev, "Firmware data not available\n");
2085 ret = -EINVAL;
2086 goto exit;
2087 }
2088
2089 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
2090 if (!priv->fw_data) {
2091 ret = -ENOMEM;
2092 goto exit;
2093 }
2094 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2095
2096 signature = le16_to_cpu(priv->fw_data->signature);
2097 switch (signature & 0xfff0) {
2098 case 0x92e0:
2099 case 0x92c0:
2100 case 0x88c0:
2101 case 0x5300:
2102 case 0x2300:
2103 break;
2104 default:
2105 ret = -EINVAL;
2106 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2107 __func__, signature);
2108 }
2109
2110 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2111 le16_to_cpu(priv->fw_data->major_version),
2112 priv->fw_data->minor_version, signature);
2113
2114exit:
2115 release_firmware(fw);
2116 return ret;
2117}
2118
2119void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2120{
2121 u16 val16;
2122 int i = 100;
2123
2124
2125 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2126
2127 for (i = 100; i > 0; i--) {
2128 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2129
2130 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2131 dev_dbg(&priv->udev->dev,
2132 "%s: Firmware self reset success!\n", __func__);
2133 break;
2134 }
2135 udelay(50);
2136 }
2137
2138 if (!i) {
2139
2140 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2141 val16 &= ~SYS_FUNC_CPU_ENABLE;
2142 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2143 }
2144}
2145
2146static int
2147rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv)
2148{
2149 struct rtl8xxxu_reg8val *array = priv->fops->mactable;
2150 int i, ret;
2151 u16 reg;
2152 u8 val;
2153
2154 for (i = 0; ; i++) {
2155 reg = array[i].reg;
2156 val = array[i].val;
2157
2158 if (reg == 0xffff && val == 0xff)
2159 break;
2160
2161 ret = rtl8xxxu_write8(priv, reg, val);
2162 if (ret != 1) {
2163 dev_warn(&priv->udev->dev,
2164 "Failed to initialize MAC "
2165 "(reg: %04x, val %02x)\n", reg, val);
2166 return -EAGAIN;
2167 }
2168 }
2169
2170 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
2171 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2172
2173 return 0;
2174}
2175
2176int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2177 struct rtl8xxxu_reg32val *array)
2178{
2179 int i, ret;
2180 u16 reg;
2181 u32 val;
2182
2183 for (i = 0; ; i++) {
2184 reg = array[i].reg;
2185 val = array[i].val;
2186
2187 if (reg == 0xffff && val == 0xffffffff)
2188 break;
2189
2190 ret = rtl8xxxu_write32(priv, reg, val);
2191 if (ret != sizeof(val)) {
2192 dev_warn(&priv->udev->dev,
2193 "Failed to initialize PHY\n");
2194 return -EAGAIN;
2195 }
2196 udelay(1);
2197 }
2198
2199 return 0;
2200}
2201
2202void rtl8xxxu_gen1_init_phy_bb(struct rtl8xxxu_priv *priv)
2203{
2204 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2205 u16 val16;
2206 u32 val32;
2207
2208 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2209 udelay(2);
2210 val8 |= AFE_PLL_320_ENABLE;
2211 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2212 udelay(2);
2213
2214 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2215 udelay(2);
2216
2217 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2218 val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2219 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2220
2221 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2222 val32 &= ~AFE_XTAL_RF_GATE;
2223 if (priv->has_bluetooth)
2224 val32 &= ~AFE_XTAL_BT_GATE;
2225 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2226
2227
2228 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2229 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2230
2231 if (priv->hi_pa)
2232 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2233 else if (priv->tx_paths == 2)
2234 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2235 else
2236 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2237
2238 if (priv->rtl_chip == RTL8188R && priv->hi_pa &&
2239 priv->vendor_umc && priv->chip_cut == 1)
2240 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2241
2242 if (priv->hi_pa)
2243 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2244 else
2245 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2246
2247 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2248 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2249 ldohci12 = 0x57;
2250 lpldo = 1;
2251 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2252 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2253}
2254
2255
2256
2257
2258static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2259{
2260 u8 val8;
2261 u32 val32;
2262
2263 priv->fops->init_phy_bb(priv);
2264
2265 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2266
2267
2268
2269
2270
2271 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2272 val32 &= ~(BIT(0) | BIT(1));
2273 val32 |= BIT(1);
2274 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2275
2276 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2277 val32 &= ~0x300033;
2278 val32 |= 0x200022;
2279 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2280
2281 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2282 val32 &= ~CCK0_AFE_RX_MASK;
2283 val32 &= 0x00ffffff;
2284 val32 |= 0x40000000;
2285 val32 |= CCK0_AFE_RX_ANT_B;
2286 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2287
2288 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2289 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2290 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2291 OFDM_RF_PATH_TX_B);
2292 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2293
2294 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2295 val32 &= ~(BIT(4) | BIT(5));
2296 val32 |= BIT(4);
2297 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2298
2299 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2300 val32 &= ~(BIT(27) | BIT(26));
2301 val32 |= BIT(27);
2302 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2303
2304 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2305 val32 &= ~(BIT(27) | BIT(26));
2306 val32 |= BIT(27);
2307 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2308
2309 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2310 val32 &= ~(BIT(27) | BIT(26));
2311 val32 |= BIT(27);
2312 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2313
2314 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2315 val32 &= ~(BIT(27) | BIT(26));
2316 val32 |= BIT(27);
2317 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2318
2319 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2320 val32 &= ~(BIT(27) | BIT(26));
2321 val32 |= BIT(27);
2322 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2323 }
2324
2325 if (priv->has_xtalk) {
2326 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2327
2328 val8 = priv->xtalk;
2329 val32 &= 0xff000fff;
2330 val32 |= ((val8 | (val8 << 6)) << 12);
2331
2332 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2333 }
2334
2335 if (priv->rtl_chip == RTL8192E)
2336 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb);
2337
2338 return 0;
2339}
2340
2341static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2342 struct rtl8xxxu_rfregval *array,
2343 enum rtl8xxxu_rfpath path)
2344{
2345 int i, ret;
2346 u8 reg;
2347 u32 val;
2348
2349 for (i = 0; ; i++) {
2350 reg = array[i].reg;
2351 val = array[i].val;
2352
2353 if (reg == 0xff && val == 0xffffffff)
2354 break;
2355
2356 switch (reg) {
2357 case 0xfe:
2358 msleep(50);
2359 continue;
2360 case 0xfd:
2361 mdelay(5);
2362 continue;
2363 case 0xfc:
2364 mdelay(1);
2365 continue;
2366 case 0xfb:
2367 udelay(50);
2368 continue;
2369 case 0xfa:
2370 udelay(5);
2371 continue;
2372 case 0xf9:
2373 udelay(1);
2374 continue;
2375 }
2376
2377 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2378 if (ret) {
2379 dev_warn(&priv->udev->dev,
2380 "Failed to initialize RF\n");
2381 return -EAGAIN;
2382 }
2383 udelay(1);
2384 }
2385
2386 return 0;
2387}
2388
2389int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2390 struct rtl8xxxu_rfregval *table,
2391 enum rtl8xxxu_rfpath path)
2392{
2393 u32 val32;
2394 u16 val16, rfsi_rfenv;
2395 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2396
2397 switch (path) {
2398 case RF_A:
2399 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2400 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2401 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2402 break;
2403 case RF_B:
2404 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2405 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2406 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2407 break;
2408 default:
2409 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2410 __func__, path + 'A');
2411 return -EINVAL;
2412 }
2413
2414 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2415 rfsi_rfenv &= FPGA0_RF_RFENV;
2416
2417
2418
2419
2420 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2421 val32 |= BIT(20);
2422 rtl8xxxu_write32(priv, reg_int_oe, val32);
2423 udelay(1);
2424
2425 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2426 val32 |= BIT(4);
2427 rtl8xxxu_write32(priv, reg_int_oe, val32);
2428 udelay(1);
2429
2430
2431
2432
2433 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2434 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2435 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2436 udelay(1);
2437
2438 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2439 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2440 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2441 udelay(1);
2442
2443 rtl8xxxu_init_rf_regs(priv, table, path);
2444
2445
2446 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2447 val16 &= ~FPGA0_RF_RFENV;
2448 val16 |= rfsi_rfenv;
2449 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2450
2451 return 0;
2452}
2453
2454static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2455{
2456 int ret = -EBUSY;
2457 int count = 0;
2458 u32 value;
2459
2460 value = LLT_OP_WRITE | address << 8 | data;
2461
2462 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2463
2464 do {
2465 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2466 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2467 ret = 0;
2468 break;
2469 }
2470 } while (count++ < 20);
2471
2472 return ret;
2473}
2474
2475int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv)
2476{
2477 int ret;
2478 int i;
2479 u8 last_tx_page;
2480
2481 last_tx_page = priv->fops->total_page_num;
2482
2483 for (i = 0; i < last_tx_page; i++) {
2484 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2485 if (ret)
2486 goto exit;
2487 }
2488
2489 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2490 if (ret)
2491 goto exit;
2492
2493
2494 for (i = last_tx_page + 1; i < 0xff; i++) {
2495 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2496 if (ret)
2497 goto exit;
2498 }
2499
2500
2501 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2502 if (ret)
2503 goto exit;
2504
2505exit:
2506 return ret;
2507}
2508
2509int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv)
2510{
2511 u32 val32;
2512 int ret = 0;
2513 int i;
2514
2515 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2516 val32 |= AUTO_LLT_INIT_LLT;
2517 rtl8xxxu_write32(priv, REG_AUTO_LLT, val32);
2518
2519 for (i = 500; i; i--) {
2520 val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT);
2521 if (!(val32 & AUTO_LLT_INIT_LLT))
2522 break;
2523 usleep_range(2, 4);
2524 }
2525
2526 if (!i) {
2527 ret = -EBUSY;
2528 dev_warn(&priv->udev->dev, "LLT table init failed\n");
2529 }
2530
2531 return ret;
2532}
2533
2534static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2535{
2536 u16 val16, hi, lo;
2537 u16 hiq, mgq, bkq, beq, viq, voq;
2538 int hip, mgp, bkp, bep, vip, vop;
2539 int ret = 0;
2540
2541 switch (priv->ep_tx_count) {
2542 case 1:
2543 if (priv->ep_tx_high_queue) {
2544 hi = TRXDMA_QUEUE_HIGH;
2545 } else if (priv->ep_tx_low_queue) {
2546 hi = TRXDMA_QUEUE_LOW;
2547 } else if (priv->ep_tx_normal_queue) {
2548 hi = TRXDMA_QUEUE_NORMAL;
2549 } else {
2550 hi = 0;
2551 ret = -EINVAL;
2552 }
2553
2554 hiq = hi;
2555 mgq = hi;
2556 bkq = hi;
2557 beq = hi;
2558 viq = hi;
2559 voq = hi;
2560
2561 hip = 0;
2562 mgp = 0;
2563 bkp = 0;
2564 bep = 0;
2565 vip = 0;
2566 vop = 0;
2567 break;
2568 case 2:
2569 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2570 hi = TRXDMA_QUEUE_HIGH;
2571 lo = TRXDMA_QUEUE_LOW;
2572 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2573 hi = TRXDMA_QUEUE_NORMAL;
2574 lo = TRXDMA_QUEUE_LOW;
2575 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2576 hi = TRXDMA_QUEUE_HIGH;
2577 lo = TRXDMA_QUEUE_NORMAL;
2578 } else {
2579 ret = -EINVAL;
2580 hi = 0;
2581 lo = 0;
2582 }
2583
2584 hiq = hi;
2585 mgq = hi;
2586 bkq = lo;
2587 beq = lo;
2588 viq = hi;
2589 voq = hi;
2590
2591 hip = 0;
2592 mgp = 0;
2593 bkp = 1;
2594 bep = 1;
2595 vip = 0;
2596 vop = 0;
2597 break;
2598 case 3:
2599 beq = TRXDMA_QUEUE_LOW;
2600 bkq = TRXDMA_QUEUE_LOW;
2601 viq = TRXDMA_QUEUE_NORMAL;
2602 voq = TRXDMA_QUEUE_HIGH;
2603 mgq = TRXDMA_QUEUE_HIGH;
2604 hiq = TRXDMA_QUEUE_HIGH;
2605
2606 hip = hiq ^ 3;
2607 mgp = mgq ^ 3;
2608 bkp = bkq ^ 3;
2609 bep = beq ^ 3;
2610 vip = viq ^ 3;
2611 vop = viq ^ 3;
2612 break;
2613 default:
2614 ret = -EINVAL;
2615 }
2616
2617
2618
2619
2620
2621 if (!ret) {
2622 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2623 val16 &= 0x7;
2624 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2625 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2626 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2627 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2628 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2629 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2630 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2631
2632 priv->pipe_out[TXDESC_QUEUE_VO] =
2633 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2634 priv->pipe_out[TXDESC_QUEUE_VI] =
2635 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2636 priv->pipe_out[TXDESC_QUEUE_BE] =
2637 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2638 priv->pipe_out[TXDESC_QUEUE_BK] =
2639 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2640 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2641 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2642 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2643 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2644 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2645 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2646 priv->pipe_out[TXDESC_QUEUE_CMD] =
2647 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2648 }
2649
2650 return ret;
2651}
2652
2653void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, bool iqk_ok,
2654 int result[][8], int candidate, bool tx_only)
2655{
2656 u32 oldval, x, tx0_a, reg;
2657 int y, tx0_c;
2658 u32 val32;
2659
2660 if (!iqk_ok)
2661 return;
2662
2663 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2664 oldval = val32 >> 22;
2665
2666 x = result[candidate][0];
2667 if ((x & 0x00000200) != 0)
2668 x = x | 0xfffffc00;
2669 tx0_a = (x * oldval) >> 8;
2670
2671 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2672 val32 &= ~0x3ff;
2673 val32 |= tx0_a;
2674 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2675
2676 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2677 val32 &= ~BIT(31);
2678 if ((x * oldval >> 7) & 0x1)
2679 val32 |= BIT(31);
2680 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2681
2682 y = result[candidate][1];
2683 if ((y & 0x00000200) != 0)
2684 y = y | 0xfffffc00;
2685 tx0_c = (y * oldval) >> 8;
2686
2687 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2688 val32 &= ~0xf0000000;
2689 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2690 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2691
2692 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2693 val32 &= ~0x003f0000;
2694 val32 |= ((tx0_c & 0x3f) << 16);
2695 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2696
2697 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2698 val32 &= ~BIT(29);
2699 if ((y * oldval >> 7) & 0x1)
2700 val32 |= BIT(29);
2701 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2702
2703 if (tx_only) {
2704 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2705 return;
2706 }
2707
2708 reg = result[candidate][2];
2709
2710 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2711 val32 &= ~0x3ff;
2712 val32 |= (reg & 0x3ff);
2713 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2714
2715 reg = result[candidate][3] & 0x3F;
2716
2717 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2718 val32 &= ~0xfc00;
2719 val32 |= ((reg << 10) & 0xfc00);
2720 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2721
2722 reg = (result[candidate][3] >> 6) & 0xF;
2723
2724 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2725 val32 &= ~0xf0000000;
2726 val32 |= (reg << 28);
2727 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2728}
2729
2730void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, bool iqk_ok,
2731 int result[][8], int candidate, bool tx_only)
2732{
2733 u32 oldval, x, tx1_a, reg;
2734 int y, tx1_c;
2735 u32 val32;
2736
2737 if (!iqk_ok)
2738 return;
2739
2740 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2741 oldval = val32 >> 22;
2742
2743 x = result[candidate][4];
2744 if ((x & 0x00000200) != 0)
2745 x = x | 0xfffffc00;
2746 tx1_a = (x * oldval) >> 8;
2747
2748 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2749 val32 &= ~0x3ff;
2750 val32 |= tx1_a;
2751 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2752
2753 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2754 val32 &= ~BIT(27);
2755 if ((x * oldval >> 7) & 0x1)
2756 val32 |= BIT(27);
2757 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2758
2759 y = result[candidate][5];
2760 if ((y & 0x00000200) != 0)
2761 y = y | 0xfffffc00;
2762 tx1_c = (y * oldval) >> 8;
2763
2764 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
2765 val32 &= ~0xf0000000;
2766 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
2767 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
2768
2769 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2770 val32 &= ~0x003f0000;
2771 val32 |= ((tx1_c & 0x3f) << 16);
2772 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2773
2774 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2775 val32 &= ~BIT(25);
2776 if ((y * oldval >> 7) & 0x1)
2777 val32 |= BIT(25);
2778 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2779
2780 if (tx_only) {
2781 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2782 return;
2783 }
2784
2785 reg = result[candidate][6];
2786
2787 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2788 val32 &= ~0x3ff;
2789 val32 |= (reg & 0x3ff);
2790 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2791
2792 reg = result[candidate][7] & 0x3f;
2793
2794 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
2795 val32 &= ~0xfc00;
2796 val32 |= ((reg << 10) & 0xfc00);
2797 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
2798
2799 reg = (result[candidate][7] >> 6) & 0xf;
2800
2801 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
2802 val32 &= ~0x0000f000;
2803 val32 |= (reg << 12);
2804 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
2805}
2806
2807#define MAX_TOLERANCE 5
2808
2809static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
2810 int result[][8], int c1, int c2)
2811{
2812 u32 i, j, diff, simubitmap, bound = 0;
2813 int candidate[2] = {-1, -1};
2814 bool retval = true;
2815
2816 if (priv->tx_paths > 1)
2817 bound = 8;
2818 else
2819 bound = 4;
2820
2821 simubitmap = 0;
2822
2823 for (i = 0; i < bound; i++) {
2824 diff = (result[c1][i] > result[c2][i]) ?
2825 (result[c1][i] - result[c2][i]) :
2826 (result[c2][i] - result[c1][i]);
2827 if (diff > MAX_TOLERANCE) {
2828 if ((i == 2 || i == 6) && !simubitmap) {
2829 if (result[c1][i] + result[c1][i + 1] == 0)
2830 candidate[(i / 4)] = c2;
2831 else if (result[c2][i] + result[c2][i + 1] == 0)
2832 candidate[(i / 4)] = c1;
2833 else
2834 simubitmap = simubitmap | (1 << i);
2835 } else {
2836 simubitmap = simubitmap | (1 << i);
2837 }
2838 }
2839 }
2840
2841 if (simubitmap == 0) {
2842 for (i = 0; i < (bound / 4); i++) {
2843 if (candidate[i] >= 0) {
2844 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2845 result[3][j] = result[candidate[i]][j];
2846 retval = false;
2847 }
2848 }
2849 return retval;
2850 } else if (!(simubitmap & 0x0f)) {
2851
2852 for (i = 0; i < 4; i++)
2853 result[3][i] = result[c1][i];
2854 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
2855
2856 for (i = 4; i < 8; i++)
2857 result[3][i] = result[c1][i];
2858 }
2859
2860 return false;
2861}
2862
2863bool rtl8xxxu_gen2_simularity_compare(struct rtl8xxxu_priv *priv,
2864 int result[][8], int c1, int c2)
2865{
2866 u32 i, j, diff, simubitmap, bound = 0;
2867 int candidate[2] = {-1, -1};
2868 int tmp1, tmp2;
2869 bool retval = true;
2870
2871 if (priv->tx_paths > 1)
2872 bound = 8;
2873 else
2874 bound = 4;
2875
2876 simubitmap = 0;
2877
2878 for (i = 0; i < bound; i++) {
2879 if (i & 1) {
2880 if ((result[c1][i] & 0x00000200))
2881 tmp1 = result[c1][i] | 0xfffffc00;
2882 else
2883 tmp1 = result[c1][i];
2884
2885 if ((result[c2][i]& 0x00000200))
2886 tmp2 = result[c2][i] | 0xfffffc00;
2887 else
2888 tmp2 = result[c2][i];
2889 } else {
2890 tmp1 = result[c1][i];
2891 tmp2 = result[c2][i];
2892 }
2893
2894 diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
2895
2896 if (diff > MAX_TOLERANCE) {
2897 if ((i == 2 || i == 6) && !simubitmap) {
2898 if (result[c1][i] + result[c1][i + 1] == 0)
2899 candidate[(i / 4)] = c2;
2900 else if (result[c2][i] + result[c2][i + 1] == 0)
2901 candidate[(i / 4)] = c1;
2902 else
2903 simubitmap = simubitmap | (1 << i);
2904 } else {
2905 simubitmap = simubitmap | (1 << i);
2906 }
2907 }
2908 }
2909
2910 if (simubitmap == 0) {
2911 for (i = 0; i < (bound / 4); i++) {
2912 if (candidate[i] >= 0) {
2913 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
2914 result[3][j] = result[candidate[i]][j];
2915 retval = false;
2916 }
2917 }
2918 return retval;
2919 } else {
2920 if (!(simubitmap & 0x03)) {
2921
2922 for (i = 0; i < 2; i++)
2923 result[3][i] = result[c1][i];
2924 }
2925
2926 if (!(simubitmap & 0x0c)) {
2927
2928 for (i = 2; i < 4; i++)
2929 result[3][i] = result[c1][i];
2930 }
2931
2932 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2933
2934 for (i = 4; i < 6; i++)
2935 result[3][i] = result[c1][i];
2936 }
2937
2938 if (!(simubitmap & 0x30) && priv->tx_paths > 1) {
2939
2940 for (i = 6; i < 8; i++)
2941 result[3][i] = result[c1][i];
2942 }
2943 }
2944
2945 return false;
2946}
2947
2948void
2949rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
2950{
2951 int i;
2952
2953 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2954 backup[i] = rtl8xxxu_read8(priv, reg[i]);
2955
2956 backup[i] = rtl8xxxu_read32(priv, reg[i]);
2957}
2958
2959void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
2960 const u32 *reg, u32 *backup)
2961{
2962 int i;
2963
2964 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
2965 rtl8xxxu_write8(priv, reg[i], backup[i]);
2966
2967 rtl8xxxu_write32(priv, reg[i], backup[i]);
2968}
2969
2970void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2971 u32 *backup, int count)
2972{
2973 int i;
2974
2975 for (i = 0; i < count; i++)
2976 backup[i] = rtl8xxxu_read32(priv, regs[i]);
2977}
2978
2979void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
2980 u32 *backup, int count)
2981{
2982 int i;
2983
2984 for (i = 0; i < count; i++)
2985 rtl8xxxu_write32(priv, regs[i], backup[i]);
2986}
2987
2988
2989void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
2990 bool path_a_on)
2991{
2992 u32 path_on;
2993 int i;
2994
2995 if (priv->tx_paths == 1) {
2996 path_on = priv->fops->adda_1t_path_on;
2997 rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init);
2998 } else {
2999 path_on = path_a_on ? priv->fops->adda_2t_path_on_a :
3000 priv->fops->adda_2t_path_on_b;
3001
3002 rtl8xxxu_write32(priv, regs[0], path_on);
3003 }
3004
3005 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3006 rtl8xxxu_write32(priv, regs[i], path_on);
3007}
3008
3009void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3010 const u32 *regs, u32 *backup)
3011{
3012 int i = 0;
3013
3014 rtl8xxxu_write8(priv, regs[i], 0x3f);
3015
3016 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3017 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3018
3019 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3020}
3021
3022static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3023{
3024 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3025 int result = 0;
3026
3027
3028 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3029 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3030 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3031
3032 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3033
3034 0x28160502;
3035 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3036
3037
3038 if (priv->rf_paths > 1) {
3039 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3040 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3041 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3042 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3043 }
3044
3045
3046 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3047
3048
3049 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3050 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3051
3052 mdelay(1);
3053
3054
3055 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3056 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3057 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3058 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3059
3060 if (!(reg_eac & BIT(28)) &&
3061 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3062 ((reg_e9c & 0x03ff0000) != 0x00420000))
3063 result |= 0x01;
3064 else
3065 goto out;
3066
3067
3068 if (!(reg_eac & BIT(27)) &&
3069 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3070 ((reg_eac & 0x03ff0000) != 0x00360000))
3071 result |= 0x02;
3072 else
3073 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3074 __func__);
3075out:
3076 return result;
3077}
3078
3079static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3080{
3081 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3082 int result = 0;
3083
3084
3085 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3086 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3087
3088 mdelay(1);
3089
3090
3091 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3092 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3093 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3094 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3095 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3096
3097 if (!(reg_eac & BIT(31)) &&
3098 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3099 ((reg_ebc & 0x03ff0000) != 0x00420000))
3100 result |= 0x01;
3101 else
3102 goto out;
3103
3104 if (!(reg_eac & BIT(30)) &&
3105 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3106 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3107 result |= 0x02;
3108 else
3109 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3110 __func__);
3111out:
3112 return result;
3113}
3114
3115static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3116 int result[][8], int t)
3117{
3118 struct device *dev = &priv->udev->dev;
3119 u32 i, val32;
3120 int path_a_ok, path_b_ok;
3121 int retry = 2;
3122 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3123 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3124 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3125 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3126 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3127 REG_TX_TO_TX, REG_RX_CCK,
3128 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3129 REG_RX_TO_RX, REG_STANDBY,
3130 REG_SLEEP, REG_PMPD_ANAEN
3131 };
3132 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3133 REG_TXPAUSE, REG_BEACON_CTRL,
3134 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3135 };
3136 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3137 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3138 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3139 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3140 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3141 };
3142
3143
3144
3145
3146
3147
3148 if (t == 0) {
3149
3150 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3151 RTL8XXXU_ADDA_REGS);
3152 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3153 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3154 priv->bb_backup, RTL8XXXU_BB_REGS);
3155 }
3156
3157 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3158
3159 if (t == 0) {
3160 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3161 if (val32 & FPGA0_HSSI_PARM1_PI)
3162 priv->pi_enabled = 1;
3163 }
3164
3165 if (!priv->pi_enabled) {
3166
3167 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3168 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3169 }
3170
3171 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3172 val32 &= ~FPGA_RF_MODE_CCK;
3173 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3174
3175 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3176 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3177 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3178
3179 if (!priv->no_pape) {
3180 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3181 val32 |= (FPGA0_RF_PAPE |
3182 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3183 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3184 }
3185
3186 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3187 val32 &= ~BIT(10);
3188 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3189 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3190 val32 &= ~BIT(10);
3191 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3192
3193 if (priv->tx_paths > 1) {
3194 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3195 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3196 }
3197
3198
3199 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3200
3201
3202 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3203
3204 if (priv->tx_paths > 1)
3205 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3206
3207
3208 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3209 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3210 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3211
3212 for (i = 0; i < retry; i++) {
3213 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3214 if (path_a_ok == 0x03) {
3215 val32 = rtl8xxxu_read32(priv,
3216 REG_TX_POWER_BEFORE_IQK_A);
3217 result[t][0] = (val32 >> 16) & 0x3ff;
3218 val32 = rtl8xxxu_read32(priv,
3219 REG_TX_POWER_AFTER_IQK_A);
3220 result[t][1] = (val32 >> 16) & 0x3ff;
3221 val32 = rtl8xxxu_read32(priv,
3222 REG_RX_POWER_BEFORE_IQK_A_2);
3223 result[t][2] = (val32 >> 16) & 0x3ff;
3224 val32 = rtl8xxxu_read32(priv,
3225 REG_RX_POWER_AFTER_IQK_A_2);
3226 result[t][3] = (val32 >> 16) & 0x3ff;
3227 break;
3228 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3229
3230 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3231 __func__);
3232
3233 val32 = rtl8xxxu_read32(priv,
3234 REG_TX_POWER_BEFORE_IQK_A);
3235 result[t][0] = (val32 >> 16) & 0x3ff;
3236 val32 = rtl8xxxu_read32(priv,
3237 REG_TX_POWER_AFTER_IQK_A);
3238 result[t][1] = (val32 >> 16) & 0x3ff;
3239 }
3240 }
3241
3242 if (!path_a_ok)
3243 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3244
3245 if (priv->tx_paths > 1) {
3246
3247
3248
3249 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3250 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3251 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3252
3253
3254 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3255
3256 for (i = 0; i < retry; i++) {
3257 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3258 if (path_b_ok == 0x03) {
3259 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3260 result[t][4] = (val32 >> 16) & 0x3ff;
3261 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3262 result[t][5] = (val32 >> 16) & 0x3ff;
3263 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3264 result[t][6] = (val32 >> 16) & 0x3ff;
3265 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3266 result[t][7] = (val32 >> 16) & 0x3ff;
3267 break;
3268 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3269
3270 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3271 result[t][4] = (val32 >> 16) & 0x3ff;
3272 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3273 result[t][5] = (val32 >> 16) & 0x3ff;
3274 }
3275 }
3276
3277 if (!path_b_ok)
3278 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3279 }
3280
3281
3282 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3283
3284 if (t) {
3285 if (!priv->pi_enabled) {
3286
3287
3288
3289
3290 val32 = 0x01000000;
3291 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3292 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3293 }
3294
3295
3296 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3297 RTL8XXXU_ADDA_REGS);
3298
3299
3300 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3301
3302
3303 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3304 priv->bb_backup, RTL8XXXU_BB_REGS);
3305
3306
3307 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3308
3309 if (priv->tx_paths > 1) {
3310 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3311 0x00032ed3);
3312 }
3313
3314
3315 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3316 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3317 }
3318}
3319
3320void rtl8xxxu_gen2_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start)
3321{
3322 struct h2c_cmd h2c;
3323
3324 memset(&h2c, 0, sizeof(struct h2c_cmd));
3325 h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION;
3326 h2c.bt_wlan_calibration.data = start;
3327
3328 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration));
3329}
3330
3331void rtl8xxxu_gen1_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3332{
3333 struct device *dev = &priv->udev->dev;
3334 int result[4][8];
3335 int i, candidate;
3336 bool path_a_ok, path_b_ok;
3337 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3338 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3339 s32 reg_tmp = 0;
3340 bool simu;
3341
3342 memset(result, 0, sizeof(result));
3343 candidate = -1;
3344
3345 path_a_ok = false;
3346 path_b_ok = false;
3347
3348 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3349
3350 for (i = 0; i < 3; i++) {
3351 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3352
3353 if (i == 1) {
3354 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3355 if (simu) {
3356 candidate = 0;
3357 break;
3358 }
3359 }
3360
3361 if (i == 2) {
3362 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3363 if (simu) {
3364 candidate = 0;
3365 break;
3366 }
3367
3368 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3369 if (simu) {
3370 candidate = 1;
3371 } else {
3372 for (i = 0; i < 8; i++)
3373 reg_tmp += result[3][i];
3374
3375 if (reg_tmp)
3376 candidate = 3;
3377 else
3378 candidate = -1;
3379 }
3380 }
3381 }
3382
3383 for (i = 0; i < 4; i++) {
3384 reg_e94 = result[i][0];
3385 reg_e9c = result[i][1];
3386 reg_ea4 = result[i][2];
3387 reg_eac = result[i][3];
3388 reg_eb4 = result[i][4];
3389 reg_ebc = result[i][5];
3390 reg_ec4 = result[i][6];
3391 reg_ecc = result[i][7];
3392 }
3393
3394 if (candidate >= 0) {
3395 reg_e94 = result[candidate][0];
3396 priv->rege94 = reg_e94;
3397 reg_e9c = result[candidate][1];
3398 priv->rege9c = reg_e9c;
3399 reg_ea4 = result[candidate][2];
3400 reg_eac = result[candidate][3];
3401 reg_eb4 = result[candidate][4];
3402 priv->regeb4 = reg_eb4;
3403 reg_ebc = result[candidate][5];
3404 priv->regebc = reg_ebc;
3405 reg_ec4 = result[candidate][6];
3406 reg_ecc = result[candidate][7];
3407 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3408 dev_dbg(dev,
3409 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3410 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3411 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3412 path_a_ok = true;
3413 path_b_ok = true;
3414 } else {
3415 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3416 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3417 }
3418
3419 if (reg_e94 && candidate >= 0)
3420 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3421 candidate, (reg_ea4 == 0));
3422
3423 if (priv->tx_paths > 1 && reg_eb4)
3424 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3425 candidate, (reg_ec4 == 0));
3426
3427 rtl8xxxu_save_regs(priv, rtl8xxxu_iqk_phy_iq_bb_reg,
3428 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3429}
3430
3431static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3432{
3433 u32 val32;
3434 u32 rf_amode, rf_bmode = 0, lstf;
3435
3436
3437 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3438
3439 if (lstf & OFDM_LSTF_MASK) {
3440
3441 val32 = lstf & ~OFDM_LSTF_MASK;
3442 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3443
3444
3445 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3446
3447
3448 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3449 (rf_amode & 0x8ffff) | 0x10000);
3450
3451
3452 if (priv->tx_paths > 1) {
3453 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3454 RF6052_REG_AC);
3455
3456 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3457 (rf_bmode & 0x8ffff) | 0x10000);
3458 }
3459 } else {
3460
3461
3462 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3463 }
3464
3465
3466 if (priv->fops->has_s0s1)
3467 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0);
3468 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3469 val32 |= 0x08000;
3470 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3471
3472 msleep(100);
3473
3474 if (priv->fops->has_s0s1)
3475 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0);
3476
3477
3478 if (lstf & OFDM_LSTF_MASK) {
3479
3480 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3481 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3482
3483
3484 if (priv->tx_paths > 1)
3485 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3486 rf_bmode);
3487 } else
3488 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3489}
3490
3491static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3492{
3493 int i;
3494 u16 reg;
3495
3496 reg = REG_MACID;
3497
3498 for (i = 0; i < ETH_ALEN; i++)
3499 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3500
3501 return 0;
3502}
3503
3504static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3505{
3506 int i;
3507 u16 reg;
3508
3509 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3510
3511 reg = REG_BSSID;
3512
3513 for (i = 0; i < ETH_ALEN; i++)
3514 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3515
3516 return 0;
3517}
3518
3519static void
3520rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3521{
3522 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3523 u8 max_agg = 0xf;
3524 int i;
3525
3526 ampdu_factor = 1 << (ampdu_factor + 2);
3527 if (ampdu_factor > max_agg)
3528 ampdu_factor = max_agg;
3529
3530 for (i = 0; i < 4; i++) {
3531 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3532 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3533
3534 if ((vals[i] & 0x0f) > ampdu_factor)
3535 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3536
3537 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3538 }
3539}
3540
3541static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3542{
3543 u8 val8;
3544
3545 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3546 val8 &= 0xf8;
3547 val8 |= density;
3548 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3549}
3550
3551static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3552{
3553 u8 val8;
3554 int count, ret = 0;
3555
3556
3557
3558
3559 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3560
3561
3562 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3563 val8 &= ~LEDCFG2_DPDT_SELECT;
3564 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3565
3566
3567 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3568 val8 |= BIT(1);
3569 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3570
3571 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3572 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3573 if ((val8 & BIT(1)) == 0)
3574 break;
3575 udelay(10);
3576 }
3577
3578 if (!count) {
3579 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3580 __func__);
3581 ret = -EBUSY;
3582 goto exit;
3583 }
3584
3585
3586 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3587 val8 |= SYS_ISO_ANALOG_IPS;
3588 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3589
3590
3591 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3592 val8 &= ~LDOA15_ENABLE;
3593 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3594
3595exit:
3596 return ret;
3597}
3598
3599int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3600{
3601 u8 val8;
3602 u8 val32;
3603 int count, ret = 0;
3604
3605 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3606
3607
3608
3609
3610 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3611 val32 = rtl8xxxu_read32(priv, 0x5f8);
3612 if (!val32)
3613 break;
3614 udelay(10);
3615 }
3616
3617 if (!count) {
3618 dev_warn(&priv->udev->dev,
3619 "%s: RX poll timed out (0x05f8)\n", __func__);
3620 ret = -EBUSY;
3621 goto exit;
3622 }
3623
3624
3625 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3626 val8 &= ~SYS_FUNC_BBRSTB;
3627 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3628
3629 udelay(2);
3630
3631
3632 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3633 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3634 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3635
3636
3637 val8 = rtl8xxxu_read8(priv, REG_CR);
3638 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3639 rtl8xxxu_write8(priv, REG_CR, val8);
3640
3641
3642 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3643 val8 &= ~BIT(1);
3644 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3645
3646
3647 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3648 val8 |= DUAL_TSF_TX_OK;
3649 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3650
3651exit:
3652 return ret;
3653}
3654
3655void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3656{
3657 u8 val8;
3658
3659
3660 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3661 val8 &= ~(BIT(3) | BIT(7));
3662 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3663
3664
3665 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3666 val8 &= ~BIT(0);
3667 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3668
3669
3670 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3671 val8 &= ~(BIT(3) | BIT(4));
3672 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3673}
3674
3675static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3676{
3677 u8 val8;
3678
3679
3680 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3681
3682
3683 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3684 val8 &= ~BIT(4);
3685 val8 |= BIT(3);
3686 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3687
3688 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3689 val8 |= BIT(7);
3690 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3691
3692
3693 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3694 val8 |= BIT(0);
3695 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3696
3697 return 0;
3698}
3699
3700int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv)
3701{
3702 struct device *dev = &priv->udev->dev;
3703 u32 val32;
3704 int retry, retval;
3705
3706 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3707
3708 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3709 val32 |= RXPKT_NUM_RW_RELEASE_EN;
3710 rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32);
3711
3712 retry = 100;
3713 retval = -EBUSY;
3714
3715 do {
3716 val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM);
3717 if (val32 & RXPKT_NUM_RXDMA_IDLE) {
3718 retval = 0;
3719 break;
3720 }
3721 } while (retry--);
3722
3723 rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0);
3724 rtl8xxxu_write32(priv, REG_RQPN, 0x80000000);
3725 mdelay(2);
3726
3727 if (!retry)
3728 dev_warn(dev, "Failed to flush FIFO\n");
3729
3730 return retval;
3731}
3732
3733void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv)
3734{
3735
3736 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3737 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
3738 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3739
3740
3741
3742
3743 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
3744
3745
3746
3747
3748
3749 if (!(!priv->chip_cut && priv->vendor_umc)) {
3750 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
3751 rtl8xxxu_write8(priv, 0xfe41, 0x94);
3752 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3753
3754 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
3755 rtl8xxxu_write8(priv, 0xfe41, 0x19);
3756 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3757
3758 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
3759 rtl8xxxu_write8(priv, 0xfe41, 0x91);
3760 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3761
3762 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
3763 rtl8xxxu_write8(priv, 0xfe41, 0x81);
3764 rtl8xxxu_write8(priv, 0xfe42, 0x80);
3765 }
3766}
3767
3768void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv)
3769{
3770 u32 val32;
3771
3772 val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK);
3773 val32 |= TXDMA_OFFSET_DROP_DATA_EN;
3774 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32);
3775}
3776
3777void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
3778{
3779 u8 val8;
3780 u16 val16;
3781 u32 val32;
3782
3783
3784
3785
3786 if (priv->rtl_chip == RTL8188R) {
3787 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
3788 val32 |= BIT(1);
3789 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
3790 }
3791
3792 rtl8xxxu_flush_fifo(priv);
3793
3794 rtl8xxxu_active_to_lps(priv);
3795
3796
3797 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
3798
3799
3800 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
3801 rtl8xxxu_firmware_self_reset(priv);
3802
3803
3804 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
3805 val16 &= ~SYS_FUNC_CPU_ENABLE;
3806 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
3807
3808
3809 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
3810
3811 rtl8xxxu_active_to_emu(priv);
3812 rtl8xxxu_emu_to_disabled(priv);
3813
3814
3815 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3816 val8 &= ~BIT(0);
3817 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3818
3819 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
3820 val8 |= BIT(0);
3821 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
3822
3823
3824 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
3825}
3826
3827#ifdef NEED_PS_TDMA
3828static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv,
3829 u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5)
3830{
3831 struct h2c_cmd h2c;
3832
3833 memset(&h2c, 0, sizeof(struct h2c_cmd));
3834 h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA;
3835 h2c.b_type_dma.data1 = arg1;
3836 h2c.b_type_dma.data2 = arg2;
3837 h2c.b_type_dma.data3 = arg3;
3838 h2c.b_type_dma.data4 = arg4;
3839 h2c.b_type_dma.data5 = arg5;
3840 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma));
3841}
3842#endif
3843
3844void rtl8xxxu_gen2_disable_rf(struct rtl8xxxu_priv *priv)
3845{
3846 u32 val32;
3847
3848 val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA);
3849 val32 &= ~(BIT(22) | BIT(23));
3850 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32);
3851}
3852
3853static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv)
3854{
3855 struct rtl8xxxu_fileops *fops = priv->fops;
3856 u32 hq, lq, nq, eq, pubq;
3857 u32 val32;
3858
3859 hq = 0;
3860 lq = 0;
3861 nq = 0;
3862 eq = 0;
3863 pubq = 0;
3864
3865 if (priv->ep_tx_high_queue)
3866 hq = fops->page_num_hi;
3867 if (priv->ep_tx_low_queue)
3868 lq = fops->page_num_lo;
3869 if (priv->ep_tx_normal_queue)
3870 nq = fops->page_num_norm;
3871
3872 val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT);
3873 rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32);
3874
3875 pubq = fops->total_page_num - hq - lq - nq - 1;
3876
3877 val32 = RQPN_LOAD;
3878 val32 |= (hq << RQPN_HI_PQ_SHIFT);
3879 val32 |= (lq << RQPN_LO_PQ_SHIFT);
3880 val32 |= (pubq << RQPN_PUB_PQ_SHIFT);
3881
3882 rtl8xxxu_write32(priv, REG_RQPN, val32);
3883}
3884
3885static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
3886{
3887 struct rtl8xxxu_priv *priv = hw->priv;
3888 struct device *dev = &priv->udev->dev;
3889 struct rtl8xxxu_fileops *fops = priv->fops;
3890 bool macpower;
3891 int ret;
3892 u8 val8;
3893 u16 val16;
3894 u32 val32;
3895
3896
3897 val8 = rtl8xxxu_read8(priv, REG_CR);
3898
3899
3900
3901
3902
3903 if (val8 == 0xea)
3904 macpower = false;
3905 else
3906 macpower = true;
3907
3908 ret = fops->power_on(priv);
3909 if (ret < 0) {
3910 dev_warn(dev, "%s: Failed power on\n", __func__);
3911 goto exit;
3912 }
3913
3914 if (!macpower)
3915 rtl8xxxu_init_queue_reserved_page(priv);
3916
3917 ret = rtl8xxxu_init_queue_priority(priv);
3918 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
3919 if (ret)
3920 goto exit;
3921
3922
3923
3924
3925 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, fops->trxff_boundary);
3926
3927 ret = rtl8xxxu_download_firmware(priv);
3928 dev_dbg(dev, "%s: download_firmware %i\n", __func__, ret);
3929 if (ret)
3930 goto exit;
3931 ret = rtl8xxxu_start_firmware(priv);
3932 dev_dbg(dev, "%s: start_firmware %i\n", __func__, ret);
3933 if (ret)
3934 goto exit;
3935
3936 if (fops->phy_init_antenna_selection)
3937 fops->phy_init_antenna_selection(priv);
3938
3939 ret = rtl8xxxu_init_mac(priv);
3940
3941 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
3942 if (ret)
3943 goto exit;
3944
3945 ret = rtl8xxxu_init_phy_bb(priv);
3946 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
3947 if (ret)
3948 goto exit;
3949
3950 ret = fops->init_phy_rf(priv);
3951 if (ret)
3952 goto exit;
3953
3954
3955 if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E)
3956 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
3957
3958 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
3959 FPGA0_RF_ANTSWB |
3960 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB) << FPGA0_RF_BD_CTRL_SHIFT);
3961 if (!priv->no_pape) {
3962 val32 |= (FPGA0_RF_PAPE |
3963 (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3964 }
3965 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3966
3967
3968 if (priv->rtl_chip != RTL8192E)
3969 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210);
3970
3971 if (!macpower) {
3972
3973
3974
3975 val8 = fops->total_page_num + 1;
3976
3977 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
3978 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
3979 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
3980 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
3981 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
3982 }
3983
3984
3985
3986
3987
3988 val8 = (fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) |
3989 (fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT);
3990 if (priv->rtl_chip != RTL8192E)
3991 rtl8xxxu_write8(priv, REG_PBP, val8);
3992
3993 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
3994 if (!macpower) {
3995 ret = fops->llt_init(priv);
3996 if (ret) {
3997 dev_warn(dev, "%s: LLT table init failed\n", __func__);
3998 goto exit;
3999 }
4000
4001
4002
4003
4004 fops->usb_quirks(priv);
4005
4006
4007
4008
4009 if (fops->has_tx_report) {
4010 val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL);
4011 val8 |= TX_REPORT_CTRL_TIMER_ENABLE;
4012 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8);
4013
4014 rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02);
4015
4016 rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0);
4017
4018
4019 val8 = rtl8xxxu_read8(priv, 0xa3);
4020 val8 &= 0xf8;
4021 rtl8xxxu_write8(priv, 0xa3, val8);
4022 }
4023 }
4024
4025
4026
4027
4028 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4029
4030 if (priv->rtl_chip == RTL8192E) {
4031 rtl8xxxu_write32(priv, REG_HIMR0, 0x00);
4032 rtl8xxxu_write32(priv, REG_HIMR1, 0x00);
4033 } else {
4034
4035
4036
4037 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4038 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4039 }
4040
4041 rtl8xxxu_set_mac(priv);
4042 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4043
4044
4045
4046
4047 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
4048 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4049 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4050 rtl8xxxu_write32(priv, REG_RCR, val32);
4051
4052
4053
4054
4055 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4056 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4057
4058
4059
4060
4061 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4062 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4063 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4064 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4065
4066
4067 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4068 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4069 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4070
4071
4072
4073
4074 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4075
4076
4077 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4078
4079
4080 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4081
4082
4083 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4084 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4085 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4086 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4087
4088
4089 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4090 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4091 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4092 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4093
4094 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4095 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4096 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4097
4098
4099 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4100
4101
4102
4103
4104 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4105 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4106 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4107 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4108 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4109 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4110
4111
4112
4113
4114 if (priv->rtl_chip == RTL8723B) {
4115
4116
4117
4118 val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B);
4119 val8 &= ~(BIT(4) | BIT(5));
4120 val8 |= BIT(4);
4121 val8 |= BIT(1) | BIT(2) | BIT(3);
4122 rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8);
4123
4124
4125
4126
4127 val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B);
4128 val8 |= BIT(7);
4129 rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8);
4130
4131 rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14);
4132 rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e);
4133 rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff);
4134 rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18);
4135 rtl8xxxu_write8(priv, REG_PIFS, 0x00);
4136 rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50);
4137 rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50);
4138
4139 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL);
4140 val8 |= BIT(5) | BIT(6);
4141 rtl8xxxu_write8(priv, REG_RSV_CTRL, val8);
4142 }
4143
4144 if (fops->init_aggregation)
4145 fops->init_aggregation(priv);
4146
4147
4148
4149
4150 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4151 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4152 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4153
4154
4155
4156
4157 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4158
4159
4160
4161
4162 fops->set_tx_power(priv, 1, false);
4163
4164
4165 if (priv->rtl_chip != RTL8192E) {
4166 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4167 val8 |= LEDCFG2_DPDT_SELECT;
4168 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4169 }
4170
4171 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4172
4173
4174 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4175
4176 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4177
4178 if (fops->init_statistics)
4179 fops->init_statistics(priv);
4180
4181 if (priv->rtl_chip == RTL8192E) {
4182
4183
4184
4185
4186 val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL);
4187 val8 &= ~BIT(3);
4188 rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8);
4189
4190
4191
4192 rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00);
4193 }
4194
4195 rtl8723a_phy_lc_calibrate(priv);
4196
4197 fops->phy_iq_calibrate(priv);
4198
4199
4200
4201
4202 if (fops->gen2_thermal_meter)
4203 rtl8xxxu_write_rfreg(priv,
4204 RF_A, RF6052_REG_T_METER_8723B, 0x37cf8);
4205 else
4206 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4207
4208
4209 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4210 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4211
4212 if (priv->rtl_chip == RTL8723A) {
4213
4214
4215
4216
4217
4218 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4219 if ((val32 & 0xff000000) != 0x83000000) {
4220 val32 |= FPGA_RF_MODE_CCK;
4221 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4222 }
4223 } else if (priv->rtl_chip == RTL8192E) {
4224 rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00);
4225 }
4226
4227 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4228 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4229
4230 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4231
4232 if (priv->rtl_chip == RTL8192E) {
4233
4234
4235
4236 val32 = rtl8xxxu_read32(priv, REG_AFE_MISC);
4237 rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75);
4238 val32 &= 0xfff00fff;
4239 val32 |= 0x0007e000;
4240 rtl8xxxu_write32(priv, REG_AFE_MISC, val32);
4241 }
4242exit:
4243 return ret;
4244}
4245
4246static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4247 struct ieee80211_key_conf *key, const u8 *mac)
4248{
4249 u32 cmd, val32, addr, ctrl;
4250 int j, i, tmp_debug;
4251
4252 tmp_debug = rtl8xxxu_debug;
4253 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4254 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4255
4256
4257
4258
4259
4260 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4261 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4262
4263 for (j = 5; j >= 0; j--) {
4264 switch (j) {
4265 case 0:
4266 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4267 break;
4268 case 1:
4269 val32 = mac[2] | (mac[3] << 8) |
4270 (mac[4] << 16) | (mac[5] << 24);
4271 break;
4272 default:
4273 i = (j - 2) << 2;
4274 val32 = key->key[i] | (key->key[i + 1] << 8) |
4275 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4276 break;
4277 }
4278
4279 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4280 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4281 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4282 udelay(100);
4283 }
4284
4285 rtl8xxxu_debug = tmp_debug;
4286}
4287
4288static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
4289 struct ieee80211_vif *vif, const u8 *mac)
4290{
4291 struct rtl8xxxu_priv *priv = hw->priv;
4292 u8 val8;
4293
4294 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4295 val8 |= BEACON_DISABLE_TSF_UPDATE;
4296 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4297}
4298
4299static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4300 struct ieee80211_vif *vif)
4301{
4302 struct rtl8xxxu_priv *priv = hw->priv;
4303 u8 val8;
4304
4305 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4306 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4307 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4308}
4309
4310void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv, u32 ramask, int sgi)
4311{
4312 struct h2c_cmd h2c;
4313
4314 memset(&h2c, 0, sizeof(struct h2c_cmd));
4315
4316 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4317 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4318 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4319
4320 h2c.ramask.arg = 0x80;
4321 if (sgi)
4322 h2c.ramask.arg |= 0x20;
4323
4324 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4325 __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask));
4326 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.ramask));
4327}
4328
4329void rtl8xxxu_gen2_update_rate_mask(struct rtl8xxxu_priv *priv,
4330 u32 ramask, int sgi)
4331{
4332 struct h2c_cmd h2c;
4333 u8 bw = 0;
4334
4335 memset(&h2c, 0, sizeof(struct h2c_cmd));
4336
4337 h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID;
4338 h2c.b_macid_cfg.ramask0 = ramask & 0xff;
4339 h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff;
4340 h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff;
4341 h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff;
4342
4343 h2c.ramask.arg = 0x80;
4344 h2c.b_macid_cfg.data1 = 0;
4345 if (sgi)
4346 h2c.b_macid_cfg.data1 |= BIT(7);
4347
4348 h2c.b_macid_cfg.data2 = bw;
4349
4350 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n",
4351 __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg));
4352 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg));
4353}
4354
4355void rtl8xxxu_gen1_report_connect(struct rtl8xxxu_priv *priv,
4356 u8 macid, bool connect)
4357{
4358 struct h2c_cmd h2c;
4359
4360 memset(&h2c, 0, sizeof(struct h2c_cmd));
4361
4362 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4363
4364 if (connect)
4365 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4366 else
4367 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4368
4369 rtl8xxxu_gen1_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss));
4370}
4371
4372void rtl8xxxu_gen2_report_connect(struct rtl8xxxu_priv *priv,
4373 u8 macid, bool connect)
4374{
4375#ifdef RTL8XXXU_GEN2_REPORT_CONNECT
4376
4377
4378
4379
4380
4381
4382 struct h2c_cmd h2c;
4383
4384 memset(&h2c, 0, sizeof(struct h2c_cmd));
4385
4386 h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT;
4387 if (connect)
4388 h2c.media_status_rpt.parm |= BIT(0);
4389 else
4390 h2c.media_status_rpt.parm &= ~BIT(0);
4391
4392 rtl8xxxu_gen2_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt));
4393#endif
4394}
4395
4396void rtl8xxxu_gen1_init_aggregation(struct rtl8xxxu_priv *priv)
4397{
4398 u8 agg_ctrl, usb_spec, page_thresh, timeout;
4399
4400 usb_spec = rtl8xxxu_read8(priv, REG_USB_SPECIAL_OPTION);
4401 usb_spec &= ~USB_SPEC_USB_AGG_ENABLE;
4402 rtl8xxxu_write8(priv, REG_USB_SPECIAL_OPTION, usb_spec);
4403
4404 agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL);
4405 agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN;
4406
4407 if (!rtl8xxxu_dma_aggregation) {
4408 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4409 return;
4410 }
4411
4412 agg_ctrl |= TRXDMA_CTRL_RXDMA_AGG_EN;
4413 rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl);
4414
4415
4416
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426
4427
4428 page_thresh = (priv->fops->rx_agg_buf_size / 512);
4429 if (rtl8xxxu_dma_agg_pages >= 0) {
4430 if (rtl8xxxu_dma_agg_pages <= page_thresh)
4431 timeout = page_thresh;
4432 else if (rtl8xxxu_dma_agg_pages <= 6)
4433 dev_err(&priv->udev->dev,
4434 "%s: dma_agg_pages=%i too small, minimum is 6\n",
4435 __func__, rtl8xxxu_dma_agg_pages);
4436 else
4437 dev_err(&priv->udev->dev,
4438 "%s: dma_agg_pages=%i larger than limit %i\n",
4439 __func__, rtl8xxxu_dma_agg_pages, page_thresh);
4440 }
4441 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH, page_thresh);
4442
4443
4444
4445
4446
4447 timeout = 4;
4448
4449 if (rtl8xxxu_dma_agg_timeout >= 0) {
4450 if (rtl8xxxu_dma_agg_timeout <= 127)
4451 timeout = rtl8xxxu_dma_agg_timeout;
4452 else
4453 dev_err(&priv->udev->dev,
4454 "%s: Invalid dma_agg_timeout: %i\n",
4455 __func__, rtl8xxxu_dma_agg_timeout);
4456 }
4457
4458 rtl8xxxu_write8(priv, REG_RXDMA_AGG_PG_TH + 1, timeout);
4459 rtl8xxxu_write8(priv, REG_USB_DMA_AGG_TO, timeout);
4460 priv->rx_buf_aggregation = 1;
4461}
4462
4463static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4464{
4465 u32 val32;
4466 u8 rate_idx = 0;
4467
4468 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4469
4470 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4471 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4472 val32 |= rate_cfg;
4473 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4474
4475 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4476
4477 while (rate_cfg) {
4478 rate_cfg = (rate_cfg >> 1);
4479 rate_idx++;
4480 }
4481 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4482}
4483
4484static void
4485rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4486 struct ieee80211_bss_conf *bss_conf, u32 changed)
4487{
4488 struct rtl8xxxu_priv *priv = hw->priv;
4489 struct device *dev = &priv->udev->dev;
4490 struct ieee80211_sta *sta;
4491 u32 val32;
4492 u8 val8;
4493
4494 if (changed & BSS_CHANGED_ASSOC) {
4495 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4496
4497 rtl8xxxu_set_linktype(priv, vif->type);
4498
4499 if (bss_conf->assoc) {
4500 u32 ramask;
4501 int sgi = 0;
4502
4503 rcu_read_lock();
4504 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4505 if (!sta) {
4506 dev_info(dev, "%s: ASSOC no sta found\n",
4507 __func__);
4508 rcu_read_unlock();
4509 goto error;
4510 }
4511
4512 if (sta->ht_cap.ht_supported)
4513 dev_info(dev, "%s: HT supported\n", __func__);
4514 if (sta->vht_cap.vht_supported)
4515 dev_info(dev, "%s: VHT supported\n", __func__);
4516
4517
4518 ramask = (sta->supp_rates[0] & 0xfff) |
4519 sta->ht_cap.mcs.rx_mask[0] << 12 |
4520 sta->ht_cap.mcs.rx_mask[1] << 20;
4521 if (sta->ht_cap.cap &
4522 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4523 sgi = 1;
4524 rcu_read_unlock();
4525
4526 priv->fops->update_rate_mask(priv, ramask, sgi);
4527
4528 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4529
4530 rtl8xxxu_stop_tx_beacon(priv);
4531
4532
4533 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4534 0xc000 | bss_conf->aid);
4535
4536 priv->fops->report_connect(priv, 0, true);
4537 } else {
4538 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4539 val8 |= BEACON_DISABLE_TSF_UPDATE;
4540 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4541
4542 priv->fops->report_connect(priv, 0, false);
4543 }
4544 }
4545
4546 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4547 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4548 bss_conf->use_short_preamble);
4549 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4550 if (bss_conf->use_short_preamble)
4551 val32 |= RSR_ACK_SHORT_PREAMBLE;
4552 else
4553 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4554 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4555 }
4556
4557 if (changed & BSS_CHANGED_ERP_SLOT) {
4558 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4559 bss_conf->use_short_slot);
4560
4561 if (bss_conf->use_short_slot)
4562 val8 = 9;
4563 else
4564 val8 = 20;
4565 rtl8xxxu_write8(priv, REG_SLOT, val8);
4566 }
4567
4568 if (changed & BSS_CHANGED_BSSID) {
4569 dev_dbg(dev, "Changed BSSID!\n");
4570 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4571 }
4572
4573 if (changed & BSS_CHANGED_BASIC_RATES) {
4574 dev_dbg(dev, "Changed BASIC_RATES!\n");
4575 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4576 }
4577error:
4578 return;
4579}
4580
4581static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4582{
4583 u32 rtlqueue;
4584
4585 switch (queue) {
4586 case IEEE80211_AC_VO:
4587 rtlqueue = TXDESC_QUEUE_VO;
4588 break;
4589 case IEEE80211_AC_VI:
4590 rtlqueue = TXDESC_QUEUE_VI;
4591 break;
4592 case IEEE80211_AC_BE:
4593 rtlqueue = TXDESC_QUEUE_BE;
4594 break;
4595 case IEEE80211_AC_BK:
4596 rtlqueue = TXDESC_QUEUE_BK;
4597 break;
4598 default:
4599 rtlqueue = TXDESC_QUEUE_BE;
4600 }
4601
4602 return rtlqueue;
4603}
4604
4605static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4606{
4607 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4608 u32 queue;
4609
4610 if (ieee80211_is_mgmt(hdr->frame_control))
4611 queue = TXDESC_QUEUE_MGNT;
4612 else
4613 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4614
4615 return queue;
4616}
4617
4618
4619
4620
4621
4622
4623static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc)
4624{
4625 __le16 *ptr = (__le16 *)tx_desc;
4626 u16 csum = 0;
4627 int i;
4628
4629
4630
4631
4632
4633 tx_desc->csum = cpu_to_le16(0);
4634
4635 for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++)
4636 csum = csum ^ le16_to_cpu(ptr[i]);
4637
4638 tx_desc->csum |= cpu_to_le16(csum);
4639}
4640
4641static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4642{
4643 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4644 unsigned long flags;
4645
4646 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4647 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4648 list_del(&tx_urb->list);
4649 priv->tx_urb_free_count--;
4650 usb_free_urb(&tx_urb->urb);
4651 }
4652 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4653}
4654
4655static struct rtl8xxxu_tx_urb *
4656rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4657{
4658 struct rtl8xxxu_tx_urb *tx_urb;
4659 unsigned long flags;
4660
4661 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4662 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4663 struct rtl8xxxu_tx_urb, list);
4664 if (tx_urb) {
4665 list_del(&tx_urb->list);
4666 priv->tx_urb_free_count--;
4667 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4668 !priv->tx_stopped) {
4669 priv->tx_stopped = true;
4670 ieee80211_stop_queues(priv->hw);
4671 }
4672 }
4673
4674 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4675
4676 return tx_urb;
4677}
4678
4679static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4680 struct rtl8xxxu_tx_urb *tx_urb)
4681{
4682 unsigned long flags;
4683
4684 INIT_LIST_HEAD(&tx_urb->list);
4685
4686 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4687
4688 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4689 priv->tx_urb_free_count++;
4690 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4691 priv->tx_stopped) {
4692 priv->tx_stopped = false;
4693 ieee80211_wake_queues(priv->hw);
4694 }
4695
4696 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4697}
4698
4699static void rtl8xxxu_tx_complete(struct urb *urb)
4700{
4701 struct sk_buff *skb = (struct sk_buff *)urb->context;
4702 struct ieee80211_tx_info *tx_info;
4703 struct ieee80211_hw *hw;
4704 struct rtl8xxxu_priv *priv;
4705 struct rtl8xxxu_tx_urb *tx_urb =
4706 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4707
4708 tx_info = IEEE80211_SKB_CB(skb);
4709 hw = tx_info->rate_driver_data[0];
4710 priv = hw->priv;
4711
4712 skb_pull(skb, priv->fops->tx_desc_size);
4713
4714 ieee80211_tx_info_clear_status(tx_info);
4715 tx_info->status.rates[0].idx = -1;
4716 tx_info->status.rates[0].count = 0;
4717
4718 if (!urb->status)
4719 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4720
4721 ieee80211_tx_status_irqsafe(hw, skb);
4722
4723 rtl8xxxu_free_tx_urb(priv, tx_urb);
4724}
4725
4726static void rtl8xxxu_dump_action(struct device *dev,
4727 struct ieee80211_hdr *hdr)
4728{
4729 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4730 u16 cap, timeout;
4731
4732 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4733 return;
4734
4735 switch (mgmt->u.action.u.addba_resp.action_code) {
4736 case WLAN_ACTION_ADDBA_RESP:
4737 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4738 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4739 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4740 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4741 "status %02x\n",
4742 timeout,
4743 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4744 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4745 (cap >> 1) & 0x1,
4746 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4747 break;
4748 case WLAN_ACTION_ADDBA_REQ:
4749 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4750 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4751 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4752 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4753 timeout,
4754 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4755 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4756 (cap >> 1) & 0x1);
4757 break;
4758 default:
4759 dev_info(dev, "action frame %02x\n",
4760 mgmt->u.action.u.addba_resp.action_code);
4761 break;
4762 }
4763}
4764
4765
4766
4767
4768
4769void
4770rtl8xxxu_fill_txdesc_v1(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4771 struct ieee80211_tx_info *tx_info,
4772 struct rtl8xxxu_txdesc32 *tx_desc, bool sgi,
4773 bool short_preamble, bool ampdu_enable, u32 rts_rate)
4774{
4775 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4776 struct rtl8xxxu_priv *priv = hw->priv;
4777 struct device *dev = &priv->udev->dev;
4778 u32 rate;
4779 u16 rate_flags = tx_info->control.rates[0].flags;
4780 u16 seq_number;
4781
4782 if (rate_flags & IEEE80211_TX_RC_MCS &&
4783 !ieee80211_is_mgmt(hdr->frame_control))
4784 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4785 else
4786 rate = tx_rate->hw_value;
4787
4788 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4789 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4790 __func__, rate, cpu_to_le16(tx_desc->pkt_size));
4791
4792 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4793
4794 tx_desc->txdw5 = cpu_to_le32(rate);
4795
4796 if (ieee80211_is_data(hdr->frame_control))
4797 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4798
4799 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT);
4800
4801 if (ampdu_enable)
4802 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE);
4803 else
4804 tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK);
4805
4806 if (ieee80211_is_mgmt(hdr->frame_control)) {
4807 tx_desc->txdw5 = cpu_to_le32(rate);
4808 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_USE_DRIVER_RATE);
4809 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT);
4810 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE);
4811 }
4812
4813 if (ieee80211_is_data_qos(hdr->frame_control))
4814 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS);
4815
4816 if (short_preamble)
4817 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE);
4818
4819 if (sgi)
4820 tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI);
4821
4822
4823
4824
4825 tx_desc->txdw4 |= cpu_to_le32(rts_rate << TXDESC32_RTS_RATE_SHIFT);
4826 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4827 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_RTS_CTS_ENABLE);
4828 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4829 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4830 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_CTS_SELF_ENABLE);
4831 tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE);
4832 }
4833}
4834
4835
4836
4837
4838
4839void
4840rtl8xxxu_fill_txdesc_v2(struct ieee80211_hw *hw, struct ieee80211_hdr *hdr,
4841 struct ieee80211_tx_info *tx_info,
4842 struct rtl8xxxu_txdesc32 *tx_desc32, bool sgi,
4843 bool short_preamble, bool ampdu_enable, u32 rts_rate)
4844{
4845 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4846 struct rtl8xxxu_priv *priv = hw->priv;
4847 struct device *dev = &priv->udev->dev;
4848 struct rtl8xxxu_txdesc40 *tx_desc40;
4849 u32 rate;
4850 u16 rate_flags = tx_info->control.rates[0].flags;
4851 u16 seq_number;
4852
4853 tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc32;
4854
4855 if (rate_flags & IEEE80211_TX_RC_MCS &&
4856 !ieee80211_is_mgmt(hdr->frame_control))
4857 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4858 else
4859 rate = tx_rate->hw_value;
4860
4861 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4862 dev_info(dev, "%s: TX rate: %d, pkt size %d\n",
4863 __func__, rate, cpu_to_le16(tx_desc40->pkt_size));
4864
4865 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4866
4867 tx_desc40->txdw4 = cpu_to_le32(rate);
4868 if (ieee80211_is_data(hdr->frame_control)) {
4869 tx_desc40->txdw4 |= cpu_to_le32(0x1f <<
4870 TXDESC40_DATA_RATE_FB_SHIFT);
4871 }
4872
4873 tx_desc40->txdw9 = cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT);
4874
4875 if (ampdu_enable)
4876 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE);
4877 else
4878 tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK);
4879
4880 if (ieee80211_is_mgmt(hdr->frame_control)) {
4881 tx_desc40->txdw4 = cpu_to_le32(rate);
4882 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_USE_DRIVER_RATE);
4883 tx_desc40->txdw4 |=
4884 cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT);
4885 tx_desc40->txdw4 |= cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE);
4886 }
4887
4888 if (short_preamble)
4889 tx_desc40->txdw5 |= cpu_to_le32(TXDESC40_SHORT_PREAMBLE);
4890
4891 tx_desc40->txdw4 |= cpu_to_le32(rts_rate << TXDESC40_RTS_RATE_SHIFT);
4892
4893
4894
4895 if (rate_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
4896 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE);
4897 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE);
4898 } else if (rate_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
4899
4900
4901
4902
4903 tx_desc40->txdw3 |= cpu_to_le32(TXDESC40_CTS_SELF_ENABLE);
4904 }
4905}
4906
4907static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4908 struct ieee80211_tx_control *control,
4909 struct sk_buff *skb)
4910{
4911 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4912 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4913 struct rtl8xxxu_priv *priv = hw->priv;
4914 struct rtl8xxxu_txdesc32 *tx_desc;
4915 struct rtl8xxxu_tx_urb *tx_urb;
4916 struct ieee80211_sta *sta = NULL;
4917 struct ieee80211_vif *vif = tx_info->control.vif;
4918 struct device *dev = &priv->udev->dev;
4919 u32 queue, rts_rate;
4920 u16 pktlen = skb->len;
4921 u16 seq_number;
4922 u16 rate_flag = tx_info->control.rates[0].flags;
4923 int tx_desc_size = priv->fops->tx_desc_size;
4924 int ret;
4925 bool usedesc40, ampdu_enable, sgi = false, short_preamble = false;
4926
4927 if (skb_headroom(skb) < tx_desc_size) {
4928 dev_warn(dev,
4929 "%s: Not enough headroom (%i) for tx descriptor\n",
4930 __func__, skb_headroom(skb));
4931 goto error;
4932 }
4933
4934 if (unlikely(skb->len > (65535 - tx_desc_size))) {
4935 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4936 __func__, skb->len);
4937 goto error;
4938 }
4939
4940 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4941 if (!tx_urb) {
4942 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4943 goto error;
4944 }
4945
4946 if (ieee80211_is_action(hdr->frame_control))
4947 rtl8xxxu_dump_action(dev, hdr);
4948
4949 usedesc40 = (tx_desc_size == 40);
4950 tx_info->rate_driver_data[0] = hw;
4951
4952 if (control && control->sta)
4953 sta = control->sta;
4954
4955 tx_desc = skb_push(skb, tx_desc_size);
4956
4957 memset(tx_desc, 0, tx_desc_size);
4958 tx_desc->pkt_size = cpu_to_le16(pktlen);
4959 tx_desc->pkt_offset = tx_desc_size;
4960
4961 tx_desc->txdw0 =
4962 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4963 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4964 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4965 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4966
4967 queue = rtl8xxxu_queue_select(hw, skb);
4968 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4969
4970 if (tx_info->control.hw_key) {
4971 switch (tx_info->control.hw_key->cipher) {
4972 case WLAN_CIPHER_SUITE_WEP40:
4973 case WLAN_CIPHER_SUITE_WEP104:
4974 case WLAN_CIPHER_SUITE_TKIP:
4975 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4976 break;
4977 case WLAN_CIPHER_SUITE_CCMP:
4978 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4979 break;
4980 default:
4981 break;
4982 }
4983 }
4984
4985
4986 ampdu_enable = false;
4987 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4988 if (sta->ht_cap.ht_supported) {
4989 u32 ampdu, val32;
4990
4991 ampdu = (u32)sta->ht_cap.ampdu_density;
4992 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4993 tx_desc->txdw2 |= cpu_to_le32(val32);
4994
4995 ampdu_enable = true;
4996 }
4997 }
4998
4999 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
5000 (ieee80211_is_data_qos(hdr->frame_control) &&
5001 sta && sta->ht_cap.cap &
5002 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)))
5003 sgi = true;
5004
5005 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
5006 (sta && vif && vif->bss_conf.use_short_preamble))
5007 short_preamble = true;
5008
5009 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS)
5010 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5011 else if (rate_flag & IEEE80211_TX_RC_USE_CTS_PROTECT)
5012 rts_rate = ieee80211_get_rts_cts_rate(hw, tx_info)->hw_value;
5013 else
5014 rts_rate = 0;
5015
5016 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
5017
5018 priv->fops->fill_txdesc(hw, hdr, tx_info, tx_desc, sgi, short_preamble,
5019 ampdu_enable, rts_rate);
5020
5021 rtl8xxxu_calc_tx_desc_csum(tx_desc);
5022
5023 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5024 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5025
5026 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5027 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5028 if (ret) {
5029 usb_unanchor_urb(&tx_urb->urb);
5030 rtl8xxxu_free_tx_urb(priv, tx_urb);
5031 goto error;
5032 }
5033 return;
5034error:
5035 dev_kfree_skb(skb);
5036}
5037
5038static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5039 struct ieee80211_rx_status *rx_status,
5040 struct rtl8723au_phy_stats *phy_stats,
5041 u32 rxmcs)
5042{
5043 if (phy_stats->sgi_en)
5044 rx_status->enc_flags |= RX_ENC_FLAG_SHORT_GI;
5045
5046 if (rxmcs < DESC_RATE_6M) {
5047
5048
5049
5050 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5051
5052 switch (cck_agc_rpt & 0xc0) {
5053 case 0xc0:
5054 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5055 break;
5056 case 0x80:
5057 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5058 break;
5059 case 0x40:
5060 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5061 break;
5062 case 0x00:
5063 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5064 break;
5065 }
5066 } else {
5067 rx_status->signal =
5068 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5069 }
5070}
5071
5072static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5073{
5074 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5075 unsigned long flags;
5076
5077 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5078
5079 list_for_each_entry_safe(rx_urb, tmp,
5080 &priv->rx_urb_pending_list, list) {
5081 list_del(&rx_urb->list);
5082 priv->rx_urb_pending_count--;
5083 usb_free_urb(&rx_urb->urb);
5084 }
5085
5086 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5087}
5088
5089static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5090 struct rtl8xxxu_rx_urb *rx_urb)
5091{
5092 struct sk_buff *skb;
5093 unsigned long flags;
5094 int pending = 0;
5095
5096 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5097
5098 if (!priv->shutdown) {
5099 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5100 priv->rx_urb_pending_count++;
5101 pending = priv->rx_urb_pending_count;
5102 } else {
5103 skb = (struct sk_buff *)rx_urb->urb.context;
5104 dev_kfree_skb(skb);
5105 usb_free_urb(&rx_urb->urb);
5106 }
5107
5108 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5109
5110 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5111 schedule_work(&priv->rx_urb_wq);
5112}
5113
5114static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5115{
5116 struct rtl8xxxu_priv *priv;
5117 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5118 struct list_head local;
5119 struct sk_buff *skb;
5120 unsigned long flags;
5121 int ret;
5122
5123 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5124 INIT_LIST_HEAD(&local);
5125
5126 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5127
5128 list_splice_init(&priv->rx_urb_pending_list, &local);
5129 priv->rx_urb_pending_count = 0;
5130
5131 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5132
5133 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5134 list_del_init(&rx_urb->list);
5135 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5136
5137
5138
5139
5140
5141 switch (ret) {
5142 case 0:
5143 break;
5144 case -ENOMEM:
5145 case -EAGAIN:
5146 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5147 break;
5148 default:
5149 pr_info("failed to requeue urb %i\n", ret);
5150 skb = (struct sk_buff *)rx_urb->urb.context;
5151 dev_kfree_skb(skb);
5152 usb_free_urb(&rx_urb->urb);
5153 }
5154 }
5155}
5156
5157static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv,
5158 struct sk_buff *skb)
5159{
5160 struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data;
5161 struct device *dev = &priv->udev->dev;
5162 int len;
5163
5164 len = skb->len - 2;
5165
5166 dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n",
5167 c2h->id, c2h->seq, len, c2h->bt_info.response_source);
5168
5169 switch(c2h->id) {
5170 case C2H_8723B_BT_INFO:
5171 if (c2h->bt_info.response_source >
5172 BT_INFO_SRC_8723B_BT_ACTIVE_SEND)
5173 dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n");
5174 else
5175 dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n");
5176
5177 if (c2h->bt_info.bt_has_reset)
5178 dev_dbg(dev, "BT has been reset\n");
5179 if (c2h->bt_info.tx_rx_mask)
5180 dev_dbg(dev, "BT TRx mask\n");
5181
5182 break;
5183 case C2H_8723B_BT_MP_INFO:
5184 dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n",
5185 c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status);
5186 break;
5187 case C2H_8723B_RA_REPORT:
5188 dev_dbg(dev,
5189 "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n",
5190 c2h->ra_report.rate, c2h->ra_report.dummy0_0,
5191 c2h->ra_report.macid, c2h->ra_report.noisy_state);
5192 break;
5193 default:
5194 dev_info(dev, "Unhandled C2H event %02x seq %02x\n",
5195 c2h->id, c2h->seq);
5196 print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE,
5197 16, 1, c2h->raw.payload, len, false);
5198 break;
5199 }
5200}
5201
5202int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5203{
5204 struct ieee80211_hw *hw = priv->hw;
5205 struct ieee80211_rx_status *rx_status;
5206 struct rtl8xxxu_rxdesc16 *rx_desc;
5207 struct rtl8723au_phy_stats *phy_stats;
5208 struct sk_buff *next_skb = NULL;
5209 __le32 *_rx_desc_le;
5210 u32 *_rx_desc;
5211 int drvinfo_sz, desc_shift;
5212 int i, pkt_cnt, pkt_len, urb_len, pkt_offset;
5213
5214 urb_len = skb->len;
5215 pkt_cnt = 0;
5216
5217 do {
5218 rx_desc = (struct rtl8xxxu_rxdesc16 *)skb->data;
5219 _rx_desc_le = (__le32 *)skb->data;
5220 _rx_desc = (u32 *)skb->data;
5221
5222 for (i = 0;
5223 i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++)
5224 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5225
5226
5227
5228
5229
5230 if (!pkt_cnt)
5231 pkt_cnt = rx_desc->pkt_cnt;
5232 pkt_len = rx_desc->pktlen;
5233
5234 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5235 desc_shift = rx_desc->shift;
5236 pkt_offset = roundup(pkt_len + drvinfo_sz + desc_shift +
5237 sizeof(struct rtl8xxxu_rxdesc16), 128);
5238
5239
5240
5241
5242
5243 if (pkt_cnt > 1 &&
5244 urb_len > (pkt_offset + sizeof(struct rtl8xxxu_rxdesc16)))
5245 next_skb = skb_clone(skb, GFP_ATOMIC);
5246
5247 rx_status = IEEE80211_SKB_RXCB(skb);
5248 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5249
5250 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16));
5251
5252 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5253
5254 skb_pull(skb, drvinfo_sz + desc_shift);
5255
5256 skb_trim(skb, pkt_len);
5257
5258 if (rx_desc->phy_stats)
5259 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5260 rx_desc->rxmcs);
5261
5262 rx_status->mactime = rx_desc->tsfl;
5263 rx_status->flag |= RX_FLAG_MACTIME_START;
5264
5265 if (!rx_desc->swdec)
5266 rx_status->flag |= RX_FLAG_DECRYPTED;
5267 if (rx_desc->crc32)
5268 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5269 if (rx_desc->bw)
5270 rx_status->bw = RATE_INFO_BW_40;
5271
5272 if (rx_desc->rxht) {
5273 rx_status->encoding = RX_ENC_HT;
5274 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5275 } else {
5276 rx_status->rate_idx = rx_desc->rxmcs;
5277 }
5278
5279 rx_status->freq = hw->conf.chandef.chan->center_freq;
5280 rx_status->band = hw->conf.chandef.chan->band;
5281
5282 ieee80211_rx_irqsafe(hw, skb);
5283
5284 skb = next_skb;
5285 if (skb)
5286 skb_pull(next_skb, pkt_offset);
5287
5288 pkt_cnt--;
5289 urb_len -= pkt_offset;
5290 } while (skb && urb_len > 0 && pkt_cnt > 0);
5291
5292 return RX_TYPE_DATA_PKT;
5293}
5294
5295int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, struct sk_buff *skb)
5296{
5297 struct ieee80211_hw *hw = priv->hw;
5298 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
5299 struct rtl8xxxu_rxdesc24 *rx_desc =
5300 (struct rtl8xxxu_rxdesc24 *)skb->data;
5301 struct rtl8723au_phy_stats *phy_stats;
5302 __le32 *_rx_desc_le = (__le32 *)skb->data;
5303 u32 *_rx_desc = (u32 *)skb->data;
5304 int drvinfo_sz, desc_shift;
5305 int i;
5306
5307 for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++)
5308 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5309
5310 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5311
5312 skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24));
5313
5314 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5315
5316 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5317 desc_shift = rx_desc->shift;
5318 skb_pull(skb, drvinfo_sz + desc_shift);
5319
5320 if (rx_desc->rpt_sel) {
5321 struct device *dev = &priv->udev->dev;
5322 dev_dbg(dev, "%s: C2H packet\n", __func__);
5323 rtl8723bu_handle_c2h(priv, skb);
5324 dev_kfree_skb(skb);
5325 return RX_TYPE_C2H;
5326 }
5327
5328 if (rx_desc->phy_stats)
5329 rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats,
5330 rx_desc->rxmcs);
5331
5332 rx_status->mactime = rx_desc->tsfl;
5333 rx_status->flag |= RX_FLAG_MACTIME_START;
5334
5335 if (!rx_desc->swdec)
5336 rx_status->flag |= RX_FLAG_DECRYPTED;
5337 if (rx_desc->crc32)
5338 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5339 if (rx_desc->bw)
5340 rx_status->bw = RATE_INFO_BW_40;
5341
5342 if (rx_desc->rxmcs >= DESC_RATE_MCS0) {
5343 rx_status->encoding = RX_ENC_HT;
5344 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5345 } else {
5346 rx_status->rate_idx = rx_desc->rxmcs;
5347 }
5348
5349 rx_status->freq = hw->conf.chandef.chan->center_freq;
5350 rx_status->band = hw->conf.chandef.chan->band;
5351
5352 ieee80211_rx_irqsafe(hw, skb);
5353 return RX_TYPE_DATA_PKT;
5354}
5355
5356static void rtl8xxxu_rx_complete(struct urb *urb)
5357{
5358 struct rtl8xxxu_rx_urb *rx_urb =
5359 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5360 struct ieee80211_hw *hw = rx_urb->hw;
5361 struct rtl8xxxu_priv *priv = hw->priv;
5362 struct sk_buff *skb = (struct sk_buff *)urb->context;
5363 struct device *dev = &priv->udev->dev;
5364
5365 skb_put(skb, urb->actual_length);
5366
5367 if (urb->status == 0) {
5368 priv->fops->parse_rx_desc(priv, skb);
5369
5370 skb = NULL;
5371 rx_urb->urb.context = NULL;
5372 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5373 } else {
5374 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5375 goto cleanup;
5376 }
5377 return;
5378
5379cleanup:
5380 usb_free_urb(urb);
5381 dev_kfree_skb(skb);
5382 return;
5383}
5384
5385static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5386 struct rtl8xxxu_rx_urb *rx_urb)
5387{
5388 struct rtl8xxxu_fileops *fops = priv->fops;
5389 struct sk_buff *skb;
5390 int skb_size;
5391 int ret, rx_desc_sz;
5392
5393 rx_desc_sz = fops->rx_desc_size;
5394
5395 if (priv->rx_buf_aggregation && fops->rx_agg_buf_size) {
5396 skb_size = fops->rx_agg_buf_size;
5397 skb_size += (rx_desc_sz + sizeof(struct rtl8723au_phy_stats));
5398 } else {
5399 skb_size = IEEE80211_MAX_FRAME_LEN;
5400 }
5401
5402 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5403 if (!skb)
5404 return -ENOMEM;
5405
5406 memset(skb->data, 0, rx_desc_sz);
5407 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5408 skb_size, rtl8xxxu_rx_complete, skb);
5409 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5410 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5411 if (ret)
5412 usb_unanchor_urb(&rx_urb->urb);
5413 return ret;
5414}
5415
5416static void rtl8xxxu_int_complete(struct urb *urb)
5417{
5418 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5419 struct device *dev = &priv->udev->dev;
5420 int ret;
5421
5422 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_INTERRUPT)
5423 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5424 if (urb->status == 0) {
5425 usb_anchor_urb(urb, &priv->int_anchor);
5426 ret = usb_submit_urb(urb, GFP_ATOMIC);
5427 if (ret)
5428 usb_unanchor_urb(urb);
5429 } else {
5430 dev_dbg(dev, "%s: Error %i\n", __func__, urb->status);
5431 }
5432}
5433
5434
5435static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5436{
5437 struct rtl8xxxu_priv *priv = hw->priv;
5438 struct urb *urb;
5439 u32 val32;
5440 int ret;
5441
5442 urb = usb_alloc_urb(0, GFP_KERNEL);
5443 if (!urb)
5444 return -ENOMEM;
5445
5446 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5447 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5448 rtl8xxxu_int_complete, priv, 1);
5449 usb_anchor_urb(urb, &priv->int_anchor);
5450 ret = usb_submit_urb(urb, GFP_KERNEL);
5451 if (ret) {
5452 usb_unanchor_urb(urb);
5453 goto error;
5454 }
5455
5456 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5457 val32 |= USB_HIMR_CPWM;
5458 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5459
5460error:
5461 return ret;
5462}
5463
5464static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5465 struct ieee80211_vif *vif)
5466{
5467 struct rtl8xxxu_priv *priv = hw->priv;
5468 int ret;
5469 u8 val8;
5470
5471 switch (vif->type) {
5472 case NL80211_IFTYPE_STATION:
5473 rtl8xxxu_stop_tx_beacon(priv);
5474
5475 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5476 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5477 BEACON_DISABLE_TSF_UPDATE;
5478 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5479 ret = 0;
5480 break;
5481 default:
5482 ret = -EOPNOTSUPP;
5483 }
5484
5485 rtl8xxxu_set_linktype(priv, vif->type);
5486
5487 return ret;
5488}
5489
5490static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5491 struct ieee80211_vif *vif)
5492{
5493 struct rtl8xxxu_priv *priv = hw->priv;
5494
5495 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5496}
5497
5498static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5499{
5500 struct rtl8xxxu_priv *priv = hw->priv;
5501 struct device *dev = &priv->udev->dev;
5502 u16 val16;
5503 int ret = 0, channel;
5504 bool ht40;
5505
5506 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5507 dev_info(dev,
5508 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5509 __func__, hw->conf.chandef.chan->hw_value,
5510 changed, hw->conf.chandef.width);
5511
5512 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5513 val16 = ((hw->conf.long_frame_max_tx_count <<
5514 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5515 ((hw->conf.short_frame_max_tx_count <<
5516 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5517 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5518 }
5519
5520 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5521 switch (hw->conf.chandef.width) {
5522 case NL80211_CHAN_WIDTH_20_NOHT:
5523 case NL80211_CHAN_WIDTH_20:
5524 ht40 = false;
5525 break;
5526 case NL80211_CHAN_WIDTH_40:
5527 ht40 = true;
5528 break;
5529 default:
5530 ret = -ENOTSUPP;
5531 goto exit;
5532 }
5533
5534 channel = hw->conf.chandef.chan->hw_value;
5535
5536 priv->fops->set_tx_power(priv, channel, ht40);
5537
5538 priv->fops->config_channel(hw);
5539 }
5540
5541exit:
5542 return ret;
5543}
5544
5545static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5546 struct ieee80211_vif *vif, u16 queue,
5547 const struct ieee80211_tx_queue_params *param)
5548{
5549 struct rtl8xxxu_priv *priv = hw->priv;
5550 struct device *dev = &priv->udev->dev;
5551 u32 val32;
5552 u8 aifs, acm_ctrl, acm_bit;
5553
5554 aifs = param->aifs;
5555
5556 val32 = aifs |
5557 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5558 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5559 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5560
5561 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5562 dev_dbg(dev,
5563 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5564 __func__, queue, val32, param->acm, acm_ctrl);
5565
5566 switch (queue) {
5567 case IEEE80211_AC_VO:
5568 acm_bit = ACM_HW_CTRL_VO;
5569 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5570 break;
5571 case IEEE80211_AC_VI:
5572 acm_bit = ACM_HW_CTRL_VI;
5573 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5574 break;
5575 case IEEE80211_AC_BE:
5576 acm_bit = ACM_HW_CTRL_BE;
5577 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5578 break;
5579 case IEEE80211_AC_BK:
5580 acm_bit = ACM_HW_CTRL_BK;
5581 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5582 break;
5583 default:
5584 acm_bit = 0;
5585 break;
5586 }
5587
5588 if (param->acm)
5589 acm_ctrl |= acm_bit;
5590 else
5591 acm_ctrl &= ~acm_bit;
5592 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5593
5594 return 0;
5595}
5596
5597static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5598 unsigned int changed_flags,
5599 unsigned int *total_flags, u64 multicast)
5600{
5601 struct rtl8xxxu_priv *priv = hw->priv;
5602 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
5603
5604 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5605 __func__, changed_flags, *total_flags);
5606
5607
5608
5609
5610
5611 if (*total_flags & FIF_FCSFAIL)
5612 rcr |= RCR_ACCEPT_CRC32;
5613 else
5614 rcr &= ~RCR_ACCEPT_CRC32;
5615
5616
5617
5618
5619
5620 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5621 rcr &= ~RCR_CHECK_BSSID_BEACON;
5622 else
5623 rcr |= RCR_CHECK_BSSID_BEACON;
5624
5625 if (*total_flags & FIF_CONTROL)
5626 rcr |= RCR_ACCEPT_CTRL_FRAME;
5627 else
5628 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5629
5630 if (*total_flags & FIF_OTHER_BSS) {
5631 rcr |= RCR_ACCEPT_AP;
5632 rcr &= ~RCR_CHECK_BSSID_MATCH;
5633 } else {
5634 rcr &= ~RCR_ACCEPT_AP;
5635 rcr |= RCR_CHECK_BSSID_MATCH;
5636 }
5637
5638 if (*total_flags & FIF_PSPOLL)
5639 rcr |= RCR_ACCEPT_PM;
5640 else
5641 rcr &= ~RCR_ACCEPT_PM;
5642
5643
5644
5645
5646
5647 rtl8xxxu_write32(priv, REG_RCR, rcr);
5648
5649 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5650 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5651 FIF_PROBE_REQ);
5652}
5653
5654static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5655{
5656 if (rts > 2347)
5657 return -EINVAL;
5658
5659 return 0;
5660}
5661
5662static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5663 struct ieee80211_vif *vif,
5664 struct ieee80211_sta *sta,
5665 struct ieee80211_key_conf *key)
5666{
5667 struct rtl8xxxu_priv *priv = hw->priv;
5668 struct device *dev = &priv->udev->dev;
5669 u8 mac_addr[ETH_ALEN];
5670 u8 val8;
5671 u16 val16;
5672 u32 val32;
5673 int retval = -EOPNOTSUPP;
5674
5675 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5676 __func__, cmd, key->cipher, key->keyidx);
5677
5678 if (vif->type != NL80211_IFTYPE_STATION)
5679 return -EOPNOTSUPP;
5680
5681 if (key->keyidx > 3)
5682 return -EOPNOTSUPP;
5683
5684 switch (key->cipher) {
5685 case WLAN_CIPHER_SUITE_WEP40:
5686 case WLAN_CIPHER_SUITE_WEP104:
5687
5688 break;
5689 case WLAN_CIPHER_SUITE_CCMP:
5690 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5691 break;
5692 case WLAN_CIPHER_SUITE_TKIP:
5693 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5694 default:
5695 return -EOPNOTSUPP;
5696 }
5697
5698 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5699 dev_dbg(dev, "%s: pairwise key\n", __func__);
5700 ether_addr_copy(mac_addr, sta->addr);
5701 } else {
5702 dev_dbg(dev, "%s: group key\n", __func__);
5703 eth_broadcast_addr(mac_addr);
5704 }
5705
5706 val16 = rtl8xxxu_read16(priv, REG_CR);
5707 val16 |= CR_SECURITY_ENABLE;
5708 rtl8xxxu_write16(priv, REG_CR, val16);
5709
5710 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5711 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5712 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5713 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5714
5715 switch (cmd) {
5716 case SET_KEY:
5717 key->hw_key_idx = key->keyidx;
5718 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5719 rtl8xxxu_cam_write(priv, key, mac_addr);
5720 retval = 0;
5721 break;
5722 case DISABLE_KEY:
5723 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5724 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5725 key->keyidx << CAM_CMD_KEY_SHIFT;
5726 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5727 retval = 0;
5728 break;
5729 default:
5730 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5731 }
5732
5733 return retval;
5734}
5735
5736static int
5737rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5738 struct ieee80211_ampdu_params *params)
5739{
5740 struct rtl8xxxu_priv *priv = hw->priv;
5741 struct device *dev = &priv->udev->dev;
5742 u8 ampdu_factor, ampdu_density;
5743 struct ieee80211_sta *sta = params->sta;
5744 enum ieee80211_ampdu_mlme_action action = params->action;
5745
5746 switch (action) {
5747 case IEEE80211_AMPDU_TX_START:
5748 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5749 ampdu_factor = sta->ht_cap.ampdu_factor;
5750 ampdu_density = sta->ht_cap.ampdu_density;
5751 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5752 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5753 dev_dbg(dev,
5754 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5755 ampdu_factor, ampdu_density);
5756 break;
5757 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5758 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5759 rtl8xxxu_set_ampdu_factor(priv, 0);
5760 rtl8xxxu_set_ampdu_min_space(priv, 0);
5761 break;
5762 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5763 dev_dbg(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5764 __func__);
5765 rtl8xxxu_set_ampdu_factor(priv, 0);
5766 rtl8xxxu_set_ampdu_min_space(priv, 0);
5767 break;
5768 case IEEE80211_AMPDU_RX_START:
5769 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5770 break;
5771 case IEEE80211_AMPDU_RX_STOP:
5772 dev_dbg(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5773 break;
5774 default:
5775 break;
5776 }
5777 return 0;
5778}
5779
5780static int rtl8xxxu_start(struct ieee80211_hw *hw)
5781{
5782 struct rtl8xxxu_priv *priv = hw->priv;
5783 struct rtl8xxxu_rx_urb *rx_urb;
5784 struct rtl8xxxu_tx_urb *tx_urb;
5785 unsigned long flags;
5786 int ret, i;
5787
5788 ret = 0;
5789
5790 init_usb_anchor(&priv->rx_anchor);
5791 init_usb_anchor(&priv->tx_anchor);
5792 init_usb_anchor(&priv->int_anchor);
5793
5794 priv->fops->enable_rf(priv);
5795 if (priv->usb_interrupts) {
5796 ret = rtl8xxxu_submit_int_urb(hw);
5797 if (ret)
5798 goto exit;
5799 }
5800
5801 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5802 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5803 if (!tx_urb) {
5804 if (!i)
5805 ret = -ENOMEM;
5806
5807 goto error_out;
5808 }
5809 usb_init_urb(&tx_urb->urb);
5810 INIT_LIST_HEAD(&tx_urb->list);
5811 tx_urb->hw = hw;
5812 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5813 priv->tx_urb_free_count++;
5814 }
5815
5816 priv->tx_stopped = false;
5817
5818 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5819 priv->shutdown = false;
5820 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5821
5822 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5823 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5824 if (!rx_urb) {
5825 if (!i)
5826 ret = -ENOMEM;
5827
5828 goto error_out;
5829 }
5830 usb_init_urb(&rx_urb->urb);
5831 INIT_LIST_HEAD(&rx_urb->list);
5832 rx_urb->hw = hw;
5833
5834 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5835 }
5836exit:
5837
5838
5839
5840 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
5841 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5842
5843 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5844
5845 return ret;
5846
5847error_out:
5848 rtl8xxxu_free_tx_resources(priv);
5849
5850
5851
5852 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5853 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5854
5855 return ret;
5856}
5857
5858static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5859{
5860 struct rtl8xxxu_priv *priv = hw->priv;
5861 unsigned long flags;
5862
5863 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5864
5865 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5866 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5867
5868 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5869 priv->shutdown = true;
5870 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5871
5872 usb_kill_anchored_urbs(&priv->rx_anchor);
5873 usb_kill_anchored_urbs(&priv->tx_anchor);
5874 if (priv->usb_interrupts)
5875 usb_kill_anchored_urbs(&priv->int_anchor);
5876
5877 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5878
5879 priv->fops->disable_rf(priv);
5880
5881
5882
5883
5884 if (priv->usb_interrupts)
5885 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5886
5887 rtl8xxxu_free_rx_resources(priv);
5888 rtl8xxxu_free_tx_resources(priv);
5889}
5890
5891static const struct ieee80211_ops rtl8xxxu_ops = {
5892 .tx = rtl8xxxu_tx,
5893 .add_interface = rtl8xxxu_add_interface,
5894 .remove_interface = rtl8xxxu_remove_interface,
5895 .config = rtl8xxxu_config,
5896 .conf_tx = rtl8xxxu_conf_tx,
5897 .bss_info_changed = rtl8xxxu_bss_info_changed,
5898 .configure_filter = rtl8xxxu_configure_filter,
5899 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5900 .start = rtl8xxxu_start,
5901 .stop = rtl8xxxu_stop,
5902 .sw_scan_start = rtl8xxxu_sw_scan_start,
5903 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5904 .set_key = rtl8xxxu_set_key,
5905 .ampdu_action = rtl8xxxu_ampdu_action,
5906};
5907
5908static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5909 struct usb_interface *interface)
5910{
5911 struct usb_interface_descriptor *interface_desc;
5912 struct usb_host_interface *host_interface;
5913 struct usb_endpoint_descriptor *endpoint;
5914 struct device *dev = &priv->udev->dev;
5915 int i, j = 0, endpoints;
5916 u8 dir, xtype, num;
5917 int ret = 0;
5918
5919 host_interface = &interface->altsetting[0];
5920 interface_desc = &host_interface->desc;
5921 endpoints = interface_desc->bNumEndpoints;
5922
5923 for (i = 0; i < endpoints; i++) {
5924 endpoint = &host_interface->endpoint[i].desc;
5925
5926 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5927 num = usb_endpoint_num(endpoint);
5928 xtype = usb_endpoint_type(endpoint);
5929 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5930 dev_dbg(dev,
5931 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5932 __func__, dir, num, xtype);
5933 if (usb_endpoint_dir_in(endpoint) &&
5934 usb_endpoint_xfer_bulk(endpoint)) {
5935 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5936 dev_dbg(dev, "%s: in endpoint num %i\n",
5937 __func__, num);
5938
5939 if (priv->pipe_in) {
5940 dev_warn(dev,
5941 "%s: Too many IN pipes\n", __func__);
5942 ret = -EINVAL;
5943 goto exit;
5944 }
5945
5946 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5947 }
5948
5949 if (usb_endpoint_dir_in(endpoint) &&
5950 usb_endpoint_xfer_int(endpoint)) {
5951 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5952 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5953 __func__, num);
5954
5955 if (priv->pipe_interrupt) {
5956 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5957 __func__);
5958 ret = -EINVAL;
5959 goto exit;
5960 }
5961
5962 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5963 }
5964
5965 if (usb_endpoint_dir_out(endpoint) &&
5966 usb_endpoint_xfer_bulk(endpoint)) {
5967 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5968 dev_dbg(dev, "%s: out endpoint num %i\n",
5969 __func__, num);
5970 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5971 dev_warn(dev,
5972 "%s: Too many OUT pipes\n", __func__);
5973 ret = -EINVAL;
5974 goto exit;
5975 }
5976 priv->out_ep[j++] = num;
5977 }
5978 }
5979exit:
5980 priv->nr_out_eps = j;
5981 return ret;
5982}
5983
5984static int rtl8xxxu_probe(struct usb_interface *interface,
5985 const struct usb_device_id *id)
5986{
5987 struct rtl8xxxu_priv *priv;
5988 struct ieee80211_hw *hw;
5989 struct usb_device *udev;
5990 struct ieee80211_supported_band *sband;
5991 int ret;
5992 int untested = 1;
5993
5994 udev = usb_get_dev(interface_to_usbdev(interface));
5995
5996 switch (id->idVendor) {
5997 case USB_VENDOR_ID_REALTEK:
5998 switch(id->idProduct) {
5999 case 0x1724:
6000 case 0x8176:
6001 case 0x8178:
6002 case 0x817f:
6003 case 0x818b:
6004 untested = 0;
6005 break;
6006 }
6007 break;
6008 case 0x7392:
6009 if (id->idProduct == 0x7811)
6010 untested = 0;
6011 break;
6012 case 0x050d:
6013 if (id->idProduct == 0x1004)
6014 untested = 0;
6015 break;
6016 case 0x20f4:
6017 if (id->idProduct == 0x648b)
6018 untested = 0;
6019 break;
6020 case 0x2001:
6021 if (id->idProduct == 0x3308)
6022 untested = 0;
6023 break;
6024 case 0x2357:
6025 if (id->idProduct == 0x0109)
6026 untested = 0;
6027 break;
6028 default:
6029 break;
6030 }
6031
6032 if (untested) {
6033 rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE;
6034 dev_info(&udev->dev,
6035 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
6036 id->idVendor, id->idProduct);
6037 dev_info(&udev->dev,
6038 "Please report results to Jes.Sorensen@gmail.com\n");
6039 }
6040
6041 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
6042 if (!hw) {
6043 ret = -ENOMEM;
6044 priv = NULL;
6045 goto exit;
6046 }
6047
6048 priv = hw->priv;
6049 priv->hw = hw;
6050 priv->udev = udev;
6051 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
6052 mutex_init(&priv->usb_buf_mutex);
6053 mutex_init(&priv->h2c_mutex);
6054 INIT_LIST_HEAD(&priv->tx_urb_free_list);
6055 spin_lock_init(&priv->tx_urb_lock);
6056 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
6057 spin_lock_init(&priv->rx_urb_lock);
6058 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
6059
6060 usb_set_intfdata(interface, hw);
6061
6062 ret = rtl8xxxu_parse_usb(priv, interface);
6063 if (ret)
6064 goto exit;
6065
6066 ret = rtl8xxxu_identify_chip(priv);
6067 if (ret) {
6068 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
6069 goto exit;
6070 }
6071
6072 ret = rtl8xxxu_read_efuse(priv);
6073 if (ret) {
6074 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
6075 goto exit;
6076 }
6077
6078 ret = priv->fops->parse_efuse(priv);
6079 if (ret) {
6080 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
6081 goto exit;
6082 }
6083
6084 rtl8xxxu_print_chipinfo(priv);
6085
6086 ret = priv->fops->load_firmware(priv);
6087 if (ret) {
6088 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
6089 goto exit;
6090 }
6091
6092 ret = rtl8xxxu_init_device(hw);
6093 if (ret)
6094 goto exit;
6095
6096 hw->wiphy->max_scan_ssids = 1;
6097 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
6098 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
6099 hw->queues = 4;
6100
6101 sband = &rtl8xxxu_supported_band;
6102 sband->ht_cap.ht_supported = true;
6103 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
6104 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
6105 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
6106 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
6107 sband->ht_cap.mcs.rx_mask[0] = 0xff;
6108 sband->ht_cap.mcs.rx_mask[4] = 0x01;
6109 if (priv->rf_paths > 1) {
6110 sband->ht_cap.mcs.rx_mask[1] = 0xff;
6111 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
6112 }
6113 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
6114
6115
6116
6117
6118
6119 if (rtl8xxxu_ht40_2g) {
6120 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
6121 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
6122 }
6123 hw->wiphy->bands[NL80211_BAND_2GHZ] = sband;
6124
6125 hw->wiphy->rts_threshold = 2347;
6126
6127 SET_IEEE80211_DEV(priv->hw, &interface->dev);
6128 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
6129
6130 hw->extra_tx_headroom = priv->fops->tx_desc_size;
6131 ieee80211_hw_set(hw, SIGNAL_DBM);
6132
6133
6134
6135 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
6136 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
6137
6138 wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
6139
6140 ret = ieee80211_register_hw(priv->hw);
6141 if (ret) {
6142 dev_err(&udev->dev, "%s: Failed to register: %i\n",
6143 __func__, ret);
6144 goto exit;
6145 }
6146
6147 return 0;
6148
6149exit:
6150 usb_set_intfdata(interface, NULL);
6151
6152 if (priv) {
6153 kfree(priv->fw_data);
6154 mutex_destroy(&priv->usb_buf_mutex);
6155 mutex_destroy(&priv->h2c_mutex);
6156 }
6157 usb_put_dev(udev);
6158
6159 ieee80211_free_hw(hw);
6160
6161 return ret;
6162}
6163
6164static void rtl8xxxu_disconnect(struct usb_interface *interface)
6165{
6166 struct rtl8xxxu_priv *priv;
6167 struct ieee80211_hw *hw;
6168
6169 hw = usb_get_intfdata(interface);
6170 priv = hw->priv;
6171
6172 ieee80211_unregister_hw(hw);
6173
6174 priv->fops->power_off(priv);
6175
6176 usb_set_intfdata(interface, NULL);
6177
6178 dev_info(&priv->udev->dev, "disconnecting\n");
6179
6180 kfree(priv->fw_data);
6181 mutex_destroy(&priv->usb_buf_mutex);
6182 mutex_destroy(&priv->h2c_mutex);
6183
6184 if (priv->udev->state != USB_STATE_NOTATTACHED) {
6185 dev_info(&priv->udev->dev,
6186 "Device still attached, trying to reset\n");
6187 usb_reset_device(priv->udev);
6188 }
6189 usb_put_dev(priv->udev);
6190 ieee80211_free_hw(hw);
6191}
6192
6193static const struct usb_device_id dev_table[] = {
6194{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
6195 .driver_info = (unsigned long)&rtl8723au_fops},
6196{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
6197 .driver_info = (unsigned long)&rtl8723au_fops},
6198{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
6199 .driver_info = (unsigned long)&rtl8723au_fops},
6200{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
6201 .driver_info = (unsigned long)&rtl8192eu_fops},
6202
6203{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0108, 0xff, 0xff, 0xff),
6204 .driver_info = (unsigned long)&rtl8192eu_fops},
6205
6206{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3319, 0xff, 0xff, 0xff),
6207 .driver_info = (unsigned long)&rtl8192eu_fops},
6208
6209{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0109, 0xff, 0xff, 0xff),
6210 .driver_info = (unsigned long)&rtl8192eu_fops},
6211{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff),
6212 .driver_info = (unsigned long)&rtl8723bu_fops},
6213#ifdef CONFIG_RTL8XXXU_UNTESTED
6214
6215{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
6216 .driver_info = (unsigned long)&rtl8192cu_fops},
6217{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
6218 .driver_info = (unsigned long)&rtl8192cu_fops},
6219{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
6220 .driver_info = (unsigned long)&rtl8192cu_fops},
6221
6222{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6223 .driver_info = (unsigned long)&rtl8192cu_fops},
6224
6225{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6226 .driver_info = (unsigned long)&rtl8192cu_fops},
6227
6228{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6229 .driver_info = (unsigned long)&rtl8192cu_fops},
6230
6231{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6232 .driver_info = (unsigned long)&rtl8192cu_fops},
6233
6234{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6235 .driver_info = (unsigned long)&rtl8192cu_fops},
6236{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6237 .driver_info = (unsigned long)&rtl8192cu_fops},
6238{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6239 .driver_info = (unsigned long)&rtl8192cu_fops},
6240{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6241 .driver_info = (unsigned long)&rtl8192cu_fops},
6242{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6243 .driver_info = (unsigned long)&rtl8192cu_fops},
6244{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6245 .driver_info = (unsigned long)&rtl8192cu_fops},
6246{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6247 .driver_info = (unsigned long)&rtl8192cu_fops},
6248{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6249 .driver_info = (unsigned long)&rtl8192cu_fops},
6250{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6251 .driver_info = (unsigned long)&rtl8192cu_fops},
6252{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6253 .driver_info = (unsigned long)&rtl8192cu_fops},
6254{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6255 .driver_info = (unsigned long)&rtl8192cu_fops},
6256{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6257 .driver_info = (unsigned long)&rtl8192cu_fops},
6258{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6259 .driver_info = (unsigned long)&rtl8192cu_fops},
6260{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6261 .driver_info = (unsigned long)&rtl8192cu_fops},
6262{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6263 .driver_info = (unsigned long)&rtl8192cu_fops},
6264{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6265 .driver_info = (unsigned long)&rtl8192cu_fops},
6266{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6267 .driver_info = (unsigned long)&rtl8192cu_fops},
6268{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6269 .driver_info = (unsigned long)&rtl8192cu_fops},
6270{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6271 .driver_info = (unsigned long)&rtl8192cu_fops},
6272{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6273 .driver_info = (unsigned long)&rtl8192cu_fops},
6274{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6275 .driver_info = (unsigned long)&rtl8192cu_fops},
6276{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6277 .driver_info = (unsigned long)&rtl8192cu_fops},
6278{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6279 .driver_info = (unsigned long)&rtl8192cu_fops},
6280{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6281 .driver_info = (unsigned long)&rtl8192cu_fops},
6282{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6283 .driver_info = (unsigned long)&rtl8192cu_fops},
6284{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6285 .driver_info = (unsigned long)&rtl8192cu_fops},
6286{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6287 .driver_info = (unsigned long)&rtl8192cu_fops},
6288{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6289 .driver_info = (unsigned long)&rtl8192cu_fops},
6290{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6291 .driver_info = (unsigned long)&rtl8192cu_fops},
6292{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6293 .driver_info = (unsigned long)&rtl8192cu_fops},
6294{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6295 .driver_info = (unsigned long)&rtl8192cu_fops},
6296{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6297 .driver_info = (unsigned long)&rtl8192cu_fops},
6298{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6299 .driver_info = (unsigned long)&rtl8192cu_fops},
6300{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6301 .driver_info = (unsigned long)&rtl8192cu_fops},
6302{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6303 .driver_info = (unsigned long)&rtl8192cu_fops},
6304{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6305 .driver_info = (unsigned long)&rtl8192cu_fops},
6306{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6307 .driver_info = (unsigned long)&rtl8192cu_fops},
6308{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6309 .driver_info = (unsigned long)&rtl8192cu_fops},
6310
6311{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6312 .driver_info = (unsigned long)&rtl8192cu_fops},
6313{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6314 .driver_info = (unsigned long)&rtl8192cu_fops},
6315{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6316 .driver_info = (unsigned long)&rtl8192cu_fops},
6317{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6318 .driver_info = (unsigned long)&rtl8192cu_fops},
6319{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6320 .driver_info = (unsigned long)&rtl8192cu_fops},
6321{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6322 .driver_info = (unsigned long)&rtl8192cu_fops},
6323{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6324 .driver_info = (unsigned long)&rtl8192cu_fops},
6325{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6326 .driver_info = (unsigned long)&rtl8192cu_fops},
6327{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6328 .driver_info = (unsigned long)&rtl8192cu_fops},
6329{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6330 .driver_info = (unsigned long)&rtl8192cu_fops},
6331{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6332 .driver_info = (unsigned long)&rtl8192cu_fops},
6333{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6334 .driver_info = (unsigned long)&rtl8192cu_fops},
6335{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6336 .driver_info = (unsigned long)&rtl8192cu_fops},
6337{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6338 .driver_info = (unsigned long)&rtl8192cu_fops},
6339{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6340 .driver_info = (unsigned long)&rtl8192cu_fops},
6341{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6342 .driver_info = (unsigned long)&rtl8192cu_fops},
6343{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6344 .driver_info = (unsigned long)&rtl8192cu_fops},
6345{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6346 .driver_info = (unsigned long)&rtl8192cu_fops},
6347{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6348 .driver_info = (unsigned long)&rtl8192cu_fops},
6349{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6350 .driver_info = (unsigned long)&rtl8192cu_fops},
6351{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6352 .driver_info = (unsigned long)&rtl8192cu_fops},
6353{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6354 .driver_info = (unsigned long)&rtl8192cu_fops},
6355{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6356 .driver_info = (unsigned long)&rtl8192cu_fops},
6357{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6358 .driver_info = (unsigned long)&rtl8192cu_fops},
6359
6360{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0107, 0xff, 0xff, 0xff),
6361 .driver_info = (unsigned long)&rtl8192eu_fops},
6362{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab33, 0xff, 0xff, 0xff),
6363 .driver_info = (unsigned long)&rtl8192eu_fops},
6364{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818c, 0xff, 0xff, 0xff),
6365 .driver_info = (unsigned long)&rtl8192eu_fops},
6366#endif
6367{ }
6368};
6369
6370static struct usb_driver rtl8xxxu_driver = {
6371 .name = DRIVER_NAME,
6372 .probe = rtl8xxxu_probe,
6373 .disconnect = rtl8xxxu_disconnect,
6374 .id_table = dev_table,
6375 .no_dynamic_id = 1,
6376 .disable_hub_initiated_lpm = 1,
6377};
6378
6379static int __init rtl8xxxu_module_init(void)
6380{
6381 int res;
6382
6383 res = usb_register(&rtl8xxxu_driver);
6384 if (res < 0)
6385 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6386
6387 return res;
6388}
6389
6390static void __exit rtl8xxxu_module_exit(void)
6391{
6392 usb_deregister(&rtl8xxxu_driver);
6393}
6394
6395
6396MODULE_DEVICE_TABLE(usb, dev_table);
6397
6398module_init(rtl8xxxu_module_init);
6399module_exit(rtl8xxxu_module_exit);
6400
