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26#ifndef __RTL92D__FW__H__
27#define __RTL92D__FW__H__
28
29#define FW_8192D_START_ADDRESS 0x1000
30#define FW_8192D_PAGE_SIZE 4096
31#define FW_8192D_POLLING_TIMEOUT_COUNT 1000
32
33#define IS_FW_HEADER_EXIST(_pfwhdr) \
34 ((GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x92C0 || \
35 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFF0) == 0x88C0 || \
36 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D0 || \
37 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D1 || \
38 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D2 || \
39 (GET_FIRMWARE_HDR_SIGNATURE(_pfwhdr) & 0xFFFF) == 0x92D3)
40
41
42
43
44
45
46#define SHIFT_AND_MASK_LE(__pdesc, __shift, __mask) \
47 ((le32_to_cpu(*(((__le32 *)(__pdesc)))) >> (__shift)) & \
48 BIT_LEN_MASK_32(__mask))
49
50
51
52#define GET_FIRMWARE_HDR_SIGNATURE(__fwhdr) \
53 SHIFT_AND_MASK_LE(__fwhdr, 0, 16)
54#define GET_FIRMWARE_HDR_CATEGORY(__fwhdr) \
55 SHIFT_AND_MASK_LE(__fwhdr, 16, 8)
56#define GET_FIRMWARE_HDR_FUNCTION(__fwhdr) \
57 SHIFT_AND_MASK_LE(__fwhdr, 24, 8)
58#define GET_FIRMWARE_HDR_VERSION(__fwhdr) \
59 SHIFT_AND_MASK_LE(__fwhdr + 4, 0, 16)
60#define GET_FIRMWARE_HDR_SUB_VER(__fwhdr) \
61 SHIFT_AND_MASK_LE(__fwhdr + 4, 16, 8)
62#define GET_FIRMWARE_HDR_RSVD1(__fwhdr) \
63 SHIFT_AND_MASK_LE(__fwhdr + 4, 24, 8)
64
65
66#define GET_FIRMWARE_HDR_MONTH(__fwhdr) \
67 SHIFT_AND_MASK_LE(__fwhdr + 8, 0, 8)
68#define GET_FIRMWARE_HDR_DATE(__fwhdr) \
69 SHIFT_AND_MASK_LE(__fwhdr + 8, 8, 8)
70#define GET_FIRMWARE_HDR_HOUR(__fwhdr) \
71 SHIFT_AND_MASK_LE(__fwhdr + 8, 16, 8)
72#define GET_FIRMWARE_HDR_MINUTE(__fwhdr) \
73 SHIFT_AND_MASK_LE(__fwhdr + 8, 24, 8)
74#define GET_FIRMWARE_HDR_ROMCODE_SIZE(__fwhdr) \
75 SHIFT_AND_MASK_LE(__fwhdr + 12, 0, 16)
76#define GET_FIRMWARE_HDR_RSVD2(__fwhdr) \
77 SHIFT_AND_MASK_LE(__fwhdr + 12, 16, 16)
78
79
80#define GET_FIRMWARE_HDR_SVN_IDX(__fwhdr) \
81 SHIFT_AND_MASK_LE(__fwhdr + 16, 0, 32)
82#define GET_FIRMWARE_HDR_RSVD3(__fwhdr) \
83 SHIFT_AND_MASK_LE(__fwhdr + 20, 0, 32)
84
85
86#define GET_FIRMWARE_HDR_RSVD4(__fwhdr) \
87 SHIFT_AND_MASK_LE(__fwhdr + 24, 0, 32)
88#define GET_FIRMWARE_HDR_RSVD5(__fwhdr) \
89 SHIFT_AND_MASK_LE(__fwhdr + 28, 0, 32)
90
91#define pagenum_128(_len) \
92 (u32)(((_len) >> 7) + ((_len) & 0x7F ? 1 : 0))
93
94#define SET_H2CCMD_PWRMODE_PARM_MODE(__ph2ccmd, __val) \
95 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
96#define SET_H2CCMD_PWRMODE_PARM_SMART_PS(__ph2ccmd, __val) \
97 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
98#define SET_H2CCMD_PWRMODE_PARM_BCN_PASS_TIME(__ph2ccmd, __val) \
99 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
100#define SET_H2CCMD_JOINBSSRPT_PARM_OPMODE(__ph2ccmd, __val) \
101 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
102#define SET_H2CCMD_RSVDPAGE_LOC_PROBE_RSP(__ph2ccmd, __val) \
103 SET_BITS_TO_LE_1BYTE(__ph2ccmd, 0, 8, __val)
104#define SET_H2CCMD_RSVDPAGE_LOC_PSPOLL(__ph2ccmd, __val) \
105 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 1, 0, 8, __val)
106#define SET_H2CCMD_RSVDPAGE_LOC_NULL_DATA(__ph2ccmd, __val) \
107 SET_BITS_TO_LE_1BYTE((__ph2ccmd) + 2, 0, 8, __val)
108
109int rtl92d_download_fw(struct ieee80211_hw *hw);
110void rtl92d_fill_h2c_cmd(struct ieee80211_hw *hw, u8 element_id,
111 u32 cmd_len, u8 *p_cmdbuffer);
112void rtl92d_firmware_selfreset(struct ieee80211_hw *hw);
113void rtl92d_set_fw_rsvdpagepkt(struct ieee80211_hw *hw, bool b_dl_finished);
114void rtl92d_set_fw_joinbss_report_cmd(struct ieee80211_hw *hw, u8 mstatus);
115
116#endif
117