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26#include "../wifi.h"
27#include "../core.h"
28#include "../pci.h"
29#include "../base.h"
30#include "reg.h"
31#include "def.h"
32#include "phy.h"
33#include "dm.h"
34#include "hw.h"
35#include "sw.h"
36#include "trx.h"
37#include "led.h"
38
39#include <linux/module.h>
40
41static void rtl92d_init_aspm_vars(struct ieee80211_hw *hw)
42{
43 struct rtl_priv *rtlpriv = rtl_priv(hw);
44 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
45
46
47 rtlpci->const_amdpci_aspm = 0;
48
49
50
51
52
53
54
55
56
57
58 rtlpci->const_pci_aspm = 3;
59
60
61 rtlpci->const_devicepci_aspm_setting = 0x03;
62
63
64 rtlpci->const_hostpci_aspm_setting = 0x02;
65
66
67
68
69
70
71
72
73
74 rtlpci->const_hwsw_rfoff_d3 = 0;
75
76
77
78
79
80
81
82
83 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
84}
85
86static int rtl92d_init_sw_vars(struct ieee80211_hw *hw)
87{
88 int err;
89 u8 tid;
90 struct rtl_priv *rtlpriv = rtl_priv(hw);
91 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
92 char *fw_name = "rtlwifi/rtl8192defw.bin";
93
94 rtlpriv->dm.dm_initialgain_enable = true;
95 rtlpriv->dm.dm_flag = 0;
96 rtlpriv->dm.disable_framebursting = false;
97 rtlpriv->dm.thermalvalue = 0;
98 rtlpriv->dm.useramask = true;
99
100
101 if (rtlpriv->rtlhal.current_bandtype == BAND_ON_5G)
102 rtlpriv->phy.current_channel = 36;
103 else
104 rtlpriv->phy.current_channel = 1;
105
106 if (rtlpriv->rtlhal.macphymode != SINGLEMAC_SINGLEPHY) {
107 rtlpriv->rtlhal.disable_amsdu_8k = true;
108
109 rtlpci->rxbuffersize = 4096;
110 }
111
112 rtlpci->transmit_config = CFENDFORM | BIT(12) | BIT(13);
113
114 rtlpci->receive_config = (
115 RCR_APPFCS
116 | RCR_AMF
117 | RCR_ADF
118 | RCR_APP_MIC
119 | RCR_APP_ICV
120 | RCR_AICV
121 | RCR_ACRC32
122 | RCR_AB
123 | RCR_AM
124 | RCR_APM
125 | RCR_APP_PHYST_RXFF
126 | RCR_HTC_LOC_CTRL
127 );
128
129 rtlpci->irq_mask[0] = (u32) (
130 IMR_ROK
131 | IMR_VODOK
132 | IMR_VIDOK
133 | IMR_BEDOK
134 | IMR_BKDOK
135 | IMR_MGNTDOK
136 | IMR_HIGHDOK
137 | IMR_BDOK
138 | IMR_RDU
139 | IMR_RXFOVW
140 );
141
142 rtlpci->irq_mask[1] = (u32) (IMR_CPWM | IMR_C2HCMD);
143
144
145 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
146 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
147 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
148 if (!rtlpriv->psc.inactiveps)
149 pr_info("Power Save off (module option)\n");
150 if (!rtlpriv->psc.fwctrl_lps)
151 pr_info("FW Power Save off (module option)\n");
152 rtlpriv->psc.reg_fwctrl_lps = 3;
153 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
154
155
156 rtl92d_init_aspm_vars(hw);
157
158 if (rtlpriv->psc.reg_fwctrl_lps == 1)
159 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
160 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
161 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
162 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
163 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
164
165
166 rtlpriv->rtlhal.earlymode_enable = false;
167 for (tid = 0; tid < 8; tid++)
168 skb_queue_head_init(&rtlpriv->mac80211.skb_waitq[tid]);
169
170
171 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
172 if (!rtlpriv->rtlhal.pfirmware) {
173 pr_err("Can't alloc buffer for fw\n");
174 return 1;
175 }
176
177 rtlpriv->max_fw_size = 0x8000;
178 pr_info("Driver for Realtek RTL8192DE WLAN interface\n");
179 pr_info("Loading firmware file %s\n", fw_name);
180
181
182 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
183 rtlpriv->io.dev, GFP_KERNEL, hw,
184 rtl_fw_cb);
185 if (err) {
186 pr_err("Failed to request firmware!\n");
187 vfree(rtlpriv->rtlhal.pfirmware);
188 rtlpriv->rtlhal.pfirmware = NULL;
189 return 1;
190 }
191
192 return 0;
193}
194
195static void rtl92d_deinit_sw_vars(struct ieee80211_hw *hw)
196{
197 struct rtl_priv *rtlpriv = rtl_priv(hw);
198 u8 tid;
199
200 if (rtlpriv->rtlhal.pfirmware) {
201 vfree(rtlpriv->rtlhal.pfirmware);
202 rtlpriv->rtlhal.pfirmware = NULL;
203 }
204 for (tid = 0; tid < 8; tid++)
205 skb_queue_purge(&rtlpriv->mac80211.skb_waitq[tid]);
206}
207
208static struct rtl_hal_ops rtl8192de_hal_ops = {
209 .init_sw_vars = rtl92d_init_sw_vars,
210 .deinit_sw_vars = rtl92d_deinit_sw_vars,
211 .read_eeprom_info = rtl92de_read_eeprom_info,
212 .interrupt_recognized = rtl92de_interrupt_recognized,
213 .hw_init = rtl92de_hw_init,
214 .hw_disable = rtl92de_card_disable,
215 .hw_suspend = rtl92de_suspend,
216 .hw_resume = rtl92de_resume,
217 .enable_interrupt = rtl92de_enable_interrupt,
218 .disable_interrupt = rtl92de_disable_interrupt,
219 .set_network_type = rtl92de_set_network_type,
220 .set_chk_bssid = rtl92de_set_check_bssid,
221 .set_qos = rtl92de_set_qos,
222 .set_bcn_reg = rtl92de_set_beacon_related_registers,
223 .set_bcn_intv = rtl92de_set_beacon_interval,
224 .update_interrupt_mask = rtl92de_update_interrupt_mask,
225 .get_hw_reg = rtl92de_get_hw_reg,
226 .set_hw_reg = rtl92de_set_hw_reg,
227 .update_rate_tbl = rtl92de_update_hal_rate_tbl,
228 .fill_tx_desc = rtl92de_tx_fill_desc,
229 .fill_tx_cmddesc = rtl92de_tx_fill_cmddesc,
230 .query_rx_desc = rtl92de_rx_query_desc,
231 .set_channel_access = rtl92de_update_channel_access_setting,
232 .radio_onoff_checking = rtl92de_gpio_radio_on_off_checking,
233 .set_bw_mode = rtl92d_phy_set_bw_mode,
234 .switch_channel = rtl92d_phy_sw_chnl,
235 .dm_watchdog = rtl92d_dm_watchdog,
236 .scan_operation_backup = rtl_phy_scan_operation_backup,
237 .set_rf_power_state = rtl92d_phy_set_rf_power_state,
238 .led_control = rtl92de_led_control,
239 .set_desc = rtl92de_set_desc,
240 .get_desc = rtl92de_get_desc,
241 .tx_polling = rtl92de_tx_polling,
242 .enable_hw_sec = rtl92de_enable_hw_security_config,
243 .set_key = rtl92de_set_key,
244 .init_sw_leds = rtl92de_init_sw_leds,
245 .get_bbreg = rtl92d_phy_query_bb_reg,
246 .set_bbreg = rtl92d_phy_set_bb_reg,
247 .get_rfreg = rtl92d_phy_query_rf_reg,
248 .set_rfreg = rtl92d_phy_set_rf_reg,
249 .linked_set_reg = rtl92d_linked_set_reg,
250 .get_btc_status = rtl_btc_status_false,
251};
252
253static struct rtl_mod_params rtl92de_mod_params = {
254 .sw_crypto = false,
255 .inactiveps = true,
256 .swctrl_lps = true,
257 .fwctrl_lps = false,
258 .aspm_support = 1,
259 .debug_level = 0,
260 .debug_mask = 0,
261};
262
263static const struct rtl_hal_cfg rtl92de_hal_cfg = {
264 .bar_id = 2,
265 .write_readback = true,
266 .name = "rtl8192de",
267 .ops = &rtl8192de_hal_ops,
268 .mod_params = &rtl92de_mod_params,
269
270 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
271 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
272 .maps[SYS_CLK] = REG_SYS_CLKR,
273 .maps[MAC_RCR_AM] = RCR_AM,
274 .maps[MAC_RCR_AB] = RCR_AB,
275 .maps[MAC_RCR_ACRC32] = RCR_ACRC32,
276 .maps[MAC_RCR_ACF] = RCR_ACF,
277 .maps[MAC_RCR_AAP] = RCR_AAP,
278
279 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
280 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
281 .maps[EFUSE_CLK] = 0,
282 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
283 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
284 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
285 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
286 .maps[EFUSE_ANA8M] = 0,
287 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
288 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
289 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
290
291 .maps[RWCAM] = REG_CAMCMD,
292 .maps[WCAMI] = REG_CAMWRITE,
293 .maps[RCAMO] = REG_CAMREAD,
294 .maps[CAMDBG] = REG_CAMDBG,
295 .maps[SECR] = REG_SECCFG,
296 .maps[SEC_CAM_NONE] = CAM_NONE,
297 .maps[SEC_CAM_WEP40] = CAM_WEP40,
298 .maps[SEC_CAM_TKIP] = CAM_TKIP,
299 .maps[SEC_CAM_AES] = CAM_AES,
300 .maps[SEC_CAM_WEP104] = CAM_WEP104,
301
302 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
303 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
304 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
305 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
306 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
307 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
308 .maps[RTL_IMR_BCNDOK8] = IMR_BCNDOK8,
309 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
310 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
311 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
312 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
313 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
314 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
315 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
316 .maps[RTL_IMR_TIMEOUT2] = IMR_TIMEOUT2,
317 .maps[RTL_IMR_TIMEOUT1] = IMR_TIMEOUT1,
318
319 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
320 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
321 .maps[RTL_IMR_BCNINT] = IMR_BCNINT,
322 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
323 .maps[RTL_IMR_RDU] = IMR_RDU,
324 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
325 .maps[RTL_IMR_BDOK] = IMR_BDOK,
326 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
327 .maps[RTL_IMR_TBDER] = IMR_TBDER,
328 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
329 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
330 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
331 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
332 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
333 .maps[RTL_IMR_VODOK] = IMR_VODOK,
334 .maps[RTL_IMR_ROK] = IMR_ROK,
335 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNINT | IMR_TBDOK | IMR_TBDER),
336
337 .maps[RTL_RC_CCK_RATE1M] = DESC_RATE1M,
338 .maps[RTL_RC_CCK_RATE2M] = DESC_RATE2M,
339 .maps[RTL_RC_CCK_RATE5_5M] = DESC_RATE5_5M,
340 .maps[RTL_RC_CCK_RATE11M] = DESC_RATE11M,
341 .maps[RTL_RC_OFDM_RATE6M] = DESC_RATE6M,
342 .maps[RTL_RC_OFDM_RATE9M] = DESC_RATE9M,
343 .maps[RTL_RC_OFDM_RATE12M] = DESC_RATE12M,
344 .maps[RTL_RC_OFDM_RATE18M] = DESC_RATE18M,
345 .maps[RTL_RC_OFDM_RATE24M] = DESC_RATE24M,
346 .maps[RTL_RC_OFDM_RATE36M] = DESC_RATE36M,
347 .maps[RTL_RC_OFDM_RATE48M] = DESC_RATE48M,
348 .maps[RTL_RC_OFDM_RATE54M] = DESC_RATE54M,
349
350 .maps[RTL_RC_HT_RATEMCS7] = DESC_RATEMCS7,
351 .maps[RTL_RC_HT_RATEMCS15] = DESC_RATEMCS15,
352};
353
354static const struct pci_device_id rtl92de_pci_ids[] = {
355 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8193, rtl92de_hal_cfg)},
356 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x002B, rtl92de_hal_cfg)},
357 {},
358};
359
360MODULE_DEVICE_TABLE(pci, rtl92de_pci_ids);
361
362MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
363MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
364MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
365MODULE_LICENSE("GPL");
366MODULE_DESCRIPTION("Realtek 8192DE 802.11n Dual Mac PCI wireless");
367MODULE_FIRMWARE("rtlwifi/rtl8192defw.bin");
368
369module_param_named(swenc, rtl92de_mod_params.sw_crypto, bool, 0444);
370module_param_named(debug_level, rtl92de_mod_params.debug_level, int, 0644);
371module_param_named(ips, rtl92de_mod_params.inactiveps, bool, 0444);
372module_param_named(swlps, rtl92de_mod_params.swctrl_lps, bool, 0444);
373module_param_named(fwlps, rtl92de_mod_params.fwctrl_lps, bool, 0444);
374module_param_named(aspm, rtl92de_mod_params.aspm_support, int, 0444);
375module_param_named(debug_mask, rtl92de_mod_params.debug_mask, ullong, 0644);
376MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
377MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
378MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 1)\n");
379MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 0)\n");
380MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
381MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
382MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
383
384static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
385
386static struct pci_driver rtl92de_driver = {
387 .name = KBUILD_MODNAME,
388 .id_table = rtl92de_pci_ids,
389 .probe = rtl_pci_probe,
390 .remove = rtl_pci_disconnect,
391 .driver.pm = &rtlwifi_pm_ops,
392};
393
394
395
396spinlock_t globalmutex_power;
397spinlock_t globalmutex_for_fwdownload;
398spinlock_t globalmutex_for_power_and_efuse;
399
400static int __init rtl92de_module_init(void)
401{
402 int ret = 0;
403
404 spin_lock_init(&globalmutex_power);
405 spin_lock_init(&globalmutex_for_fwdownload);
406 spin_lock_init(&globalmutex_for_power_and_efuse);
407
408 ret = pci_register_driver(&rtl92de_driver);
409 if (ret)
410 WARN_ONCE(true, "rtl8192de: No device found\n");
411 return ret;
412}
413
414static void __exit rtl92de_module_exit(void)
415{
416 pci_unregister_driver(&rtl92de_driver);
417}
418
419module_init(rtl92de_module_init);
420module_exit(rtl92de_module_exit);
421
