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26#include "../wifi.h"
27#include "../core.h"
28#include "../pci.h"
29#include "reg.h"
30#include "def.h"
31#include "phy.h"
32#include "dm.h"
33#include "hw.h"
34#include "sw.h"
35#include "fw.h"
36#include "trx.h"
37#include "led.h"
38#include "table.h"
39
40#include "../btcoexist/rtl_btc.h"
41
42#include <linux/vmalloc.h>
43#include <linux/module.h>
44
45static void rtl92ee_init_aspm_vars(struct ieee80211_hw *hw)
46{
47 struct rtl_priv *rtlpriv = rtl_priv(hw);
48 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
49
50
51 rtlpci->const_amdpci_aspm = 0;
52
53
54
55
56
57
58
59
60
61
62 rtlpci->const_pci_aspm = 3;
63
64
65 rtlpci->const_devicepci_aspm_setting = 0x03;
66
67
68 rtlpci->const_hostpci_aspm_setting = 0x02;
69
70
71
72
73
74
75
76
77
78 rtlpci->const_hwsw_rfoff_d3 = 0;
79
80
81
82
83
84
85
86
87 rtlpci->const_support_pciaspm = rtlpriv->cfg->mod_params->aspm_support;
88}
89
90int rtl92ee_init_sw_vars(struct ieee80211_hw *hw)
91{
92 struct rtl_priv *rtlpriv = rtl_priv(hw);
93 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
94 int err = 0;
95 char *fw_name;
96
97 rtl92ee_bt_reg_init(hw);
98 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
99 rtlpriv->btcoexist.btc_ops = rtl_btc_get_ops_pointer();
100
101 rtlpriv->dm.dm_initialgain_enable = 1;
102 rtlpriv->dm.dm_flag = 0;
103 rtlpriv->dm.disable_framebursting = 0;
104 rtlpci->transmit_config = CFENDFORM | BIT(15);
105
106
107 rtlpriv->rtlhal.current_bandtype = BAND_ON_2_4G;
108 rtlpriv->rtlhal.bandset = BAND_ON_2_4G;
109 rtlpriv->rtlhal.macphymode = SINGLEMAC_SINGLEPHY;
110
111 rtlpci->receive_config = (RCR_APPFCS |
112 RCR_APP_MIC |
113 RCR_APP_ICV |
114 RCR_APP_PHYST_RXFF |
115 RCR_HTC_LOC_CTRL |
116 RCR_AMF |
117 RCR_ACF |
118 RCR_ACRC32 |
119 RCR_AB |
120 RCR_AM |
121 RCR_APM |
122 0);
123
124 rtlpci->irq_mask[0] = (u32)(IMR_PSTIMEOUT |
125 IMR_C2HCMD |
126 IMR_HIGHDOK |
127 IMR_MGNTDOK |
128 IMR_BKDOK |
129 IMR_BEDOK |
130 IMR_VIDOK |
131 IMR_VODOK |
132 IMR_RDU |
133 IMR_ROK |
134 0);
135 rtlpci->irq_mask[1] = (u32)(IMR_RXFOVW | 0);
136
137
138 rtlpriv->psc.inactiveps = rtlpriv->cfg->mod_params->inactiveps;
139 rtlpriv->psc.swctrl_lps = rtlpriv->cfg->mod_params->swctrl_lps;
140 rtlpriv->psc.fwctrl_lps = rtlpriv->cfg->mod_params->fwctrl_lps;
141 rtlpci->msi_support = rtlpriv->cfg->mod_params->msi_support;
142 if (rtlpriv->cfg->mod_params->disable_watchdog)
143 pr_info("watchdog disabled\n");
144 rtlpriv->psc.reg_fwctrl_lps = 3;
145 rtlpriv->psc.reg_max_lps_awakeintvl = 5;
146
147
148
149 rtl92ee_init_aspm_vars(hw);
150
151 if (rtlpriv->psc.reg_fwctrl_lps == 1)
152 rtlpriv->psc.fwctrl_psmode = FW_PS_MIN_MODE;
153 else if (rtlpriv->psc.reg_fwctrl_lps == 2)
154 rtlpriv->psc.fwctrl_psmode = FW_PS_MAX_MODE;
155 else if (rtlpriv->psc.reg_fwctrl_lps == 3)
156 rtlpriv->psc.fwctrl_psmode = FW_PS_DTIM_MODE;
157
158
159 rtlpriv->rtlhal.earlymode_enable = false;
160
161
162 rtlpriv->psc.low_power_enable = false;
163
164
165 rtlpriv->rtlhal.pfirmware = vzalloc(0x8000);
166 if (!rtlpriv->rtlhal.pfirmware) {
167 pr_err("Can't alloc buffer for fw\n");
168 return 1;
169 }
170
171
172 fw_name = "rtlwifi/rtl8192eefw.bin";
173
174 rtlpriv->max_fw_size = 0x8000;
175 pr_info("Using firmware %s\n", fw_name);
176 err = request_firmware_nowait(THIS_MODULE, 1, fw_name,
177 rtlpriv->io.dev, GFP_KERNEL, hw,
178 rtl_fw_cb);
179 if (err) {
180 pr_err("Failed to request firmware!\n");
181 vfree(rtlpriv->rtlhal.pfirmware);
182 rtlpriv->rtlhal.pfirmware = NULL;
183 return 1;
184 }
185
186 return 0;
187}
188
189void rtl92ee_deinit_sw_vars(struct ieee80211_hw *hw)
190{
191 struct rtl_priv *rtlpriv = rtl_priv(hw);
192
193 if (rtlpriv->rtlhal.pfirmware) {
194 vfree(rtlpriv->rtlhal.pfirmware);
195 rtlpriv->rtlhal.pfirmware = NULL;
196 }
197}
198
199
200bool rtl92ee_get_btc_status(void)
201{
202 return true;
203}
204
205static struct rtl_hal_ops rtl8192ee_hal_ops = {
206 .init_sw_vars = rtl92ee_init_sw_vars,
207 .deinit_sw_vars = rtl92ee_deinit_sw_vars,
208 .read_eeprom_info = rtl92ee_read_eeprom_info,
209 .interrupt_recognized = rtl92ee_interrupt_recognized,
210 .hw_init = rtl92ee_hw_init,
211 .hw_disable = rtl92ee_card_disable,
212 .hw_suspend = rtl92ee_suspend,
213 .hw_resume = rtl92ee_resume,
214 .enable_interrupt = rtl92ee_enable_interrupt,
215 .disable_interrupt = rtl92ee_disable_interrupt,
216 .set_network_type = rtl92ee_set_network_type,
217 .set_chk_bssid = rtl92ee_set_check_bssid,
218 .set_qos = rtl92ee_set_qos,
219 .set_bcn_reg = rtl92ee_set_beacon_related_registers,
220 .set_bcn_intv = rtl92ee_set_beacon_interval,
221 .update_interrupt_mask = rtl92ee_update_interrupt_mask,
222 .get_hw_reg = rtl92ee_get_hw_reg,
223 .set_hw_reg = rtl92ee_set_hw_reg,
224 .update_rate_tbl = rtl92ee_update_hal_rate_tbl,
225 .pre_fill_tx_bd_desc = rtl92ee_pre_fill_tx_bd_desc,
226 .rx_desc_buff_remained_cnt = rtl92ee_rx_desc_buff_remained_cnt,
227 .rx_check_dma_ok = rtl92ee_rx_check_dma_ok,
228 .fill_tx_desc = rtl92ee_tx_fill_desc,
229 .fill_tx_cmddesc = rtl92ee_tx_fill_cmddesc,
230 .query_rx_desc = rtl92ee_rx_query_desc,
231 .set_channel_access = rtl92ee_update_channel_access_setting,
232 .radio_onoff_checking = rtl92ee_gpio_radio_on_off_checking,
233 .set_bw_mode = rtl92ee_phy_set_bw_mode,
234 .switch_channel = rtl92ee_phy_sw_chnl,
235 .dm_watchdog = rtl92ee_dm_watchdog,
236 .scan_operation_backup = rtl92ee_phy_scan_operation_backup,
237 .set_rf_power_state = rtl92ee_phy_set_rf_power_state,
238 .led_control = rtl92ee_led_control,
239 .set_desc = rtl92ee_set_desc,
240 .get_desc = rtl92ee_get_desc,
241 .is_tx_desc_closed = rtl92ee_is_tx_desc_closed,
242 .get_available_desc = rtl92ee_get_available_desc,
243 .tx_polling = rtl92ee_tx_polling,
244 .enable_hw_sec = rtl92ee_enable_hw_security_config,
245 .set_key = rtl92ee_set_key,
246 .init_sw_leds = rtl92ee_init_sw_leds,
247 .get_bbreg = rtl92ee_phy_query_bb_reg,
248 .set_bbreg = rtl92ee_phy_set_bb_reg,
249 .get_rfreg = rtl92ee_phy_query_rf_reg,
250 .set_rfreg = rtl92ee_phy_set_rf_reg,
251 .fill_h2c_cmd = rtl92ee_fill_h2c_cmd,
252 .get_btc_status = rtl92ee_get_btc_status,
253 .rx_command_packet = rtl92ee_rx_command_packet,
254 .c2h_content_parsing = rtl92ee_c2h_content_parsing,
255};
256
257static struct rtl_mod_params rtl92ee_mod_params = {
258 .sw_crypto = false,
259 .inactiveps = true,
260 .swctrl_lps = false,
261 .fwctrl_lps = true,
262 .msi_support = true,
263 .dma64 = false,
264 .aspm_support = 1,
265 .debug_level = 0,
266 .debug_mask = 0,
267};
268
269static const struct rtl_hal_cfg rtl92ee_hal_cfg = {
270 .bar_id = 2,
271 .write_readback = true,
272 .name = "rtl92ee_pci",
273 .ops = &rtl8192ee_hal_ops,
274 .mod_params = &rtl92ee_mod_params,
275
276 .maps[SYS_ISO_CTRL] = REG_SYS_ISO_CTRL,
277 .maps[SYS_FUNC_EN] = REG_SYS_FUNC_EN,
278 .maps[SYS_CLK] = REG_SYS_CLKR,
279 .maps[MAC_RCR_AM] = AM,
280 .maps[MAC_RCR_AB] = AB,
281 .maps[MAC_RCR_ACRC32] = ACRC32,
282 .maps[MAC_RCR_ACF] = ACF,
283 .maps[MAC_RCR_AAP] = AAP,
284 .maps[MAC_HIMR] = REG_HIMR,
285 .maps[MAC_HIMRE] = REG_HIMRE,
286
287 .maps[EFUSE_ACCESS] = REG_EFUSE_ACCESS,
288
289 .maps[EFUSE_TEST] = REG_EFUSE_TEST,
290 .maps[EFUSE_CTRL] = REG_EFUSE_CTRL,
291 .maps[EFUSE_CLK] = 0,
292 .maps[EFUSE_CLK_CTRL] = REG_EFUSE_CTRL,
293 .maps[EFUSE_PWC_EV12V] = PWC_EV12V,
294 .maps[EFUSE_FEN_ELDR] = FEN_ELDR,
295 .maps[EFUSE_LOADER_CLK_EN] = LOADER_CLK_EN,
296 .maps[EFUSE_ANA8M] = ANA8M,
297 .maps[EFUSE_HWSET_MAX_SIZE] = HWSET_MAX_SIZE,
298 .maps[EFUSE_MAX_SECTION_MAP] = EFUSE_MAX_SECTION,
299 .maps[EFUSE_REAL_CONTENT_SIZE] = EFUSE_REAL_CONTENT_LEN,
300 .maps[EFUSE_OOB_PROTECT_BYTES_LEN] = EFUSE_OOB_PROTECT_BYTES,
301
302 .maps[RWCAM] = REG_CAMCMD,
303 .maps[WCAMI] = REG_CAMWRITE,
304 .maps[RCAMO] = REG_CAMREAD,
305 .maps[CAMDBG] = REG_CAMDBG,
306 .maps[SECR] = REG_SECCFG,
307 .maps[SEC_CAM_NONE] = CAM_NONE,
308 .maps[SEC_CAM_WEP40] = CAM_WEP40,
309 .maps[SEC_CAM_TKIP] = CAM_TKIP,
310 .maps[SEC_CAM_AES] = CAM_AES,
311 .maps[SEC_CAM_WEP104] = CAM_WEP104,
312
313 .maps[RTL_IMR_BCNDMAINT6] = IMR_BCNDMAINT6,
314 .maps[RTL_IMR_BCNDMAINT5] = IMR_BCNDMAINT5,
315 .maps[RTL_IMR_BCNDMAINT4] = IMR_BCNDMAINT4,
316 .maps[RTL_IMR_BCNDMAINT3] = IMR_BCNDMAINT3,
317 .maps[RTL_IMR_BCNDMAINT2] = IMR_BCNDMAINT2,
318 .maps[RTL_IMR_BCNDMAINT1] = IMR_BCNDMAINT1,
319 .maps[RTL_IMR_BCNDOK7] = IMR_BCNDOK7,
320 .maps[RTL_IMR_BCNDOK6] = IMR_BCNDOK6,
321 .maps[RTL_IMR_BCNDOK5] = IMR_BCNDOK5,
322 .maps[RTL_IMR_BCNDOK4] = IMR_BCNDOK4,
323 .maps[RTL_IMR_BCNDOK3] = IMR_BCNDOK3,
324 .maps[RTL_IMR_BCNDOK2] = IMR_BCNDOK2,
325 .maps[RTL_IMR_BCNDOK1] = IMR_BCNDOK1,
326
327 .maps[RTL_IMR_TXFOVW] = IMR_TXFOVW,
328 .maps[RTL_IMR_PSTIMEOUT] = IMR_PSTIMEOUT,
329 .maps[RTL_IMR_BCNINT] = IMR_BCNDMAINT0,
330 .maps[RTL_IMR_RXFOVW] = IMR_RXFOVW,
331 .maps[RTL_IMR_RDU] = IMR_RDU,
332 .maps[RTL_IMR_ATIMEND] = IMR_ATIMEND,
333 .maps[RTL_IMR_BDOK] = IMR_BCNDOK0,
334 .maps[RTL_IMR_MGNTDOK] = IMR_MGNTDOK,
335 .maps[RTL_IMR_TBDER] = IMR_TBDER,
336 .maps[RTL_IMR_HIGHDOK] = IMR_HIGHDOK,
337 .maps[RTL_IMR_TBDOK] = IMR_TBDOK,
338 .maps[RTL_IMR_BKDOK] = IMR_BKDOK,
339 .maps[RTL_IMR_BEDOK] = IMR_BEDOK,
340 .maps[RTL_IMR_VIDOK] = IMR_VIDOK,
341 .maps[RTL_IMR_VODOK] = IMR_VODOK,
342 .maps[RTL_IMR_ROK] = IMR_ROK,
343 .maps[RTL_IBSS_INT_MASKS] = (IMR_BCNDMAINT0 | IMR_TBDOK | IMR_TBDER),
344
345 .maps[RTL_RC_CCK_RATE1M] = DESC92C_RATE1M,
346 .maps[RTL_RC_CCK_RATE2M] = DESC92C_RATE2M,
347 .maps[RTL_RC_CCK_RATE5_5M] = DESC92C_RATE5_5M,
348 .maps[RTL_RC_CCK_RATE11M] = DESC92C_RATE11M,
349 .maps[RTL_RC_OFDM_RATE6M] = DESC92C_RATE6M,
350 .maps[RTL_RC_OFDM_RATE9M] = DESC92C_RATE9M,
351 .maps[RTL_RC_OFDM_RATE12M] = DESC92C_RATE12M,
352 .maps[RTL_RC_OFDM_RATE18M] = DESC92C_RATE18M,
353 .maps[RTL_RC_OFDM_RATE24M] = DESC92C_RATE24M,
354 .maps[RTL_RC_OFDM_RATE36M] = DESC92C_RATE36M,
355 .maps[RTL_RC_OFDM_RATE48M] = DESC92C_RATE48M,
356 .maps[RTL_RC_OFDM_RATE54M] = DESC92C_RATE54M,
357
358 .maps[RTL_RC_HT_RATEMCS7] = DESC92C_RATEMCS7,
359 .maps[RTL_RC_HT_RATEMCS15] = DESC92C_RATEMCS15,
360};
361
362static const struct pci_device_id rtl92ee_pci_ids[] = {
363 {RTL_PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x818B, rtl92ee_hal_cfg)},
364 {},
365};
366
367MODULE_DEVICE_TABLE(pci, rtl92ee_pci_ids);
368
369MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
370MODULE_AUTHOR("Larry Finger <Larry.Finger@lwfinger.net>");
371MODULE_LICENSE("GPL");
372MODULE_DESCRIPTION("Realtek 8192EE 802.11n PCI wireless");
373MODULE_FIRMWARE("rtlwifi/rtl8192eefw.bin");
374
375module_param_named(swenc, rtl92ee_mod_params.sw_crypto, bool, 0444);
376module_param_named(debug_level, rtl92ee_mod_params.debug_level, int, 0644);
377module_param_named(debug_mask, rtl92ee_mod_params.debug_mask, ullong, 0644);
378module_param_named(ips, rtl92ee_mod_params.inactiveps, bool, 0444);
379module_param_named(swlps, rtl92ee_mod_params.swctrl_lps, bool, 0444);
380module_param_named(fwlps, rtl92ee_mod_params.fwctrl_lps, bool, 0444);
381module_param_named(msi, rtl92ee_mod_params.msi_support, bool, 0444);
382module_param_named(dma64, rtl92ee_mod_params.dma64, bool, 0444);
383module_param_named(aspm, rtl92ee_mod_params.aspm_support, int, 0444);
384module_param_named(disable_watchdog, rtl92ee_mod_params.disable_watchdog,
385 bool, 0444);
386MODULE_PARM_DESC(swenc, "Set to 1 for software crypto (default 0)\n");
387MODULE_PARM_DESC(ips, "Set to 0 to not use link power save (default 1)\n");
388MODULE_PARM_DESC(swlps, "Set to 1 to use SW control power save (default 0)\n");
389MODULE_PARM_DESC(fwlps, "Set to 1 to use FW control power save (default 1)\n");
390MODULE_PARM_DESC(msi, "Set to 1 to use MSI interrupts mode (default 1)\n");
391MODULE_PARM_DESC(dma64, "Set to 1 to use DMA 64 (default 0)\n");
392MODULE_PARM_DESC(aspm, "Set to 1 to enable ASPM (default 1)\n");
393MODULE_PARM_DESC(debug_level, "Set debug level (0-5) (default 0)");
394MODULE_PARM_DESC(debug_mask, "Set debug mask (default 0)");
395MODULE_PARM_DESC(disable_watchdog, "Set to 1 to disable the watchdog (default 0)\n");
396
397static SIMPLE_DEV_PM_OPS(rtlwifi_pm_ops, rtl_pci_suspend, rtl_pci_resume);
398
399static struct pci_driver rtl92ee_driver = {
400 .name = KBUILD_MODNAME,
401 .id_table = rtl92ee_pci_ids,
402 .probe = rtl_pci_probe,
403 .remove = rtl_pci_disconnect,
404 .driver.pm = &rtlwifi_pm_ops,
405};
406
407module_pci_driver(rtl92ee_driver);
408
