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22#ifndef __WL18XX_CONF_H__
23#define __WL18XX_CONF_H__
24
25#define WL18XX_CONF_MAGIC 0x10e100ca
26#define WL18XX_CONF_VERSION (WLCORE_CONF_VERSION | 0x0007)
27#define WL18XX_CONF_MASK 0x0000ffff
28#define WL18XX_CONF_SIZE (WLCORE_CONF_SIZE + \
29 sizeof(struct wl18xx_priv_conf))
30
31#define NUM_OF_CHANNELS_11_ABG 150
32#define NUM_OF_CHANNELS_11_P 7
33#define SRF_TABLE_LEN 16
34#define PIN_MUXING_SIZE 2
35#define WL18XX_TRACE_LOSS_GAPS_TX 10
36#define WL18XX_TRACE_LOSS_GAPS_RX 18
37
38struct wl18xx_mac_and_phy_params {
39 u8 phy_standalone;
40 u8 spare0;
41 u8 enable_clpc;
42 u8 enable_tx_low_pwr_on_siso_rdl;
43 u8 auto_detect;
44 u8 dedicated_fem;
45
46 u8 low_band_component;
47
48
49 u8 low_band_component_type;
50
51 u8 high_band_component;
52
53
54 u8 high_band_component_type;
55 u8 number_of_assembled_ant2_4;
56 u8 number_of_assembled_ant5;
57 u8 pin_muxing_platform_options[PIN_MUXING_SIZE];
58 u8 external_pa_dc2dc;
59 u8 tcxo_ldo_voltage;
60 u8 xtal_itrim_val;
61 u8 srf_state;
62 u8 srf1[SRF_TABLE_LEN];
63 u8 srf2[SRF_TABLE_LEN];
64 u8 srf3[SRF_TABLE_LEN];
65 u8 io_configuration;
66 u8 sdio_configuration;
67 u8 settings;
68 u8 rx_profile;
69 u8 per_chan_pwr_limit_arr_11abg[NUM_OF_CHANNELS_11_ABG];
70 u8 pwr_limit_reference_11_abg;
71 u8 per_chan_pwr_limit_arr_11p[NUM_OF_CHANNELS_11_P];
72 u8 pwr_limit_reference_11p;
73 u8 spare1;
74 u8 per_chan_bo_mode_11_abg[13];
75 u8 per_chan_bo_mode_11_p[4];
76 u8 primary_clock_setting_time;
77 u8 clock_valid_on_wake_up;
78 u8 secondary_clock_setting_time;
79 u8 board_type;
80
81 u8 psat;
82
83 s8 low_power_val;
84 s8 med_power_val;
85 s8 high_power_val;
86 s8 per_sub_band_tx_trace_loss[WL18XX_TRACE_LOSS_GAPS_TX];
87 s8 per_sub_band_rx_trace_loss[WL18XX_TRACE_LOSS_GAPS_RX];
88 u8 tx_rf_margin;
89
90 s8 low_power_val_2nd;
91 s8 med_power_val_2nd;
92 s8 high_power_val_2nd;
93
94 u8 padding[1];
95} __packed;
96
97enum wl18xx_ht_mode {
98
99 HT_MODE_DEFAULT = 0,
100
101
102 HT_MODE_WIDE = 1,
103
104
105 HT_MODE_SISO20 = 2,
106};
107
108struct wl18xx_ht_settings {
109
110 u8 mode;
111} __packed;
112
113struct conf_ap_sleep_settings {
114
115
116
117 u8 idle_duty_cycle;
118
119
120
121 u8 connected_duty_cycle;
122
123
124
125 u8 max_stations_thresh;
126
127
128
129 u8 idle_conn_thresh;
130} __packed;
131
132struct wl18xx_priv_conf {
133
134 struct wl18xx_ht_settings ht;
135
136
137 struct wl18xx_mac_and_phy_params phy;
138
139 struct conf_ap_sleep_settings ap_sleep;
140} __packed;
141
142enum wl18xx_sg_params {
143 WL18XX_CONF_SG_PARAM_0 = 0,
144
145
146 WL18XX_CONF_SG_ANTENNA_CONFIGURATION,
147 WL18XX_CONF_SG_ZIGBEE_COEX,
148 WL18XX_CONF_SG_TIME_SYNC,
149
150 WL18XX_CONF_SG_PARAM_4,
151 WL18XX_CONF_SG_PARAM_5,
152 WL18XX_CONF_SG_PARAM_6,
153 WL18XX_CONF_SG_PARAM_7,
154 WL18XX_CONF_SG_PARAM_8,
155 WL18XX_CONF_SG_PARAM_9,
156 WL18XX_CONF_SG_PARAM_10,
157 WL18XX_CONF_SG_PARAM_11,
158 WL18XX_CONF_SG_PARAM_12,
159 WL18XX_CONF_SG_PARAM_13,
160 WL18XX_CONF_SG_PARAM_14,
161 WL18XX_CONF_SG_PARAM_15,
162 WL18XX_CONF_SG_PARAM_16,
163 WL18XX_CONF_SG_PARAM_17,
164 WL18XX_CONF_SG_PARAM_18,
165 WL18XX_CONF_SG_PARAM_19,
166 WL18XX_CONF_SG_PARAM_20,
167 WL18XX_CONF_SG_PARAM_21,
168 WL18XX_CONF_SG_PARAM_22,
169 WL18XX_CONF_SG_PARAM_23,
170 WL18XX_CONF_SG_PARAM_24,
171 WL18XX_CONF_SG_PARAM_25,
172
173
174 WL18XX_CONF_SG_AUTO_SCAN_PROBE_REQ,
175 WL18XX_CONF_SG_ACTIVE_SCAN_DURATION_FACTOR_HV3,
176
177 WL18XX_CONF_SG_PARAM_28,
178
179
180 WL18XX_CONF_SG_PARAM_29,
181 WL18XX_CONF_SG_PARAM_30,
182 WL18XX_CONF_SG_PASSIVE_SCAN_DURATION_FACTOR_HV3,
183
184
185 WL18XX_CONF_SG_CONSECUTIVE_HV3_IN_PASSIVE_SCAN,
186 WL18XX_CONF_SG_BEACON_HV3_COLL_TH_IN_PASSIVE_SCAN,
187 WL18XX_CONF_SG_TX_RX_PROTECT_BW_IN_PASSIVE_SCAN,
188
189
190 WL18XX_CONF_SG_STA_FORCE_PS_IN_BT_SCO,
191 WL18XX_CONF_SG_PARAM_36,
192 WL18XX_CONF_SG_BEACON_MISS_PERCENT,
193 WL18XX_CONF_SG_PARAM_38,
194 WL18XX_CONF_SG_RXT,
195 WL18XX_CONF_SG_UNUSED,
196 WL18XX_CONF_SG_ADAPTIVE_RXT_TXT,
197 WL18XX_CONF_SG_GENERAL_USAGE_BIT_MAP,
198 WL18XX_CONF_SG_HV3_MAX_SERVED,
199 WL18XX_CONF_SG_PARAM_44,
200 WL18XX_CONF_SG_PARAM_45,
201 WL18XX_CONF_SG_CONSECUTIVE_CTS_THRESHOLD,
202 WL18XX_CONF_SG_GEMINI_PARAM_47,
203 WL18XX_CONF_SG_STA_CONNECTION_PROTECTION_TIME,
204
205
206 WL18XX_CONF_SG_AP_BEACON_MISS_TX,
207 WL18XX_CONF_SG_PARAM_50,
208 WL18XX_CONF_SG_AP_BEACON_WINDOW_INTERVAL,
209 WL18XX_CONF_SG_AP_CONNECTION_PROTECTION_TIME,
210 WL18XX_CONF_SG_PARAM_53,
211 WL18XX_CONF_SG_PARAM_54,
212
213
214 WL18XX_CONF_SG_CTS_DILUTED_BAD_RX_PACKETS_TH,
215 WL18XX_CONF_SG_CTS_CHOP_IN_DUAL_ANT_SCO_MASTER,
216
217 WL18XX_CONF_SG_TEMP_PARAM_1,
218 WL18XX_CONF_SG_TEMP_PARAM_2,
219 WL18XX_CONF_SG_TEMP_PARAM_3,
220 WL18XX_CONF_SG_TEMP_PARAM_4,
221 WL18XX_CONF_SG_TEMP_PARAM_5,
222 WL18XX_CONF_SG_TEMP_PARAM_6,
223 WL18XX_CONF_SG_TEMP_PARAM_7,
224 WL18XX_CONF_SG_TEMP_PARAM_8,
225 WL18XX_CONF_SG_TEMP_PARAM_9,
226 WL18XX_CONF_SG_TEMP_PARAM_10,
227
228 WL18XX_CONF_SG_PARAMS_MAX,
229 WL18XX_CONF_SG_PARAMS_ALL = 0xff
230};
231
232#endif
233