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11#include <linux/delay.h>
12#include <linux/init.h>
13#include <linux/interrupt.h>
14#include <linux/io.h>
15#include <linux/kernel.h>
16#include <linux/of_address.h>
17#include <linux/of_pci.h>
18#include <linux/pci.h>
19#include <linux/platform_device.h>
20#include <linux/pm_runtime.h>
21#include <linux/sizes.h>
22#include <linux/slab.h>
23
24
25#define RCAR_AHBPCI_PCICOM_OFFSET 0x800
26
27#define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
28#define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
29#define RCAR_PCIAHB_PREFETCH0 0x0
30#define RCAR_PCIAHB_PREFETCH4 0x1
31#define RCAR_PCIAHB_PREFETCH8 0x2
32#define RCAR_PCIAHB_PREFETCH16 0x3
33
34#define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
35#define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
36#define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
37#define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
38#define RCAR_AHBPCI_WIN1_HOST (1 << 30)
39#define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
40
41#define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
42#define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
43#define RCAR_PCI_INT_SIGTABORT (1 << 0)
44#define RCAR_PCI_INT_SIGRETABORT (1 << 1)
45#define RCAR_PCI_INT_REMABORT (1 << 2)
46#define RCAR_PCI_INT_PERR (1 << 3)
47#define RCAR_PCI_INT_SIGSERR (1 << 4)
48#define RCAR_PCI_INT_RESERR (1 << 5)
49#define RCAR_PCI_INT_WIN1ERR (1 << 12)
50#define RCAR_PCI_INT_WIN2ERR (1 << 13)
51#define RCAR_PCI_INT_A (1 << 16)
52#define RCAR_PCI_INT_B (1 << 17)
53#define RCAR_PCI_INT_PME (1 << 19)
54#define RCAR_PCI_INT_ALLERRORS (RCAR_PCI_INT_SIGTABORT | \
55 RCAR_PCI_INT_SIGRETABORT | \
56 RCAR_PCI_INT_REMABORT | \
57 RCAR_PCI_INT_PERR | \
58 RCAR_PCI_INT_SIGSERR | \
59 RCAR_PCI_INT_RESERR | \
60 RCAR_PCI_INT_WIN1ERR | \
61 RCAR_PCI_INT_WIN2ERR)
62
63#define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
64#define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
65#define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
66#define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
67#define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
68#define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
69#define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
70 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
71 RCAR_AHB_BUS_MMODE_WR_INCR | \
72 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
73 RCAR_AHB_BUS_SMODE_READYCTR)
74
75#define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
76#define RCAR_USBCTR_USBH_RST (1 << 0)
77#define RCAR_USBCTR_PCICLK_MASK (1 << 1)
78#define RCAR_USBCTR_PLL_RST (1 << 2)
79#define RCAR_USBCTR_DIRPD (1 << 8)
80#define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
81#define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
82#define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
83#define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
84#define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
85#define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
86
87#define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
88#define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
89#define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
90#define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
91
92#define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
93
94struct rcar_pci_priv {
95 struct device *dev;
96 void __iomem *reg;
97 struct resource mem_res;
98 struct resource *cfg_res;
99 unsigned busnr;
100 int irq;
101 unsigned long window_size;
102 unsigned long window_addr;
103 unsigned long window_pci;
104};
105
106
107static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
108 int where)
109{
110 struct pci_sys_data *sys = bus->sysdata;
111 struct rcar_pci_priv *priv = sys->private_data;
112 int slot, val;
113
114 if (sys->busnr != bus->number || PCI_FUNC(devfn))
115 return NULL;
116
117
118 slot = PCI_SLOT(devfn);
119 if (slot > 2)
120 return NULL;
121
122
123 if (slot == 0x0 && where >= 0x40)
124 return NULL;
125
126 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
127 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
128
129 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
130 return priv->reg + (slot >> 1) * 0x100 + where;
131}
132
133
134static int rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
135{
136 struct pci_sys_data *sys = dev->bus->sysdata;
137 struct rcar_pci_priv *priv = sys->private_data;
138 int irq;
139
140 irq = of_irq_parse_and_map_pci(dev, slot, pin);
141 if (!irq)
142 irq = priv->irq;
143
144 return irq;
145}
146
147#ifdef CONFIG_PCI_DEBUG
148
149
150static irqreturn_t rcar_pci_err_irq(int irq, void *pw)
151{
152 struct rcar_pci_priv *priv = pw;
153 struct device *dev = priv->dev;
154 u32 status = ioread32(priv->reg + RCAR_PCI_INT_STATUS_REG);
155
156 if (status & RCAR_PCI_INT_ALLERRORS) {
157 dev_err(dev, "error irq: status %08x\n", status);
158
159
160 iowrite32(status & RCAR_PCI_INT_ALLERRORS,
161 priv->reg + RCAR_PCI_INT_STATUS_REG);
162 return IRQ_HANDLED;
163 }
164
165 return IRQ_NONE;
166}
167
168static void rcar_pci_setup_errirq(struct rcar_pci_priv *priv)
169{
170 struct device *dev = priv->dev;
171 int ret;
172 u32 val;
173
174 ret = devm_request_irq(dev, priv->irq, rcar_pci_err_irq,
175 IRQF_SHARED, "error irq", priv);
176 if (ret) {
177 dev_err(dev, "cannot claim IRQ for error handling\n");
178 return;
179 }
180
181 val = ioread32(priv->reg + RCAR_PCI_INT_ENABLE_REG);
182 val |= RCAR_PCI_INT_ALLERRORS;
183 iowrite32(val, priv->reg + RCAR_PCI_INT_ENABLE_REG);
184}
185#else
186static inline void rcar_pci_setup_errirq(struct rcar_pci_priv *priv) { }
187#endif
188
189
190static int rcar_pci_setup(int nr, struct pci_sys_data *sys)
191{
192 struct rcar_pci_priv *priv = sys->private_data;
193 struct device *dev = priv->dev;
194 void __iomem *reg = priv->reg;
195 u32 val;
196 int ret;
197
198 pm_runtime_enable(dev);
199 pm_runtime_get_sync(dev);
200
201 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
202 dev_info(dev, "PCI: bus%u revision %x\n", sys->busnr, val);
203
204
205 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
206 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
207 iowrite32(val, reg + RCAR_USBCTR_REG);
208 udelay(4);
209
210
211 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
212 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
213
214
215 switch (priv->window_size) {
216 case SZ_2G:
217 val |= RCAR_USBCTR_PCIAHB_WIN1_2G;
218 break;
219 case SZ_1G:
220 val |= RCAR_USBCTR_PCIAHB_WIN1_1G;
221 break;
222 case SZ_512M:
223 val |= RCAR_USBCTR_PCIAHB_WIN1_512M;
224 break;
225 default:
226 pr_warn("unknown window size %ld - defaulting to 256M\n",
227 priv->window_size);
228 priv->window_size = SZ_256M;
229
230 case SZ_256M:
231 val |= RCAR_USBCTR_PCIAHB_WIN1_256M;
232 break;
233 }
234 iowrite32(val, reg + RCAR_USBCTR_REG);
235
236
237 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
238
239
240 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
241 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
242 RCAR_PCI_ARBITER_PCIBP_MODE;
243 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
244
245
246 iowrite32(priv->window_addr | RCAR_PCIAHB_PREFETCH16,
247 reg + RCAR_PCIAHB_WIN1_CTR_REG);
248
249
250 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
251 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
252
253
254 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
255 reg + RCAR_AHBPCI_WIN1_CTR_REG);
256
257 iowrite32(priv->window_pci | PCI_BASE_ADDRESS_MEM_PREFETCH,
258 reg + PCI_BASE_ADDRESS_1);
259
260 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
261 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
262
263 val = ioread32(reg + PCI_COMMAND);
264 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
265 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
266 iowrite32(val, reg + PCI_COMMAND);
267
268
269 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
270 reg + RCAR_PCI_INT_ENABLE_REG);
271
272 if (priv->irq > 0)
273 rcar_pci_setup_errirq(priv);
274
275
276 pci_add_resource(&sys->resources, &priv->mem_res);
277 ret = devm_request_pci_bus_resources(dev, &sys->resources);
278 if (ret < 0)
279 return ret;
280
281
282 sys->busnr = priv->busnr;
283 return 1;
284}
285
286static struct pci_ops rcar_pci_ops = {
287 .map_bus = rcar_pci_cfg_base,
288 .read = pci_generic_config_read,
289 .write = pci_generic_config_write,
290};
291
292static int rcar_pci_parse_map_dma_ranges(struct rcar_pci_priv *pci,
293 struct device_node *np)
294{
295 struct device *dev = pci->dev;
296 struct of_pci_range range;
297 struct of_pci_range_parser parser;
298 int index = 0;
299
300
301 if (of_pci_dma_range_parser_init(&parser, np))
302 return 0;
303
304
305 for_each_of_pci_range(&parser, &range) {
306
307 if (index)
308 return -EINVAL;
309
310 pci->window_addr = (unsigned long)range.cpu_addr;
311 pci->window_pci = (unsigned long)range.pci_addr;
312 pci->window_size = (unsigned long)range.size;
313
314
315 if (!(range.flags & IORESOURCE_PREFETCH)) {
316 dev_err(dev, "window must be prefetchable\n");
317 return -EINVAL;
318 }
319 if (pci->window_addr) {
320 u32 lowaddr = 1 << (ffs(pci->window_addr) - 1);
321
322 if (lowaddr < pci->window_size) {
323 dev_err(dev, "invalid window size/addr\n");
324 return -EINVAL;
325 }
326 }
327 index++;
328 }
329
330 return 0;
331}
332
333static int rcar_pci_probe(struct platform_device *pdev)
334{
335 struct device *dev = &pdev->dev;
336 struct resource *cfg_res, *mem_res;
337 struct rcar_pci_priv *priv;
338 void __iomem *reg;
339 struct hw_pci hw;
340 void *hw_private[1];
341
342 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
343 reg = devm_ioremap_resource(dev, cfg_res);
344 if (IS_ERR(reg))
345 return PTR_ERR(reg);
346
347 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
348 if (!mem_res || !mem_res->start)
349 return -ENODEV;
350
351 if (mem_res->start & 0xFFFF)
352 return -EINVAL;
353
354 priv = devm_kzalloc(dev, sizeof(struct rcar_pci_priv), GFP_KERNEL);
355 if (!priv)
356 return -ENOMEM;
357
358 priv->mem_res = *mem_res;
359 priv->cfg_res = cfg_res;
360
361 priv->irq = platform_get_irq(pdev, 0);
362 priv->reg = reg;
363 priv->dev = dev;
364
365 if (priv->irq < 0) {
366 dev_err(dev, "no valid irq found\n");
367 return priv->irq;
368 }
369
370
371 priv->window_addr = 0x40000000;
372 priv->window_pci = 0x40000000;
373 priv->window_size = SZ_1G;
374
375 if (dev->of_node) {
376 struct resource busnr;
377 int ret;
378
379 ret = of_pci_parse_bus_range(dev->of_node, &busnr);
380 if (ret < 0) {
381 dev_err(dev, "failed to parse bus-range\n");
382 return ret;
383 }
384
385 priv->busnr = busnr.start;
386 if (busnr.end != busnr.start)
387 dev_warn(dev, "only one bus number supported\n");
388
389 ret = rcar_pci_parse_map_dma_ranges(priv, dev->of_node);
390 if (ret < 0) {
391 dev_err(dev, "failed to parse dma-range\n");
392 return ret;
393 }
394 } else {
395 priv->busnr = pdev->id;
396 }
397
398 hw_private[0] = priv;
399 memset(&hw, 0, sizeof(hw));
400 hw.nr_controllers = ARRAY_SIZE(hw_private);
401 hw.io_optional = 1;
402 hw.private_data = hw_private;
403 hw.map_irq = rcar_pci_map_irq;
404 hw.ops = &rcar_pci_ops;
405 hw.setup = rcar_pci_setup;
406 pci_common_init_dev(dev, &hw);
407 return 0;
408}
409
410static const struct of_device_id rcar_pci_of_match[] = {
411 { .compatible = "renesas,pci-r8a7790", },
412 { .compatible = "renesas,pci-r8a7791", },
413 { .compatible = "renesas,pci-r8a7794", },
414 { .compatible = "renesas,pci-rcar-gen2", },
415 { },
416};
417
418static struct platform_driver rcar_pci_driver = {
419 .driver = {
420 .name = "pci-rcar-gen2",
421 .suppress_bind_attrs = true,
422 .of_match_table = rcar_pci_of_match,
423 },
424 .probe = rcar_pci_probe,
425};
426builtin_platform_driver(rcar_pci_driver);
427
