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6
7#include <linux/kernel.h>
8#include <linux/pci.h>
9#include <linux/msi.h>
10#include <linux/clk.h>
11#include <linux/module.h>
12#include <linux/mbus.h>
13#include <linux/slab.h>
14#include <linux/delay.h>
15#include <linux/interrupt.h>
16#include <linux/irqchip/arm-gic-v3.h>
17#include <linux/platform_device.h>
18#include <linux/of_address.h>
19#include <linux/of_pci.h>
20#include <linux/of_irq.h>
21#include <linux/of_platform.h>
22#include <linux/phy/phy.h>
23
24#include "pcie-iproc.h"
25
26#define EP_PERST_SOURCE_SELECT_SHIFT 2
27#define EP_PERST_SOURCE_SELECT BIT(EP_PERST_SOURCE_SELECT_SHIFT)
28#define EP_MODE_SURVIVE_PERST_SHIFT 1
29#define EP_MODE_SURVIVE_PERST BIT(EP_MODE_SURVIVE_PERST_SHIFT)
30#define RC_PCIE_RST_OUTPUT_SHIFT 0
31#define RC_PCIE_RST_OUTPUT BIT(RC_PCIE_RST_OUTPUT_SHIFT)
32#define PAXC_RESET_MASK 0x7f
33
34#define GIC_V3_CFG_SHIFT 0
35#define GIC_V3_CFG BIT(GIC_V3_CFG_SHIFT)
36
37#define MSI_ENABLE_CFG_SHIFT 0
38#define MSI_ENABLE_CFG BIT(MSI_ENABLE_CFG_SHIFT)
39
40#define CFG_IND_ADDR_MASK 0x00001ffc
41
42#define CFG_ADDR_BUS_NUM_SHIFT 20
43#define CFG_ADDR_BUS_NUM_MASK 0x0ff00000
44#define CFG_ADDR_DEV_NUM_SHIFT 15
45#define CFG_ADDR_DEV_NUM_MASK 0x000f8000
46#define CFG_ADDR_FUNC_NUM_SHIFT 12
47#define CFG_ADDR_FUNC_NUM_MASK 0x00007000
48#define CFG_ADDR_REG_NUM_SHIFT 2
49#define CFG_ADDR_REG_NUM_MASK 0x00000ffc
50#define CFG_ADDR_CFG_TYPE_SHIFT 0
51#define CFG_ADDR_CFG_TYPE_MASK 0x00000003
52
53#define SYS_RC_INTX_MASK 0xf
54
55#define PCIE_PHYLINKUP_SHIFT 3
56#define PCIE_PHYLINKUP BIT(PCIE_PHYLINKUP_SHIFT)
57#define PCIE_DL_ACTIVE_SHIFT 2
58#define PCIE_DL_ACTIVE BIT(PCIE_DL_ACTIVE_SHIFT)
59
60#define APB_ERR_EN_SHIFT 0
61#define APB_ERR_EN BIT(APB_ERR_EN_SHIFT)
62
63#define CFG_RETRY_STATUS 0xffff0001
64#define CFG_RETRY_STATUS_TIMEOUT_US 500000
65
66
67#define MAP_REG(base_reg, index) ((base_reg) + (index) * 2)
68
69
70
71
72
73#define MAX_NUM_OB_WINDOW_SIZES 4
74
75#define OARR_VALID_SHIFT 0
76#define OARR_VALID BIT(OARR_VALID_SHIFT)
77#define OARR_SIZE_CFG_SHIFT 1
78
79
80
81
82
83#define MAX_NUM_IB_REGION_SIZES 9
84
85#define IMAP_VALID_SHIFT 0
86#define IMAP_VALID BIT(IMAP_VALID_SHIFT)
87
88#define IPROC_PCI_EXP_CAP 0xac
89
90#define IPROC_PCIE_REG_INVALID 0xffff
91
92
93
94
95
96
97
98struct iproc_pcie_ob_map {
99 resource_size_t window_sizes[MAX_NUM_OB_WINDOW_SIZES];
100 unsigned int nr_sizes;
101};
102
103static const struct iproc_pcie_ob_map paxb_ob_map[] = {
104 {
105
106 .window_sizes = { 128, 256 },
107 .nr_sizes = 2,
108 },
109 {
110
111 .window_sizes = { 128, 256 },
112 .nr_sizes = 2,
113 },
114};
115
116static const struct iproc_pcie_ob_map paxb_v2_ob_map[] = {
117 {
118
119 .window_sizes = { 128, 256 },
120 .nr_sizes = 2,
121 },
122 {
123
124 .window_sizes = { 128, 256 },
125 .nr_sizes = 2,
126 },
127 {
128
129 .window_sizes = { 128, 256, 512, 1024 },
130 .nr_sizes = 4,
131 },
132 {
133
134 .window_sizes = { 128, 256, 512, 1024 },
135 .nr_sizes = 4,
136 },
137};
138
139
140
141
142enum iproc_pcie_ib_map_type {
143
144 IPROC_PCIE_IB_MAP_MEM = 0,
145
146
147 IPROC_PCIE_IB_MAP_IO,
148
149
150 IPROC_PCIE_IB_MAP_INVALID
151};
152
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154
155
156
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159
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161
162
163
164
165
166
167struct iproc_pcie_ib_map {
168 enum iproc_pcie_ib_map_type type;
169 unsigned int size_unit;
170 resource_size_t region_sizes[MAX_NUM_IB_REGION_SIZES];
171 unsigned int nr_sizes;
172 unsigned int nr_windows;
173 u16 imap_addr_offset;
174 u16 imap_window_offset;
175};
176
177static const struct iproc_pcie_ib_map paxb_v2_ib_map[] = {
178 {
179
180 .type = IPROC_PCIE_IB_MAP_IO,
181 .size_unit = SZ_1K,
182 .region_sizes = { 32 },
183 .nr_sizes = 1,
184 .nr_windows = 8,
185 .imap_addr_offset = 0x40,
186 .imap_window_offset = 0x4,
187 },
188 {
189
190 .type = IPROC_PCIE_IB_MAP_INVALID,
191 },
192 {
193
194 .type = IPROC_PCIE_IB_MAP_MEM,
195 .size_unit = SZ_1M,
196 .region_sizes = { 64, 128, 256, 512, 1024, 2048, 4096, 8192,
197 16384 },
198 .nr_sizes = 9,
199 .nr_windows = 1,
200 .imap_addr_offset = 0x4,
201 .imap_window_offset = 0x8,
202 },
203 {
204
205 .type = IPROC_PCIE_IB_MAP_MEM,
206 .size_unit = SZ_1G,
207 .region_sizes = { 1, 2, 4, 8, 16, 32 },
208 .nr_sizes = 6,
209 .nr_windows = 8,
210 .imap_addr_offset = 0x4,
211 .imap_window_offset = 0x8,
212 },
213 {
214
215 .type = IPROC_PCIE_IB_MAP_MEM,
216 .size_unit = SZ_1G,
217 .region_sizes = { 32, 64, 128, 256, 512 },
218 .nr_sizes = 5,
219 .nr_windows = 8,
220 .imap_addr_offset = 0x4,
221 .imap_window_offset = 0x8,
222 },
223};
224
225
226
227
228enum iproc_pcie_reg {
229
230 IPROC_PCIE_CLK_CTRL = 0,
231
232
233
234
235
236 IPROC_PCIE_MSI_GIC_MODE,
237
238
239
240
241
242
243 IPROC_PCIE_MSI_BASE_ADDR,
244 IPROC_PCIE_MSI_WINDOW_SIZE,
245
246
247
248
249
250
251 IPROC_PCIE_MSI_ADDR_LO,
252 IPROC_PCIE_MSI_ADDR_HI,
253
254
255 IPROC_PCIE_MSI_EN_CFG,
256
257
258 IPROC_PCIE_CFG_IND_ADDR,
259 IPROC_PCIE_CFG_IND_DATA,
260
261
262 IPROC_PCIE_CFG_ADDR,
263 IPROC_PCIE_CFG_DATA,
264
265
266 IPROC_PCIE_INTX_EN,
267
268
269 IPROC_PCIE_OARR0,
270 IPROC_PCIE_OMAP0,
271 IPROC_PCIE_OARR1,
272 IPROC_PCIE_OMAP1,
273 IPROC_PCIE_OARR2,
274 IPROC_PCIE_OMAP2,
275 IPROC_PCIE_OARR3,
276 IPROC_PCIE_OMAP3,
277
278
279 IPROC_PCIE_IARR0,
280 IPROC_PCIE_IMAP0,
281 IPROC_PCIE_IARR1,
282 IPROC_PCIE_IMAP1,
283 IPROC_PCIE_IARR2,
284 IPROC_PCIE_IMAP2,
285 IPROC_PCIE_IARR3,
286 IPROC_PCIE_IMAP3,
287 IPROC_PCIE_IARR4,
288 IPROC_PCIE_IMAP4,
289
290
291 IPROC_PCIE_LINK_STATUS,
292
293
294 IPROC_PCIE_APB_ERR_EN,
295
296
297 IPROC_PCIE_MAX_NUM_REG,
298};
299
300
301static const u16 iproc_pcie_reg_paxb_bcma[] = {
302 [IPROC_PCIE_CLK_CTRL] = 0x000,
303 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
304 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
305 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
306 [IPROC_PCIE_CFG_DATA] = 0x1fc,
307 [IPROC_PCIE_INTX_EN] = 0x330,
308 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
309};
310
311
312static const u16 iproc_pcie_reg_paxb[] = {
313 [IPROC_PCIE_CLK_CTRL] = 0x000,
314 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
315 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
316 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
317 [IPROC_PCIE_CFG_DATA] = 0x1fc,
318 [IPROC_PCIE_INTX_EN] = 0x330,
319 [IPROC_PCIE_OARR0] = 0xd20,
320 [IPROC_PCIE_OMAP0] = 0xd40,
321 [IPROC_PCIE_OARR1] = 0xd28,
322 [IPROC_PCIE_OMAP1] = 0xd48,
323 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
324 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
325};
326
327
328static const u16 iproc_pcie_reg_paxb_v2[] = {
329 [IPROC_PCIE_CLK_CTRL] = 0x000,
330 [IPROC_PCIE_CFG_IND_ADDR] = 0x120,
331 [IPROC_PCIE_CFG_IND_DATA] = 0x124,
332 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
333 [IPROC_PCIE_CFG_DATA] = 0x1fc,
334 [IPROC_PCIE_INTX_EN] = 0x330,
335 [IPROC_PCIE_OARR0] = 0xd20,
336 [IPROC_PCIE_OMAP0] = 0xd40,
337 [IPROC_PCIE_OARR1] = 0xd28,
338 [IPROC_PCIE_OMAP1] = 0xd48,
339 [IPROC_PCIE_OARR2] = 0xd60,
340 [IPROC_PCIE_OMAP2] = 0xd68,
341 [IPROC_PCIE_OARR3] = 0xdf0,
342 [IPROC_PCIE_OMAP3] = 0xdf8,
343 [IPROC_PCIE_IARR0] = 0xd00,
344 [IPROC_PCIE_IMAP0] = 0xc00,
345 [IPROC_PCIE_IARR2] = 0xd10,
346 [IPROC_PCIE_IMAP2] = 0xcc0,
347 [IPROC_PCIE_IARR3] = 0xe00,
348 [IPROC_PCIE_IMAP3] = 0xe08,
349 [IPROC_PCIE_IARR4] = 0xe68,
350 [IPROC_PCIE_IMAP4] = 0xe70,
351 [IPROC_PCIE_LINK_STATUS] = 0xf0c,
352 [IPROC_PCIE_APB_ERR_EN] = 0xf40,
353};
354
355
356static const u16 iproc_pcie_reg_paxc[] = {
357 [IPROC_PCIE_CLK_CTRL] = 0x000,
358 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
359 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
360 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
361 [IPROC_PCIE_CFG_DATA] = 0x1fc,
362};
363
364
365static const u16 iproc_pcie_reg_paxc_v2[] = {
366 [IPROC_PCIE_MSI_GIC_MODE] = 0x050,
367 [IPROC_PCIE_MSI_BASE_ADDR] = 0x074,
368 [IPROC_PCIE_MSI_WINDOW_SIZE] = 0x078,
369 [IPROC_PCIE_MSI_ADDR_LO] = 0x07c,
370 [IPROC_PCIE_MSI_ADDR_HI] = 0x080,
371 [IPROC_PCIE_MSI_EN_CFG] = 0x09c,
372 [IPROC_PCIE_CFG_IND_ADDR] = 0x1f0,
373 [IPROC_PCIE_CFG_IND_DATA] = 0x1f4,
374 [IPROC_PCIE_CFG_ADDR] = 0x1f8,
375 [IPROC_PCIE_CFG_DATA] = 0x1fc,
376};
377
378static inline struct iproc_pcie *iproc_data(struct pci_bus *bus)
379{
380 struct iproc_pcie *pcie = bus->sysdata;
381 return pcie;
382}
383
384static inline bool iproc_pcie_reg_is_invalid(u16 reg_offset)
385{
386 return !!(reg_offset == IPROC_PCIE_REG_INVALID);
387}
388
389static inline u16 iproc_pcie_reg_offset(struct iproc_pcie *pcie,
390 enum iproc_pcie_reg reg)
391{
392 return pcie->reg_offsets[reg];
393}
394
395static inline u32 iproc_pcie_read_reg(struct iproc_pcie *pcie,
396 enum iproc_pcie_reg reg)
397{
398 u16 offset = iproc_pcie_reg_offset(pcie, reg);
399
400 if (iproc_pcie_reg_is_invalid(offset))
401 return 0;
402
403 return readl(pcie->base + offset);
404}
405
406static inline void iproc_pcie_write_reg(struct iproc_pcie *pcie,
407 enum iproc_pcie_reg reg, u32 val)
408{
409 u16 offset = iproc_pcie_reg_offset(pcie, reg);
410
411 if (iproc_pcie_reg_is_invalid(offset))
412 return;
413
414 writel(val, pcie->base + offset);
415}
416
417
418
419
420
421
422
423static inline void iproc_pcie_apb_err_disable(struct pci_bus *bus,
424 bool disable)
425{
426 struct iproc_pcie *pcie = iproc_data(bus);
427 u32 val;
428
429 if (bus->number && pcie->has_apb_err_disable) {
430 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_APB_ERR_EN);
431 if (disable)
432 val &= ~APB_ERR_EN;
433 else
434 val |= APB_ERR_EN;
435 iproc_pcie_write_reg(pcie, IPROC_PCIE_APB_ERR_EN, val);
436 }
437}
438
439static void __iomem *iproc_pcie_map_ep_cfg_reg(struct iproc_pcie *pcie,
440 unsigned int busno,
441 unsigned int slot,
442 unsigned int fn,
443 int where)
444{
445 u16 offset;
446 u32 val;
447
448
449 val = (busno << CFG_ADDR_BUS_NUM_SHIFT) |
450 (slot << CFG_ADDR_DEV_NUM_SHIFT) |
451 (fn << CFG_ADDR_FUNC_NUM_SHIFT) |
452 (where & CFG_ADDR_REG_NUM_MASK) |
453 (1 & CFG_ADDR_CFG_TYPE_MASK);
454
455 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_ADDR, val);
456 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_DATA);
457
458 if (iproc_pcie_reg_is_invalid(offset))
459 return NULL;
460
461 return (pcie->base + offset);
462}
463
464static unsigned int iproc_pcie_cfg_retry(void __iomem *cfg_data_p)
465{
466 int timeout = CFG_RETRY_STATUS_TIMEOUT_US;
467 unsigned int data;
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486 data = readl(cfg_data_p);
487 while (data == CFG_RETRY_STATUS && timeout--) {
488 udelay(1);
489 data = readl(cfg_data_p);
490 }
491
492 if (data == CFG_RETRY_STATUS)
493 data = 0xffffffff;
494
495 return data;
496}
497
498static int iproc_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
499 int where, int size, u32 *val)
500{
501 struct iproc_pcie *pcie = iproc_data(bus);
502 unsigned int slot = PCI_SLOT(devfn);
503 unsigned int fn = PCI_FUNC(devfn);
504 unsigned int busno = bus->number;
505 void __iomem *cfg_data_p;
506 unsigned int data;
507 int ret;
508
509
510 if (busno == 0) {
511 ret = pci_generic_config_read32(bus, devfn, where, size, val);
512 if (ret != PCIBIOS_SUCCESSFUL)
513 return ret;
514
515
516 if ((where & ~0x3) == IPROC_PCI_EXP_CAP + PCI_EXP_RTCTL)
517 *val &= ~(PCI_EXP_RTCAP_CRSVIS << 16);
518 return PCIBIOS_SUCCESSFUL;
519 }
520
521 cfg_data_p = iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
522
523 if (!cfg_data_p)
524 return PCIBIOS_DEVICE_NOT_FOUND;
525
526 data = iproc_pcie_cfg_retry(cfg_data_p);
527
528 *val = data;
529 if (size <= 2)
530 *val = (data >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
531
532 return PCIBIOS_SUCCESSFUL;
533}
534
535
536
537
538
539static void __iomem *iproc_pcie_map_cfg_bus(struct iproc_pcie *pcie,
540 int busno, unsigned int devfn,
541 int where)
542{
543 unsigned slot = PCI_SLOT(devfn);
544 unsigned fn = PCI_FUNC(devfn);
545 u16 offset;
546
547
548 if (busno == 0) {
549 if (slot > 0 || fn > 0)
550 return NULL;
551
552 iproc_pcie_write_reg(pcie, IPROC_PCIE_CFG_IND_ADDR,
553 where & CFG_IND_ADDR_MASK);
554 offset = iproc_pcie_reg_offset(pcie, IPROC_PCIE_CFG_IND_DATA);
555 if (iproc_pcie_reg_is_invalid(offset))
556 return NULL;
557 else
558 return (pcie->base + offset);
559 }
560
561
562
563
564
565 if (pcie->ep_is_internal)
566 if (slot > 0)
567 return NULL;
568
569 return iproc_pcie_map_ep_cfg_reg(pcie, busno, slot, fn, where);
570}
571
572static void __iomem *iproc_pcie_bus_map_cfg_bus(struct pci_bus *bus,
573 unsigned int devfn,
574 int where)
575{
576 return iproc_pcie_map_cfg_bus(iproc_data(bus), bus->number, devfn,
577 where);
578}
579
580static int iproc_pci_raw_config_read32(struct iproc_pcie *pcie,
581 unsigned int devfn, int where,
582 int size, u32 *val)
583{
584 void __iomem *addr;
585
586 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
587 if (!addr) {
588 *val = ~0;
589 return PCIBIOS_DEVICE_NOT_FOUND;
590 }
591
592 *val = readl(addr);
593
594 if (size <= 2)
595 *val = (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1);
596
597 return PCIBIOS_SUCCESSFUL;
598}
599
600static int iproc_pci_raw_config_write32(struct iproc_pcie *pcie,
601 unsigned int devfn, int where,
602 int size, u32 val)
603{
604 void __iomem *addr;
605 u32 mask, tmp;
606
607 addr = iproc_pcie_map_cfg_bus(pcie, 0, devfn, where & ~0x3);
608 if (!addr)
609 return PCIBIOS_DEVICE_NOT_FOUND;
610
611 if (size == 4) {
612 writel(val, addr);
613 return PCIBIOS_SUCCESSFUL;
614 }
615
616 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
617 tmp = readl(addr) & mask;
618 tmp |= val << ((where & 0x3) * 8);
619 writel(tmp, addr);
620
621 return PCIBIOS_SUCCESSFUL;
622}
623
624static int iproc_pcie_config_read32(struct pci_bus *bus, unsigned int devfn,
625 int where, int size, u32 *val)
626{
627 int ret;
628 struct iproc_pcie *pcie = iproc_data(bus);
629
630 iproc_pcie_apb_err_disable(bus, true);
631 if (pcie->type == IPROC_PCIE_PAXB_V2)
632 ret = iproc_pcie_config_read(bus, devfn, where, size, val);
633 else
634 ret = pci_generic_config_read32(bus, devfn, where, size, val);
635 iproc_pcie_apb_err_disable(bus, false);
636
637 return ret;
638}
639
640static int iproc_pcie_config_write32(struct pci_bus *bus, unsigned int devfn,
641 int where, int size, u32 val)
642{
643 int ret;
644
645 iproc_pcie_apb_err_disable(bus, true);
646 ret = pci_generic_config_write32(bus, devfn, where, size, val);
647 iproc_pcie_apb_err_disable(bus, false);
648
649 return ret;
650}
651
652static struct pci_ops iproc_pcie_ops = {
653 .map_bus = iproc_pcie_bus_map_cfg_bus,
654 .read = iproc_pcie_config_read32,
655 .write = iproc_pcie_config_write32,
656};
657
658static void iproc_pcie_perst_ctrl(struct iproc_pcie *pcie, bool assert)
659{
660 u32 val;
661
662
663
664
665
666
667 if (pcie->ep_is_internal)
668 return;
669
670 if (assert) {
671 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
672 val &= ~EP_PERST_SOURCE_SELECT & ~EP_MODE_SURVIVE_PERST &
673 ~RC_PCIE_RST_OUTPUT;
674 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
675 udelay(250);
676 } else {
677 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_CLK_CTRL);
678 val |= RC_PCIE_RST_OUTPUT;
679 iproc_pcie_write_reg(pcie, IPROC_PCIE_CLK_CTRL, val);
680 msleep(100);
681 }
682}
683
684int iproc_pcie_shutdown(struct iproc_pcie *pcie)
685{
686 iproc_pcie_perst_ctrl(pcie, true);
687 msleep(500);
688
689 return 0;
690}
691EXPORT_SYMBOL_GPL(iproc_pcie_shutdown);
692
693static int iproc_pcie_check_link(struct iproc_pcie *pcie)
694{
695 struct device *dev = pcie->dev;
696 u32 hdr_type, link_ctrl, link_status, class, val;
697 bool link_is_active = false;
698
699
700
701
702
703 if (pcie->ep_is_internal)
704 return 0;
705
706 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_LINK_STATUS);
707 if (!(val & PCIE_PHYLINKUP) || !(val & PCIE_DL_ACTIVE)) {
708 dev_err(dev, "PHY or data link is INACTIVE!\n");
709 return -ENODEV;
710 }
711
712
713 iproc_pci_raw_config_read32(pcie, 0, PCI_HEADER_TYPE, 1, &hdr_type);
714 if ((hdr_type & 0x7f) != PCI_HEADER_TYPE_BRIDGE) {
715 dev_err(dev, "in EP mode, hdr=%#02x\n", hdr_type);
716 return -EFAULT;
717 }
718
719
720#define PCI_BRIDGE_CTRL_REG_OFFSET 0x43c
721#define PCI_CLASS_BRIDGE_MASK 0xffff00
722#define PCI_CLASS_BRIDGE_SHIFT 8
723 iproc_pci_raw_config_read32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
724 4, &class);
725 class &= ~PCI_CLASS_BRIDGE_MASK;
726 class |= (PCI_CLASS_BRIDGE_PCI << PCI_CLASS_BRIDGE_SHIFT);
727 iproc_pci_raw_config_write32(pcie, 0, PCI_BRIDGE_CTRL_REG_OFFSET,
728 4, class);
729
730
731 iproc_pci_raw_config_read32(pcie, 0, IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
732 2, &link_status);
733 if (link_status & PCI_EXP_LNKSTA_NLW)
734 link_is_active = true;
735
736 if (!link_is_active) {
737
738#define PCI_TARGET_LINK_SPEED_MASK 0xf
739#define PCI_TARGET_LINK_SPEED_GEN2 0x2
740#define PCI_TARGET_LINK_SPEED_GEN1 0x1
741 iproc_pci_raw_config_read32(pcie, 0,
742 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
743 4, &link_ctrl);
744 if ((link_ctrl & PCI_TARGET_LINK_SPEED_MASK) ==
745 PCI_TARGET_LINK_SPEED_GEN2) {
746 link_ctrl &= ~PCI_TARGET_LINK_SPEED_MASK;
747 link_ctrl |= PCI_TARGET_LINK_SPEED_GEN1;
748 iproc_pci_raw_config_write32(pcie, 0,
749 IPROC_PCI_EXP_CAP + PCI_EXP_LNKCTL2,
750 4, link_ctrl);
751 msleep(100);
752
753 iproc_pci_raw_config_read32(pcie, 0,
754 IPROC_PCI_EXP_CAP + PCI_EXP_LNKSTA,
755 2, &link_status);
756 if (link_status & PCI_EXP_LNKSTA_NLW)
757 link_is_active = true;
758 }
759 }
760
761 dev_info(dev, "link: %s\n", link_is_active ? "UP" : "DOWN");
762
763 return link_is_active ? 0 : -ENODEV;
764}
765
766static void iproc_pcie_enable(struct iproc_pcie *pcie)
767{
768 iproc_pcie_write_reg(pcie, IPROC_PCIE_INTX_EN, SYS_RC_INTX_MASK);
769}
770
771static inline bool iproc_pcie_ob_is_valid(struct iproc_pcie *pcie,
772 int window_idx)
773{
774 u32 val;
775
776 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_OARR0, window_idx));
777
778 return !!(val & OARR_VALID);
779}
780
781static inline int iproc_pcie_ob_write(struct iproc_pcie *pcie, int window_idx,
782 int size_idx, u64 axi_addr, u64 pci_addr)
783{
784 struct device *dev = pcie->dev;
785 u16 oarr_offset, omap_offset;
786
787
788
789
790
791 oarr_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OARR0,
792 window_idx));
793 omap_offset = iproc_pcie_reg_offset(pcie, MAP_REG(IPROC_PCIE_OMAP0,
794 window_idx));
795 if (iproc_pcie_reg_is_invalid(oarr_offset) ||
796 iproc_pcie_reg_is_invalid(omap_offset))
797 return -EINVAL;
798
799
800
801
802
803 writel(lower_32_bits(axi_addr) | (size_idx << OARR_SIZE_CFG_SHIFT) |
804 OARR_VALID, pcie->base + oarr_offset);
805 writel(upper_32_bits(axi_addr), pcie->base + oarr_offset + 4);
806
807
808 writel(lower_32_bits(pci_addr), pcie->base + omap_offset);
809 writel(upper_32_bits(pci_addr), pcie->base + omap_offset + 4);
810
811 dev_info(dev, "ob window [%d]: offset 0x%x axi %pap pci %pap\n",
812 window_idx, oarr_offset, &axi_addr, &pci_addr);
813 dev_info(dev, "oarr lo 0x%x oarr hi 0x%x\n",
814 readl(pcie->base + oarr_offset),
815 readl(pcie->base + oarr_offset + 4));
816 dev_info(dev, "omap lo 0x%x omap hi 0x%x\n",
817 readl(pcie->base + omap_offset),
818 readl(pcie->base + omap_offset + 4));
819
820 return 0;
821}
822
823
824
825
826
827
828
829
830
831
832
833
834static int iproc_pcie_setup_ob(struct iproc_pcie *pcie, u64 axi_addr,
835 u64 pci_addr, resource_size_t size)
836{
837 struct iproc_pcie_ob *ob = &pcie->ob;
838 struct device *dev = pcie->dev;
839 int ret = -EINVAL, window_idx, size_idx;
840
841 if (axi_addr < ob->axi_offset) {
842 dev_err(dev, "axi address %pap less than offset %pap\n",
843 &axi_addr, &ob->axi_offset);
844 return -EINVAL;
845 }
846
847
848
849
850
851 axi_addr -= ob->axi_offset;
852
853
854 for (window_idx = ob->nr_windows - 1; window_idx >= 0; window_idx--) {
855 const struct iproc_pcie_ob_map *ob_map =
856 &pcie->ob_map[window_idx];
857
858
859
860
861
862 if (iproc_pcie_ob_is_valid(pcie, window_idx))
863 continue;
864
865
866
867
868
869
870 for (size_idx = ob_map->nr_sizes - 1; size_idx >= 0;
871 size_idx--) {
872 resource_size_t window_size =
873 ob_map->window_sizes[size_idx] * SZ_1M;
874
875 if (size < window_size)
876 continue;
877
878 if (!IS_ALIGNED(axi_addr, window_size) ||
879 !IS_ALIGNED(pci_addr, window_size)) {
880 dev_err(dev,
881 "axi %pap or pci %pap not aligned\n",
882 &axi_addr, &pci_addr);
883 return -EINVAL;
884 }
885
886
887
888
889
890 ret = iproc_pcie_ob_write(pcie, window_idx, size_idx,
891 axi_addr, pci_addr);
892 if (ret)
893 goto err_ob;
894
895 size -= window_size;
896 if (size == 0)
897 return 0;
898
899
900
901
902
903
904 axi_addr += window_size;
905 pci_addr += window_size;
906 break;
907 }
908 }
909
910err_ob:
911 dev_err(dev, "unable to configure outbound mapping\n");
912 dev_err(dev,
913 "axi %pap, axi offset %pap, pci %pap, res size %pap\n",
914 &axi_addr, &ob->axi_offset, &pci_addr, &size);
915
916 return ret;
917}
918
919static int iproc_pcie_map_ranges(struct iproc_pcie *pcie,
920 struct list_head *resources)
921{
922 struct device *dev = pcie->dev;
923 struct resource_entry *window;
924 int ret;
925
926 resource_list_for_each_entry(window, resources) {
927 struct resource *res = window->res;
928 u64 res_type = resource_type(res);
929
930 switch (res_type) {
931 case IORESOURCE_IO:
932 case IORESOURCE_BUS:
933 break;
934 case IORESOURCE_MEM:
935 ret = iproc_pcie_setup_ob(pcie, res->start,
936 res->start - window->offset,
937 resource_size(res));
938 if (ret)
939 return ret;
940 break;
941 default:
942 dev_err(dev, "invalid resource %pR\n", res);
943 return -EINVAL;
944 }
945 }
946
947 return 0;
948}
949
950static inline bool iproc_pcie_ib_is_in_use(struct iproc_pcie *pcie,
951 int region_idx)
952{
953 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
954 u32 val;
955
956 val = iproc_pcie_read_reg(pcie, MAP_REG(IPROC_PCIE_IARR0, region_idx));
957
958 return !!(val & (BIT(ib_map->nr_sizes) - 1));
959}
960
961static inline bool iproc_pcie_ib_check_type(const struct iproc_pcie_ib_map *ib_map,
962 enum iproc_pcie_ib_map_type type)
963{
964 return !!(ib_map->type == type);
965}
966
967static int iproc_pcie_ib_write(struct iproc_pcie *pcie, int region_idx,
968 int size_idx, int nr_windows, u64 axi_addr,
969 u64 pci_addr, resource_size_t size)
970{
971 struct device *dev = pcie->dev;
972 const struct iproc_pcie_ib_map *ib_map = &pcie->ib_map[region_idx];
973 u16 iarr_offset, imap_offset;
974 u32 val;
975 int window_idx;
976
977 iarr_offset = iproc_pcie_reg_offset(pcie,
978 MAP_REG(IPROC_PCIE_IARR0, region_idx));
979 imap_offset = iproc_pcie_reg_offset(pcie,
980 MAP_REG(IPROC_PCIE_IMAP0, region_idx));
981 if (iproc_pcie_reg_is_invalid(iarr_offset) ||
982 iproc_pcie_reg_is_invalid(imap_offset))
983 return -EINVAL;
984
985 dev_info(dev, "ib region [%d]: offset 0x%x axi %pap pci %pap\n",
986 region_idx, iarr_offset, &axi_addr, &pci_addr);
987
988
989
990
991
992 writel(lower_32_bits(pci_addr) | BIT(size_idx),
993 pcie->base + iarr_offset);
994 writel(upper_32_bits(pci_addr), pcie->base + iarr_offset + 4);
995
996 dev_info(dev, "iarr lo 0x%x iarr hi 0x%x\n",
997 readl(pcie->base + iarr_offset),
998 readl(pcie->base + iarr_offset + 4));
999
1000
1001
1002
1003
1004 size >>= ilog2(nr_windows);
1005 for (window_idx = 0; window_idx < nr_windows; window_idx++) {
1006 val = readl(pcie->base + imap_offset);
1007 val |= lower_32_bits(axi_addr) | IMAP_VALID;
1008 writel(val, pcie->base + imap_offset);
1009 writel(upper_32_bits(axi_addr),
1010 pcie->base + imap_offset + ib_map->imap_addr_offset);
1011
1012 dev_info(dev, "imap window [%d] lo 0x%x hi 0x%x\n",
1013 window_idx, readl(pcie->base + imap_offset),
1014 readl(pcie->base + imap_offset +
1015 ib_map->imap_addr_offset));
1016
1017 imap_offset += ib_map->imap_window_offset;
1018 axi_addr += size;
1019 }
1020
1021 return 0;
1022}
1023
1024static int iproc_pcie_setup_ib(struct iproc_pcie *pcie,
1025 struct of_pci_range *range,
1026 enum iproc_pcie_ib_map_type type)
1027{
1028 struct device *dev = pcie->dev;
1029 struct iproc_pcie_ib *ib = &pcie->ib;
1030 int ret;
1031 unsigned int region_idx, size_idx;
1032 u64 axi_addr = range->cpu_addr, pci_addr = range->pci_addr;
1033 resource_size_t size = range->size;
1034
1035
1036 for (region_idx = 0; region_idx < ib->nr_regions; region_idx++) {
1037 const struct iproc_pcie_ib_map *ib_map =
1038 &pcie->ib_map[region_idx];
1039
1040
1041
1042
1043
1044 if (iproc_pcie_ib_is_in_use(pcie, region_idx) ||
1045 !iproc_pcie_ib_check_type(ib_map, type))
1046 continue;
1047
1048
1049 for (size_idx = 0; size_idx < ib_map->nr_sizes; size_idx++) {
1050 resource_size_t region_size =
1051 ib_map->region_sizes[size_idx] * ib_map->size_unit;
1052
1053 if (size != region_size)
1054 continue;
1055
1056 if (!IS_ALIGNED(axi_addr, region_size) ||
1057 !IS_ALIGNED(pci_addr, region_size)) {
1058 dev_err(dev,
1059 "axi %pap or pci %pap not aligned\n",
1060 &axi_addr, &pci_addr);
1061 return -EINVAL;
1062 }
1063
1064
1065 ret = iproc_pcie_ib_write(pcie, region_idx, size_idx,
1066 ib_map->nr_windows, axi_addr,
1067 pci_addr, size);
1068 if (ret)
1069 goto err_ib;
1070 else
1071 return 0;
1072
1073 }
1074 }
1075 ret = -EINVAL;
1076
1077err_ib:
1078 dev_err(dev, "unable to configure inbound mapping\n");
1079 dev_err(dev, "axi %pap, pci %pap, res size %pap\n",
1080 &axi_addr, &pci_addr, &size);
1081
1082 return ret;
1083}
1084
1085static int iproc_pcie_map_dma_ranges(struct iproc_pcie *pcie)
1086{
1087 struct of_pci_range range;
1088 struct of_pci_range_parser parser;
1089 int ret;
1090
1091
1092 ret = of_pci_dma_range_parser_init(&parser, pcie->dev->of_node);
1093 if (ret)
1094 return ret;
1095
1096 for_each_of_pci_range(&parser, &range) {
1097
1098 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_MEM);
1099 if (ret)
1100 return ret;
1101 }
1102
1103 return 0;
1104}
1105
1106static int iproce_pcie_get_msi(struct iproc_pcie *pcie,
1107 struct device_node *msi_node,
1108 u64 *msi_addr)
1109{
1110 struct device *dev = pcie->dev;
1111 int ret;
1112 struct resource res;
1113
1114
1115
1116
1117
1118 if (!of_device_is_compatible(msi_node, "arm,gic-v3-its")) {
1119 dev_err(dev, "unable to find compatible MSI controller\n");
1120 return -ENODEV;
1121 }
1122
1123
1124 ret = of_address_to_resource(msi_node, 0, &res);
1125 if (ret < 0) {
1126 dev_err(dev, "unable to obtain MSI controller resources\n");
1127 return ret;
1128 }
1129
1130 *msi_addr = res.start + GITS_TRANSLATER;
1131 return 0;
1132}
1133
1134static int iproc_pcie_paxb_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1135{
1136 int ret;
1137 struct of_pci_range range;
1138
1139 memset(&range, 0, sizeof(range));
1140 range.size = SZ_32K;
1141 range.pci_addr = range.cpu_addr = msi_addr & ~(range.size - 1);
1142
1143 ret = iproc_pcie_setup_ib(pcie, &range, IPROC_PCIE_IB_MAP_IO);
1144 return ret;
1145}
1146
1147static void iproc_pcie_paxc_v2_msi_steer(struct iproc_pcie *pcie, u64 msi_addr)
1148{
1149 u32 val;
1150
1151
1152
1153
1154
1155
1156
1157 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_BASE_ADDR,
1158 (u32)(msi_addr >> 13));
1159
1160
1161 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_WINDOW_SIZE, 0);
1162
1163
1164 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_GIC_MODE);
1165 val |= GIC_V3_CFG;
1166 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_GIC_MODE, val);
1167
1168
1169
1170
1171
1172 msi_addr >>= 2;
1173 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_HI,
1174 upper_32_bits(msi_addr));
1175 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_ADDR_LO,
1176 lower_32_bits(msi_addr));
1177
1178
1179 val = iproc_pcie_read_reg(pcie, IPROC_PCIE_MSI_EN_CFG);
1180 val |= MSI_ENABLE_CFG;
1181 iproc_pcie_write_reg(pcie, IPROC_PCIE_MSI_EN_CFG, val);
1182}
1183
1184static int iproc_pcie_msi_steer(struct iproc_pcie *pcie,
1185 struct device_node *msi_node)
1186{
1187 struct device *dev = pcie->dev;
1188 int ret;
1189 u64 msi_addr;
1190
1191 ret = iproce_pcie_get_msi(pcie, msi_node, &msi_addr);
1192 if (ret < 0) {
1193 dev_err(dev, "msi steering failed\n");
1194 return ret;
1195 }
1196
1197 switch (pcie->type) {
1198 case IPROC_PCIE_PAXB_V2:
1199 ret = iproc_pcie_paxb_v2_msi_steer(pcie, msi_addr);
1200 if (ret)
1201 return ret;
1202 break;
1203 case IPROC_PCIE_PAXC_V2:
1204 iproc_pcie_paxc_v2_msi_steer(pcie, msi_addr);
1205 break;
1206 default:
1207 return -EINVAL;
1208 }
1209
1210 return 0;
1211}
1212
1213static int iproc_pcie_msi_enable(struct iproc_pcie *pcie)
1214{
1215 struct device_node *msi_node;
1216 int ret;
1217
1218
1219
1220
1221
1222
1223 msi_node = of_parse_phandle(pcie->dev->of_node, "msi-parent", 0);
1224 if (!msi_node) {
1225 const __be32 *msi_map = NULL;
1226 int len;
1227 u32 phandle;
1228
1229 msi_map = of_get_property(pcie->dev->of_node, "msi-map", &len);
1230 if (!msi_map)
1231 return -ENODEV;
1232
1233 phandle = be32_to_cpup(msi_map + 1);
1234 msi_node = of_find_node_by_phandle(phandle);
1235 if (!msi_node)
1236 return -ENODEV;
1237 }
1238
1239
1240
1241
1242
1243
1244 if (pcie->need_msi_steer) {
1245 ret = iproc_pcie_msi_steer(pcie, msi_node);
1246 if (ret)
1247 return ret;
1248 }
1249
1250
1251
1252
1253
1254 return iproc_msi_init(pcie, msi_node);
1255}
1256
1257static void iproc_pcie_msi_disable(struct iproc_pcie *pcie)
1258{
1259 iproc_msi_exit(pcie);
1260}
1261
1262static int iproc_pcie_rev_init(struct iproc_pcie *pcie)
1263{
1264 struct device *dev = pcie->dev;
1265 unsigned int reg_idx;
1266 const u16 *regs;
1267
1268 switch (pcie->type) {
1269 case IPROC_PCIE_PAXB_BCMA:
1270 regs = iproc_pcie_reg_paxb_bcma;
1271 break;
1272 case IPROC_PCIE_PAXB:
1273 regs = iproc_pcie_reg_paxb;
1274 pcie->has_apb_err_disable = true;
1275 if (pcie->need_ob_cfg) {
1276 pcie->ob_map = paxb_ob_map;
1277 pcie->ob.nr_windows = ARRAY_SIZE(paxb_ob_map);
1278 }
1279 break;
1280 case IPROC_PCIE_PAXB_V2:
1281 regs = iproc_pcie_reg_paxb_v2;
1282 pcie->has_apb_err_disable = true;
1283 if (pcie->need_ob_cfg) {
1284 pcie->ob_map = paxb_v2_ob_map;
1285 pcie->ob.nr_windows = ARRAY_SIZE(paxb_v2_ob_map);
1286 }
1287 pcie->ib.nr_regions = ARRAY_SIZE(paxb_v2_ib_map);
1288 pcie->ib_map = paxb_v2_ib_map;
1289 pcie->need_msi_steer = true;
1290 dev_warn(dev, "reads of config registers that contain %#x return incorrect data\n",
1291 CFG_RETRY_STATUS);
1292 break;
1293 case IPROC_PCIE_PAXC:
1294 regs = iproc_pcie_reg_paxc;
1295 pcie->ep_is_internal = true;
1296 break;
1297 case IPROC_PCIE_PAXC_V2:
1298 regs = iproc_pcie_reg_paxc_v2;
1299 pcie->ep_is_internal = true;
1300 pcie->need_msi_steer = true;
1301 break;
1302 default:
1303 dev_err(dev, "incompatible iProc PCIe interface\n");
1304 return -EINVAL;
1305 }
1306
1307 pcie->reg_offsets = devm_kcalloc(dev, IPROC_PCIE_MAX_NUM_REG,
1308 sizeof(*pcie->reg_offsets),
1309 GFP_KERNEL);
1310 if (!pcie->reg_offsets)
1311 return -ENOMEM;
1312
1313
1314 pcie->reg_offsets[0] = (pcie->type == IPROC_PCIE_PAXC_V2) ?
1315 IPROC_PCIE_REG_INVALID : regs[0];
1316 for (reg_idx = 1; reg_idx < IPROC_PCIE_MAX_NUM_REG; reg_idx++)
1317 pcie->reg_offsets[reg_idx] = regs[reg_idx] ?
1318 regs[reg_idx] : IPROC_PCIE_REG_INVALID;
1319
1320 return 0;
1321}
1322
1323int iproc_pcie_setup(struct iproc_pcie *pcie, struct list_head *res)
1324{
1325 struct device *dev;
1326 int ret;
1327 struct pci_bus *child;
1328 struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);
1329
1330 dev = pcie->dev;
1331
1332 ret = iproc_pcie_rev_init(pcie);
1333 if (ret) {
1334 dev_err(dev, "unable to initialize controller parameters\n");
1335 return ret;
1336 }
1337
1338 ret = devm_request_pci_bus_resources(dev, res);
1339 if (ret)
1340 return ret;
1341
1342 ret = phy_init(pcie->phy);
1343 if (ret) {
1344 dev_err(dev, "unable to initialize PCIe PHY\n");
1345 return ret;
1346 }
1347
1348 ret = phy_power_on(pcie->phy);
1349 if (ret) {
1350 dev_err(dev, "unable to power on PCIe PHY\n");
1351 goto err_exit_phy;
1352 }
1353
1354 iproc_pcie_perst_ctrl(pcie, true);
1355 iproc_pcie_perst_ctrl(pcie, false);
1356
1357 if (pcie->need_ob_cfg) {
1358 ret = iproc_pcie_map_ranges(pcie, res);
1359 if (ret) {
1360 dev_err(dev, "map failed\n");
1361 goto err_power_off_phy;
1362 }
1363 }
1364
1365 if (pcie->need_ib_cfg) {
1366 ret = iproc_pcie_map_dma_ranges(pcie);
1367 if (ret && ret != -ENOENT)
1368 goto err_power_off_phy;
1369 }
1370
1371 ret = iproc_pcie_check_link(pcie);
1372 if (ret) {
1373 dev_err(dev, "no PCIe EP device detected\n");
1374 goto err_power_off_phy;
1375 }
1376
1377 iproc_pcie_enable(pcie);
1378
1379 if (IS_ENABLED(CONFIG_PCI_MSI))
1380 if (iproc_pcie_msi_enable(pcie))
1381 dev_info(dev, "not using iProc MSI\n");
1382
1383 list_splice_init(res, &host->windows);
1384 host->busnr = 0;
1385 host->dev.parent = dev;
1386 host->ops = &iproc_pcie_ops;
1387 host->sysdata = pcie;
1388 host->map_irq = pcie->map_irq;
1389 host->swizzle_irq = pci_common_swizzle;
1390
1391 ret = pci_scan_root_bus_bridge(host);
1392 if (ret < 0) {
1393 dev_err(dev, "failed to scan host: %d\n", ret);
1394 goto err_power_off_phy;
1395 }
1396
1397 pci_assign_unassigned_bus_resources(host->bus);
1398
1399 pcie->root_bus = host->bus;
1400
1401 list_for_each_entry(child, &host->bus->children, node)
1402 pcie_bus_configure_settings(child);
1403
1404 pci_bus_add_devices(host->bus);
1405
1406 return 0;
1407
1408err_power_off_phy:
1409 phy_power_off(pcie->phy);
1410err_exit_phy:
1411 phy_exit(pcie->phy);
1412 return ret;
1413}
1414EXPORT_SYMBOL(iproc_pcie_setup);
1415
1416int iproc_pcie_remove(struct iproc_pcie *pcie)
1417{
1418 pci_stop_root_bus(pcie->root_bus);
1419 pci_remove_root_bus(pcie->root_bus);
1420
1421 iproc_pcie_msi_disable(pcie);
1422
1423 phy_power_off(pcie->phy);
1424 phy_exit(pcie->phy);
1425
1426 return 0;
1427}
1428EXPORT_SYMBOL(iproc_pcie_remove);
1429
1430MODULE_AUTHOR("Ray Jui <rjui@broadcom.com>");
1431MODULE_DESCRIPTION("Broadcom iPROC PCIe common driver");
1432MODULE_LICENSE("GPL v2");
1433