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15#include <linux/types.h>
16#include <linux/kernel.h>
17#include <linux/export.h>
18#include <linux/pci.h>
19#include <linux/init.h>
20#include <linux/delay.h>
21#include <linux/acpi.h>
22#include <linux/dmi.h>
23#include <linux/pci-aspm.h>
24#include <linux/ioport.h>
25#include <linux/sched.h>
26#include <linux/ktime.h>
27#include <linux/mm.h>
28#include <linux/platform_data/x86/apple.h>
29#include <linux/pm_runtime.h>
30#include <asm/dma.h>
31#include "pci.h"
32
33
34
35
36
37
38
39static void quirk_mmio_always_on(struct pci_dev *dev)
40{
41 dev->mmio_always_on = 1;
42}
43DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
44 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
45
46
47
48
49
50static void quirk_mellanox_tavor(struct pci_dev *dev)
51{
52 dev->broken_parity_status = 1;
53}
54DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
55DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
56
57
58
59static void quirk_passive_release(struct pci_dev *dev)
60{
61 struct pci_dev *d = NULL;
62 unsigned char dlc;
63
64
65
66 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
67 pci_read_config_byte(d, 0x82, &dlc);
68 if (!(dlc & 1<<1)) {
69 pci_info(d, "PIIX3: Enabling Passive Release\n");
70 dlc |= 1<<1;
71 pci_write_config_byte(d, 0x82, dlc);
72 }
73 }
74}
75DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
76DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
77
78
79
80
81
82
83
84
85static void quirk_isa_dma_hangs(struct pci_dev *dev)
86{
87 if (!isa_dma_bridge_buggy) {
88 isa_dma_bridge_buggy = 1;
89 pci_info(dev, "Activating ISA DMA hang workarounds\n");
90 }
91}
92
93
94
95
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
97DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
98DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
101DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
102DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
103
104
105
106
107
108static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
109{
110 u32 pmbase;
111 u16 pm1a;
112
113 pci_read_config_dword(dev, 0x40, &pmbase);
114 pmbase = pmbase & 0xff80;
115 pm1a = inw(pmbase);
116
117 if (pm1a & 0x10) {
118 pci_info(dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
119 outw(0x10, pmbase);
120 }
121}
122DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
123
124
125
126
127static void quirk_nopcipci(struct pci_dev *dev)
128{
129 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
130 pci_info(dev, "Disabling direct PCI/PCI transfers\n");
131 pci_pci_problems |= PCIPCI_FAIL;
132 }
133}
134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
135DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
136
137static void quirk_nopciamd(struct pci_dev *dev)
138{
139 u8 rev;
140 pci_read_config_byte(dev, 0x08, &rev);
141 if (rev == 0x13) {
142
143 pci_info(dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
144 pci_pci_problems |= PCIAGP_FAIL;
145 }
146}
147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
148
149
150
151
152static void quirk_triton(struct pci_dev *dev)
153{
154 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
155 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
156 pci_pci_problems |= PCIPCI_TRITON;
157 }
158}
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
163
164
165
166
167
168
169
170
171
172
173
174static void quirk_vialatency(struct pci_dev *dev)
175{
176 struct pci_dev *p;
177 u8 busarb;
178
179
180
181 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
182 if (p != NULL) {
183
184
185 if (p->revision < 0x40 || p->revision > 0x42)
186 goto exit;
187 } else {
188 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
189 if (p == NULL)
190 goto exit;
191
192 if (p->revision < 0x10 || p->revision > 0x12)
193 goto exit;
194 }
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209 pci_read_config_byte(dev, 0x76, &busarb);
210
211
212 busarb &= ~(1<<5);
213 busarb |= (1<<4);
214 pci_write_config_byte(dev, 0x76, busarb);
215 pci_info(dev, "Applying VIA southbridge workaround\n");
216exit:
217 pci_dev_put(p);
218}
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
220DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
222
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
224DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
225DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
226
227
228
229
230static void quirk_viaetbf(struct pci_dev *dev)
231{
232 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
233 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
234 pci_pci_problems |= PCIPCI_VIAETBF;
235 }
236}
237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
238
239static void quirk_vsfx(struct pci_dev *dev)
240{
241 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
242 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
243 pci_pci_problems |= PCIPCI_VSFX;
244 }
245}
246DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
247
248
249
250
251
252
253
254static void quirk_alimagik(struct pci_dev *dev)
255{
256 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
257 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
258 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
259 }
260}
261DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
262DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
263
264
265
266
267
268static void quirk_natoma(struct pci_dev *dev)
269{
270 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
271 pci_info(dev, "Limiting direct PCI/PCI transfers\n");
272 pci_pci_problems |= PCIPCI_NATOMA;
273 }
274}
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
279DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
280DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
281
282
283
284
285
286static void quirk_citrine(struct pci_dev *dev)
287{
288 dev->cfg_size = 0xA0;
289}
290DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
291
292
293
294
295
296static void quirk_nfp6000(struct pci_dev *dev)
297{
298 dev->cfg_size = 0x600;
299}
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
301DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
302DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
303
304
305static void quirk_extend_bar_to_page(struct pci_dev *dev)
306{
307 int i;
308
309 for (i = 0; i <= PCI_STD_RESOURCE_END; i++) {
310 struct resource *r = &dev->resource[i];
311
312 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
313 r->end = PAGE_SIZE - 1;
314 r->start = 0;
315 r->flags |= IORESOURCE_UNSET;
316 pci_info(dev, "expanded BAR %d to page size: %pR\n",
317 i, r);
318 }
319 }
320}
321DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
322
323
324
325
326
327static void quirk_s3_64M(struct pci_dev *dev)
328{
329 struct resource *r = &dev->resource[0];
330
331 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
332 r->flags |= IORESOURCE_UNSET;
333 r->start = 0;
334 r->end = 0x3ffffff;
335 }
336}
337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
339
340static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
341 const char *name)
342{
343 u32 region;
344 struct pci_bus_region bus_region;
345 struct resource *res = dev->resource + pos;
346
347 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), ®ion);
348
349 if (!region)
350 return;
351
352 res->name = pci_name(dev);
353 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
354 res->flags |=
355 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
356 region &= ~(size - 1);
357
358
359 bus_region.start = region;
360 bus_region.end = region + size - 1;
361 pcibios_bus_to_resource(dev->bus, res, &bus_region);
362
363 pci_info(dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
364 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
365}
366
367
368
369
370
371
372
373
374
375
376static void quirk_cs5536_vsa(struct pci_dev *dev)
377{
378 static char *name = "CS5536 ISA bridge";
379
380 if (pci_resource_len(dev, 0) != 8) {
381 quirk_io(dev, 0, 8, name);
382 quirk_io(dev, 1, 256, name);
383 quirk_io(dev, 2, 64, name);
384 pci_info(dev, "%s bug detected (incorrect header); workaround applied\n",
385 name);
386 }
387}
388DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
389
390static void quirk_io_region(struct pci_dev *dev, int port,
391 unsigned size, int nr, const char *name)
392{
393 u16 region;
394 struct pci_bus_region bus_region;
395 struct resource *res = dev->resource + nr;
396
397 pci_read_config_word(dev, port, ®ion);
398 region &= ~(size - 1);
399
400 if (!region)
401 return;
402
403 res->name = pci_name(dev);
404 res->flags = IORESOURCE_IO;
405
406
407 bus_region.start = region;
408 bus_region.end = region + size - 1;
409 pcibios_bus_to_resource(dev->bus, res, &bus_region);
410
411 if (!pci_claim_resource(dev, nr))
412 pci_info(dev, "quirk: %pR claimed by %s\n", res, name);
413}
414
415
416
417
418
419static void quirk_ati_exploding_mce(struct pci_dev *dev)
420{
421 pci_info(dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
422
423 request_region(0x3b0, 0x0C, "RadeonIGP");
424 request_region(0x3d3, 0x01, "RadeonIGP");
425}
426DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
427
428
429
430
431
432
433
434
435
436
437
438static void quirk_amd_nl_class(struct pci_dev *pdev)
439{
440 u32 class = pdev->class;
441
442
443 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
444 pci_info(pdev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
445 class, pdev->class);
446}
447DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
448 quirk_amd_nl_class);
449
450
451
452
453
454
455
456
457
458
459
460
461static void quirk_ali7101_acpi(struct pci_dev *dev)
462{
463 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
464 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
465}
466DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
467
468static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
469{
470 u32 devres;
471 u32 mask, size, base;
472
473 pci_read_config_dword(dev, port, &devres);
474 if ((devres & enable) != enable)
475 return;
476 mask = (devres >> 16) & 15;
477 base = devres & 0xffff;
478 size = 16;
479 for (;;) {
480 unsigned bit = size >> 1;
481 if ((bit & mask) == bit)
482 break;
483 size = bit;
484 }
485
486
487
488
489
490 base &= -size;
491 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base + size - 1);
492}
493
494static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
495{
496 u32 devres;
497 u32 mask, size, base;
498
499 pci_read_config_dword(dev, port, &devres);
500 if ((devres & enable) != enable)
501 return;
502 base = devres & 0xffff0000;
503 mask = (devres & 0x3f) << 16;
504 size = 128 << 16;
505 for (;;) {
506 unsigned bit = size >> 1;
507 if ((bit & mask) == bit)
508 break;
509 size = bit;
510 }
511
512
513
514
515 base &= -size;
516 pci_info(dev, "%s MMIO at %04x-%04x\n", name, base, base + size - 1);
517}
518
519
520
521
522
523
524
525static void quirk_piix4_acpi(struct pci_dev *dev)
526{
527 u32 res_a;
528
529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
531
532
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538
539
540
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
552}
553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
555
556#define ICH_PMBASE 0x40
557#define ICH_ACPI_CNTL 0x44
558#define ICH4_ACPI_EN 0x10
559#define ICH6_ACPI_EN 0x80
560#define ICH4_GPIOBASE 0x58
561#define ICH4_GPIO_CNTL 0x5c
562#define ICH4_GPIO_EN 0x10
563#define ICH6_GPIOBASE 0x48
564#define ICH6_GPIO_CNTL 0x4c
565#define ICH6_GPIO_EN 0x10
566
567
568
569
570
571
572static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
573{
574 u8 enable;
575
576
577
578
579
580
581
582
583
584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
588
589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
593}
594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
604
605static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
606{
607 u8 enable;
608
609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
613
614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
618}
619
620static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
621{
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632
633
634
635
636
637
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644
645 pci_info(dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646}
647
648static void quirk_ich6_lpc(struct pci_dev *dev)
649{
650
651 ich6_lpc_acpi_gpio(dev);
652
653
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656}
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
660static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
661{
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667
668 if (!(val & 1))
669 return;
670
671
672
673
674
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679
680 pci_info(dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681}
682
683
684static void quirk_ich7_lpc(struct pci_dev *dev)
685{
686
687 ich6_lpc_acpi_gpio(dev);
688
689
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694}
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
708
709
710
711
712
713static void quirk_vt82c586_acpi(struct pci_dev *dev)
714{
715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
718}
719DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
720
721
722
723
724
725
726
727static void quirk_vt82c686_acpi(struct pci_dev *dev)
728{
729 quirk_vt82c586_acpi(dev);
730
731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
733
734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
735}
736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
737
738
739
740
741
742
743static void quirk_vt8235_acpi(struct pci_dev *dev)
744{
745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
747}
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
750
751
752
753
754static void quirk_xio2000a(struct pci_dev *dev)
755{
756 struct pci_dev *pdev;
757 u16 command;
758
759 pci_warn(dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
768
769#ifdef CONFIG_X86_IO_APIC
770
771#include <asm/io_apic.h>
772
773
774
775
776
777
778
779
780static void quirk_via_ioapic(struct pci_dev *dev)
781{
782 u8 tmp;
783
784 if (nr_ioapics < 1)
785 tmp = 0;
786 else
787 tmp = 0x1f;
788
789 pci_info(dev, "%sbling VIA external APIC routing\n",
790 tmp == 0 ? "Disa" : "Ena");
791
792
793 pci_write_config_byte(dev, 0x58, tmp);
794}
795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
796DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
797
798
799
800
801
802
803
804static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
805{
806 u8 misc_control2;
807#define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
811 pci_info(dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814}
815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
816DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
817
818
819
820
821
822
823
824
825
826
827static void quirk_amd_ioapic(struct pci_dev *dev)
828{
829 if (dev->revision >= 0x02) {
830 pci_warn(dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 pci_warn(dev, " : booting with the \"noapic\" option\n");
832 }
833}
834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
835#endif
836
837#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
838
839static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
840{
841
842 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn;
844}
845DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
846#endif
847
848
849
850
851
852static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
853{
854 if (dev->subordinate && dev->revision <= 0x12) {
855 pci_info(dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
856 dev->revision);
857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
858 }
859}
860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
861
862
863
864
865
866
867
868
869
870static void quirk_via_acpi(struct pci_dev *d)
871{
872
873
874
875 u8 irq;
876 pci_read_config_byte(d, 0x42, &irq);
877 irq &= 0xf;
878 if (irq && (irq != 2))
879 d->irq = irq;
880}
881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
883
884
885
886
887
888
889static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
890
891static void quirk_via_bridge(struct pci_dev *dev)
892{
893
894 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686:
896
897
898
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
901 break;
902 case PCI_DEVICE_ID_VIA_8237:
903 case PCI_DEVICE_ID_VIA_8237A:
904 via_vlink_dev_lo = 15;
905 break;
906 case PCI_DEVICE_ID_VIA_8235:
907 via_vlink_dev_lo = 16;
908 break;
909 case PCI_DEVICE_ID_VIA_8231:
910 case PCI_DEVICE_ID_VIA_8233_0:
911 case PCI_DEVICE_ID_VIA_8233A:
912 case PCI_DEVICE_ID_VIA_8233C_0:
913 via_vlink_dev_lo = 17;
914 break;
915 }
916}
917DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
918DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
919DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
920DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
922DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939static void quirk_via_vlink(struct pci_dev *dev)
940{
941 u8 irq, new_irq;
942
943
944 if (via_vlink_dev_lo == -1)
945 return;
946
947 new_irq = dev->irq;
948
949
950 if (!new_irq || new_irq > 15)
951 return;
952
953
954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
956 return;
957
958
959
960
961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) {
963 pci_info(dev, "VIA VLink IRQ fixup, from %d to %d\n",
964 irq, new_irq);
965 udelay(15);
966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
967 }
968}
969DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
970
971
972
973
974
975
976
977static void quirk_vt82c598_id(struct pci_dev *dev)
978{
979 pci_write_config_byte(dev, 0xfc, 0);
980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
981}
982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
983
984
985
986
987
988
989
990static void quirk_cardbus_legacy(struct pci_dev *dev)
991{
992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
993}
994DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
996DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
998
999
1000
1001
1002
1003
1004
1005
1006static void quirk_amd_ordering(struct pci_dev *dev)
1007{
1008 u32 pcic;
1009 pci_read_config_dword(dev, 0x4C, &pcic);
1010 if ((pcic & 6) != 6) {
1011 pcic |= 6;
1012 pci_warn(dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
1013 pci_write_config_dword(dev, 0x4C, pcic);
1014 pci_read_config_dword(dev, 0x84, &pcic);
1015 pcic |= (1 << 23);
1016 pci_write_config_dword(dev, 0x84, pcic);
1017 }
1018}
1019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
1021
1022
1023
1024
1025
1026
1027
1028
1029static void quirk_dunord(struct pci_dev *dev)
1030{
1031 struct resource *r = &dev->resource[1];
1032
1033 r->flags |= IORESOURCE_UNSET;
1034 r->start = 0;
1035 r->end = 0xffffff;
1036}
1037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
1038
1039
1040
1041
1042
1043
1044
1045static void quirk_transparent_bridge(struct pci_dev *dev)
1046{
1047 dev->transparent = 1;
1048}
1049DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
1051
1052
1053
1054
1055
1056
1057
1058static void quirk_mediagx_master(struct pci_dev *dev)
1059{
1060 u8 reg;
1061
1062 pci_read_config_byte(dev, 0x41, ®);
1063 if (reg & 2) {
1064 reg &= ~2;
1065 pci_info(dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1066 reg);
1067 pci_write_config_byte(dev, 0x41, reg);
1068 }
1069}
1070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1072
1073
1074
1075
1076
1077
1078static void quirk_disable_pxb(struct pci_dev *pdev)
1079{
1080 u16 config;
1081
1082 if (pdev->revision != 0x04)
1083 return;
1084 pci_read_config_word(pdev, 0x40, &config);
1085 if (config & (1<<6)) {
1086 config &= ~(1<<6);
1087 pci_write_config_word(pdev, 0x40, config);
1088 pci_info(pdev, "C0 revision 450NX. Disabling PCI restreaming\n");
1089 }
1090}
1091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1092DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
1093
1094static void quirk_amd_ide_mode(struct pci_dev *pdev)
1095{
1096
1097 u8 tmp;
1098
1099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1100 if (tmp == 0x01) {
1101 pci_read_config_byte(pdev, 0x40, &tmp);
1102 pci_write_config_byte(pdev, 0x40, tmp|1);
1103 pci_write_config_byte(pdev, 0x9, 1);
1104 pci_write_config_byte(pdev, 0xa, 6);
1105 pci_write_config_byte(pdev, 0x40, tmp);
1106
1107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
1108 pci_info(pdev, "set SATA to AHCI mode\n");
1109 }
1110}
1111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1112DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
1113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
1115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1119
1120
1121
1122
1123static void quirk_svwks_csb5ide(struct pci_dev *pdev)
1124{
1125 u8 prog;
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1127 if (prog & 5) {
1128 prog &= ~5;
1129 pdev->class &= ~5;
1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1131
1132 }
1133}
1134DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
1135
1136
1137
1138
1139static void quirk_ide_samemode(struct pci_dev *pdev)
1140{
1141 u8 prog;
1142
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1144
1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
1146 pci_info(pdev, "IDE mode mismatch; forcing legacy mode\n");
1147 prog &= ~5;
1148 pdev->class &= ~5;
1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
1150 }
1151}
1152DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
1153
1154
1155
1156
1157
1158static void quirk_no_ata_d3(struct pci_dev *pdev)
1159{
1160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
1161}
1162
1163DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1165DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1167
1168DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1170
1171
1172DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1174
1175
1176
1177
1178static void quirk_eisa_bridge(struct pci_dev *dev)
1179{
1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1181}
1182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210static int asus_hides_smbus;
1211
1212static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
1213{
1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
1216 switch (dev->subsystem_device) {
1217 case 0x8025:
1218 case 0x8070:
1219 case 0x8088:
1220 case 0x1626:
1221 asus_hides_smbus = 1;
1222 }
1223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
1224 switch (dev->subsystem_device) {
1225 case 0x80b1:
1226 case 0x80b2:
1227 case 0x8093:
1228 asus_hides_smbus = 1;
1229 }
1230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
1231 switch (dev->subsystem_device) {
1232 case 0x8030:
1233 asus_hides_smbus = 1;
1234 }
1235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
1236 switch (dev->subsystem_device) {
1237 case 0x8070:
1238 asus_hides_smbus = 1;
1239 }
1240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
1241 switch (dev->subsystem_device) {
1242 case 0x80c9:
1243 asus_hides_smbus = 1;
1244 }
1245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
1246 switch (dev->subsystem_device) {
1247 case 0x1751:
1248 case 0x1821:
1249 case 0x1897:
1250 asus_hides_smbus = 1;
1251 }
1252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1253 switch (dev->subsystem_device) {
1254 case 0x184b:
1255 case 0x186a:
1256 asus_hides_smbus = 1;
1257 }
1258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1259 switch (dev->subsystem_device) {
1260 case 0x80f2:
1261 asus_hides_smbus = 1;
1262 }
1263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
1264 switch (dev->subsystem_device) {
1265 case 0x1882:
1266 case 0x1977:
1267 asus_hides_smbus = 1;
1268 }
1269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1271 switch (dev->subsystem_device) {
1272 case 0x088C:
1273 case 0x0890:
1274 asus_hides_smbus = 1;
1275 }
1276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
1277 switch (dev->subsystem_device) {
1278 case 0x12bc:
1279 case 0x12bd:
1280 case 0x006a:
1281 asus_hides_smbus = 1;
1282 }
1283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x12bf:
1286 asus_hides_smbus = 1;
1287 }
1288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1290 switch (dev->subsystem_device) {
1291 case 0xC00C:
1292 asus_hides_smbus = 1;
1293 }
1294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1296 switch (dev->subsystem_device) {
1297 case 0x0058:
1298 asus_hides_smbus = 1;
1299 }
1300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
1301 switch (dev->subsystem_device) {
1302 case 0xB16C:
1303
1304
1305
1306 asus_hides_smbus = 1;
1307 }
1308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
1309 switch (dev->subsystem_device) {
1310 case 0x00b8:
1311 case 0x00b9:
1312 case 0x00ba:
1313
1314
1315
1316
1317
1318 asus_hides_smbus = 1;
1319 }
1320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1321 switch (dev->subsystem_device) {
1322 case 0x001A:
1323
1324
1325
1326 asus_hides_smbus = 1;
1327 }
1328 }
1329}
1330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
1334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
1335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
1340
1341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
1342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
1343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
1344
1345static void asus_hides_smbus_lpc(struct pci_dev *dev)
1346{
1347 u16 val;
1348
1349 if (likely(!asus_hides_smbus))
1350 return;
1351
1352 pci_read_config_word(dev, 0xF2, &val);
1353 if (val & 0x8) {
1354 pci_write_config_word(dev, 0xF2, val & (~0x8));
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8)
1357 pci_info(dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1358 val);
1359 else
1360 pci_info(dev, "Enabled i801 SMBus device\n");
1361 }
1362}
1363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1370DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
1377
1378
1379static void __iomem *asus_rcba_base;
1380static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
1381{
1382 u32 rcba;
1383
1384 if (likely(!asus_hides_smbus))
1385 return;
1386 WARN_ON(asus_rcba_base);
1387
1388 pci_read_config_dword(dev, 0xF0, &rcba);
1389
1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1391 if (asus_rcba_base == NULL)
1392 return;
1393}
1394
1395static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1396{
1397 u32 val;
1398
1399 if (likely(!asus_hides_smbus || !asus_rcba_base))
1400 return;
1401
1402 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418);
1404}
1405
1406static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1407{
1408 if (likely(!asus_hides_smbus || !asus_rcba_base))
1409 return;
1410 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL;
1412 pci_info(dev, "Enabled ICH6/i801 SMBus device\n");
1413}
1414
1415static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1416{
1417 asus_hides_smbus_lpc_ich6_suspend(dev);
1418 asus_hides_smbus_lpc_ich6_resume_early(dev);
1419 asus_hides_smbus_lpc_ich6_resume(dev);
1420}
1421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
1422DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1423DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
1425
1426
1427
1428
1429static void quirk_sis_96x_smbus(struct pci_dev *dev)
1430{
1431 u8 val = 0;
1432 pci_read_config_byte(dev, 0x77, &val);
1433 if (val & 0x10) {
1434 pci_info(dev, "Enabling SiS 96x SMBus\n");
1435 pci_write_config_byte(dev, 0x77, val & ~0x10);
1436 }
1437}
1438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1442DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
1446
1447
1448
1449
1450
1451
1452
1453
1454
1455#define SIS_DETECT_REGISTER 0x40
1456
1457static void quirk_sis_503(struct pci_dev *dev)
1458{
1459 u8 reg;
1460 u16 devid;
1461
1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, ®);
1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1467 return;
1468 }
1469
1470
1471
1472
1473
1474
1475 dev->device = devid;
1476 quirk_sis_96x_smbus(dev);
1477}
1478DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1479DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
1480
1481
1482
1483
1484
1485
1486
1487
1488static void asus_hides_ac97_lpc(struct pci_dev *dev)
1489{
1490 u8 val;
1491 int asus_hides_ac97 = 0;
1492
1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1494 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1495 asus_hides_ac97 = 1;
1496 }
1497
1498 if (!asus_hides_ac97)
1499 return;
1500
1501 pci_read_config_byte(dev, 0x50, &val);
1502 if (val & 0xc0) {
1503 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1504 pci_read_config_byte(dev, 0x50, &val);
1505 if (val & 0xc0)
1506 pci_info(dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1507 val);
1508 else
1509 pci_info(dev, "Enabled onboard AC97/MC97 devices\n");
1510 }
1511}
1512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1513DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
1514
1515#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
1516
1517
1518
1519
1520
1521
1522static void quirk_jmicron_ata(struct pci_dev *pdev)
1523{
1524 u32 conf1, conf5, class;
1525 u8 hdr;
1526
1527
1528 if (PCI_FUNC(pdev->devfn))
1529 return;
1530
1531 pci_read_config_dword(pdev, 0x40, &conf1);
1532 pci_read_config_dword(pdev, 0x80, &conf5);
1533
1534 conf1 &= ~0x00CFF302;
1535 conf5 &= ~(1 << 24);
1536
1537 switch (pdev->device) {
1538 case PCI_DEVICE_ID_JMICRON_JMB360:
1539 case PCI_DEVICE_ID_JMICRON_JMB362:
1540 case PCI_DEVICE_ID_JMICRON_JMB364:
1541
1542 conf1 |= 0x0002A100;
1543 break;
1544
1545 case PCI_DEVICE_ID_JMICRON_JMB365:
1546 case PCI_DEVICE_ID_JMICRON_JMB366:
1547
1548 conf5 |= (1 << 24);
1549
1550 case PCI_DEVICE_ID_JMICRON_JMB361:
1551 case PCI_DEVICE_ID_JMICRON_JMB363:
1552 case PCI_DEVICE_ID_JMICRON_JMB369:
1553
1554
1555 conf1 |= 0x00C2A1B3;
1556 break;
1557
1558 case PCI_DEVICE_ID_JMICRON_JMB368:
1559
1560 conf1 |= 0x00C00000;
1561 break;
1562 }
1563
1564 pci_write_config_dword(pdev, 0x40, conf1);
1565 pci_write_config_dword(pdev, 0x80, conf5);
1566
1567
1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1569 pdev->hdr_type = hdr & 0x7f;
1570 pdev->multifunction = !!(hdr & 0x80);
1571
1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1573 pdev->class = class >> 8;
1574}
1575DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1584DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1585DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
1586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
1587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
1588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
1589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
1592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
1593
1594#endif
1595
1596static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1597{
1598 if (dev->multifunction) {
1599 device_disable_async_suspend(&dev->dev);
1600 pci_info(dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1601 }
1602}
1603DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1604DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1607
1608#ifdef CONFIG_X86_IO_APIC
1609static void quirk_alder_ioapic(struct pci_dev *pdev)
1610{
1611 int i;
1612
1613 if ((pdev->class >> 8) != 0xff00)
1614 return;
1615
1616
1617
1618
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]);
1621
1622
1623
1624 for (i = 1; i < 6; i++)
1625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
1626}
1627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
1628#endif
1629
1630static void quirk_pcie_mch(struct pci_dev *pdev)
1631{
1632 pdev->no_msi = 1;
1633}
1634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
1637
1638DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
1639
1640
1641
1642
1643
1644static void quirk_pcie_pxh(struct pci_dev *dev)
1645{
1646 dev->no_msi = 1;
1647 pci_warn(dev, "PXH quirk detected; SHPC device MSI disabled\n");
1648}
1649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1653DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1654
1655
1656
1657
1658
1659static void quirk_intel_pcie_pm(struct pci_dev *dev)
1660{
1661 pci_pm_d3_delay = 120;
1662 dev->no_d1d2 = 1;
1663}
1664
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
1686
1687static void quirk_radeon_pm(struct pci_dev *dev)
1688{
1689 if (dev->subsystem_vendor == PCI_VENDOR_ID_APPLE &&
1690 dev->subsystem_device == 0x00e2) {
1691 if (dev->d3_delay < 20) {
1692 dev->d3_delay = 20;
1693 pci_info(dev, "extending delay after power-on from D3 to %d msec\n",
1694 dev->d3_delay);
1695 }
1696 }
1697}
1698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x6741, quirk_radeon_pm);
1699
1700#ifdef CONFIG_X86_IO_APIC
1701static int dmi_disable_ioapicreroute(const struct dmi_system_id *d)
1702{
1703 noioapicreroute = 1;
1704 pr_info("%s detected: disable boot interrupt reroute\n", d->ident);
1705
1706 return 0;
1707}
1708
1709static const struct dmi_system_id boot_interrupt_dmi_table[] = {
1710
1711
1712
1713 {
1714 .callback = dmi_disable_ioapicreroute,
1715 .ident = "ASUSTek Computer INC. M2N-LR",
1716 .matches = {
1717 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTek Computer INC."),
1718 DMI_MATCH(DMI_PRODUCT_NAME, "M2N-LR"),
1719 },
1720 },
1721 {}
1722};
1723
1724
1725
1726
1727
1728
1729
1730static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1731{
1732 dmi_check_system(boot_interrupt_dmi_table);
1733 if (noioapicquirk || noioapicreroute)
1734 return;
1735
1736 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
1737 pci_info(dev, "rerouting interrupts for [%04x:%04x]\n",
1738 dev->vendor, dev->device);
1739}
1740DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1742DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1743DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1745DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1746DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1748DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1749DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1750DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1751DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1752DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1753DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1754DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1755DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1756
1757
1758
1759
1760
1761
1762
1763
1764
1765
1766#define INTEL_6300_IOAPIC_ABAR 0x40
1767#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1768
1769static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1770{
1771 u16 pci_config_word;
1772
1773 if (noioapicquirk)
1774 return;
1775
1776 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1777 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1778 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1779
1780 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1781 dev->vendor, dev->device);
1782}
1783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1784DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1785
1786
1787
1788
1789#define BC_HT1000_FEATURE_REG 0x64
1790#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1791#define BC_HT1000_MAP_IDX 0xC00
1792#define BC_HT1000_MAP_DATA 0xC01
1793
1794static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1795{
1796 u32 pci_config_dword;
1797 u8 irq;
1798
1799 if (noioapicquirk)
1800 return;
1801
1802 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1803 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1804 BC_HT1000_PIC_REGS_ENABLE);
1805
1806 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1807 outb(irq, BC_HT1000_MAP_IDX);
1808 outb(0x00, BC_HT1000_MAP_DATA);
1809 }
1810
1811 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1812
1813 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1814 dev->vendor, dev->device);
1815}
1816DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1817DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1818
1819
1820
1821
1822
1823
1824
1825
1826
1827#define AMD_813X_MISC 0x40
1828#define AMD_813X_NOIOAMODE (1<<0)
1829#define AMD_813X_REV_B1 0x12
1830#define AMD_813X_REV_B2 0x13
1831
1832static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1833{
1834 u32 pci_config_dword;
1835
1836 if (noioapicquirk)
1837 return;
1838 if ((dev->revision == AMD_813X_REV_B1) ||
1839 (dev->revision == AMD_813X_REV_B2))
1840 return;
1841
1842 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1843 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1844 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1845
1846 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1847 dev->vendor, dev->device);
1848}
1849DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1850DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1851DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1852DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1853
1854#define AMD_8111_PCI_IRQ_ROUTING 0x56
1855
1856static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1857{
1858 u16 pci_config_word;
1859
1860 if (noioapicquirk)
1861 return;
1862
1863 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1864 if (!pci_config_word) {
1865 pci_info(dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1866 dev->vendor, dev->device);
1867 return;
1868 }
1869 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
1870 pci_info(dev, "disabled boot interrupts on device [%04x:%04x]\n",
1871 dev->vendor, dev->device);
1872}
1873DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1874DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1875#endif
1876
1877
1878
1879
1880
1881
1882static void quirk_tc86c001_ide(struct pci_dev *dev)
1883{
1884 struct resource *r = &dev->resource[0];
1885
1886 if (r->start & 0x8) {
1887 r->flags |= IORESOURCE_UNSET;
1888 r->start = 0;
1889 r->end = 0xf;
1890 }
1891}
1892DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1893 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1894 quirk_tc86c001_ide);
1895
1896
1897
1898
1899
1900
1901
1902
1903static void quirk_plx_pci9050(struct pci_dev *dev)
1904{
1905 unsigned int bar;
1906
1907
1908 if (dev->revision >= 2)
1909 return;
1910 for (bar = 0; bar <= 1; bar++)
1911 if (pci_resource_len(dev, bar) == 0x80 &&
1912 (pci_resource_start(dev, bar) & 0x80)) {
1913 struct resource *r = &dev->resource[bar];
1914 pci_info(dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
1915 bar);
1916 r->flags |= IORESOURCE_UNSET;
1917 r->start = 0;
1918 r->end = 0xff;
1919 }
1920}
1921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1922 quirk_plx_pci9050);
1923
1924
1925
1926
1927
1928
1929
1930
1931
1932DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1933DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
1934
1935static void quirk_netmos(struct pci_dev *dev)
1936{
1937 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1938 unsigned int num_serial = dev->subsystem_device & 0xf;
1939
1940
1941
1942
1943
1944
1945
1946
1947
1948
1949
1950 switch (dev->device) {
1951 case PCI_DEVICE_ID_NETMOS_9835:
1952
1953 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1954 dev->subsystem_device == 0x0299)
1955 return;
1956 case PCI_DEVICE_ID_NETMOS_9735:
1957 case PCI_DEVICE_ID_NETMOS_9745:
1958 case PCI_DEVICE_ID_NETMOS_9845:
1959 case PCI_DEVICE_ID_NETMOS_9855:
1960 if (num_parallel) {
1961 pci_info(dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
1962 dev->device, num_parallel, num_serial);
1963 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1964 (dev->class & 0xff);
1965 }
1966 }
1967}
1968DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1969 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
1970
1971static void quirk_e100_interrupt(struct pci_dev *dev)
1972{
1973 u16 command, pmcsr;
1974 u8 __iomem *csr;
1975 u8 cmd_hi;
1976
1977 switch (dev->device) {
1978
1979 case 0x1029:
1980 case 0x1030 ... 0x1034:
1981 case 0x1038 ... 0x103E:
1982 case 0x1050 ... 0x1057:
1983 case 0x1059:
1984 case 0x1064 ... 0x106B:
1985 case 0x1091 ... 0x1095:
1986 case 0x1209:
1987 case 0x1229:
1988 case 0x2449:
1989 case 0x2459:
1990 case 0x245D:
1991 case 0x27DC:
1992 break;
1993 default:
1994 return;
1995 }
1996
1997
1998
1999
2000
2001
2002
2003
2004 pci_read_config_word(dev, PCI_COMMAND, &command);
2005
2006 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
2007 return;
2008
2009
2010
2011
2012
2013 if (dev->pm_cap) {
2014 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
2015 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2016 return;
2017 }
2018
2019
2020 csr = ioremap(pci_resource_start(dev, 0), 8);
2021 if (!csr) {
2022 pci_warn(dev, "Can't map e100 registers\n");
2023 return;
2024 }
2025
2026 cmd_hi = readb(csr + 3);
2027 if (cmd_hi == 0) {
2028 pci_warn(dev, "Firmware left e100 interrupts enabled; disabling\n");
2029 writeb(1, csr + 3);
2030 }
2031
2032 iounmap(csr);
2033}
2034DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2035 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
2036
2037
2038
2039
2040
2041static void quirk_disable_aspm_l0s(struct pci_dev *dev)
2042{
2043 pci_info(dev, "Disabling L0s\n");
2044 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2045}
2046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2048DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2049DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2055DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2060
2061static void fixup_rev1_53c810(struct pci_dev *dev)
2062{
2063 u32 class = dev->class;
2064
2065
2066
2067
2068
2069 if (class)
2070 return;
2071
2072 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2073 pci_info(dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2074 class, dev->class);
2075}
2076DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2077
2078
2079static void quirk_p64h2_1k_io(struct pci_dev *dev)
2080{
2081 u16 en1k;
2082
2083 pci_read_config_word(dev, 0x40, &en1k);
2084
2085 if (en1k & 0x200) {
2086 pci_info(dev, "Enable I/O Space to 1KB granularity\n");
2087 dev->io_window_1k = 1;
2088 }
2089}
2090DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2091
2092
2093
2094
2095
2096static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
2097{
2098 uint8_t b;
2099 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2100 if (!(b & 0x20)) {
2101 pci_write_config_byte(dev, 0xf41, b | 0x20);
2102 pci_info(dev, "Linking AER extended capability\n");
2103 }
2104 }
2105}
2106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2107 quirk_nvidia_ck804_pcie_aer_ext_cap);
2108DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2109 quirk_nvidia_ck804_pcie_aer_ext_cap);
2110
2111static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
2112{
2113
2114
2115
2116
2117
2118
2119
2120
2121
2122
2123
2124 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2125 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
2126 uint8_t b;
2127
2128
2129
2130 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2131 if (!p)
2132 return;
2133 pci_dev_put(p);
2134
2135 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2136 if (b & 0x40) {
2137
2138 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2139
2140 pci_info(dev, "Disabling VIA CX700 PCI parking\n");
2141 }
2142 }
2143
2144 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2145 if (b != 0) {
2146
2147 pci_write_config_byte(dev, 0x72, 0x0);
2148
2149
2150 pci_write_config_byte(dev, 0x75, 0x1);
2151
2152
2153 pci_write_config_byte(dev, 0x77, 0x0);
2154
2155 pci_info(dev, "Disabling VIA CX700 PCI caching\n");
2156 }
2157 }
2158}
2159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
2160
2161static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
2162{
2163 u32 rev;
2164
2165 pci_read_config_dword(dev, 0xf4, &rev);
2166
2167
2168 if (rev == 0x05719000) {
2169 int readrq = pcie_get_readrq(dev);
2170 if (readrq > 2048)
2171 pcie_set_readrq(dev, 2048);
2172 }
2173}
2174
2175DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2176 PCI_DEVICE_ID_TIGON3_5719,
2177 quirk_brcm_5719_limit_mrrs);
2178
2179#ifdef CONFIG_PCIE_IPROC_PLATFORM
2180static void quirk_paxc_bridge(struct pci_dev *pdev)
2181{
2182
2183
2184
2185
2186 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2187 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2188
2189
2190
2191
2192
2193
2194 pdev->pcie_mpss = 2;
2195}
2196DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2197DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2198#endif
2199
2200
2201
2202
2203
2204
2205
2206static void quirk_unhide_mch_dev6(struct pci_dev *dev)
2207{
2208 u8 reg;
2209
2210 if (pci_read_config_byte(dev, 0xF4, ®) == 0 && !(reg & 0x02)) {
2211 pci_info(dev, "Enabling MCH 'Overflow' Device\n");
2212 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2213 }
2214}
2215
2216DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2217 quirk_unhide_mch_dev6);
2218DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2219 quirk_unhide_mch_dev6);
2220
2221#ifdef CONFIG_PCI_MSI
2222
2223
2224
2225
2226
2227
2228static void quirk_disable_all_msi(struct pci_dev *dev)
2229{
2230 pci_no_msi();
2231 pci_warn(dev, "MSI quirk detected; MSI disabled\n");
2232}
2233DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2234DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
2236DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
2237DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
2238DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
2239DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
2240DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
2241
2242
2243static void quirk_disable_msi(struct pci_dev *dev)
2244{
2245 if (dev->subordinate) {
2246 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2247 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2248 }
2249}
2250DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
2251DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
2252DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
2253
2254
2255
2256
2257
2258
2259
2260static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
2261{
2262 struct pci_dev *apc_bridge;
2263
2264 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2265 if (apc_bridge) {
2266 if (apc_bridge->device == 0x9602)
2267 quirk_disable_msi(apc_bridge);
2268 pci_dev_put(apc_bridge);
2269 }
2270}
2271DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2272DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2273
2274
2275
2276static int msi_ht_cap_enabled(struct pci_dev *dev)
2277{
2278 int pos, ttl = PCI_FIND_CAP_TTL;
2279
2280 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2281 while (pos && ttl--) {
2282 u8 flags;
2283
2284 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2285 &flags) == 0) {
2286 pci_info(dev, "Found %s HT MSI Mapping\n",
2287 flags & HT_MSI_FLAGS_ENABLE ?
2288 "enabled" : "disabled");
2289 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
2290 }
2291
2292 pos = pci_find_next_ht_capability(dev, pos,
2293 HT_CAPTYPE_MSI_MAPPING);
2294 }
2295 return 0;
2296}
2297
2298
2299static void quirk_msi_ht_cap(struct pci_dev *dev)
2300{
2301 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
2302 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2303 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2304 }
2305}
2306DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2307 quirk_msi_ht_cap);
2308
2309
2310
2311
2312static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
2313{
2314 struct pci_dev *pdev;
2315
2316 if (!dev->subordinate)
2317 return;
2318
2319
2320
2321
2322 pdev = pci_get_slot(dev->bus, 0);
2323 if (!pdev)
2324 return;
2325 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
2326 pci_warn(dev, "MSI quirk detected; subordinate MSI disabled\n");
2327 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2328 }
2329 pci_dev_put(pdev);
2330}
2331DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2332 quirk_nvidia_ck804_msi_ht_cap);
2333
2334
2335static void ht_enable_msi_mapping(struct pci_dev *dev)
2336{
2337 int pos, ttl = PCI_FIND_CAP_TTL;
2338
2339 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2340 while (pos && ttl--) {
2341 u8 flags;
2342
2343 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2344 &flags) == 0) {
2345 pci_info(dev, "Enabling HT MSI Mapping\n");
2346
2347 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2348 flags | HT_MSI_FLAGS_ENABLE);
2349 }
2350 pos = pci_find_next_ht_capability(dev, pos,
2351 HT_CAPTYPE_MSI_MAPPING);
2352 }
2353}
2354DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2355 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2356 ht_enable_msi_mapping);
2357
2358DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2359 ht_enable_msi_mapping);
2360
2361
2362
2363
2364
2365static void nvenet_msi_disable(struct pci_dev *dev)
2366{
2367 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2368
2369 if (board_name &&
2370 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2371 strstr(board_name, "P5N32-E SLI"))) {
2372 pci_info(dev, "Disabling MSI for MCP55 NIC on P5N32-SLI\n");
2373 dev->no_msi = 1;
2374 }
2375}
2376DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2377 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2378 nvenet_msi_disable);
2379
2380
2381
2382
2383
2384
2385
2386
2387
2388
2389
2390static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
2391{
2392 u32 cfg;
2393
2394 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2395 return;
2396
2397 pci_read_config_dword(dev, 0x74, &cfg);
2398
2399 if (cfg & ((1 << 2) | (1 << 15))) {
2400 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2401 cfg &= ~((1 << 2) | (1 << 15));
2402 pci_write_config_dword(dev, 0x74, cfg);
2403 }
2404}
2405
2406DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2407 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2408 nvbridge_check_legacy_irq_routing);
2409
2410DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2411 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2412 nvbridge_check_legacy_irq_routing);
2413
2414static int ht_check_msi_mapping(struct pci_dev *dev)
2415{
2416 int pos, ttl = PCI_FIND_CAP_TTL;
2417 int found = 0;
2418
2419
2420 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2421 while (pos && ttl--) {
2422 u8 flags;
2423
2424 if (found < 1)
2425 found = 1;
2426 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2427 &flags) == 0) {
2428 if (flags & HT_MSI_FLAGS_ENABLE) {
2429 if (found < 2) {
2430 found = 2;
2431 break;
2432 }
2433 }
2434 }
2435 pos = pci_find_next_ht_capability(dev, pos,
2436 HT_CAPTYPE_MSI_MAPPING);
2437 }
2438
2439 return found;
2440}
2441
2442static int host_bridge_with_leaf(struct pci_dev *host_bridge)
2443{
2444 struct pci_dev *dev;
2445 int pos;
2446 int i, dev_no;
2447 int found = 0;
2448
2449 dev_no = host_bridge->devfn >> 3;
2450 for (i = dev_no + 1; i < 0x20; i++) {
2451 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2452 if (!dev)
2453 continue;
2454
2455
2456 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2457 if (pos != 0) {
2458 pci_dev_put(dev);
2459 break;
2460 }
2461
2462 if (ht_check_msi_mapping(dev)) {
2463 found = 1;
2464 pci_dev_put(dev);
2465 break;
2466 }
2467 pci_dev_put(dev);
2468 }
2469
2470 return found;
2471}
2472
2473#define PCI_HT_CAP_SLAVE_CTRL0 4
2474#define PCI_HT_CAP_SLAVE_CTRL1 8
2475
2476static int is_end_of_ht_chain(struct pci_dev *dev)
2477{
2478 int pos, ctrl_off;
2479 int end = 0;
2480 u16 flags, ctrl;
2481
2482 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2483
2484 if (!pos)
2485 goto out;
2486
2487 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2488
2489 ctrl_off = ((flags >> 10) & 1) ?
2490 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2491 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2492
2493 if (ctrl & (1 << 6))
2494 end = 1;
2495
2496out:
2497 return end;
2498}
2499
2500static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
2501{
2502 struct pci_dev *host_bridge;
2503 int pos;
2504 int i, dev_no;
2505 int found = 0;
2506
2507 dev_no = dev->devfn >> 3;
2508 for (i = dev_no; i >= 0; i--) {
2509 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2510 if (!host_bridge)
2511 continue;
2512
2513 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2514 if (pos != 0) {
2515 found = 1;
2516 break;
2517 }
2518 pci_dev_put(host_bridge);
2519 }
2520
2521 if (!found)
2522 return;
2523
2524
2525 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2526 host_bridge_with_leaf(host_bridge))
2527 goto out;
2528
2529
2530 if (msi_ht_cap_enabled(host_bridge))
2531 goto out;
2532
2533 ht_enable_msi_mapping(dev);
2534
2535out:
2536 pci_dev_put(host_bridge);
2537}
2538
2539static void ht_disable_msi_mapping(struct pci_dev *dev)
2540{
2541 int pos, ttl = PCI_FIND_CAP_TTL;
2542
2543 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2544 while (pos && ttl--) {
2545 u8 flags;
2546
2547 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2548 &flags) == 0) {
2549 pci_info(dev, "Disabling HT MSI Mapping\n");
2550
2551 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2552 flags & ~HT_MSI_FLAGS_ENABLE);
2553 }
2554 pos = pci_find_next_ht_capability(dev, pos,
2555 HT_CAPTYPE_MSI_MAPPING);
2556 }
2557}
2558
2559static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
2560{
2561 struct pci_dev *host_bridge;
2562 int pos;
2563 int found;
2564
2565 if (!pci_msi_enabled())
2566 return;
2567
2568
2569 found = ht_check_msi_mapping(dev);
2570
2571
2572 if (found == 0)
2573 return;
2574
2575
2576
2577
2578
2579 host_bridge = pci_get_domain_bus_and_slot(pci_domain_nr(dev->bus), 0,
2580 PCI_DEVFN(0, 0));
2581 if (host_bridge == NULL) {
2582 pci_warn(dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
2583 return;
2584 }
2585
2586 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2587 if (pos != 0) {
2588
2589 if (found == 1) {
2590
2591 if (all)
2592 ht_enable_msi_mapping(dev);
2593 else
2594 nv_ht_enable_msi_mapping(dev);
2595 }
2596 goto out;
2597 }
2598
2599
2600 if (found == 1)
2601 goto out;
2602
2603
2604 ht_disable_msi_mapping(dev);
2605
2606out:
2607 pci_dev_put(host_bridge);
2608}
2609
2610static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
2611{
2612 return __nv_msi_ht_cap_quirk(dev, 1);
2613}
2614
2615static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
2616{
2617 return __nv_msi_ht_cap_quirk(dev, 0);
2618}
2619
2620DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2621DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
2622
2623DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2624DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
2625
2626static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
2627{
2628 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2629}
2630static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
2631{
2632 struct pci_dev *p;
2633
2634
2635
2636
2637
2638 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2639 NULL);
2640 if (!p)
2641 return;
2642
2643 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2644 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2645 pci_dev_put(p);
2646}
2647static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2648{
2649
2650 if (dev->revision < 0x18) {
2651 pci_info(dev, "set MSI_INTX_DISABLE_BUG flag\n");
2652 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2653 }
2654}
2655DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2656 PCI_DEVICE_ID_TIGON3_5780,
2657 quirk_msi_intx_disable_bug);
2658DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2659 PCI_DEVICE_ID_TIGON3_5780S,
2660 quirk_msi_intx_disable_bug);
2661DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2662 PCI_DEVICE_ID_TIGON3_5714,
2663 quirk_msi_intx_disable_bug);
2664DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2665 PCI_DEVICE_ID_TIGON3_5714S,
2666 quirk_msi_intx_disable_bug);
2667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2668 PCI_DEVICE_ID_TIGON3_5715,
2669 quirk_msi_intx_disable_bug);
2670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2671 PCI_DEVICE_ID_TIGON3_5715S,
2672 quirk_msi_intx_disable_bug);
2673
2674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
2675 quirk_msi_intx_disable_ati_bug);
2676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
2677 quirk_msi_intx_disable_ati_bug);
2678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
2679 quirk_msi_intx_disable_ati_bug);
2680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
2681 quirk_msi_intx_disable_ati_bug);
2682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
2683 quirk_msi_intx_disable_ati_bug);
2684
2685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2686 quirk_msi_intx_disable_bug);
2687DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2688 quirk_msi_intx_disable_bug);
2689DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2690 quirk_msi_intx_disable_bug);
2691
2692DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2693 quirk_msi_intx_disable_bug);
2694DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2695 quirk_msi_intx_disable_bug);
2696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2697 quirk_msi_intx_disable_bug);
2698DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2699 quirk_msi_intx_disable_bug);
2700DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2701 quirk_msi_intx_disable_bug);
2702DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2703 quirk_msi_intx_disable_bug);
2704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2705 quirk_msi_intx_disable_qca_bug);
2706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2707 quirk_msi_intx_disable_qca_bug);
2708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2709 quirk_msi_intx_disable_qca_bug);
2710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2711 quirk_msi_intx_disable_qca_bug);
2712DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2713 quirk_msi_intx_disable_qca_bug);
2714#endif
2715
2716
2717
2718
2719
2720
2721
2722static void quirk_hotplug_bridge(struct pci_dev *dev)
2723{
2724 dev->is_hotplug_bridge = 1;
2725}
2726
2727DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2728
2729
2730
2731
2732
2733
2734
2735
2736
2737
2738
2739
2740
2741
2742
2743
2744
2745
2746
2747
2748
2749
2750
2751
2752
2753
2754
2755
2756#ifdef CONFIG_MMC_RICOH_MMC
2757static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2758{
2759
2760 u8 write_enable;
2761 u8 write_target;
2762 u8 disable;
2763
2764
2765 if (PCI_FUNC(dev->devfn))
2766 return;
2767
2768 pci_read_config_byte(dev, 0xB7, &disable);
2769 if (disable & 0x02)
2770 return;
2771
2772 pci_read_config_byte(dev, 0x8E, &write_enable);
2773 pci_write_config_byte(dev, 0x8E, 0xAA);
2774 pci_read_config_byte(dev, 0x8D, &write_target);
2775 pci_write_config_byte(dev, 0x8D, 0xB7);
2776 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2777 pci_write_config_byte(dev, 0x8E, write_enable);
2778 pci_write_config_byte(dev, 0x8D, write_target);
2779
2780 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2781 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2782}
2783DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2784DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2785
2786static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2787{
2788
2789 u8 write_enable;
2790 u8 disable;
2791
2792
2793 if (PCI_FUNC(dev->devfn))
2794 return;
2795
2796
2797
2798
2799
2800
2801
2802
2803
2804
2805
2806
2807 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2808 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
2809 pci_write_config_byte(dev, 0xf9, 0xfc);
2810 pci_write_config_byte(dev, 0x150, 0x10);
2811 pci_write_config_byte(dev, 0xf9, 0x00);
2812 pci_write_config_byte(dev, 0xfc, 0x01);
2813 pci_write_config_byte(dev, 0xe1, 0x32);
2814 pci_write_config_byte(dev, 0xfc, 0x00);
2815
2816 pci_notice(dev, "MMC controller base frequency changed to 50Mhz.\n");
2817 }
2818
2819 pci_read_config_byte(dev, 0xCB, &disable);
2820
2821 if (disable & 0x02)
2822 return;
2823
2824 pci_read_config_byte(dev, 0xCA, &write_enable);
2825 pci_write_config_byte(dev, 0xCA, 0x57);
2826 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2827 pci_write_config_byte(dev, 0xCA, write_enable);
2828
2829 pci_notice(dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2830 pci_notice(dev, "MMC cards are now supported by standard SDHCI controller\n");
2831
2832}
2833DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2834DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2835DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2836DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2837DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2838DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2839#endif
2840
2841#ifdef CONFIG_DMAR_TABLE
2842#define VTUNCERRMSK_REG 0x1ac
2843#define VTD_MSK_SPEC_ERRORS (1 << 31)
2844
2845
2846
2847
2848
2849
2850
2851
2852
2853
2854static void vtd_mask_spec_errors(struct pci_dev *dev)
2855{
2856 u32 word;
2857
2858 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2859 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2860}
2861DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2862DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2863#endif
2864
2865static void fixup_ti816x_class(struct pci_dev *dev)
2866{
2867 u32 class = dev->class;
2868
2869
2870 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2871 pci_info(dev, "PCI class overridden (%#08x -> %#08x)\n",
2872 class, dev->class);
2873}
2874DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
2875 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
2876
2877
2878
2879
2880static void fixup_mpss_256(struct pci_dev *dev)
2881{
2882 dev->pcie_mpss = 1;
2883}
2884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2885 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2886DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2887 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2888DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2889 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2890
2891
2892
2893
2894
2895
2896
2897
2898static void quirk_intel_mc_errata(struct pci_dev *dev)
2899{
2900 int err;
2901 u16 rcc;
2902
2903 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2904 pcie_bus_config == PCIE_BUS_DEFAULT)
2905 return;
2906
2907
2908
2909
2910
2911 err = pci_read_config_word(dev, 0x48, &rcc);
2912 if (err) {
2913 pci_err(dev, "Error attempting to read the read completion coalescing register\n");
2914 return;
2915 }
2916
2917 if (!(rcc & (1 << 10)))
2918 return;
2919
2920 rcc &= ~(1 << 10);
2921
2922 err = pci_write_config_word(dev, 0x48, rcc);
2923 if (err) {
2924 pci_err(dev, "Error attempting to write the read completion coalescing register\n");
2925 return;
2926 }
2927
2928 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
2929}
2930
2931DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
2932DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
2933DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
2934DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
2935DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
2936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
2937DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
2938DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
2939DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
2940DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
2941DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
2942DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
2943DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
2944DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
2945
2946DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
2947DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
2948DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
2949DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
2950DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
2951DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
2952DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
2953DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
2954DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
2955DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
2956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
2957
2958
2959
2960
2961
2962
2963
2964static void quirk_intel_ntb(struct pci_dev *dev)
2965{
2966 int rc;
2967 u8 val;
2968
2969 rc = pci_read_config_byte(dev, 0x00D0, &val);
2970 if (rc)
2971 return;
2972
2973 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
2974
2975 rc = pci_read_config_byte(dev, 0x00D1, &val);
2976 if (rc)
2977 return;
2978
2979 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
2980}
2981DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
2982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
2983
2984static ktime_t fixup_debug_start(struct pci_dev *dev,
2985 void (*fn)(struct pci_dev *dev))
2986{
2987 if (initcall_debug)
2988 pci_info(dev, "calling %pF @ %i\n", fn, task_pid_nr(current));
2989
2990 return ktime_get();
2991}
2992
2993static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
2994 void (*fn)(struct pci_dev *dev))
2995{
2996 ktime_t delta, rettime;
2997 unsigned long long duration;
2998
2999 rettime = ktime_get();
3000 delta = ktime_sub(rettime, calltime);
3001 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3002 if (initcall_debug || duration > 10000)
3003 pci_info(dev, "%pF took %lld usecs\n", fn, duration);
3004}
3005
3006
3007
3008
3009
3010
3011
3012
3013
3014
3015
3016
3017
3018#define I915_DEIER_REG 0x4400c
3019static void disable_igfx_irq(struct pci_dev *dev)
3020{
3021 void __iomem *regs = pci_iomap(dev, 0, 0);
3022 if (regs == NULL) {
3023 pci_warn(dev, "igfx quirk: Can't iomap PCI device\n");
3024 return;
3025 }
3026
3027
3028 if (readl(regs + I915_DEIER_REG) != 0) {
3029 pci_warn(dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
3030
3031 writel(0, regs + I915_DEIER_REG);
3032 }
3033
3034 pci_iounmap(dev, regs);
3035}
3036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
3037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
3038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
3039
3040
3041
3042
3043
3044static void quirk_remove_d3_delay(struct pci_dev *dev)
3045{
3046 dev->d3_delay = 0;
3047}
3048
3049DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
3050DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
3051DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
3052
3053DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3054DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3055DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3056DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3057DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3058DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3059DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
3060DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3061DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3062DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
3063DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
3064
3065DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
3066DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3067DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
3068DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
3069DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
3071DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3072DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
3074
3075
3076
3077
3078
3079
3080static void quirk_broken_intx_masking(struct pci_dev *dev)
3081{
3082 dev->broken_intx_masking = 1;
3083}
3084DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3085 quirk_broken_intx_masking);
3086DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601,
3087 quirk_broken_intx_masking);
3088DECLARE_PCI_FIXUP_FINAL(0x1b7c, 0x0004,
3089 quirk_broken_intx_masking);
3090
3091
3092
3093
3094
3095
3096
3097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3098 quirk_broken_intx_masking);
3099
3100
3101
3102
3103
3104DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3105 quirk_broken_intx_masking);
3106DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3107 quirk_broken_intx_masking);
3108DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3109 quirk_broken_intx_masking);
3110DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3111 quirk_broken_intx_masking);
3112DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3113 quirk_broken_intx_masking);
3114DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3115 quirk_broken_intx_masking);
3116DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3117 quirk_broken_intx_masking);
3118DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3119 quirk_broken_intx_masking);
3120DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3121 quirk_broken_intx_masking);
3122DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3123 quirk_broken_intx_masking);
3124DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3125 quirk_broken_intx_masking);
3126DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158a,
3127 quirk_broken_intx_masking);
3128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x158b,
3129 quirk_broken_intx_masking);
3130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3131 quirk_broken_intx_masking);
3132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3133 quirk_broken_intx_masking);
3134DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3135 quirk_broken_intx_masking);
3136
3137static u16 mellanox_broken_intx_devs[] = {
3138 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3139 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3140 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3141 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3142 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3143 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3144 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3145 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3146 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3147 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3148 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3149 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3150 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3151 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
3152};
3153
3154#define CONNECTX_4_CURR_MAX_MINOR 99
3155#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3156
3157
3158
3159
3160
3161
3162
3163static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3164{
3165 __be32 __iomem *fw_ver;
3166 u16 fw_major;
3167 u16 fw_minor;
3168 u16 fw_subminor;
3169 u32 fw_maj_min;
3170 u32 fw_sub_min;
3171 int i;
3172
3173 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3174 if (pdev->device == mellanox_broken_intx_devs[i]) {
3175 pdev->broken_intx_masking = 1;
3176 return;
3177 }
3178 }
3179
3180
3181
3182
3183 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3184 return;
3185
3186 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3187 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3188 return;
3189
3190
3191 if (pci_enable_device_mem(pdev)) {
3192 pci_warn(pdev, "Can't enable device memory\n");
3193 return;
3194 }
3195
3196 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3197 if (!fw_ver) {
3198 pci_warn(pdev, "Can't map ConnectX-4 initialization segment\n");
3199 goto out;
3200 }
3201
3202
3203 fw_maj_min = ioread32be(fw_ver);
3204 fw_sub_min = ioread32be(fw_ver + 1);
3205 fw_major = fw_maj_min & 0xffff;
3206 fw_minor = fw_maj_min >> 16;
3207 fw_subminor = fw_sub_min & 0xffff;
3208 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3209 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3210 pci_warn(pdev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3211 fw_major, fw_minor, fw_subminor, pdev->device ==
3212 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3213 pdev->broken_intx_masking = 1;
3214 }
3215
3216 iounmap(fw_ver);
3217
3218out:
3219 pci_disable_device(pdev);
3220}
3221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3222 mellanox_check_broken_intx_masking);
3223
3224static void quirk_no_bus_reset(struct pci_dev *dev)
3225{
3226 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3227}
3228
3229
3230
3231
3232
3233
3234
3235
3236DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
3237DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3238DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
3239DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
3240
3241
3242
3243
3244
3245
3246DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CAVIUM, 0xa100, quirk_no_bus_reset);
3247
3248static void quirk_no_pm_reset(struct pci_dev *dev)
3249{
3250
3251
3252
3253
3254 if (!pci_is_root_bus(dev->bus))
3255 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3256}
3257
3258
3259
3260
3261
3262
3263
3264
3265
3266DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3267 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3268
3269
3270
3271
3272
3273
3274static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3275{
3276 if (pdev->is_hotplug_bridge &&
3277 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3278 pdev->revision <= 1))
3279 pdev->no_msi = 1;
3280}
3281DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3282 quirk_thunderbolt_hotplug_msi);
3283DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3284 quirk_thunderbolt_hotplug_msi);
3285DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3286 quirk_thunderbolt_hotplug_msi);
3287DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3288 quirk_thunderbolt_hotplug_msi);
3289DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3290 quirk_thunderbolt_hotplug_msi);
3291
3292#ifdef CONFIG_ACPI
3293
3294
3295
3296
3297
3298
3299
3300
3301
3302
3303
3304
3305
3306
3307
3308static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3309{
3310 acpi_handle bridge, SXIO, SXFP, SXLV;
3311
3312 if (!x86_apple_machine)
3313 return;
3314 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3315 return;
3316 bridge = ACPI_HANDLE(&dev->dev);
3317 if (!bridge)
3318 return;
3319
3320
3321
3322
3323
3324
3325 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3326 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3327 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3328 return;
3329 pci_info(dev, "quirk: cutting power to thunderbolt controller...\n");
3330
3331
3332 acpi_execute_simple_method(SXIO, NULL, 1);
3333 acpi_execute_simple_method(SXFP, NULL, 0);
3334 msleep(300);
3335 acpi_execute_simple_method(SXLV, NULL, 0);
3336 acpi_execute_simple_method(SXIO, NULL, 0);
3337 acpi_execute_simple_method(SXLV, NULL, 0);
3338}
3339DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3340 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3341 quirk_apple_poweroff_thunderbolt);
3342
3343
3344
3345
3346
3347
3348
3349
3350
3351
3352static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3353{
3354 struct pci_dev *sibling = NULL;
3355 struct pci_dev *nhi = NULL;
3356
3357 if (!x86_apple_machine)
3358 return;
3359 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3360 return;
3361
3362
3363
3364
3365 sibling = pci_get_slot(dev->bus, 0x0);
3366 if (sibling == dev)
3367 goto out;
3368 if (!sibling || !sibling->subordinate)
3369 goto out;
3370 nhi = pci_get_slot(sibling->subordinate, 0x0);
3371 if (!nhi)
3372 goto out;
3373 if (nhi->vendor != PCI_VENDOR_ID_INTEL
3374 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3375 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
3376 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
3377 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
3378 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
3379 goto out;
3380 pci_info(dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
3381 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3382out:
3383 pci_dev_put(nhi);
3384 pci_dev_put(sibling);
3385}
3386DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3387 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3388 quirk_apple_wait_for_thunderbolt);
3389DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3390 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3391 quirk_apple_wait_for_thunderbolt);
3392DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3393 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3394 quirk_apple_wait_for_thunderbolt);
3395DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
3396 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
3397 quirk_apple_wait_for_thunderbolt);
3398#endif
3399
3400static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3401 struct pci_fixup *end)
3402{
3403 ktime_t calltime;
3404
3405 for (; f < end; f++)
3406 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3407 f->class == (u32) PCI_ANY_ID) &&
3408 (f->vendor == dev->vendor ||
3409 f->vendor == (u16) PCI_ANY_ID) &&
3410 (f->device == dev->device ||
3411 f->device == (u16) PCI_ANY_ID)) {
3412 calltime = fixup_debug_start(dev, f->hook);
3413 f->hook(dev);
3414 fixup_debug_report(dev, calltime, f->hook);
3415 }
3416}
3417
3418extern struct pci_fixup __start_pci_fixups_early[];
3419extern struct pci_fixup __end_pci_fixups_early[];
3420extern struct pci_fixup __start_pci_fixups_header[];
3421extern struct pci_fixup __end_pci_fixups_header[];
3422extern struct pci_fixup __start_pci_fixups_final[];
3423extern struct pci_fixup __end_pci_fixups_final[];
3424extern struct pci_fixup __start_pci_fixups_enable[];
3425extern struct pci_fixup __end_pci_fixups_enable[];
3426extern struct pci_fixup __start_pci_fixups_resume[];
3427extern struct pci_fixup __end_pci_fixups_resume[];
3428extern struct pci_fixup __start_pci_fixups_resume_early[];
3429extern struct pci_fixup __end_pci_fixups_resume_early[];
3430extern struct pci_fixup __start_pci_fixups_suspend[];
3431extern struct pci_fixup __end_pci_fixups_suspend[];
3432extern struct pci_fixup __start_pci_fixups_suspend_late[];
3433extern struct pci_fixup __end_pci_fixups_suspend_late[];
3434
3435static bool pci_apply_fixup_final_quirks;
3436
3437void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3438{
3439 struct pci_fixup *start, *end;
3440
3441 switch (pass) {
3442 case pci_fixup_early:
3443 start = __start_pci_fixups_early;
3444 end = __end_pci_fixups_early;
3445 break;
3446
3447 case pci_fixup_header:
3448 start = __start_pci_fixups_header;
3449 end = __end_pci_fixups_header;
3450 break;
3451
3452 case pci_fixup_final:
3453 if (!pci_apply_fixup_final_quirks)
3454 return;
3455 start = __start_pci_fixups_final;
3456 end = __end_pci_fixups_final;
3457 break;
3458
3459 case pci_fixup_enable:
3460 start = __start_pci_fixups_enable;
3461 end = __end_pci_fixups_enable;
3462 break;
3463
3464 case pci_fixup_resume:
3465 start = __start_pci_fixups_resume;
3466 end = __end_pci_fixups_resume;
3467 break;
3468
3469 case pci_fixup_resume_early:
3470 start = __start_pci_fixups_resume_early;
3471 end = __end_pci_fixups_resume_early;
3472 break;
3473
3474 case pci_fixup_suspend:
3475 start = __start_pci_fixups_suspend;
3476 end = __end_pci_fixups_suspend;
3477 break;
3478
3479 case pci_fixup_suspend_late:
3480 start = __start_pci_fixups_suspend_late;
3481 end = __end_pci_fixups_suspend_late;
3482 break;
3483
3484 default:
3485
3486 return;
3487 }
3488 pci_do_fixups(dev, start, end);
3489}
3490EXPORT_SYMBOL(pci_fixup_device);
3491
3492
3493static int __init pci_apply_final_quirks(void)
3494{
3495 struct pci_dev *dev = NULL;
3496 u8 cls = 0;
3497 u8 tmp;
3498
3499 if (pci_cache_line_size)
3500 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3501 pci_cache_line_size << 2);
3502
3503 pci_apply_fixup_final_quirks = true;
3504 for_each_pci_dev(dev) {
3505 pci_fixup_device(pci_fixup_final, dev);
3506
3507
3508
3509
3510
3511 if (!pci_cache_line_size) {
3512 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3513 if (!cls)
3514 cls = tmp;
3515 if (!tmp || cls == tmp)
3516 continue;
3517
3518 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3519 cls << 2, tmp << 2,
3520 pci_dfl_cache_line_size << 2);
3521 pci_cache_line_size = pci_dfl_cache_line_size;
3522 }
3523 }
3524
3525 if (!pci_cache_line_size) {
3526 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3527 cls << 2, pci_dfl_cache_line_size << 2);
3528 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
3529 }
3530
3531 return 0;
3532}
3533
3534fs_initcall_sync(pci_apply_final_quirks);
3535
3536
3537
3538
3539
3540
3541static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3542{
3543
3544
3545
3546
3547
3548
3549
3550
3551 if (!probe)
3552 pcie_flr(dev);
3553 return 0;
3554}
3555
3556#define SOUTH_CHICKEN2 0xc2004
3557#define PCH_PP_STATUS 0xc7200
3558#define PCH_PP_CONTROL 0xc7204
3559#define MSG_CTL 0x45010
3560#define NSDE_PWR_STATE 0xd0100
3561#define IGD_OPERATION_TIMEOUT 10000
3562
3563static int reset_ivb_igd(struct pci_dev *dev, int probe)
3564{
3565 void __iomem *mmio_base;
3566 unsigned long timeout;
3567 u32 val;
3568
3569 if (probe)
3570 return 0;
3571
3572 mmio_base = pci_iomap(dev, 0, 0);
3573 if (!mmio_base)
3574 return -ENOMEM;
3575
3576 iowrite32(0x00000002, mmio_base + MSG_CTL);
3577
3578
3579
3580
3581
3582
3583
3584 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3585
3586 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3587 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3588
3589 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3590 do {
3591 val = ioread32(mmio_base + PCH_PP_STATUS);
3592 if ((val & 0xb0000000) == 0)
3593 goto reset_complete;
3594 msleep(10);
3595 } while (time_before(jiffies, timeout));
3596 pci_warn(dev, "timeout during reset\n");
3597
3598reset_complete:
3599 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3600
3601 pci_iounmap(dev, mmio_base);
3602 return 0;
3603}
3604
3605
3606
3607
3608static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3609{
3610 u16 old_command;
3611 u16 msix_flags;
3612
3613
3614
3615
3616
3617 if ((dev->device & 0xf000) != 0x4000)
3618 return -ENOTTY;
3619
3620
3621
3622
3623
3624 if (probe)
3625 return 0;
3626
3627
3628
3629
3630
3631
3632
3633 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3634 pci_write_config_word(dev, PCI_COMMAND,
3635 old_command | PCI_COMMAND_MASTER);
3636
3637
3638
3639
3640
3641 pci_save_state(dev);
3642
3643
3644
3645
3646
3647
3648
3649
3650 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3651 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3652 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3653 msix_flags |
3654 PCI_MSIX_FLAGS_ENABLE |
3655 PCI_MSIX_FLAGS_MASKALL);
3656
3657 pcie_flr(dev);
3658
3659
3660
3661
3662
3663
3664 pci_restore_state(dev);
3665 pci_write_config_word(dev, PCI_COMMAND, old_command);
3666 return 0;
3667}
3668
3669#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
3670#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3671#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
3672
3673static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
3674 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3675 reset_intel_82599_sfp_virtfn },
3676 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3677 reset_ivb_igd },
3678 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3679 reset_ivb_igd },
3680 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3681 reset_chelsio_generic_dev },
3682 { 0 }
3683};
3684
3685
3686
3687
3688
3689
3690int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3691{
3692 const struct pci_dev_reset_methods *i;
3693
3694 for (i = pci_dev_reset_methods; i->reset; i++) {
3695 if ((i->vendor == dev->vendor ||
3696 i->vendor == (u16)PCI_ANY_ID) &&
3697 (i->device == dev->device ||
3698 i->device == (u16)PCI_ANY_ID))
3699 return i->reset(dev, probe);
3700 }
3701
3702 return -ENOTTY;
3703}
3704
3705static void quirk_dma_func0_alias(struct pci_dev *dev)
3706{
3707 if (PCI_FUNC(dev->devfn) != 0)
3708 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
3709}
3710
3711
3712
3713
3714
3715
3716DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3717DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3718
3719static void quirk_dma_func1_alias(struct pci_dev *dev)
3720{
3721 if (PCI_FUNC(dev->devfn) != 1)
3722 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
3723}
3724
3725
3726
3727
3728
3729
3730
3731DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3732 quirk_dma_func1_alias);
3733DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3734 quirk_dma_func1_alias);
3735DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3736 quirk_dma_func1_alias);
3737
3738DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3739 quirk_dma_func1_alias);
3740
3741DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3742 quirk_dma_func1_alias);
3743
3744DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3745 quirk_dma_func1_alias);
3746
3747DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3748 quirk_dma_func1_alias);
3749
3750DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3751 quirk_dma_func1_alias);
3752
3753DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3754 quirk_dma_func1_alias);
3755
3756DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3757 quirk_dma_func1_alias);
3758DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3759 quirk_dma_func1_alias);
3760DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3761 quirk_dma_func1_alias);
3762
3763DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3764 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3765 quirk_dma_func1_alias);
3766
3767DECLARE_PCI_FIXUP_HEADER(0x1c28,
3768 0x0122,
3769 quirk_dma_func1_alias);
3770
3771
3772
3773
3774
3775
3776
3777
3778
3779
3780
3781
3782
3783
3784
3785
3786static const struct pci_device_id fixed_dma_alias_tbl[] = {
3787 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3788 PCI_VENDOR_ID_ADAPTEC2, 0x02bb),
3789 .driver_data = PCI_DEVFN(1, 0) },
3790 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3791 PCI_VENDOR_ID_ADAPTEC2, 0x02bc),
3792 .driver_data = PCI_DEVFN(1, 0) },
3793 { 0 }
3794};
3795
3796static void quirk_fixed_dma_alias(struct pci_dev *dev)
3797{
3798 const struct pci_device_id *id;
3799
3800 id = pci_match_id(fixed_dma_alias_tbl, dev);
3801 if (id)
3802 pci_add_dma_alias(dev, id->driver_data);
3803}
3804
3805DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3806
3807
3808
3809
3810
3811
3812
3813
3814
3815
3816static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3817{
3818 if (!pci_is_root_bus(pdev->bus) &&
3819 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3820 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3821 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3822 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3823}
3824
3825DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3826 quirk_use_pcie_bridge_dma_alias);
3827
3828DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
3829
3830DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
3831
3832DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8893, quirk_use_pcie_bridge_dma_alias);
3833
3834DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
3835
3836
3837
3838
3839
3840
3841
3842static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3843{
3844 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3845 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3846 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3847}
3848DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3849DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3850
3851
3852
3853
3854
3855
3856static void quirk_bridge_cavm_thrx2_pcie_root(struct pci_dev *pdev)
3857{
3858 pdev->dev_flags |= PCI_DEV_FLAGS_BRIDGE_XLATE_ROOT;
3859}
3860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9000,
3861 quirk_bridge_cavm_thrx2_pcie_root);
3862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_BROADCOM, 0x9084,
3863 quirk_bridge_cavm_thrx2_pcie_root);
3864
3865
3866
3867
3868
3869static void quirk_tw686x_class(struct pci_dev *pdev)
3870{
3871 u32 class = pdev->class;
3872
3873
3874 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3875 pci_info(pdev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3876 class, pdev->class);
3877}
3878DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
3879 quirk_tw686x_class);
3880DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
3881 quirk_tw686x_class);
3882DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
3883 quirk_tw686x_class);
3884DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
3885 quirk_tw686x_class);
3886
3887
3888
3889
3890
3891
3892static void quirk_relaxedordering_disable(struct pci_dev *dev)
3893{
3894 dev->dev_flags |= PCI_DEV_FLAGS_NO_RELAXED_ORDERING;
3895 pci_info(dev, "Disable Relaxed Ordering Attributes to avoid PCIe Completion erratum\n");
3896}
3897
3898
3899
3900
3901
3902
3903DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f01, PCI_CLASS_NOT_DEFINED, 8,
3904 quirk_relaxedordering_disable);
3905DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f02, PCI_CLASS_NOT_DEFINED, 8,
3906 quirk_relaxedordering_disable);
3907DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f03, PCI_CLASS_NOT_DEFINED, 8,
3908 quirk_relaxedordering_disable);
3909DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f04, PCI_CLASS_NOT_DEFINED, 8,
3910 quirk_relaxedordering_disable);
3911DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f05, PCI_CLASS_NOT_DEFINED, 8,
3912 quirk_relaxedordering_disable);
3913DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f06, PCI_CLASS_NOT_DEFINED, 8,
3914 quirk_relaxedordering_disable);
3915DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f07, PCI_CLASS_NOT_DEFINED, 8,
3916 quirk_relaxedordering_disable);
3917DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f08, PCI_CLASS_NOT_DEFINED, 8,
3918 quirk_relaxedordering_disable);
3919DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f09, PCI_CLASS_NOT_DEFINED, 8,
3920 quirk_relaxedordering_disable);
3921DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0a, PCI_CLASS_NOT_DEFINED, 8,
3922 quirk_relaxedordering_disable);
3923DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0b, PCI_CLASS_NOT_DEFINED, 8,
3924 quirk_relaxedordering_disable);
3925DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0c, PCI_CLASS_NOT_DEFINED, 8,
3926 quirk_relaxedordering_disable);
3927DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0d, PCI_CLASS_NOT_DEFINED, 8,
3928 quirk_relaxedordering_disable);
3929DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x6f0e, PCI_CLASS_NOT_DEFINED, 8,
3930 quirk_relaxedordering_disable);
3931DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f01, PCI_CLASS_NOT_DEFINED, 8,
3932 quirk_relaxedordering_disable);
3933DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f02, PCI_CLASS_NOT_DEFINED, 8,
3934 quirk_relaxedordering_disable);
3935DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f03, PCI_CLASS_NOT_DEFINED, 8,
3936 quirk_relaxedordering_disable);
3937DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f04, PCI_CLASS_NOT_DEFINED, 8,
3938 quirk_relaxedordering_disable);
3939DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f05, PCI_CLASS_NOT_DEFINED, 8,
3940 quirk_relaxedordering_disable);
3941DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f06, PCI_CLASS_NOT_DEFINED, 8,
3942 quirk_relaxedordering_disable);
3943DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f07, PCI_CLASS_NOT_DEFINED, 8,
3944 quirk_relaxedordering_disable);
3945DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f08, PCI_CLASS_NOT_DEFINED, 8,
3946 quirk_relaxedordering_disable);
3947DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f09, PCI_CLASS_NOT_DEFINED, 8,
3948 quirk_relaxedordering_disable);
3949DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0a, PCI_CLASS_NOT_DEFINED, 8,
3950 quirk_relaxedordering_disable);
3951DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0b, PCI_CLASS_NOT_DEFINED, 8,
3952 quirk_relaxedordering_disable);
3953DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0c, PCI_CLASS_NOT_DEFINED, 8,
3954 quirk_relaxedordering_disable);
3955DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0d, PCI_CLASS_NOT_DEFINED, 8,
3956 quirk_relaxedordering_disable);
3957DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, 0x2f0e, PCI_CLASS_NOT_DEFINED, 8,
3958 quirk_relaxedordering_disable);
3959
3960
3961
3962
3963
3964
3965
3966
3967
3968
3969DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a00, PCI_CLASS_NOT_DEFINED, 8,
3970 quirk_relaxedordering_disable);
3971DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a01, PCI_CLASS_NOT_DEFINED, 8,
3972 quirk_relaxedordering_disable);
3973DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AMD, 0x1a02, PCI_CLASS_NOT_DEFINED, 8,
3974 quirk_relaxedordering_disable);
3975
3976
3977
3978
3979
3980
3981
3982
3983
3984
3985
3986
3987
3988
3989
3990
3991
3992
3993
3994
3995
3996
3997
3998
3999static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4000{
4001 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4002
4003 if (!root_port) {
4004 pci_warn(pdev, "PCIe Completion erratum may cause device errors\n");
4005 return;
4006 }
4007
4008 pci_info(root_port, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4009 dev_name(&pdev->dev));
4010 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4011 PCI_EXP_DEVCTL_RELAX_EN |
4012 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4013}
4014
4015
4016
4017
4018
4019static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4020{
4021
4022
4023
4024
4025
4026
4027 if ((pdev->device & 0xff00) == 0x5400)
4028 quirk_disable_root_port_attributes(pdev);
4029}
4030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4031 quirk_chelsio_T5_disable_root_port_attributes);
4032
4033
4034
4035
4036
4037
4038
4039
4040
4041
4042
4043
4044
4045
4046
4047
4048
4049
4050
4051
4052
4053
4054
4055
4056
4057
4058static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4059{
4060#ifdef CONFIG_ACPI
4061 struct acpi_table_header *header = NULL;
4062 acpi_status status;
4063
4064
4065 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4066 return -ENODEV;
4067
4068
4069 status = acpi_get_table("IVRS", 0, &header);
4070 if (ACPI_FAILURE(status))
4071 return -ENODEV;
4072
4073
4074 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4075
4076 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4077#else
4078 return -ENODEV;
4079#endif
4080}
4081
4082static bool pci_quirk_cavium_acs_match(struct pci_dev *dev)
4083{
4084
4085
4086
4087
4088
4089
4090 return (pci_is_pcie(dev) &&
4091 (pci_pcie_type(dev) == PCI_EXP_TYPE_ROOT_PORT) &&
4092 ((dev->device & 0xf800) == 0xa000));
4093}
4094
4095static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4096{
4097
4098
4099
4100
4101
4102
4103
4104
4105 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
4106
4107 if (!pci_quirk_cavium_acs_match(dev))
4108 return -ENOTTY;
4109
4110 return acs_flags ? 0 : 1;
4111}
4112
4113static int pci_quirk_xgene_acs(struct pci_dev *dev, u16 acs_flags)
4114{
4115
4116
4117
4118
4119
4120 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF);
4121
4122 return acs_flags ? 0 : 1;
4123}
4124
4125
4126
4127
4128
4129
4130
4131static const u16 pci_quirk_intel_pch_acs_ids[] = {
4132
4133 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4134 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4135
4136 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4137 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4138
4139 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4140 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4141
4142 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4143 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4144
4145 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4146 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4147
4148 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4149 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
4150
4151 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
4152
4153 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4154 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
4155
4156 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
4157};
4158
4159static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4160{
4161 int i;
4162
4163
4164 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4165 return false;
4166
4167 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4168 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4169 return true;
4170
4171 return false;
4172}
4173
4174#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4175
4176static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4177{
4178 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4179 INTEL_PCH_ACS_FLAGS : 0;
4180
4181 if (!pci_quirk_intel_pch_acs_match(dev))
4182 return -ENOTTY;
4183
4184 return acs_flags & ~flags ? 0 : 1;
4185}
4186
4187
4188
4189
4190
4191
4192
4193
4194
4195
4196
4197static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4198{
4199 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4200 int ret = acs_flags & ~flags ? 0 : 1;
4201
4202 pci_info(dev, "Using QCOM ACS Quirk (%d)\n", ret);
4203
4204 return ret;
4205}
4206
4207
4208
4209
4210
4211
4212
4213
4214
4215
4216
4217
4218
4219
4220
4221
4222
4223
4224
4225
4226
4227
4228
4229
4230
4231
4232
4233
4234
4235
4236
4237
4238
4239static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4240{
4241 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4242 return false;
4243
4244 switch (dev->device) {
4245 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a:
4246 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee:
4247 return true;
4248 }
4249
4250 return false;
4251}
4252
4253#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4254
4255static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4256{
4257 int pos;
4258 u32 cap, ctrl;
4259
4260 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4261 return -ENOTTY;
4262
4263 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4264 if (!pos)
4265 return -ENOTTY;
4266
4267
4268 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4269 acs_flags &= (cap | PCI_ACS_EC);
4270
4271 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4272
4273 return acs_flags & ~ctrl ? 0 : 1;
4274}
4275
4276static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
4277{
4278
4279
4280
4281
4282
4283
4284
4285
4286
4287 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4288 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4289
4290 return acs_flags ? 0 : 1;
4291}
4292
4293static const struct pci_dev_acs_enabled {
4294 u16 vendor;
4295 u16 device;
4296 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4297} pci_dev_acs_enabled[] = {
4298 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4299 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4300 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4301 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4302 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4303 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
4304 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4305 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
4306 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4307 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
4308 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
4309 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4310 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4311 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4312 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4313 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4314 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4315 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4316 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4317 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4318 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4319 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4320 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4321 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4322 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4323 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4324 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4325 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4326 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4327 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4328 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
4329
4330 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4331 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4332 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4333 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4334 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4335 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4336 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4337
4338 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4339 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4340 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4341 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4342 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4343 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4344 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4345 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4346
4347 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4348 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4349 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4350
4351 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4352 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4353 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4354 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4355
4356 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4357 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4358 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4359 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
4360
4361 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4362 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
4363
4364 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4365 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
4366
4367 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
4368 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
4369 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs },
4370 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs },
4371
4372 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
4373
4374 { PCI_VENDOR_ID_AMCC, 0xE004, pci_quirk_xgene_acs },
4375
4376 { PCI_VENDOR_ID_AMPERE, 0xE005, pci_quirk_xgene_acs },
4377 { PCI_VENDOR_ID_AMPERE, 0xE006, pci_quirk_xgene_acs },
4378 { PCI_VENDOR_ID_AMPERE, 0xE007, pci_quirk_xgene_acs },
4379 { PCI_VENDOR_ID_AMPERE, 0xE008, pci_quirk_xgene_acs },
4380 { PCI_VENDOR_ID_AMPERE, 0xE009, pci_quirk_xgene_acs },
4381 { PCI_VENDOR_ID_AMPERE, 0xE00A, pci_quirk_xgene_acs },
4382 { PCI_VENDOR_ID_AMPERE, 0xE00B, pci_quirk_xgene_acs },
4383 { PCI_VENDOR_ID_AMPERE, 0xE00C, pci_quirk_xgene_acs },
4384 { 0 }
4385};
4386
4387int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4388{
4389 const struct pci_dev_acs_enabled *i;
4390 int ret;
4391
4392
4393
4394
4395
4396
4397
4398 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4399 if ((i->vendor == dev->vendor ||
4400 i->vendor == (u16)PCI_ANY_ID) &&
4401 (i->device == dev->device ||
4402 i->device == (u16)PCI_ANY_ID)) {
4403 ret = i->acs_enabled(dev, acs_flags);
4404 if (ret >= 0)
4405 return ret;
4406 }
4407 }
4408
4409 return -ENOTTY;
4410}
4411
4412
4413#define INTEL_LPC_RCBA_REG 0xf0
4414
4415#define INTEL_LPC_RCBA_MASK 0xffffc000
4416
4417#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4418
4419
4420#define INTEL_BSPR_REG 0x1104
4421
4422#define INTEL_BSPR_REG_BPNPD (1 << 8)
4423
4424#define INTEL_BSPR_REG_BPPD (1 << 9)
4425
4426
4427#define INTEL_UPDCR_REG 0x1114
4428
4429#define INTEL_UPDCR_REG_MASK 0x3f
4430
4431static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4432{
4433 u32 rcba, bspr, updcr;
4434 void __iomem *rcba_mem;
4435
4436
4437
4438
4439
4440
4441 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4442 INTEL_LPC_RCBA_REG, &rcba);
4443 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4444 return -EINVAL;
4445
4446 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4447 PAGE_ALIGN(INTEL_UPDCR_REG));
4448 if (!rcba_mem)
4449 return -ENOMEM;
4450
4451
4452
4453
4454
4455
4456
4457
4458 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4459 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4460 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4461 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4462 if (updcr & INTEL_UPDCR_REG_MASK) {
4463 pci_info(dev, "Disabling UPDCR peer decodes\n");
4464 updcr &= ~INTEL_UPDCR_REG_MASK;
4465 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4466 }
4467 }
4468
4469 iounmap(rcba_mem);
4470 return 0;
4471}
4472
4473
4474#define INTEL_MPC_REG 0xd8
4475
4476#define INTEL_MPC_REG_IRBNCE (1 << 26)
4477
4478static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4479{
4480 u32 mpc;
4481
4482
4483
4484
4485
4486
4487
4488 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4489 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4490 pci_info(dev, "Enabling MPC IRBNCE\n");
4491 mpc |= INTEL_MPC_REG_IRBNCE;
4492 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4493 }
4494}
4495
4496static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4497{
4498 if (!pci_quirk_intel_pch_acs_match(dev))
4499 return -ENOTTY;
4500
4501 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4502 pci_warn(dev, "Failed to enable Intel PCH ACS quirk\n");
4503 return 0;
4504 }
4505
4506 pci_quirk_enable_intel_rp_mpc_acs(dev);
4507
4508 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4509
4510 pci_info(dev, "Intel PCH root port ACS workaround enabled\n");
4511
4512 return 0;
4513}
4514
4515static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4516{
4517 int pos;
4518 u32 cap, ctrl;
4519
4520 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4521 return -ENOTTY;
4522
4523 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4524 if (!pos)
4525 return -ENOTTY;
4526
4527 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4528 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4529
4530 ctrl |= (cap & PCI_ACS_SV);
4531 ctrl |= (cap & PCI_ACS_RR);
4532 ctrl |= (cap & PCI_ACS_CR);
4533 ctrl |= (cap & PCI_ACS_UF);
4534
4535 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4536
4537 pci_info(dev, "Intel SPT PCH root port ACS workaround enabled\n");
4538
4539 return 0;
4540}
4541
4542static const struct pci_dev_enable_acs {
4543 u16 vendor;
4544 u16 device;
4545 int (*enable_acs)(struct pci_dev *dev);
4546} pci_dev_enable_acs[] = {
4547 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
4548 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
4549 { 0 }
4550};
4551
4552int pci_dev_specific_enable_acs(struct pci_dev *dev)
4553{
4554 const struct pci_dev_enable_acs *i;
4555 int ret;
4556
4557 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4558 if ((i->vendor == dev->vendor ||
4559 i->vendor == (u16)PCI_ANY_ID) &&
4560 (i->device == dev->device ||
4561 i->device == (u16)PCI_ANY_ID)) {
4562 ret = i->enable_acs(dev);
4563 if (ret >= 0)
4564 return ret;
4565 }
4566 }
4567
4568 return -ENOTTY;
4569}
4570
4571
4572
4573
4574
4575
4576
4577
4578static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4579{
4580 int pos, i = 0;
4581 u8 next_cap;
4582 u16 reg16, *cap;
4583 struct pci_cap_saved_state *state;
4584
4585
4586 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4587 return;
4588
4589
4590 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4591 if (!pos)
4592 return;
4593
4594
4595
4596
4597
4598 pci_read_config_byte(pdev, pos + 1, &next_cap);
4599 if (next_cap)
4600 return;
4601
4602
4603
4604
4605
4606
4607
4608
4609
4610 pos = 0x50;
4611 pci_read_config_word(pdev, pos, ®16);
4612 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4613 u32 status;
4614#ifndef PCI_EXP_SAVE_REGS
4615#define PCI_EXP_SAVE_REGS 7
4616#endif
4617 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4618
4619 pdev->pcie_cap = pos;
4620 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
4621 pdev->pcie_flags_reg = reg16;
4622 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
4623 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4624
4625 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4626 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4627 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4628 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4629
4630 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4631 return;
4632
4633
4634
4635
4636 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4637 if (!state)
4638 return;
4639
4640 state->cap.cap_nr = PCI_CAP_ID_EXP;
4641 state->cap.cap_extended = 0;
4642 state->cap.size = size;
4643 cap = (u16 *)&state->cap.data[0];
4644 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4645 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4646 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4647 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4648 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4649 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4650 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4651 hlist_add_head(&state->next, &pdev->saved_cap_space);
4652 }
4653}
4654DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
4655
4656
4657static void quirk_intel_no_flr(struct pci_dev *dev)
4658{
4659 dev->dev_flags |= PCI_DEV_FLAGS_NO_FLR_RESET;
4660}
4661DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1502, quirk_intel_no_flr);
4662DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x1503, quirk_intel_no_flr);
4663
4664static void quirk_no_ext_tags(struct pci_dev *pdev)
4665{
4666 struct pci_host_bridge *bridge = pci_find_host_bridge(pdev->bus);
4667
4668 if (!bridge)
4669 return;
4670
4671 bridge->no_ext_tags = 1;
4672 pci_info(pdev, "disabling Extended Tags (this device can't handle them)\n");
4673
4674 pci_walk_bus(bridge->bus, pci_configure_extended_tags, NULL);
4675}
4676DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0132, quirk_no_ext_tags);
4677DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0140, quirk_no_ext_tags);
4678DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0141, quirk_no_ext_tags);
4679DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0142, quirk_no_ext_tags);
4680DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0144, quirk_no_ext_tags);
4681DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0420, quirk_no_ext_tags);
4682DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, 0x0422, quirk_no_ext_tags);
4683
4684#ifdef CONFIG_PCI_ATS
4685
4686
4687
4688
4689static void quirk_no_ats(struct pci_dev *pdev)
4690{
4691 pci_info(pdev, "disabling ATS (broken on this device)\n");
4692 pdev->ats_cap = 0;
4693}
4694
4695
4696DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x98e4, quirk_no_ats);
4697#endif
4698
4699
4700static void quirk_fsl_no_msi(struct pci_dev *pdev)
4701{
4702 if (pci_pcie_type(pdev) == PCI_EXP_TYPE_ROOT_PORT)
4703 pdev->no_msi = 1;
4704}
4705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_FREESCALE, PCI_ANY_ID, quirk_fsl_no_msi);
4706
4707
4708
4709
4710
4711
4712
4713
4714
4715
4716static void quirk_gpu_hda(struct pci_dev *hda)
4717{
4718 struct pci_dev *gpu;
4719
4720 if (PCI_FUNC(hda->devfn) != 1)
4721 return;
4722
4723 gpu = pci_get_domain_bus_and_slot(pci_domain_nr(hda->bus),
4724 hda->bus->number,
4725 PCI_DEVFN(PCI_SLOT(hda->devfn), 0));
4726 if (!gpu || (gpu->class >> 16) != PCI_BASE_CLASS_DISPLAY) {
4727 pci_dev_put(gpu);
4728 return;
4729 }
4730
4731 if (!device_link_add(&hda->dev, &gpu->dev,
4732 DL_FLAG_STATELESS | DL_FLAG_PM_RUNTIME))
4733 pci_err(hda, "cannot link HDA to GPU %s\n", pci_name(gpu));
4734
4735 pm_runtime_allow(&hda->dev);
4736 pci_dev_put(gpu);
4737}
4738DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
4739 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4740DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_AMD, PCI_ANY_ID,
4741 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4742DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID,
4743 PCI_CLASS_MULTIMEDIA_HD_AUDIO, 8, quirk_gpu_hda);
4744