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16#include <linux/io.h>
17#include <linux/gpio/driver.h>
18#include <linux/of.h>
19#include <linux/of_address.h>
20#include <linux/of_device.h>
21#include <linux/of_irq.h>
22#include <linux/pinctrl/consumer.h>
23#include <linux/pinctrl/machine.h>
24#include <linux/pinctrl/pinconf.h>
25#include <linux/pinctrl/pinconf-generic.h>
26#include <linux/pinctrl/pinctrl.h>
27#include <linux/pinctrl/pinmux.h>
28#include <linux/platform_device.h>
29#include <linux/slab.h>
30#include <linux/bitops.h>
31#include <linux/regmap.h>
32#include <linux/mfd/syscon.h>
33#include <linux/delay.h>
34#include <linux/interrupt.h>
35#include <linux/pm.h>
36#include <dt-bindings/pinctrl/mt65xx.h>
37
38#include "../core.h"
39#include "../pinconf.h"
40#include "../pinctrl-utils.h"
41#include "pinctrl-mtk-common.h"
42
43#define MAX_GPIO_MODE_PER_REG 5
44#define GPIO_MODE_BITS 3
45#define GPIO_MODE_PREFIX "GPIO"
46
47static const char * const mtk_gpio_functions[] = {
48 "func0", "func1", "func2", "func3",
49 "func4", "func5", "func6", "func7",
50 "func8", "func9", "func10", "func11",
51 "func12", "func13", "func14", "func15",
52};
53
54
55
56
57
58
59
60static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
61 unsigned long pin)
62{
63 if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
64 return pctl->regmap2;
65 return pctl->regmap1;
66}
67
68static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
69{
70
71 return ((pin >> 4) & pctl->devdata->port_mask)
72 << pctl->devdata->port_shf;
73}
74
75static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
76 struct pinctrl_gpio_range *range, unsigned offset,
77 bool input)
78{
79 unsigned int reg_addr;
80 unsigned int bit;
81 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
82
83 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
84 bit = BIT(offset & 0xf);
85
86 if (pctl->devdata->spec_dir_set)
87 pctl->devdata->spec_dir_set(®_addr, offset);
88
89 if (input)
90
91 reg_addr = CLR_ADDR(reg_addr, pctl);
92 else
93 reg_addr = SET_ADDR(reg_addr, pctl);
94
95 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
96 return 0;
97}
98
99static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
100{
101 unsigned int reg_addr;
102 unsigned int bit;
103 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
104
105 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
106 bit = BIT(offset & 0xf);
107
108 if (value)
109 reg_addr = SET_ADDR(reg_addr, pctl);
110 else
111 reg_addr = CLR_ADDR(reg_addr, pctl);
112
113 regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
114}
115
116static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
117 int value, enum pin_config_param arg)
118{
119 unsigned int reg_addr, offset;
120 unsigned int bit;
121
122
123
124
125
126 if (!pctl->devdata->spec_ies_smt_set &&
127 pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
128 arg == PIN_CONFIG_INPUT_ENABLE)
129 return -EINVAL;
130
131 if (!pctl->devdata->spec_ies_smt_set &&
132 pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
133 arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
134 return -EINVAL;
135
136
137
138
139
140 if (pctl->devdata->spec_ies_smt_set) {
141 return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
142 pin, pctl->devdata->port_align, value, arg);
143 }
144
145 bit = BIT(pin & 0xf);
146
147 if (arg == PIN_CONFIG_INPUT_ENABLE)
148 offset = pctl->devdata->ies_offset;
149 else
150 offset = pctl->devdata->smt_offset;
151
152 if (value)
153 reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
154 else
155 reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
156
157 regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
158 return 0;
159}
160
161int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
162 const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
163 unsigned int pin, unsigned char align, int value)
164{
165 unsigned int i, reg_addr, bit;
166
167 for (i = 0; i < info_num; i++) {
168 if (pin >= ies_smt_infos[i].start &&
169 pin <= ies_smt_infos[i].end) {
170 break;
171 }
172 }
173
174 if (i == info_num)
175 return -EINVAL;
176
177 if (value)
178 reg_addr = ies_smt_infos[i].offset + align;
179 else
180 reg_addr = ies_smt_infos[i].offset + (align << 1);
181
182 bit = BIT(ies_smt_infos[i].bit);
183 regmap_write(regmap, reg_addr, bit);
184 return 0;
185}
186
187static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
188 struct mtk_pinctrl *pctl, unsigned long pin) {
189 int i;
190
191 for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
192 const struct mtk_pin_drv_grp *pin_drv =
193 pctl->devdata->pin_drv_grp + i;
194 if (pin == pin_drv->pin)
195 return pin_drv;
196 }
197
198 return NULL;
199}
200
201static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
202 unsigned int pin, unsigned char driving)
203{
204 const struct mtk_pin_drv_grp *pin_drv;
205 unsigned int val;
206 unsigned int bits, mask, shift;
207 const struct mtk_drv_group_desc *drv_grp;
208
209 if (pin >= pctl->devdata->npins)
210 return -EINVAL;
211
212 pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
213 if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
214 return -EINVAL;
215
216 drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
217 if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
218 && !(driving % drv_grp->step)) {
219 val = driving / drv_grp->step - 1;
220 bits = drv_grp->high_bit - drv_grp->low_bit + 1;
221 mask = BIT(bits) - 1;
222 shift = pin_drv->bit + drv_grp->low_bit;
223 mask <<= shift;
224 val <<= shift;
225 return regmap_update_bits(mtk_get_regmap(pctl, pin),
226 pin_drv->offset, mask, val);
227 }
228
229 return -EINVAL;
230}
231
232int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
233 const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
234 unsigned int info_num, unsigned int pin,
235 unsigned char align, bool isup, unsigned int r1r0)
236{
237 unsigned int i;
238 unsigned int reg_pupd, reg_set, reg_rst;
239 unsigned int bit_pupd, bit_r0, bit_r1;
240 const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
241 bool find = false;
242
243 for (i = 0; i < info_num; i++) {
244 if (pin == pupd_infos[i].pin) {
245 find = true;
246 break;
247 }
248 }
249
250 if (!find)
251 return -EINVAL;
252
253 spec_pupd_pin = pupd_infos + i;
254 reg_set = spec_pupd_pin->offset + align;
255 reg_rst = spec_pupd_pin->offset + (align << 1);
256
257 if (isup)
258 reg_pupd = reg_rst;
259 else
260 reg_pupd = reg_set;
261
262 bit_pupd = BIT(spec_pupd_pin->pupd_bit);
263 regmap_write(regmap, reg_pupd, bit_pupd);
264
265 bit_r0 = BIT(spec_pupd_pin->r0_bit);
266 bit_r1 = BIT(spec_pupd_pin->r1_bit);
267
268 switch (r1r0) {
269 case MTK_PUPD_SET_R1R0_00:
270 regmap_write(regmap, reg_rst, bit_r0);
271 regmap_write(regmap, reg_rst, bit_r1);
272 break;
273 case MTK_PUPD_SET_R1R0_01:
274 regmap_write(regmap, reg_set, bit_r0);
275 regmap_write(regmap, reg_rst, bit_r1);
276 break;
277 case MTK_PUPD_SET_R1R0_10:
278 regmap_write(regmap, reg_rst, bit_r0);
279 regmap_write(regmap, reg_set, bit_r1);
280 break;
281 case MTK_PUPD_SET_R1R0_11:
282 regmap_write(regmap, reg_set, bit_r0);
283 regmap_write(regmap, reg_set, bit_r1);
284 break;
285 default:
286 return -EINVAL;
287 }
288
289 return 0;
290}
291
292static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
293 unsigned int pin, bool enable, bool isup, unsigned int arg)
294{
295 unsigned int bit;
296 unsigned int reg_pullen, reg_pullsel, r1r0;
297 int ret;
298
299
300
301
302
303 if (pctl->devdata->spec_pull_set) {
304
305
306
307 r1r0 = enable ? arg : MTK_PUPD_SET_R1R0_00;
308 ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
309 pin, pctl->devdata->port_align, isup, r1r0);
310 if (!ret)
311 return 0;
312 }
313
314
315 if (arg != 0 && arg != 1) {
316 dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
317 arg, pin);
318 return -EINVAL;
319 }
320
321 bit = BIT(pin & 0xf);
322 if (enable)
323 reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
324 pctl->devdata->pullen_offset, pctl);
325 else
326 reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
327 pctl->devdata->pullen_offset, pctl);
328
329 if (isup)
330 reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
331 pctl->devdata->pullsel_offset, pctl);
332 else
333 reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
334 pctl->devdata->pullsel_offset, pctl);
335
336 regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
337 regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
338 return 0;
339}
340
341static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
342 unsigned int pin, enum pin_config_param param,
343 enum pin_config_param arg)
344{
345 int ret = 0;
346 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
347
348 switch (param) {
349 case PIN_CONFIG_BIAS_DISABLE:
350 ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
351 break;
352 case PIN_CONFIG_BIAS_PULL_UP:
353 ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
354 break;
355 case PIN_CONFIG_BIAS_PULL_DOWN:
356 ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
357 break;
358 case PIN_CONFIG_INPUT_ENABLE:
359 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
360 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
361 break;
362 case PIN_CONFIG_OUTPUT:
363 mtk_gpio_set(pctl->chip, pin, arg);
364 ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
365 break;
366 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
367 mtk_pmx_gpio_set_direction(pctldev, NULL, pin, true);
368 ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
369 break;
370 case PIN_CONFIG_DRIVE_STRENGTH:
371 ret = mtk_pconf_set_driving(pctl, pin, arg);
372 break;
373 default:
374 ret = -EINVAL;
375 }
376
377 return ret;
378}
379
380static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
381 unsigned group,
382 unsigned long *config)
383{
384 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
385
386 *config = pctl->groups[group].config;
387
388 return 0;
389}
390
391static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
392 unsigned long *configs, unsigned num_configs)
393{
394 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
395 struct mtk_pinctrl_group *g = &pctl->groups[group];
396 int i, ret;
397
398 for (i = 0; i < num_configs; i++) {
399 ret = mtk_pconf_parse_conf(pctldev, g->pin,
400 pinconf_to_config_param(configs[i]),
401 pinconf_to_config_argument(configs[i]));
402 if (ret < 0)
403 return ret;
404
405 g->config = configs[i];
406 }
407
408 return 0;
409}
410
411static const struct pinconf_ops mtk_pconf_ops = {
412 .pin_config_group_get = mtk_pconf_group_get,
413 .pin_config_group_set = mtk_pconf_group_set,
414};
415
416static struct mtk_pinctrl_group *
417mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
418{
419 int i;
420
421 for (i = 0; i < pctl->ngroups; i++) {
422 struct mtk_pinctrl_group *grp = pctl->groups + i;
423
424 if (grp->pin == pin)
425 return grp;
426 }
427
428 return NULL;
429}
430
431static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
432 struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
433{
434 const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
435 const struct mtk_desc_function *func = pin->functions;
436
437 while (func && func->name) {
438 if (func->muxval == fnum)
439 return func;
440 func++;
441 }
442
443 return NULL;
444}
445
446static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
447 u32 pin_num, u32 fnum)
448{
449 int i;
450
451 for (i = 0; i < pctl->devdata->npins; i++) {
452 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
453
454 if (pin->pin.number == pin_num) {
455 const struct mtk_desc_function *func =
456 pin->functions;
457
458 while (func && func->name) {
459 if (func->muxval == fnum)
460 return true;
461 func++;
462 }
463
464 break;
465 }
466 }
467
468 return false;
469}
470
471static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
472 u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
473 struct pinctrl_map **map, unsigned *reserved_maps,
474 unsigned *num_maps)
475{
476 bool ret;
477
478 if (*num_maps == *reserved_maps)
479 return -ENOSPC;
480
481 (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
482 (*map)[*num_maps].data.mux.group = grp->name;
483
484 ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
485 if (!ret) {
486 dev_err(pctl->dev, "invalid function %d on pin %d .\n",
487 fnum, pin);
488 return -EINVAL;
489 }
490
491 (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
492 (*num_maps)++;
493
494 return 0;
495}
496
497static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
498 struct device_node *node,
499 struct pinctrl_map **map,
500 unsigned *reserved_maps,
501 unsigned *num_maps)
502{
503 struct property *pins;
504 u32 pinfunc, pin, func;
505 int num_pins, num_funcs, maps_per_pin;
506 unsigned long *configs;
507 unsigned int num_configs;
508 bool has_config = false;
509 int i, err;
510 unsigned reserve = 0;
511 struct mtk_pinctrl_group *grp;
512 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
513
514 pins = of_find_property(node, "pinmux", NULL);
515 if (!pins) {
516 dev_err(pctl->dev, "missing pins property in node %s .\n",
517 node->name);
518 return -EINVAL;
519 }
520
521 err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
522 &num_configs);
523 if (err)
524 return err;
525
526 if (num_configs)
527 has_config = true;
528
529 num_pins = pins->length / sizeof(u32);
530 num_funcs = num_pins;
531 maps_per_pin = 0;
532 if (num_funcs)
533 maps_per_pin++;
534 if (has_config && num_pins >= 1)
535 maps_per_pin++;
536
537 if (!num_pins || !maps_per_pin) {
538 err = -EINVAL;
539 goto exit;
540 }
541
542 reserve = num_pins * maps_per_pin;
543
544 err = pinctrl_utils_reserve_map(pctldev, map,
545 reserved_maps, num_maps, reserve);
546 if (err < 0)
547 goto exit;
548
549 for (i = 0; i < num_pins; i++) {
550 err = of_property_read_u32_index(node, "pinmux",
551 i, &pinfunc);
552 if (err)
553 goto exit;
554
555 pin = MTK_GET_PIN_NO(pinfunc);
556 func = MTK_GET_PIN_FUNC(pinfunc);
557
558 if (pin >= pctl->devdata->npins ||
559 func >= ARRAY_SIZE(mtk_gpio_functions)) {
560 dev_err(pctl->dev, "invalid pins value.\n");
561 err = -EINVAL;
562 goto exit;
563 }
564
565 grp = mtk_pctrl_find_group_by_pin(pctl, pin);
566 if (!grp) {
567 dev_err(pctl->dev, "unable to match pin %d to group\n",
568 pin);
569 err = -EINVAL;
570 goto exit;
571 }
572
573 err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
574 reserved_maps, num_maps);
575 if (err < 0)
576 goto exit;
577
578 if (has_config) {
579 err = pinctrl_utils_add_map_configs(pctldev, map,
580 reserved_maps, num_maps, grp->name,
581 configs, num_configs,
582 PIN_MAP_TYPE_CONFIGS_GROUP);
583 if (err < 0)
584 goto exit;
585 }
586 }
587
588 err = 0;
589
590exit:
591 kfree(configs);
592 return err;
593}
594
595static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
596 struct device_node *np_config,
597 struct pinctrl_map **map, unsigned *num_maps)
598{
599 struct device_node *np;
600 unsigned reserved_maps;
601 int ret;
602
603 *map = NULL;
604 *num_maps = 0;
605 reserved_maps = 0;
606
607 for_each_child_of_node(np_config, np) {
608 ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
609 &reserved_maps, num_maps);
610 if (ret < 0) {
611 pinctrl_utils_free_map(pctldev, *map, *num_maps);
612 of_node_put(np);
613 return ret;
614 }
615 }
616
617 return 0;
618}
619
620static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
621{
622 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
623
624 return pctl->ngroups;
625}
626
627static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
628 unsigned group)
629{
630 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
631
632 return pctl->groups[group].name;
633}
634
635static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
636 unsigned group,
637 const unsigned **pins,
638 unsigned *num_pins)
639{
640 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
641
642 *pins = (unsigned *)&pctl->groups[group].pin;
643 *num_pins = 1;
644
645 return 0;
646}
647
648static const struct pinctrl_ops mtk_pctrl_ops = {
649 .dt_node_to_map = mtk_pctrl_dt_node_to_map,
650 .dt_free_map = pinctrl_utils_free_map,
651 .get_groups_count = mtk_pctrl_get_groups_count,
652 .get_group_name = mtk_pctrl_get_group_name,
653 .get_group_pins = mtk_pctrl_get_group_pins,
654};
655
656static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
657{
658 return ARRAY_SIZE(mtk_gpio_functions);
659}
660
661static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
662 unsigned selector)
663{
664 return mtk_gpio_functions[selector];
665}
666
667static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
668 unsigned function,
669 const char * const **groups,
670 unsigned * const num_groups)
671{
672 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
673
674 *groups = pctl->grp_names;
675 *num_groups = pctl->ngroups;
676
677 return 0;
678}
679
680static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
681 unsigned long pin, unsigned long mode)
682{
683 unsigned int reg_addr;
684 unsigned char bit;
685 unsigned int val;
686 unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
687 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
688
689 if (pctl->devdata->spec_pinmux_set)
690 pctl->devdata->spec_pinmux_set(mtk_get_regmap(pctl, pin),
691 pin, mode);
692
693 reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
694 + pctl->devdata->pinmux_offset;
695
696 mode &= mask;
697 bit = pin % MAX_GPIO_MODE_PER_REG;
698 mask <<= (GPIO_MODE_BITS * bit);
699 val = (mode << (GPIO_MODE_BITS * bit));
700 return regmap_update_bits(mtk_get_regmap(pctl, pin),
701 reg_addr, mask, val);
702}
703
704static const struct mtk_desc_pin *
705mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
706{
707 int i;
708 const struct mtk_desc_pin *pin;
709
710 for (i = 0; i < pctl->devdata->npins; i++) {
711 pin = pctl->devdata->pins + i;
712 if (pin->eint.eintnum == eint_num)
713 return pin;
714 }
715
716 return NULL;
717}
718
719static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
720 unsigned function,
721 unsigned group)
722{
723 bool ret;
724 const struct mtk_desc_function *desc;
725 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
726 struct mtk_pinctrl_group *g = pctl->groups + group;
727
728 ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
729 if (!ret) {
730 dev_err(pctl->dev, "invalid function %d on group %d .\n",
731 function, group);
732 return -EINVAL;
733 }
734
735 desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
736 if (!desc)
737 return -EINVAL;
738 mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
739 return 0;
740}
741
742static int mtk_pmx_find_gpio_mode(struct mtk_pinctrl *pctl,
743 unsigned offset)
744{
745 const struct mtk_desc_pin *pin = pctl->devdata->pins + offset;
746 const struct mtk_desc_function *func = pin->functions;
747
748 while (func && func->name) {
749 if (!strncmp(func->name, GPIO_MODE_PREFIX,
750 sizeof(GPIO_MODE_PREFIX)-1))
751 return func->muxval;
752 func++;
753 }
754 return -EINVAL;
755}
756
757static int mtk_pmx_gpio_request_enable(struct pinctrl_dev *pctldev,
758 struct pinctrl_gpio_range *range,
759 unsigned offset)
760{
761 int muxval;
762 struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
763
764 muxval = mtk_pmx_find_gpio_mode(pctl, offset);
765
766 if (muxval < 0) {
767 dev_err(pctl->dev, "invalid gpio pin %d.\n", offset);
768 return -EINVAL;
769 }
770
771 mtk_pmx_set_mode(pctldev, offset, muxval);
772 mtk_pconf_set_ies_smt(pctl, offset, 1, PIN_CONFIG_INPUT_ENABLE);
773
774 return 0;
775}
776
777static const struct pinmux_ops mtk_pmx_ops = {
778 .get_functions_count = mtk_pmx_get_funcs_cnt,
779 .get_function_name = mtk_pmx_get_func_name,
780 .get_function_groups = mtk_pmx_get_func_groups,
781 .set_mux = mtk_pmx_set_mux,
782 .gpio_set_direction = mtk_pmx_gpio_set_direction,
783 .gpio_request_enable = mtk_pmx_gpio_request_enable,
784};
785
786static int mtk_gpio_direction_input(struct gpio_chip *chip,
787 unsigned offset)
788{
789 return pinctrl_gpio_direction_input(chip->base + offset);
790}
791
792static int mtk_gpio_direction_output(struct gpio_chip *chip,
793 unsigned offset, int value)
794{
795 mtk_gpio_set(chip, offset, value);
796 return pinctrl_gpio_direction_output(chip->base + offset);
797}
798
799static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
800{
801 unsigned int reg_addr;
802 unsigned int bit;
803 unsigned int read_val = 0;
804
805 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
806
807 reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
808 bit = BIT(offset & 0xf);
809
810 if (pctl->devdata->spec_dir_set)
811 pctl->devdata->spec_dir_set(®_addr, offset);
812
813 regmap_read(pctl->regmap1, reg_addr, &read_val);
814 return !(read_val & bit);
815}
816
817static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
818{
819 unsigned int reg_addr;
820 unsigned int bit;
821 unsigned int read_val = 0;
822 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
823
824 reg_addr = mtk_get_port(pctl, offset) +
825 pctl->devdata->din_offset;
826
827 bit = BIT(offset & 0xf);
828 regmap_read(pctl->regmap1, reg_addr, &read_val);
829 return !!(read_val & bit);
830}
831
832static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
833{
834 const struct mtk_desc_pin *pin;
835 struct mtk_pinctrl *pctl = gpiochip_get_data(chip);
836 int irq;
837
838 pin = pctl->devdata->pins + offset;
839 if (pin->eint.eintnum == NO_EINT_SUPPORT)
840 return -EINVAL;
841
842 irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
843 if (!irq)
844 return -EINVAL;
845
846 return irq;
847}
848
849static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
850{
851 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
852 const struct mtk_desc_pin *pin;
853 int ret;
854
855 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
856
857 if (!pin) {
858 dev_err(pctl->dev, "Can not find pin\n");
859 return -EINVAL;
860 }
861
862 ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
863 if (ret) {
864 dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
865 irqd_to_hwirq(d));
866 return ret;
867 }
868
869
870 mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
871
872 mtk_pmx_gpio_set_direction(pctl->pctl_dev, NULL, pin->pin.number, true);
873
874 mtk_pconf_set_ies_smt(pctl, pin->pin.number, 1, PIN_CONFIG_INPUT_ENABLE);
875
876 return 0;
877}
878
879static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
880{
881 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
882 const struct mtk_desc_pin *pin;
883
884 pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
885
886 if (!pin) {
887 dev_err(pctl->dev, "Can not find pin\n");
888 return;
889 }
890
891 gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
892}
893
894static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
895 unsigned int eint_num, unsigned int offset)
896{
897 unsigned int eint_base = 0;
898 void __iomem *reg;
899
900 if (eint_num >= pctl->devdata->ap_num)
901 eint_base = pctl->devdata->ap_num;
902
903 reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
904
905 return reg;
906}
907
908
909
910
911
912static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
913 unsigned int eint_num)
914{
915 unsigned int sens;
916 unsigned int bit = BIT(eint_num % 32);
917 const struct mtk_eint_offsets *eint_offsets =
918 &pctl->devdata->eint_offsets;
919
920 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
921 eint_offsets->sens);
922
923 if (readl(reg) & bit)
924 sens = MT_LEVEL_SENSITIVE;
925 else
926 sens = MT_EDGE_SENSITIVE;
927
928 if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
929 return 1;
930 else
931 return 0;
932}
933
934
935
936
937
938static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
939 unsigned int eint_num)
940{
941 unsigned int bit = BIT(eint_num % 32);
942 const struct mtk_eint_offsets *eint_offsets =
943 &pctl->devdata->eint_offsets;
944
945 void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
946 eint_offsets->mask);
947
948 return !!(readl(reg) & bit);
949}
950
951static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
952{
953 int start_level, curr_level;
954 unsigned int reg_offset;
955 const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
956 u32 mask = BIT(hwirq & 0x1f);
957 u32 port = (hwirq >> 5) & eint_offsets->port_mask;
958 void __iomem *reg = pctl->eint_reg_base + (port << 2);
959 const struct mtk_desc_pin *pin;
960
961 pin = mtk_find_pin_by_eint_num(pctl, hwirq);
962 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
963 do {
964 start_level = curr_level;
965 if (start_level)
966 reg_offset = eint_offsets->pol_clr;
967 else
968 reg_offset = eint_offsets->pol_set;
969 writel(mask, reg + reg_offset);
970
971 curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
972 } while (start_level != curr_level);
973
974 return start_level;
975}
976
977static void mtk_eint_mask(struct irq_data *d)
978{
979 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
980 const struct mtk_eint_offsets *eint_offsets =
981 &pctl->devdata->eint_offsets;
982 u32 mask = BIT(d->hwirq & 0x1f);
983 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
984 eint_offsets->mask_set);
985
986 writel(mask, reg);
987}
988
989static void mtk_eint_unmask(struct irq_data *d)
990{
991 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
992 const struct mtk_eint_offsets *eint_offsets =
993 &pctl->devdata->eint_offsets;
994 u32 mask = BIT(d->hwirq & 0x1f);
995 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
996 eint_offsets->mask_clr);
997
998 writel(mask, reg);
999
1000 if (pctl->eint_dual_edges[d->hwirq])
1001 mtk_eint_flip_edge(pctl, d->hwirq);
1002}
1003
1004static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
1005 unsigned debounce)
1006{
1007 struct mtk_pinctrl *pctl = dev_get_drvdata(chip->parent);
1008 int eint_num, virq, eint_offset;
1009 unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
1010 static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
1011 128000, 256000};
1012 const struct mtk_desc_pin *pin;
1013 struct irq_data *d;
1014
1015 pin = pctl->devdata->pins + offset;
1016 if (pin->eint.eintnum == NO_EINT_SUPPORT)
1017 return -EINVAL;
1018
1019 eint_num = pin->eint.eintnum;
1020 virq = irq_find_mapping(pctl->domain, eint_num);
1021 eint_offset = (eint_num % 4) * 8;
1022 d = irq_get_irq_data(virq);
1023
1024 set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
1025 clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
1026 if (!mtk_eint_can_en_debounce(pctl, eint_num))
1027 return -ENOSYS;
1028
1029 dbnc = ARRAY_SIZE(debounce_time);
1030 for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
1031 if (debounce <= debounce_time[i]) {
1032 dbnc = i;
1033 break;
1034 }
1035 }
1036
1037 if (!mtk_eint_get_mask(pctl, eint_num)) {
1038 mtk_eint_mask(d);
1039 unmask = 1;
1040 } else {
1041 unmask = 0;
1042 }
1043
1044 clr_bit = 0xff << eint_offset;
1045 writel(clr_bit, pctl->eint_reg_base + clr_offset);
1046
1047 bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
1048 eint_offset;
1049 rst = EINT_DBNC_RST_BIT << eint_offset;
1050 writel(rst | bit, pctl->eint_reg_base + set_offset);
1051
1052
1053
1054 udelay(1);
1055 if (unmask == 1)
1056 mtk_eint_unmask(d);
1057
1058 return 0;
1059}
1060
1061static int mtk_gpio_set_config(struct gpio_chip *chip, unsigned offset,
1062 unsigned long config)
1063{
1064 u32 debounce;
1065
1066 if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
1067 return -ENOTSUPP;
1068
1069 debounce = pinconf_to_config_argument(config);
1070 return mtk_gpio_set_debounce(chip, offset, debounce);
1071}
1072
1073static const struct gpio_chip mtk_gpio_chip = {
1074 .owner = THIS_MODULE,
1075 .request = gpiochip_generic_request,
1076 .free = gpiochip_generic_free,
1077 .get_direction = mtk_gpio_get_direction,
1078 .direction_input = mtk_gpio_direction_input,
1079 .direction_output = mtk_gpio_direction_output,
1080 .get = mtk_gpio_get,
1081 .set = mtk_gpio_set,
1082 .to_irq = mtk_gpio_to_irq,
1083 .set_config = mtk_gpio_set_config,
1084 .of_gpio_n_cells = 2,
1085};
1086
1087static int mtk_eint_set_type(struct irq_data *d,
1088 unsigned int type)
1089{
1090 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1091 const struct mtk_eint_offsets *eint_offsets =
1092 &pctl->devdata->eint_offsets;
1093 u32 mask = BIT(d->hwirq & 0x1f);
1094 void __iomem *reg;
1095
1096 if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
1097 ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
1098 dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
1099 d->irq, d->hwirq, type);
1100 return -EINVAL;
1101 }
1102
1103 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
1104 pctl->eint_dual_edges[d->hwirq] = 1;
1105 else
1106 pctl->eint_dual_edges[d->hwirq] = 0;
1107
1108 if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
1109 reg = mtk_eint_get_offset(pctl, d->hwirq,
1110 eint_offsets->pol_clr);
1111 writel(mask, reg);
1112 } else {
1113 reg = mtk_eint_get_offset(pctl, d->hwirq,
1114 eint_offsets->pol_set);
1115 writel(mask, reg);
1116 }
1117
1118 if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
1119 reg = mtk_eint_get_offset(pctl, d->hwirq,
1120 eint_offsets->sens_clr);
1121 writel(mask, reg);
1122 } else {
1123 reg = mtk_eint_get_offset(pctl, d->hwirq,
1124 eint_offsets->sens_set);
1125 writel(mask, reg);
1126 }
1127
1128 if (pctl->eint_dual_edges[d->hwirq])
1129 mtk_eint_flip_edge(pctl, d->hwirq);
1130
1131 return 0;
1132}
1133
1134static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
1135{
1136 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1137 int shift = d->hwirq & 0x1f;
1138 int reg = d->hwirq >> 5;
1139
1140 if (on)
1141 pctl->wake_mask[reg] |= BIT(shift);
1142 else
1143 pctl->wake_mask[reg] &= ~BIT(shift);
1144
1145 return 0;
1146}
1147
1148static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
1149 void __iomem *eint_reg_base, u32 *buf)
1150{
1151 int port;
1152 void __iomem *reg;
1153
1154 for (port = 0; port < chip->ports; port++) {
1155 reg = eint_reg_base + (port << 2);
1156 writel_relaxed(~buf[port], reg + chip->mask_set);
1157 writel_relaxed(buf[port], reg + chip->mask_clr);
1158 }
1159}
1160
1161static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
1162 void __iomem *eint_reg_base, u32 *buf)
1163{
1164 int port;
1165 void __iomem *reg;
1166
1167 for (port = 0; port < chip->ports; port++) {
1168 reg = eint_reg_base + chip->mask + (port << 2);
1169 buf[port] = ~readl_relaxed(reg);
1170
1171 }
1172}
1173
1174static int mtk_eint_suspend(struct device *device)
1175{
1176 void __iomem *reg;
1177 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1178 const struct mtk_eint_offsets *eint_offsets =
1179 &pctl->devdata->eint_offsets;
1180
1181 reg = pctl->eint_reg_base;
1182 mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
1183 mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
1184
1185 return 0;
1186}
1187
1188static int mtk_eint_resume(struct device *device)
1189{
1190 struct mtk_pinctrl *pctl = dev_get_drvdata(device);
1191 const struct mtk_eint_offsets *eint_offsets =
1192 &pctl->devdata->eint_offsets;
1193
1194 mtk_eint_chip_write_mask(eint_offsets,
1195 pctl->eint_reg_base, pctl->cur_mask);
1196
1197 return 0;
1198}
1199
1200const struct dev_pm_ops mtk_eint_pm_ops = {
1201 .suspend_noirq = mtk_eint_suspend,
1202 .resume_noirq = mtk_eint_resume,
1203};
1204
1205static void mtk_eint_ack(struct irq_data *d)
1206{
1207 struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
1208 const struct mtk_eint_offsets *eint_offsets =
1209 &pctl->devdata->eint_offsets;
1210 u32 mask = BIT(d->hwirq & 0x1f);
1211 void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
1212 eint_offsets->ack);
1213
1214 writel(mask, reg);
1215}
1216
1217static struct irq_chip mtk_pinctrl_irq_chip = {
1218 .name = "mt-eint",
1219 .irq_disable = mtk_eint_mask,
1220 .irq_mask = mtk_eint_mask,
1221 .irq_unmask = mtk_eint_unmask,
1222 .irq_ack = mtk_eint_ack,
1223 .irq_set_type = mtk_eint_set_type,
1224 .irq_set_wake = mtk_eint_irq_set_wake,
1225 .irq_request_resources = mtk_pinctrl_irq_request_resources,
1226 .irq_release_resources = mtk_pinctrl_irq_release_resources,
1227};
1228
1229static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
1230{
1231 const struct mtk_eint_offsets *eint_offsets =
1232 &pctl->devdata->eint_offsets;
1233 void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
1234 unsigned int i;
1235
1236 for (i = 0; i < pctl->devdata->ap_num; i += 32) {
1237 writel(0xffffffff, reg);
1238 reg += 4;
1239 }
1240 return 0;
1241}
1242
1243static inline void
1244mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
1245{
1246 unsigned int rst, ctrl_offset;
1247 unsigned int bit, dbnc;
1248 const struct mtk_eint_offsets *eint_offsets =
1249 &pctl->devdata->eint_offsets;
1250
1251 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
1252 dbnc = readl(pctl->eint_reg_base + ctrl_offset);
1253 bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
1254 if ((bit & dbnc) > 0) {
1255 ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
1256 rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
1257 writel(rst, pctl->eint_reg_base + ctrl_offset);
1258 }
1259}
1260
1261static void mtk_eint_irq_handler(struct irq_desc *desc)
1262{
1263 struct irq_chip *chip = irq_desc_get_chip(desc);
1264 struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
1265 unsigned int status, eint_num;
1266 int offset, index, virq;
1267 const struct mtk_eint_offsets *eint_offsets =
1268 &pctl->devdata->eint_offsets;
1269 void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
1270 int dual_edges, start_level, curr_level;
1271 const struct mtk_desc_pin *pin;
1272
1273 chained_irq_enter(chip, desc);
1274 for (eint_num = 0;
1275 eint_num < pctl->devdata->ap_num;
1276 eint_num += 32, reg += 4) {
1277 status = readl(reg);
1278 while (status) {
1279 offset = __ffs(status);
1280 index = eint_num + offset;
1281 virq = irq_find_mapping(pctl->domain, index);
1282 status &= ~BIT(offset);
1283
1284 dual_edges = pctl->eint_dual_edges[index];
1285 if (dual_edges) {
1286
1287
1288 writel(BIT(offset), reg - eint_offsets->stat +
1289 eint_offsets->soft_clr);
1290
1291 pin = mtk_find_pin_by_eint_num(pctl, index);
1292 start_level = mtk_gpio_get(pctl->chip,
1293 pin->pin.number);
1294 }
1295
1296 generic_handle_irq(virq);
1297
1298 if (dual_edges) {
1299 curr_level = mtk_eint_flip_edge(pctl, index);
1300
1301
1302
1303 if (start_level != curr_level)
1304 writel(BIT(offset), reg -
1305 eint_offsets->stat +
1306 eint_offsets->soft_set);
1307 }
1308
1309 if (index < pctl->devdata->db_cnt)
1310 mtk_eint_debounce_process(pctl , index);
1311 }
1312 }
1313 chained_irq_exit(chip, desc);
1314}
1315
1316static int mtk_pctrl_build_state(struct platform_device *pdev)
1317{
1318 struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
1319 int i;
1320
1321 pctl->ngroups = pctl->devdata->npins;
1322
1323
1324 pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
1325 sizeof(*pctl->groups), GFP_KERNEL);
1326 if (!pctl->groups)
1327 return -ENOMEM;
1328
1329
1330 pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
1331 sizeof(*pctl->grp_names), GFP_KERNEL);
1332 if (!pctl->grp_names)
1333 return -ENOMEM;
1334
1335 for (i = 0; i < pctl->devdata->npins; i++) {
1336 const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
1337 struct mtk_pinctrl_group *group = pctl->groups + i;
1338
1339 group->name = pin->pin.name;
1340 group->pin = pin->pin.number;
1341
1342 pctl->grp_names[i] = pin->pin.name;
1343 }
1344
1345 return 0;
1346}
1347
1348int mtk_pctrl_init(struct platform_device *pdev,
1349 const struct mtk_pinctrl_devdata *data,
1350 struct regmap *regmap)
1351{
1352 struct pinctrl_pin_desc *pins;
1353 struct mtk_pinctrl *pctl;
1354 struct device_node *np = pdev->dev.of_node, *node;
1355 struct property *prop;
1356 struct resource *res;
1357 int i, ret, irq, ports_buf;
1358
1359 pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
1360 if (!pctl)
1361 return -ENOMEM;
1362
1363 platform_set_drvdata(pdev, pctl);
1364
1365 prop = of_find_property(np, "pins-are-numbered", NULL);
1366 if (!prop) {
1367 dev_err(&pdev->dev, "only support pins-are-numbered format\n");
1368 return -EINVAL;
1369 }
1370
1371 node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
1372 if (node) {
1373 pctl->regmap1 = syscon_node_to_regmap(node);
1374 if (IS_ERR(pctl->regmap1))
1375 return PTR_ERR(pctl->regmap1);
1376 } else if (regmap) {
1377 pctl->regmap1 = regmap;
1378 } else {
1379 dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
1380 return -EINVAL;
1381 }
1382
1383
1384 node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
1385 if (node) {
1386 pctl->regmap2 = syscon_node_to_regmap(node);
1387 if (IS_ERR(pctl->regmap2))
1388 return PTR_ERR(pctl->regmap2);
1389 }
1390
1391 pctl->devdata = data;
1392 ret = mtk_pctrl_build_state(pdev);
1393 if (ret) {
1394 dev_err(&pdev->dev, "build state failed: %d\n", ret);
1395 return -EINVAL;
1396 }
1397
1398 pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
1399 GFP_KERNEL);
1400 if (!pins)
1401 return -ENOMEM;
1402
1403 for (i = 0; i < pctl->devdata->npins; i++)
1404 pins[i] = pctl->devdata->pins[i].pin;
1405
1406 pctl->pctl_desc.name = dev_name(&pdev->dev);
1407 pctl->pctl_desc.owner = THIS_MODULE;
1408 pctl->pctl_desc.pins = pins;
1409 pctl->pctl_desc.npins = pctl->devdata->npins;
1410 pctl->pctl_desc.confops = &mtk_pconf_ops;
1411 pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
1412 pctl->pctl_desc.pmxops = &mtk_pmx_ops;
1413 pctl->dev = &pdev->dev;
1414
1415 pctl->pctl_dev = devm_pinctrl_register(&pdev->dev, &pctl->pctl_desc,
1416 pctl);
1417 if (IS_ERR(pctl->pctl_dev)) {
1418 dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
1419 return PTR_ERR(pctl->pctl_dev);
1420 }
1421
1422 pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
1423 if (!pctl->chip)
1424 return -ENOMEM;
1425
1426 *pctl->chip = mtk_gpio_chip;
1427 pctl->chip->ngpio = pctl->devdata->npins;
1428 pctl->chip->label = dev_name(&pdev->dev);
1429 pctl->chip->parent = &pdev->dev;
1430 pctl->chip->base = -1;
1431
1432 ret = gpiochip_add_data(pctl->chip, pctl);
1433 if (ret)
1434 return -EINVAL;
1435
1436
1437 ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
1438 0, 0, pctl->devdata->npins);
1439 if (ret) {
1440 ret = -EINVAL;
1441 goto chip_error;
1442 }
1443
1444 if (!of_property_read_bool(np, "interrupt-controller"))
1445 return 0;
1446
1447
1448 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449 if (!res) {
1450 dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
1451 ret = -EINVAL;
1452 goto chip_error;
1453 }
1454
1455 pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
1456 if (IS_ERR(pctl->eint_reg_base)) {
1457 ret = -EINVAL;
1458 goto chip_error;
1459 }
1460
1461 ports_buf = pctl->devdata->eint_offsets.ports;
1462 pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
1463 sizeof(*pctl->wake_mask), GFP_KERNEL);
1464 if (!pctl->wake_mask) {
1465 ret = -ENOMEM;
1466 goto chip_error;
1467 }
1468
1469 pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
1470 sizeof(*pctl->cur_mask), GFP_KERNEL);
1471 if (!pctl->cur_mask) {
1472 ret = -ENOMEM;
1473 goto chip_error;
1474 }
1475
1476 pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
1477 sizeof(int), GFP_KERNEL);
1478 if (!pctl->eint_dual_edges) {
1479 ret = -ENOMEM;
1480 goto chip_error;
1481 }
1482
1483 irq = irq_of_parse_and_map(np, 0);
1484 if (!irq) {
1485 dev_err(&pdev->dev, "couldn't parse and map irq\n");
1486 ret = -EINVAL;
1487 goto chip_error;
1488 }
1489
1490 pctl->domain = irq_domain_add_linear(np,
1491 pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
1492 if (!pctl->domain) {
1493 dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
1494 ret = -ENOMEM;
1495 goto chip_error;
1496 }
1497
1498 mtk_eint_init(pctl);
1499 for (i = 0; i < pctl->devdata->ap_num; i++) {
1500 int virq = irq_create_mapping(pctl->domain, i);
1501
1502 irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
1503 handle_level_irq);
1504 irq_set_chip_data(virq, pctl);
1505 }
1506
1507 irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
1508 return 0;
1509
1510chip_error:
1511 gpiochip_remove(pctl->chip);
1512 return ret;
1513}
1514
