1
2
3#include <linux/kernel.h>
4#include <linux/device.h>
5#include <linux/mutex.h>
6#include <linux/module.h>
7#include <linux/gpio.h>
8#include <linux/i2c.h>
9#include <linux/spi/spi.h>
10#include <linux/spi/mcp23s08.h>
11#include <linux/slab.h>
12#include <asm/byteorder.h>
13#include <linux/interrupt.h>
14#include <linux/of_device.h>
15#include <linux/regmap.h>
16#include <linux/pinctrl/pinctrl.h>
17#include <linux/pinctrl/pinconf.h>
18#include <linux/pinctrl/pinconf-generic.h>
19
20
21
22
23#define MCP_TYPE_S08 0
24#define MCP_TYPE_S17 1
25#define MCP_TYPE_008 2
26#define MCP_TYPE_017 3
27#define MCP_TYPE_S18 4
28#define MCP_TYPE_018 5
29
30#define MCP_MAX_DEV_PER_CS 8
31
32
33
34
35
36
37#define MCP_IODIR 0x00
38#define MCP_IPOL 0x01
39#define MCP_GPINTEN 0x02
40#define MCP_DEFVAL 0x03
41#define MCP_INTCON 0x04
42#define MCP_IOCON 0x05
43# define IOCON_MIRROR (1 << 6)
44# define IOCON_SEQOP (1 << 5)
45# define IOCON_HAEN (1 << 3)
46# define IOCON_ODR (1 << 2)
47# define IOCON_INTPOL (1 << 1)
48# define IOCON_INTCC (1)
49#define MCP_GPPU 0x06
50#define MCP_INTF 0x07
51#define MCP_INTCAP 0x08
52#define MCP_GPIO 0x09
53#define MCP_OLAT 0x0a
54
55struct mcp23s08;
56
57struct mcp23s08 {
58 u8 addr;
59 bool irq_active_high;
60 bool reg_shift;
61
62 u16 irq_rise;
63 u16 irq_fall;
64 int irq;
65 bool irq_controller;
66 int cached_gpio;
67
68 struct mutex lock;
69
70 struct gpio_chip chip;
71
72 struct regmap *regmap;
73 struct device *dev;
74
75 struct pinctrl_dev *pctldev;
76 struct pinctrl_desc pinctrl_desc;
77};
78
79static const struct reg_default mcp23x08_defaults[] = {
80 {.reg = MCP_IODIR, .def = 0xff},
81 {.reg = MCP_IPOL, .def = 0x00},
82 {.reg = MCP_GPINTEN, .def = 0x00},
83 {.reg = MCP_DEFVAL, .def = 0x00},
84 {.reg = MCP_INTCON, .def = 0x00},
85 {.reg = MCP_IOCON, .def = 0x00},
86 {.reg = MCP_GPPU, .def = 0x00},
87 {.reg = MCP_OLAT, .def = 0x00},
88};
89
90static const struct regmap_range mcp23x08_volatile_range = {
91 .range_min = MCP_INTF,
92 .range_max = MCP_GPIO,
93};
94
95static const struct regmap_access_table mcp23x08_volatile_table = {
96 .yes_ranges = &mcp23x08_volatile_range,
97 .n_yes_ranges = 1,
98};
99
100static const struct regmap_range mcp23x08_precious_range = {
101 .range_min = MCP_GPIO,
102 .range_max = MCP_GPIO,
103};
104
105static const struct regmap_access_table mcp23x08_precious_table = {
106 .yes_ranges = &mcp23x08_precious_range,
107 .n_yes_ranges = 1,
108};
109
110static const struct regmap_config mcp23x08_regmap = {
111 .reg_bits = 8,
112 .val_bits = 8,
113
114 .reg_stride = 1,
115 .volatile_table = &mcp23x08_volatile_table,
116 .precious_table = &mcp23x08_precious_table,
117 .reg_defaults = mcp23x08_defaults,
118 .num_reg_defaults = ARRAY_SIZE(mcp23x08_defaults),
119 .cache_type = REGCACHE_FLAT,
120 .max_register = MCP_OLAT,
121};
122
123static const struct reg_default mcp23x16_defaults[] = {
124 {.reg = MCP_IODIR << 1, .def = 0xffff},
125 {.reg = MCP_IPOL << 1, .def = 0x0000},
126 {.reg = MCP_GPINTEN << 1, .def = 0x0000},
127 {.reg = MCP_DEFVAL << 1, .def = 0x0000},
128 {.reg = MCP_INTCON << 1, .def = 0x0000},
129 {.reg = MCP_IOCON << 1, .def = 0x0000},
130 {.reg = MCP_GPPU << 1, .def = 0x0000},
131 {.reg = MCP_OLAT << 1, .def = 0x0000},
132};
133
134static const struct regmap_range mcp23x16_volatile_range = {
135 .range_min = MCP_INTF << 1,
136 .range_max = MCP_GPIO << 1,
137};
138
139static const struct regmap_access_table mcp23x16_volatile_table = {
140 .yes_ranges = &mcp23x16_volatile_range,
141 .n_yes_ranges = 1,
142};
143
144static const struct regmap_range mcp23x16_precious_range = {
145 .range_min = MCP_GPIO << 1,
146 .range_max = MCP_GPIO << 1,
147};
148
149static const struct regmap_access_table mcp23x16_precious_table = {
150 .yes_ranges = &mcp23x16_precious_range,
151 .n_yes_ranges = 1,
152};
153
154static const struct regmap_config mcp23x17_regmap = {
155 .reg_bits = 8,
156 .val_bits = 16,
157
158 .reg_stride = 2,
159 .max_register = MCP_OLAT << 1,
160 .volatile_table = &mcp23x16_volatile_table,
161 .precious_table = &mcp23x16_precious_table,
162 .reg_defaults = mcp23x16_defaults,
163 .num_reg_defaults = ARRAY_SIZE(mcp23x16_defaults),
164 .cache_type = REGCACHE_FLAT,
165 .val_format_endian = REGMAP_ENDIAN_LITTLE,
166};
167
168static int mcp_read(struct mcp23s08 *mcp, unsigned int reg, unsigned int *val)
169{
170 return regmap_read(mcp->regmap, reg << mcp->reg_shift, val);
171}
172
173static int mcp_write(struct mcp23s08 *mcp, unsigned int reg, unsigned int val)
174{
175 return regmap_write(mcp->regmap, reg << mcp->reg_shift, val);
176}
177
178static int mcp_set_mask(struct mcp23s08 *mcp, unsigned int reg,
179 unsigned int mask, bool enabled)
180{
181 u16 val = enabled ? 0xffff : 0x0000;
182 return regmap_update_bits(mcp->regmap, reg << mcp->reg_shift,
183 mask, val);
184}
185
186static int mcp_set_bit(struct mcp23s08 *mcp, unsigned int reg,
187 unsigned int pin, bool enabled)
188{
189 u16 mask = BIT(pin);
190 return mcp_set_mask(mcp, reg, mask, enabled);
191}
192
193static const struct pinctrl_pin_desc mcp23x08_pins[] = {
194 PINCTRL_PIN(0, "gpio0"),
195 PINCTRL_PIN(1, "gpio1"),
196 PINCTRL_PIN(2, "gpio2"),
197 PINCTRL_PIN(3, "gpio3"),
198 PINCTRL_PIN(4, "gpio4"),
199 PINCTRL_PIN(5, "gpio5"),
200 PINCTRL_PIN(6, "gpio6"),
201 PINCTRL_PIN(7, "gpio7"),
202};
203
204static const struct pinctrl_pin_desc mcp23x17_pins[] = {
205 PINCTRL_PIN(0, "gpio0"),
206 PINCTRL_PIN(1, "gpio1"),
207 PINCTRL_PIN(2, "gpio2"),
208 PINCTRL_PIN(3, "gpio3"),
209 PINCTRL_PIN(4, "gpio4"),
210 PINCTRL_PIN(5, "gpio5"),
211 PINCTRL_PIN(6, "gpio6"),
212 PINCTRL_PIN(7, "gpio7"),
213 PINCTRL_PIN(8, "gpio8"),
214 PINCTRL_PIN(9, "gpio9"),
215 PINCTRL_PIN(10, "gpio10"),
216 PINCTRL_PIN(11, "gpio11"),
217 PINCTRL_PIN(12, "gpio12"),
218 PINCTRL_PIN(13, "gpio13"),
219 PINCTRL_PIN(14, "gpio14"),
220 PINCTRL_PIN(15, "gpio15"),
221};
222
223static int mcp_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
224{
225 return 0;
226}
227
228static const char *mcp_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
229 unsigned int group)
230{
231 return NULL;
232}
233
234static int mcp_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
235 unsigned int group,
236 const unsigned int **pins,
237 unsigned int *num_pins)
238{
239 return -ENOTSUPP;
240}
241
242static const struct pinctrl_ops mcp_pinctrl_ops = {
243 .get_groups_count = mcp_pinctrl_get_groups_count,
244 .get_group_name = mcp_pinctrl_get_group_name,
245 .get_group_pins = mcp_pinctrl_get_group_pins,
246#ifdef CONFIG_OF
247 .dt_node_to_map = pinconf_generic_dt_node_to_map_pin,
248 .dt_free_map = pinconf_generic_dt_free_map,
249#endif
250};
251
252static int mcp_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
253 unsigned long *config)
254{
255 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
256 enum pin_config_param param = pinconf_to_config_param(*config);
257 unsigned int data, status;
258 int ret;
259
260 switch (param) {
261 case PIN_CONFIG_BIAS_PULL_UP:
262 ret = mcp_read(mcp, MCP_GPPU, &data);
263 if (ret < 0)
264 return ret;
265 status = (data & BIT(pin)) ? 1 : 0;
266 break;
267 default:
268 dev_err(mcp->dev, "Invalid config param %04x\n", param);
269 return -ENOTSUPP;
270 }
271
272 *config = 0;
273
274 return status ? 0 : -EINVAL;
275}
276
277static int mcp_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
278 unsigned long *configs, unsigned int num_configs)
279{
280 struct mcp23s08 *mcp = pinctrl_dev_get_drvdata(pctldev);
281 enum pin_config_param param;
282 u32 arg;
283 int ret = 0;
284 int i;
285
286 for (i = 0; i < num_configs; i++) {
287 param = pinconf_to_config_param(configs[i]);
288 arg = pinconf_to_config_argument(configs[i]);
289
290 switch (param) {
291 case PIN_CONFIG_BIAS_PULL_UP:
292 ret = mcp_set_bit(mcp, MCP_GPPU, pin, arg);
293 break;
294 default:
295 dev_err(mcp->dev, "Invalid config param %04x\n", param);
296 return -ENOTSUPP;
297 }
298 }
299
300 return ret;
301}
302
303static const struct pinconf_ops mcp_pinconf_ops = {
304 .pin_config_get = mcp_pinconf_get,
305 .pin_config_set = mcp_pinconf_set,
306 .is_generic = true,
307};
308
309
310
311#ifdef CONFIG_SPI_MASTER
312
313static int mcp23sxx_spi_write(void *context, const void *data, size_t count)
314{
315 struct mcp23s08 *mcp = context;
316 struct spi_device *spi = to_spi_device(mcp->dev);
317 struct spi_message m;
318 struct spi_transfer t[2] = { { .tx_buf = &mcp->addr, .len = 1, },
319 { .tx_buf = data, .len = count, }, };
320
321 spi_message_init(&m);
322 spi_message_add_tail(&t[0], &m);
323 spi_message_add_tail(&t[1], &m);
324
325 return spi_sync(spi, &m);
326}
327
328static int mcp23sxx_spi_gather_write(void *context,
329 const void *reg, size_t reg_size,
330 const void *val, size_t val_size)
331{
332 struct mcp23s08 *mcp = context;
333 struct spi_device *spi = to_spi_device(mcp->dev);
334 struct spi_message m;
335 struct spi_transfer t[3] = { { .tx_buf = &mcp->addr, .len = 1, },
336 { .tx_buf = reg, .len = reg_size, },
337 { .tx_buf = val, .len = val_size, }, };
338
339 spi_message_init(&m);
340 spi_message_add_tail(&t[0], &m);
341 spi_message_add_tail(&t[1], &m);
342 spi_message_add_tail(&t[2], &m);
343
344 return spi_sync(spi, &m);
345}
346
347static int mcp23sxx_spi_read(void *context, const void *reg, size_t reg_size,
348 void *val, size_t val_size)
349{
350 struct mcp23s08 *mcp = context;
351 struct spi_device *spi = to_spi_device(mcp->dev);
352 u8 tx[2];
353
354 if (reg_size != 1)
355 return -EINVAL;
356
357 tx[0] = mcp->addr | 0x01;
358 tx[1] = *((u8 *) reg);
359
360 return spi_write_then_read(spi, tx, sizeof(tx), val, val_size);
361}
362
363static const struct regmap_bus mcp23sxx_spi_regmap = {
364 .write = mcp23sxx_spi_write,
365 .gather_write = mcp23sxx_spi_gather_write,
366 .read = mcp23sxx_spi_read,
367};
368
369#endif
370
371
372
373
374
375
376
377
378struct mcp23s08_driver_data {
379 unsigned ngpio;
380 struct mcp23s08 *mcp[8];
381 struct mcp23s08 chip[];
382};
383
384
385static int mcp23s08_direction_input(struct gpio_chip *chip, unsigned offset)
386{
387 struct mcp23s08 *mcp = gpiochip_get_data(chip);
388 int status;
389
390 mutex_lock(&mcp->lock);
391 status = mcp_set_bit(mcp, MCP_IODIR, offset, true);
392 mutex_unlock(&mcp->lock);
393
394 return status;
395}
396
397static int mcp23s08_get(struct gpio_chip *chip, unsigned offset)
398{
399 struct mcp23s08 *mcp = gpiochip_get_data(chip);
400 int status, ret;
401
402 mutex_lock(&mcp->lock);
403
404
405 ret = mcp_read(mcp, MCP_GPIO, &status);
406 if (ret < 0)
407 status = 0;
408 else {
409 mcp->cached_gpio = status;
410 status = !!(status & (1 << offset));
411 }
412
413 mutex_unlock(&mcp->lock);
414 return status;
415}
416
417static int __mcp23s08_set(struct mcp23s08 *mcp, unsigned mask, bool value)
418{
419 return mcp_set_mask(mcp, MCP_OLAT, mask, value);
420}
421
422static void mcp23s08_set(struct gpio_chip *chip, unsigned offset, int value)
423{
424 struct mcp23s08 *mcp = gpiochip_get_data(chip);
425 unsigned mask = BIT(offset);
426
427 mutex_lock(&mcp->lock);
428 __mcp23s08_set(mcp, mask, !!value);
429 mutex_unlock(&mcp->lock);
430}
431
432static int
433mcp23s08_direction_output(struct gpio_chip *chip, unsigned offset, int value)
434{
435 struct mcp23s08 *mcp = gpiochip_get_data(chip);
436 unsigned mask = BIT(offset);
437 int status;
438
439 mutex_lock(&mcp->lock);
440 status = __mcp23s08_set(mcp, mask, value);
441 if (status == 0) {
442 status = mcp_set_mask(mcp, MCP_IODIR, mask, false);
443 }
444 mutex_unlock(&mcp->lock);
445 return status;
446}
447
448
449static irqreturn_t mcp23s08_irq(int irq, void *data)
450{
451 struct mcp23s08 *mcp = data;
452 int intcap, intcon, intf, i, gpio, gpio_orig, intcap_mask, defval;
453 unsigned int child_irq;
454 bool intf_set, intcap_changed, gpio_bit_changed,
455 defval_changed, gpio_set;
456
457 mutex_lock(&mcp->lock);
458 if (mcp_read(mcp, MCP_INTF, &intf))
459 goto unlock;
460
461 if (mcp_read(mcp, MCP_INTCAP, &intcap))
462 goto unlock;
463
464 if (mcp_read(mcp, MCP_INTCON, &intcon))
465 goto unlock;
466
467 if (mcp_read(mcp, MCP_DEFVAL, &defval))
468 goto unlock;
469
470
471 if (mcp_read(mcp, MCP_GPIO, &gpio))
472 goto unlock;
473
474 gpio_orig = mcp->cached_gpio;
475 mcp->cached_gpio = gpio;
476 mutex_unlock(&mcp->lock);
477
478 if (intf == 0) {
479
480 return IRQ_HANDLED;
481 }
482
483 dev_dbg(mcp->chip.parent,
484 "intcap 0x%04X intf 0x%04X gpio_orig 0x%04X gpio 0x%04X\n",
485 intcap, intf, gpio_orig, gpio);
486
487 for (i = 0; i < mcp->chip.ngpio; i++) {
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506 intf_set = intf & BIT(i);
507 if (i < 8 && intf_set)
508 intcap_mask = 0x00FF;
509 else if (i >= 8 && intf_set)
510 intcap_mask = 0xFF00;
511 else
512 intcap_mask = 0x00;
513
514 intcap_changed = (intcap_mask &
515 (intcap & BIT(i))) !=
516 (intcap_mask & (BIT(i) & gpio_orig));
517 gpio_set = BIT(i) & gpio;
518 gpio_bit_changed = (BIT(i) & gpio_orig) !=
519 (BIT(i) & gpio);
520 defval_changed = (BIT(i) & intcon) &&
521 ((BIT(i) & gpio) !=
522 (BIT(i) & defval));
523
524 if (((gpio_bit_changed || intcap_changed) &&
525 (BIT(i) & mcp->irq_rise) && gpio_set) ||
526 ((gpio_bit_changed || intcap_changed) &&
527 (BIT(i) & mcp->irq_fall) && !gpio_set) ||
528 defval_changed) {
529 child_irq = irq_find_mapping(mcp->chip.irq.domain, i);
530 handle_nested_irq(child_irq);
531 }
532 }
533
534 return IRQ_HANDLED;
535
536unlock:
537 mutex_unlock(&mcp->lock);
538 return IRQ_HANDLED;
539}
540
541static void mcp23s08_irq_mask(struct irq_data *data)
542{
543 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
544 struct mcp23s08 *mcp = gpiochip_get_data(gc);
545 unsigned int pos = data->hwirq;
546
547 mcp_set_bit(mcp, MCP_GPINTEN, pos, false);
548}
549
550static void mcp23s08_irq_unmask(struct irq_data *data)
551{
552 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
553 struct mcp23s08 *mcp = gpiochip_get_data(gc);
554 unsigned int pos = data->hwirq;
555
556 mcp_set_bit(mcp, MCP_GPINTEN, pos, true);
557}
558
559static int mcp23s08_irq_set_type(struct irq_data *data, unsigned int type)
560{
561 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
562 struct mcp23s08 *mcp = gpiochip_get_data(gc);
563 unsigned int pos = data->hwirq;
564 int status = 0;
565
566 if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) {
567 mcp_set_bit(mcp, MCP_INTCON, pos, false);
568 mcp->irq_rise |= BIT(pos);
569 mcp->irq_fall |= BIT(pos);
570 } else if (type & IRQ_TYPE_EDGE_RISING) {
571 mcp_set_bit(mcp, MCP_INTCON, pos, false);
572 mcp->irq_rise |= BIT(pos);
573 mcp->irq_fall &= ~BIT(pos);
574 } else if (type & IRQ_TYPE_EDGE_FALLING) {
575 mcp_set_bit(mcp, MCP_INTCON, pos, false);
576 mcp->irq_rise &= ~BIT(pos);
577 mcp->irq_fall |= BIT(pos);
578 } else if (type & IRQ_TYPE_LEVEL_HIGH) {
579 mcp_set_bit(mcp, MCP_INTCON, pos, true);
580 mcp_set_bit(mcp, MCP_DEFVAL, pos, false);
581 } else if (type & IRQ_TYPE_LEVEL_LOW) {
582 mcp_set_bit(mcp, MCP_INTCON, pos, true);
583 mcp_set_bit(mcp, MCP_DEFVAL, pos, true);
584 } else
585 return -EINVAL;
586
587 return status;
588}
589
590static void mcp23s08_irq_bus_lock(struct irq_data *data)
591{
592 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
593 struct mcp23s08 *mcp = gpiochip_get_data(gc);
594
595 mutex_lock(&mcp->lock);
596 regcache_cache_only(mcp->regmap, true);
597}
598
599static void mcp23s08_irq_bus_unlock(struct irq_data *data)
600{
601 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
602 struct mcp23s08 *mcp = gpiochip_get_data(gc);
603
604 regcache_cache_only(mcp->regmap, false);
605 regcache_sync(mcp->regmap);
606
607 mutex_unlock(&mcp->lock);
608}
609
610static struct irq_chip mcp23s08_irq_chip = {
611 .name = "gpio-mcp23xxx",
612 .irq_mask = mcp23s08_irq_mask,
613 .irq_unmask = mcp23s08_irq_unmask,
614 .irq_set_type = mcp23s08_irq_set_type,
615 .irq_bus_lock = mcp23s08_irq_bus_lock,
616 .irq_bus_sync_unlock = mcp23s08_irq_bus_unlock,
617};
618
619static int mcp23s08_irq_setup(struct mcp23s08 *mcp)
620{
621 struct gpio_chip *chip = &mcp->chip;
622 int err;
623 unsigned long irqflags = IRQF_ONESHOT | IRQF_SHARED;
624
625 if (mcp->irq_active_high)
626 irqflags |= IRQF_TRIGGER_HIGH;
627 else
628 irqflags |= IRQF_TRIGGER_LOW;
629
630 err = devm_request_threaded_irq(chip->parent, mcp->irq, NULL,
631 mcp23s08_irq,
632 irqflags, dev_name(chip->parent), mcp);
633 if (err != 0) {
634 dev_err(chip->parent, "unable to request IRQ#%d: %d\n",
635 mcp->irq, err);
636 return err;
637 }
638
639 err = gpiochip_irqchip_add_nested(chip,
640 &mcp23s08_irq_chip,
641 0,
642 handle_simple_irq,
643 IRQ_TYPE_NONE);
644 if (err) {
645 dev_err(chip->parent,
646 "could not connect irqchip to gpiochip: %d\n", err);
647 return err;
648 }
649
650 gpiochip_set_nested_irqchip(chip,
651 &mcp23s08_irq_chip,
652 mcp->irq);
653
654 return 0;
655}
656
657
658
659#ifdef CONFIG_DEBUG_FS
660
661#include <linux/seq_file.h>
662
663
664
665
666
667
668
669#define MCP23S08_CONFIG_REGS 8
670static int __check_mcp23s08_reg_cache(struct mcp23s08 *mcp)
671{
672 int cached[MCP23S08_CONFIG_REGS];
673 int err = 0, i;
674
675
676 for (i = 0; i < MCP23S08_CONFIG_REGS; i++) {
677 err = mcp_read(mcp, i, &cached[i]);
678 if (err)
679 goto out;
680 }
681
682 regcache_cache_bypass(mcp->regmap, true);
683
684 for (i = 0; i < MCP23S08_CONFIG_REGS; i++) {
685 int uncached;
686 err = mcp_read(mcp, i, &uncached);
687 if (err)
688 goto out;
689
690 if (uncached != cached[i]) {
691 dev_err(mcp->dev, "restoring reg 0x%02x from 0x%04x to 0x%04x (power-loss?)\n",
692 i, uncached, cached[i]);
693 mcp_write(mcp, i, cached[i]);
694 }
695 }
696
697out:
698 if (err)
699 dev_err(mcp->dev, "read error: reg=%02x, err=%d", i, err);
700 regcache_cache_bypass(mcp->regmap, false);
701 return err;
702}
703
704
705
706
707
708static void mcp23s08_dbg_show(struct seq_file *s, struct gpio_chip *chip)
709{
710 struct mcp23s08 *mcp;
711 char bank;
712 int t;
713 unsigned mask;
714 int iodir, gpio, gppu;
715
716 mcp = gpiochip_get_data(chip);
717
718
719 bank = '0' + ((mcp->addr >> 1) & 0x7);
720
721 mutex_lock(&mcp->lock);
722
723 t = __check_mcp23s08_reg_cache(mcp);
724 if (t) {
725 seq_printf(s, " I/O Error\n");
726 goto done;
727 }
728 t = mcp_read(mcp, MCP_IODIR, &iodir);
729 if (t) {
730 seq_printf(s, " I/O Error\n");
731 goto done;
732 }
733 t = mcp_read(mcp, MCP_GPIO, &gpio);
734 if (t) {
735 seq_printf(s, " I/O Error\n");
736 goto done;
737 }
738 t = mcp_read(mcp, MCP_GPPU, &gppu);
739 if (t) {
740 seq_printf(s, " I/O Error\n");
741 goto done;
742 }
743
744 for (t = 0, mask = BIT(0); t < chip->ngpio; t++, mask <<= 1) {
745 const char *label;
746
747 label = gpiochip_is_requested(chip, t);
748 if (!label)
749 continue;
750
751 seq_printf(s, " gpio-%-3d P%c.%d (%-12s) %s %s %s\n",
752 chip->base + t, bank, t, label,
753 (iodir & mask) ? "in " : "out",
754 (gpio & mask) ? "hi" : "lo",
755 (gppu & mask) ? "up" : " ");
756
757 }
758done:
759 mutex_unlock(&mcp->lock);
760}
761
762#else
763#define mcp23s08_dbg_show NULL
764#endif
765
766
767
768static int mcp23s08_probe_one(struct mcp23s08 *mcp, struct device *dev,
769 void *data, unsigned addr, unsigned type,
770 unsigned int base, int cs)
771{
772 int status, ret;
773 bool mirror = false;
774 bool open_drain = false;
775 struct regmap_config *one_regmap_config = NULL;
776 int raw_chip_address = (addr & ~0x40) >> 1;
777
778 mutex_init(&mcp->lock);
779
780 mcp->dev = dev;
781 mcp->addr = addr;
782 mcp->irq_active_high = false;
783
784 mcp->chip.direction_input = mcp23s08_direction_input;
785 mcp->chip.get = mcp23s08_get;
786 mcp->chip.direction_output = mcp23s08_direction_output;
787 mcp->chip.set = mcp23s08_set;
788 mcp->chip.dbg_show = mcp23s08_dbg_show;
789#ifdef CONFIG_OF_GPIO
790 mcp->chip.of_gpio_n_cells = 2;
791 mcp->chip.of_node = dev->of_node;
792#endif
793
794 switch (type) {
795#ifdef CONFIG_SPI_MASTER
796 case MCP_TYPE_S08:
797 case MCP_TYPE_S17:
798 switch (type) {
799 case MCP_TYPE_S08:
800 one_regmap_config =
801 devm_kmemdup(dev, &mcp23x08_regmap,
802 sizeof(struct regmap_config), GFP_KERNEL);
803 mcp->reg_shift = 0;
804 mcp->chip.ngpio = 8;
805 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
806 "mcp23s08.%d", raw_chip_address);
807 break;
808 case MCP_TYPE_S17:
809 one_regmap_config =
810 devm_kmemdup(dev, &mcp23x17_regmap,
811 sizeof(struct regmap_config), GFP_KERNEL);
812 mcp->reg_shift = 1;
813 mcp->chip.ngpio = 16;
814 mcp->chip.label = devm_kasprintf(dev, GFP_KERNEL,
815 "mcp23s17.%d", raw_chip_address);
816 break;
817 }
818 if (!one_regmap_config)
819 return -ENOMEM;
820
821 one_regmap_config->name = devm_kasprintf(dev, GFP_KERNEL, "%d", raw_chip_address);
822 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
823 one_regmap_config);
824 break;
825
826 case MCP_TYPE_S18:
827 mcp->regmap = devm_regmap_init(dev, &mcp23sxx_spi_regmap, mcp,
828 &mcp23x17_regmap);
829 mcp->reg_shift = 1;
830 mcp->chip.ngpio = 16;
831 mcp->chip.label = "mcp23s18";
832 break;
833#endif
834
835#if IS_ENABLED(CONFIG_I2C)
836 case MCP_TYPE_008:
837 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x08_regmap);
838 mcp->reg_shift = 0;
839 mcp->chip.ngpio = 8;
840 mcp->chip.label = "mcp23008";
841 break;
842
843 case MCP_TYPE_017:
844 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap);
845 mcp->reg_shift = 1;
846 mcp->chip.ngpio = 16;
847 mcp->chip.label = "mcp23017";
848 break;
849
850 case MCP_TYPE_018:
851 mcp->regmap = devm_regmap_init_i2c(data, &mcp23x17_regmap);
852 mcp->reg_shift = 1;
853 mcp->chip.ngpio = 16;
854 mcp->chip.label = "mcp23018";
855 break;
856#endif
857
858 default:
859 dev_err(dev, "invalid device type (%d)\n", type);
860 return -EINVAL;
861 }
862
863 if (IS_ERR(mcp->regmap))
864 return PTR_ERR(mcp->regmap);
865
866 mcp->chip.base = base;
867 mcp->chip.can_sleep = true;
868 mcp->chip.parent = dev;
869 mcp->chip.owner = THIS_MODULE;
870
871
872
873
874
875 ret = mcp_read(mcp, MCP_IOCON, &status);
876 if (ret < 0)
877 goto fail;
878
879 mcp->irq_controller =
880 device_property_read_bool(dev, "interrupt-controller");
881 if (mcp->irq && mcp->irq_controller) {
882 mcp->irq_active_high =
883 device_property_read_bool(dev,
884 "microchip,irq-active-high");
885
886 mirror = device_property_read_bool(dev, "microchip,irq-mirror");
887 open_drain = device_property_read_bool(dev, "drive-open-drain");
888 }
889
890 if ((status & IOCON_SEQOP) || !(status & IOCON_HAEN) || mirror ||
891 mcp->irq_active_high || open_drain) {
892
893 status &= ~(IOCON_SEQOP | (IOCON_SEQOP << 8));
894 status |= IOCON_HAEN | (IOCON_HAEN << 8);
895 if (mcp->irq_active_high)
896 status |= IOCON_INTPOL | (IOCON_INTPOL << 8);
897 else
898 status &= ~(IOCON_INTPOL | (IOCON_INTPOL << 8));
899
900 if (mirror)
901 status |= IOCON_MIRROR | (IOCON_MIRROR << 8);
902
903 if (open_drain)
904 status |= IOCON_ODR | (IOCON_ODR << 8);
905
906 if (type == MCP_TYPE_S18 || type == MCP_TYPE_018)
907 status |= IOCON_INTCC | (IOCON_INTCC << 8);
908
909 ret = mcp_write(mcp, MCP_IOCON, status);
910 if (ret < 0)
911 goto fail;
912 }
913
914 if (mcp->irq && mcp->irq_controller) {
915 ret = mcp23s08_irq_setup(mcp);
916 if (ret)
917 goto fail;
918 }
919
920 ret = devm_gpiochip_add_data(dev, &mcp->chip, mcp);
921 if (ret < 0)
922 goto fail;
923
924 if (one_regmap_config) {
925 mcp->pinctrl_desc.name = devm_kasprintf(dev, GFP_KERNEL,
926 "mcp23xxx-pinctrl.%d", raw_chip_address);
927 if (!mcp->pinctrl_desc.name)
928 return -ENOMEM;
929 } else {
930 mcp->pinctrl_desc.name = "mcp23xxx-pinctrl";
931 }
932 mcp->pinctrl_desc.pctlops = &mcp_pinctrl_ops;
933 mcp->pinctrl_desc.confops = &mcp_pinconf_ops;
934 mcp->pinctrl_desc.npins = mcp->chip.ngpio;
935 if (mcp->pinctrl_desc.npins == 8)
936 mcp->pinctrl_desc.pins = mcp23x08_pins;
937 else if (mcp->pinctrl_desc.npins == 16)
938 mcp->pinctrl_desc.pins = mcp23x17_pins;
939 mcp->pinctrl_desc.owner = THIS_MODULE;
940
941 mcp->pctldev = devm_pinctrl_register(dev, &mcp->pinctrl_desc, mcp);
942 if (IS_ERR(mcp->pctldev)) {
943 ret = PTR_ERR(mcp->pctldev);
944 goto fail;
945 }
946
947fail:
948 if (ret < 0)
949 dev_dbg(dev, "can't setup chip %d, --> %d\n", addr, ret);
950 return ret;
951}
952
953
954
955#ifdef CONFIG_OF
956#ifdef CONFIG_SPI_MASTER
957static const struct of_device_id mcp23s08_spi_of_match[] = {
958 {
959 .compatible = "microchip,mcp23s08",
960 .data = (void *) MCP_TYPE_S08,
961 },
962 {
963 .compatible = "microchip,mcp23s17",
964 .data = (void *) MCP_TYPE_S17,
965 },
966 {
967 .compatible = "microchip,mcp23s18",
968 .data = (void *) MCP_TYPE_S18,
969 },
970
971 {
972 .compatible = "mcp,mcp23s08",
973 .data = (void *) MCP_TYPE_S08,
974 },
975 {
976 .compatible = "mcp,mcp23s17",
977 .data = (void *) MCP_TYPE_S17,
978 },
979 { },
980};
981MODULE_DEVICE_TABLE(of, mcp23s08_spi_of_match);
982#endif
983
984#if IS_ENABLED(CONFIG_I2C)
985static const struct of_device_id mcp23s08_i2c_of_match[] = {
986 {
987 .compatible = "microchip,mcp23008",
988 .data = (void *) MCP_TYPE_008,
989 },
990 {
991 .compatible = "microchip,mcp23017",
992 .data = (void *) MCP_TYPE_017,
993 },
994 {
995 .compatible = "microchip,mcp23018",
996 .data = (void *) MCP_TYPE_018,
997 },
998
999 {
1000 .compatible = "mcp,mcp23008",
1001 .data = (void *) MCP_TYPE_008,
1002 },
1003 {
1004 .compatible = "mcp,mcp23017",
1005 .data = (void *) MCP_TYPE_017,
1006 },
1007 { },
1008};
1009MODULE_DEVICE_TABLE(of, mcp23s08_i2c_of_match);
1010#endif
1011#endif
1012
1013
1014#if IS_ENABLED(CONFIG_I2C)
1015
1016static int mcp230xx_probe(struct i2c_client *client,
1017 const struct i2c_device_id *id)
1018{
1019 struct mcp23s08_platform_data *pdata, local_pdata;
1020 struct mcp23s08 *mcp;
1021 int status;
1022
1023 pdata = dev_get_platdata(&client->dev);
1024 if (!pdata) {
1025 pdata = &local_pdata;
1026 pdata->base = -1;
1027 }
1028
1029 mcp = devm_kzalloc(&client->dev, sizeof(*mcp), GFP_KERNEL);
1030 if (!mcp)
1031 return -ENOMEM;
1032
1033 mcp->irq = client->irq;
1034 status = mcp23s08_probe_one(mcp, &client->dev, client, client->addr,
1035 id->driver_data, pdata->base, 0);
1036 if (status)
1037 return status;
1038
1039 i2c_set_clientdata(client, mcp);
1040
1041 return 0;
1042}
1043
1044static const struct i2c_device_id mcp230xx_id[] = {
1045 { "mcp23008", MCP_TYPE_008 },
1046 { "mcp23017", MCP_TYPE_017 },
1047 { "mcp23018", MCP_TYPE_018 },
1048 { },
1049};
1050MODULE_DEVICE_TABLE(i2c, mcp230xx_id);
1051
1052static struct i2c_driver mcp230xx_driver = {
1053 .driver = {
1054 .name = "mcp230xx",
1055 .of_match_table = of_match_ptr(mcp23s08_i2c_of_match),
1056 },
1057 .probe = mcp230xx_probe,
1058 .id_table = mcp230xx_id,
1059};
1060
1061static int __init mcp23s08_i2c_init(void)
1062{
1063 return i2c_add_driver(&mcp230xx_driver);
1064}
1065
1066static void mcp23s08_i2c_exit(void)
1067{
1068 i2c_del_driver(&mcp230xx_driver);
1069}
1070
1071#else
1072
1073static int __init mcp23s08_i2c_init(void) { return 0; }
1074static void mcp23s08_i2c_exit(void) { }
1075
1076#endif
1077
1078
1079
1080#ifdef CONFIG_SPI_MASTER
1081
1082static int mcp23s08_probe(struct spi_device *spi)
1083{
1084 struct mcp23s08_platform_data *pdata, local_pdata;
1085 unsigned addr;
1086 int chips = 0;
1087 struct mcp23s08_driver_data *data;
1088 int status, type;
1089 unsigned ngpio = 0;
1090 const struct of_device_id *match;
1091
1092 match = of_match_device(of_match_ptr(mcp23s08_spi_of_match), &spi->dev);
1093 if (match)
1094 type = (int)(uintptr_t)match->data;
1095 else
1096 type = spi_get_device_id(spi)->driver_data;
1097
1098 pdata = dev_get_platdata(&spi->dev);
1099 if (!pdata) {
1100 pdata = &local_pdata;
1101 pdata->base = -1;
1102
1103 status = device_property_read_u32(&spi->dev,
1104 "microchip,spi-present-mask", &pdata->spi_present_mask);
1105 if (status) {
1106 status = device_property_read_u32(&spi->dev,
1107 "mcp,spi-present-mask",
1108 &pdata->spi_present_mask);
1109
1110 if (status) {
1111 dev_err(&spi->dev, "missing spi-present-mask");
1112 return -ENODEV;
1113 }
1114 }
1115 }
1116
1117 if (!pdata->spi_present_mask || pdata->spi_present_mask > 0xff) {
1118 dev_err(&spi->dev, "invalid spi-present-mask");
1119 return -ENODEV;
1120 }
1121
1122 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) {
1123 if (pdata->spi_present_mask & BIT(addr))
1124 chips++;
1125 }
1126
1127 if (!chips)
1128 return -ENODEV;
1129
1130 data = devm_kzalloc(&spi->dev,
1131 sizeof(*data) + chips * sizeof(struct mcp23s08),
1132 GFP_KERNEL);
1133 if (!data)
1134 return -ENOMEM;
1135
1136 spi_set_drvdata(spi, data);
1137
1138 for (addr = 0; addr < MCP_MAX_DEV_PER_CS; addr++) {
1139 if (!(pdata->spi_present_mask & BIT(addr)))
1140 continue;
1141 chips--;
1142 data->mcp[addr] = &data->chip[chips];
1143 data->mcp[addr]->irq = spi->irq;
1144 status = mcp23s08_probe_one(data->mcp[addr], &spi->dev, spi,
1145 0x40 | (addr << 1), type,
1146 pdata->base, addr);
1147 if (status < 0)
1148 return status;
1149
1150 if (pdata->base != -1)
1151 pdata->base += data->mcp[addr]->chip.ngpio;
1152 ngpio += data->mcp[addr]->chip.ngpio;
1153 }
1154 data->ngpio = ngpio;
1155
1156 return 0;
1157}
1158
1159static const struct spi_device_id mcp23s08_ids[] = {
1160 { "mcp23s08", MCP_TYPE_S08 },
1161 { "mcp23s17", MCP_TYPE_S17 },
1162 { "mcp23s18", MCP_TYPE_S18 },
1163 { },
1164};
1165MODULE_DEVICE_TABLE(spi, mcp23s08_ids);
1166
1167static struct spi_driver mcp23s08_driver = {
1168 .probe = mcp23s08_probe,
1169 .id_table = mcp23s08_ids,
1170 .driver = {
1171 .name = "mcp23s08",
1172 .of_match_table = of_match_ptr(mcp23s08_spi_of_match),
1173 },
1174};
1175
1176static int __init mcp23s08_spi_init(void)
1177{
1178 return spi_register_driver(&mcp23s08_driver);
1179}
1180
1181static void mcp23s08_spi_exit(void)
1182{
1183 spi_unregister_driver(&mcp23s08_driver);
1184}
1185
1186#else
1187
1188static int __init mcp23s08_spi_init(void) { return 0; }
1189static void mcp23s08_spi_exit(void) { }
1190
1191#endif
1192
1193
1194
1195static int __init mcp23s08_init(void)
1196{
1197 int ret;
1198
1199 ret = mcp23s08_spi_init();
1200 if (ret)
1201 goto spi_fail;
1202
1203 ret = mcp23s08_i2c_init();
1204 if (ret)
1205 goto i2c_fail;
1206
1207 return 0;
1208
1209 i2c_fail:
1210 mcp23s08_spi_exit();
1211 spi_fail:
1212 return ret;
1213}
1214
1215
1216
1217subsys_initcall(mcp23s08_init);
1218
1219static void __exit mcp23s08_exit(void)
1220{
1221 mcp23s08_spi_exit();
1222 mcp23s08_i2c_exit();
1223}
1224module_exit(mcp23s08_exit);
1225
1226MODULE_LICENSE("GPL");
1227
