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12#include <linux/init.h>
13#include <linux/module.h>
14#include <linux/io.h>
15#include <linux/slab.h>
16#include <linux/err.h>
17#include <linux/list.h>
18#include <linux/interrupt.h>
19
20#include <linux/irqchip/chained_irq.h>
21
22#include <linux/of.h>
23#include <linux/of_device.h>
24#include <linux/of_address.h>
25#include <linux/of_irq.h>
26
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf-generic.h>
30
31#include <linux/platform_data/pinctrl-single.h>
32
33#include "core.h"
34#include "devicetree.h"
35#include "pinconf.h"
36#include "pinmux.h"
37
38#define DRIVER_NAME "pinctrl-single"
39#define PCS_OFF_DISABLED ~0U
40
41
42
43
44
45
46struct pcs_func_vals {
47 void __iomem *reg;
48 unsigned val;
49 unsigned mask;
50};
51
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60
61struct pcs_conf_vals {
62 enum pin_config_param param;
63 unsigned val;
64 unsigned enable;
65 unsigned disable;
66 unsigned mask;
67};
68
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72
73
74struct pcs_conf_type {
75 const char *name;
76 enum pin_config_param param;
77};
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86
87
88struct pcs_function {
89 const char *name;
90 struct pcs_func_vals *vals;
91 unsigned nvals;
92 const char **pgnames;
93 int npgnames;
94 struct pcs_conf_vals *conf;
95 int nconfs;
96 struct list_head node;
97};
98
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105
106struct pcs_gpiofunc_range {
107 unsigned offset;
108 unsigned npins;
109 unsigned gpiofunc;
110 struct list_head node;
111};
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121
122struct pcs_data {
123 struct pinctrl_pin_desc *pa;
124 int cur;
125};
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134
135struct pcs_soc_data {
136 unsigned flags;
137 int irq;
138 unsigned irq_enable_mask;
139 unsigned irq_status_mask;
140 void (*rearm)(void);
141};
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171
172struct pcs_device {
173 struct resource *res;
174 void __iomem *base;
175 unsigned size;
176 struct device *dev;
177 struct device_node *np;
178 struct pinctrl_dev *pctl;
179 unsigned flags;
180#define PCS_QUIRK_SHARED_IRQ (1 << 2)
181#define PCS_FEAT_IRQ (1 << 1)
182#define PCS_FEAT_PINCONF (1 << 0)
183 struct property *missing_nr_pinctrl_cells;
184 struct pcs_soc_data socdata;
185 raw_spinlock_t lock;
186 struct mutex mutex;
187 unsigned width;
188 unsigned fmask;
189 unsigned fshift;
190 unsigned foff;
191 unsigned fmax;
192 bool bits_per_mux;
193 unsigned bits_per_pin;
194 struct pcs_data pins;
195 struct list_head gpiofuncs;
196 struct list_head irqs;
197 struct irq_chip chip;
198 struct irq_domain *domain;
199 struct pinctrl_desc desc;
200 unsigned (*read)(void __iomem *reg);
201 void (*write)(unsigned val, void __iomem *reg);
202};
203
204#define PCS_QUIRK_HAS_SHARED_IRQ (pcs->flags & PCS_QUIRK_SHARED_IRQ)
205#define PCS_HAS_IRQ (pcs->flags & PCS_FEAT_IRQ)
206#define PCS_HAS_PINCONF (pcs->flags & PCS_FEAT_PINCONF)
207
208static int pcs_pinconf_get(struct pinctrl_dev *pctldev, unsigned pin,
209 unsigned long *config);
210static int pcs_pinconf_set(struct pinctrl_dev *pctldev, unsigned pin,
211 unsigned long *configs, unsigned num_configs);
212
213static enum pin_config_param pcs_bias[] = {
214 PIN_CONFIG_BIAS_PULL_DOWN,
215 PIN_CONFIG_BIAS_PULL_UP,
216};
217
218
219
220
221
222
223static struct lock_class_key pcs_lock_class;
224
225
226static struct lock_class_key pcs_request_class;
227
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234
235
236
237static unsigned __maybe_unused pcs_readb(void __iomem *reg)
238{
239 return readb(reg);
240}
241
242static unsigned __maybe_unused pcs_readw(void __iomem *reg)
243{
244 return readw(reg);
245}
246
247static unsigned __maybe_unused pcs_readl(void __iomem *reg)
248{
249 return readl(reg);
250}
251
252static void __maybe_unused pcs_writeb(unsigned val, void __iomem *reg)
253{
254 writeb(val, reg);
255}
256
257static void __maybe_unused pcs_writew(unsigned val, void __iomem *reg)
258{
259 writew(val, reg);
260}
261
262static void __maybe_unused pcs_writel(unsigned val, void __iomem *reg)
263{
264 writel(val, reg);
265}
266
267static void pcs_pin_dbg_show(struct pinctrl_dev *pctldev,
268 struct seq_file *s,
269 unsigned pin)
270{
271 struct pcs_device *pcs;
272 unsigned val, mux_bytes;
273 unsigned long offset;
274 size_t pa;
275
276 pcs = pinctrl_dev_get_drvdata(pctldev);
277
278 mux_bytes = pcs->width / BITS_PER_BYTE;
279 offset = pin * mux_bytes;
280 val = pcs->read(pcs->base + offset);
281 pa = pcs->res->start + offset;
282
283 seq_printf(s, "%zx %08x %s ", pa, val, DRIVER_NAME);
284}
285
286static void pcs_dt_free_map(struct pinctrl_dev *pctldev,
287 struct pinctrl_map *map, unsigned num_maps)
288{
289 struct pcs_device *pcs;
290
291 pcs = pinctrl_dev_get_drvdata(pctldev);
292 devm_kfree(pcs->dev, map);
293}
294
295static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
296 struct device_node *np_config,
297 struct pinctrl_map **map, unsigned *num_maps);
298
299static const struct pinctrl_ops pcs_pinctrl_ops = {
300 .get_groups_count = pinctrl_generic_get_group_count,
301 .get_group_name = pinctrl_generic_get_group_name,
302 .get_group_pins = pinctrl_generic_get_group_pins,
303 .pin_dbg_show = pcs_pin_dbg_show,
304 .dt_node_to_map = pcs_dt_node_to_map,
305 .dt_free_map = pcs_dt_free_map,
306};
307
308static int pcs_get_function(struct pinctrl_dev *pctldev, unsigned pin,
309 struct pcs_function **func)
310{
311 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
312 struct pin_desc *pdesc = pin_desc_get(pctldev, pin);
313 const struct pinctrl_setting_mux *setting;
314 struct function_desc *function;
315 unsigned fselector;
316
317
318 setting = pdesc->mux_setting;
319 if (!setting)
320 return -ENOTSUPP;
321 fselector = setting->func;
322 function = pinmux_generic_get_function(pctldev, fselector);
323 *func = function->data;
324 if (!(*func)) {
325 dev_err(pcs->dev, "%s could not find function%i\n",
326 __func__, fselector);
327 return -ENOTSUPP;
328 }
329 return 0;
330}
331
332static int pcs_set_mux(struct pinctrl_dev *pctldev, unsigned fselector,
333 unsigned group)
334{
335 struct pcs_device *pcs;
336 struct function_desc *function;
337 struct pcs_function *func;
338 int i;
339
340 pcs = pinctrl_dev_get_drvdata(pctldev);
341
342 if (!pcs->fmask)
343 return 0;
344 function = pinmux_generic_get_function(pctldev, fselector);
345 func = function->data;
346 if (!func)
347 return -EINVAL;
348
349 dev_dbg(pcs->dev, "enabling %s function%i\n",
350 func->name, fselector);
351
352 for (i = 0; i < func->nvals; i++) {
353 struct pcs_func_vals *vals;
354 unsigned long flags;
355 unsigned val, mask;
356
357 vals = &func->vals[i];
358 raw_spin_lock_irqsave(&pcs->lock, flags);
359 val = pcs->read(vals->reg);
360
361 if (pcs->bits_per_mux)
362 mask = vals->mask;
363 else
364 mask = pcs->fmask;
365
366 val &= ~mask;
367 val |= (vals->val & mask);
368 pcs->write(val, vals->reg);
369 raw_spin_unlock_irqrestore(&pcs->lock, flags);
370 }
371
372 return 0;
373}
374
375static int pcs_request_gpio(struct pinctrl_dev *pctldev,
376 struct pinctrl_gpio_range *range, unsigned pin)
377{
378 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
379 struct pcs_gpiofunc_range *frange = NULL;
380 struct list_head *pos, *tmp;
381 int mux_bytes = 0;
382 unsigned data;
383
384
385 if (!pcs->fmask)
386 return -ENOTSUPP;
387
388 list_for_each_safe(pos, tmp, &pcs->gpiofuncs) {
389 frange = list_entry(pos, struct pcs_gpiofunc_range, node);
390 if (pin >= frange->offset + frange->npins
391 || pin < frange->offset)
392 continue;
393 mux_bytes = pcs->width / BITS_PER_BYTE;
394
395 if (pcs->bits_per_mux) {
396 int byte_num, offset, pin_shift;
397
398 byte_num = (pcs->bits_per_pin * pin) / BITS_PER_BYTE;
399 offset = (byte_num / mux_bytes) * mux_bytes;
400 pin_shift = pin % (pcs->width / pcs->bits_per_pin) *
401 pcs->bits_per_pin;
402
403 data = pcs->read(pcs->base + offset);
404 data &= ~(pcs->fmask << pin_shift);
405 data |= frange->gpiofunc << pin_shift;
406 pcs->write(data, pcs->base + offset);
407 } else {
408 data = pcs->read(pcs->base + pin * mux_bytes);
409 data &= ~pcs->fmask;
410 data |= frange->gpiofunc;
411 pcs->write(data, pcs->base + pin * mux_bytes);
412 }
413 break;
414 }
415 return 0;
416}
417
418static const struct pinmux_ops pcs_pinmux_ops = {
419 .get_functions_count = pinmux_generic_get_function_count,
420 .get_function_name = pinmux_generic_get_function_name,
421 .get_function_groups = pinmux_generic_get_function_groups,
422 .set_mux = pcs_set_mux,
423 .gpio_request_enable = pcs_request_gpio,
424};
425
426
427static void pcs_pinconf_clear_bias(struct pinctrl_dev *pctldev, unsigned pin)
428{
429 unsigned long config;
430 int i;
431 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
432 config = pinconf_to_config_packed(pcs_bias[i], 0);
433 pcs_pinconf_set(pctldev, pin, &config, 1);
434 }
435}
436
437
438
439
440
441static bool pcs_pinconf_bias_disable(struct pinctrl_dev *pctldev, unsigned pin)
442{
443 unsigned long config;
444 int i;
445
446 for (i = 0; i < ARRAY_SIZE(pcs_bias); i++) {
447 config = pinconf_to_config_packed(pcs_bias[i], 0);
448 if (!pcs_pinconf_get(pctldev, pin, &config))
449 goto out;
450 }
451 return true;
452out:
453 return false;
454}
455
456static int pcs_pinconf_get(struct pinctrl_dev *pctldev,
457 unsigned pin, unsigned long *config)
458{
459 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
460 struct pcs_function *func;
461 enum pin_config_param param;
462 unsigned offset = 0, data = 0, i, j, ret;
463
464 ret = pcs_get_function(pctldev, pin, &func);
465 if (ret)
466 return ret;
467
468 for (i = 0; i < func->nconfs; i++) {
469 param = pinconf_to_config_param(*config);
470 if (param == PIN_CONFIG_BIAS_DISABLE) {
471 if (pcs_pinconf_bias_disable(pctldev, pin)) {
472 *config = 0;
473 return 0;
474 } else {
475 return -ENOTSUPP;
476 }
477 } else if (param != func->conf[i].param) {
478 continue;
479 }
480
481 offset = pin * (pcs->width / BITS_PER_BYTE);
482 data = pcs->read(pcs->base + offset) & func->conf[i].mask;
483 switch (func->conf[i].param) {
484
485 case PIN_CONFIG_BIAS_PULL_DOWN:
486 case PIN_CONFIG_BIAS_PULL_UP:
487 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
488 if ((data != func->conf[i].enable) ||
489 (data == func->conf[i].disable))
490 return -ENOTSUPP;
491 *config = 0;
492 break;
493
494 case PIN_CONFIG_INPUT_SCHMITT:
495 for (j = 0; j < func->nconfs; j++) {
496 switch (func->conf[j].param) {
497 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
498 if (data != func->conf[j].enable)
499 return -ENOTSUPP;
500 break;
501 default:
502 break;
503 }
504 }
505 *config = data;
506 break;
507 case PIN_CONFIG_DRIVE_STRENGTH:
508 case PIN_CONFIG_SLEW_RATE:
509 case PIN_CONFIG_LOW_POWER_MODE:
510 default:
511 *config = data;
512 break;
513 }
514 return 0;
515 }
516 return -ENOTSUPP;
517}
518
519static int pcs_pinconf_set(struct pinctrl_dev *pctldev,
520 unsigned pin, unsigned long *configs,
521 unsigned num_configs)
522{
523 struct pcs_device *pcs = pinctrl_dev_get_drvdata(pctldev);
524 struct pcs_function *func;
525 unsigned offset = 0, shift = 0, i, data, ret;
526 u32 arg;
527 int j;
528
529 ret = pcs_get_function(pctldev, pin, &func);
530 if (ret)
531 return ret;
532
533 for (j = 0; j < num_configs; j++) {
534 for (i = 0; i < func->nconfs; i++) {
535 if (pinconf_to_config_param(configs[j])
536 != func->conf[i].param)
537 continue;
538
539 offset = pin * (pcs->width / BITS_PER_BYTE);
540 data = pcs->read(pcs->base + offset);
541 arg = pinconf_to_config_argument(configs[j]);
542 switch (func->conf[i].param) {
543
544 case PIN_CONFIG_INPUT_SCHMITT:
545 case PIN_CONFIG_DRIVE_STRENGTH:
546 case PIN_CONFIG_SLEW_RATE:
547 case PIN_CONFIG_LOW_POWER_MODE:
548 shift = ffs(func->conf[i].mask) - 1;
549 data &= ~func->conf[i].mask;
550 data |= (arg << shift) & func->conf[i].mask;
551 break;
552
553 case PIN_CONFIG_BIAS_DISABLE:
554 pcs_pinconf_clear_bias(pctldev, pin);
555 break;
556 case PIN_CONFIG_BIAS_PULL_DOWN:
557 case PIN_CONFIG_BIAS_PULL_UP:
558 if (arg)
559 pcs_pinconf_clear_bias(pctldev, pin);
560
561 case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
562 data &= ~func->conf[i].mask;
563 if (arg)
564 data |= func->conf[i].enable;
565 else
566 data |= func->conf[i].disable;
567 break;
568 default:
569 return -ENOTSUPP;
570 }
571 pcs->write(data, pcs->base + offset);
572
573 break;
574 }
575 if (i >= func->nconfs)
576 return -ENOTSUPP;
577 }
578
579 return 0;
580}
581
582static int pcs_pinconf_group_get(struct pinctrl_dev *pctldev,
583 unsigned group, unsigned long *config)
584{
585 const unsigned *pins;
586 unsigned npins, old = 0;
587 int i, ret;
588
589 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
590 if (ret)
591 return ret;
592 for (i = 0; i < npins; i++) {
593 if (pcs_pinconf_get(pctldev, pins[i], config))
594 return -ENOTSUPP;
595
596 if (i && (old != *config))
597 return -ENOTSUPP;
598 old = *config;
599 }
600 return 0;
601}
602
603static int pcs_pinconf_group_set(struct pinctrl_dev *pctldev,
604 unsigned group, unsigned long *configs,
605 unsigned num_configs)
606{
607 const unsigned *pins;
608 unsigned npins;
609 int i, ret;
610
611 ret = pinctrl_generic_get_group_pins(pctldev, group, &pins, &npins);
612 if (ret)
613 return ret;
614 for (i = 0; i < npins; i++) {
615 if (pcs_pinconf_set(pctldev, pins[i], configs, num_configs))
616 return -ENOTSUPP;
617 }
618 return 0;
619}
620
621static void pcs_pinconf_dbg_show(struct pinctrl_dev *pctldev,
622 struct seq_file *s, unsigned pin)
623{
624}
625
626static void pcs_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
627 struct seq_file *s, unsigned selector)
628{
629}
630
631static void pcs_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
632 struct seq_file *s,
633 unsigned long config)
634{
635 pinconf_generic_dump_config(pctldev, s, config);
636}
637
638static const struct pinconf_ops pcs_pinconf_ops = {
639 .pin_config_get = pcs_pinconf_get,
640 .pin_config_set = pcs_pinconf_set,
641 .pin_config_group_get = pcs_pinconf_group_get,
642 .pin_config_group_set = pcs_pinconf_group_set,
643 .pin_config_dbg_show = pcs_pinconf_dbg_show,
644 .pin_config_group_dbg_show = pcs_pinconf_group_dbg_show,
645 .pin_config_config_dbg_show = pcs_pinconf_config_dbg_show,
646 .is_generic = true,
647};
648
649
650
651
652
653
654static int pcs_add_pin(struct pcs_device *pcs, unsigned offset,
655 unsigned pin_pos)
656{
657 struct pcs_soc_data *pcs_soc = &pcs->socdata;
658 struct pinctrl_pin_desc *pin;
659 int i;
660
661 i = pcs->pins.cur;
662 if (i >= pcs->desc.npins) {
663 dev_err(pcs->dev, "too many pins, max %i\n",
664 pcs->desc.npins);
665 return -ENOMEM;
666 }
667
668 if (pcs_soc->irq_enable_mask) {
669 unsigned val;
670
671 val = pcs->read(pcs->base + offset);
672 if (val & pcs_soc->irq_enable_mask) {
673 dev_dbg(pcs->dev, "irq enabled at boot for pin at %lx (%x), clearing\n",
674 (unsigned long)pcs->res->start + offset, val);
675 val &= ~pcs_soc->irq_enable_mask;
676 pcs->write(val, pcs->base + offset);
677 }
678 }
679
680 pin = &pcs->pins.pa[i];
681 pin->number = i;
682 pcs->pins.cur++;
683
684 return i;
685}
686
687
688
689
690
691
692
693
694
695
696static int pcs_allocate_pin_table(struct pcs_device *pcs)
697{
698 int mux_bytes, nr_pins, i;
699 int num_pins_in_register = 0;
700
701 mux_bytes = pcs->width / BITS_PER_BYTE;
702
703 if (pcs->bits_per_mux) {
704 pcs->bits_per_pin = fls(pcs->fmask);
705 nr_pins = (pcs->size * BITS_PER_BYTE) / pcs->bits_per_pin;
706 num_pins_in_register = pcs->width / pcs->bits_per_pin;
707 } else {
708 nr_pins = pcs->size / mux_bytes;
709 }
710
711 dev_dbg(pcs->dev, "allocating %i pins\n", nr_pins);
712 pcs->pins.pa = devm_kzalloc(pcs->dev,
713 sizeof(*pcs->pins.pa) * nr_pins,
714 GFP_KERNEL);
715 if (!pcs->pins.pa)
716 return -ENOMEM;
717
718 pcs->desc.pins = pcs->pins.pa;
719 pcs->desc.npins = nr_pins;
720
721 for (i = 0; i < pcs->desc.npins; i++) {
722 unsigned offset;
723 int res;
724 int byte_num;
725 int pin_pos = 0;
726
727 if (pcs->bits_per_mux) {
728 byte_num = (pcs->bits_per_pin * i) / BITS_PER_BYTE;
729 offset = (byte_num / mux_bytes) * mux_bytes;
730 pin_pos = i % num_pins_in_register;
731 } else {
732 offset = i * mux_bytes;
733 }
734 res = pcs_add_pin(pcs, offset, pin_pos);
735 if (res < 0) {
736 dev_err(pcs->dev, "error adding pins: %i\n", res);
737 return res;
738 }
739 }
740
741 return 0;
742}
743
744
745
746
747
748
749
750
751
752
753
754static struct pcs_function *pcs_add_function(struct pcs_device *pcs,
755 struct device_node *np,
756 const char *name,
757 struct pcs_func_vals *vals,
758 unsigned nvals,
759 const char **pgnames,
760 unsigned npgnames)
761{
762 struct pcs_function *function;
763 int res;
764
765 function = devm_kzalloc(pcs->dev, sizeof(*function), GFP_KERNEL);
766 if (!function)
767 return NULL;
768
769 function->vals = vals;
770 function->nvals = nvals;
771
772 res = pinmux_generic_add_function(pcs->pctl, name,
773 pgnames, npgnames,
774 function);
775 if (res)
776 return NULL;
777
778 return function;
779}
780
781
782
783
784
785
786
787
788static int pcs_get_pin_by_offset(struct pcs_device *pcs, unsigned offset)
789{
790 unsigned index;
791
792 if (offset >= pcs->size) {
793 dev_err(pcs->dev, "mux offset out of range: 0x%x (0x%x)\n",
794 offset, pcs->size);
795 return -EINVAL;
796 }
797
798 if (pcs->bits_per_mux)
799 index = (offset * BITS_PER_BYTE) / pcs->bits_per_pin;
800 else
801 index = offset / (pcs->width / BITS_PER_BYTE);
802
803 return index;
804}
805
806
807
808
809
810
811static int pcs_config_match(unsigned data, unsigned enable, unsigned disable)
812{
813 int ret = -EINVAL;
814
815 if (data == enable)
816 ret = 1;
817 else if (data == disable)
818 ret = 0;
819 return ret;
820}
821
822static void add_config(struct pcs_conf_vals **conf, enum pin_config_param param,
823 unsigned value, unsigned enable, unsigned disable,
824 unsigned mask)
825{
826 (*conf)->param = param;
827 (*conf)->val = value;
828 (*conf)->enable = enable;
829 (*conf)->disable = disable;
830 (*conf)->mask = mask;
831 (*conf)++;
832}
833
834static void add_setting(unsigned long **setting, enum pin_config_param param,
835 unsigned arg)
836{
837 **setting = pinconf_to_config_packed(param, arg);
838 (*setting)++;
839}
840
841
842static void pcs_add_conf2(struct pcs_device *pcs, struct device_node *np,
843 const char *name, enum pin_config_param param,
844 struct pcs_conf_vals **conf, unsigned long **settings)
845{
846 unsigned value[2], shift;
847 int ret;
848
849 ret = of_property_read_u32_array(np, name, value, 2);
850 if (ret)
851 return;
852
853 value[0] &= value[1];
854 shift = ffs(value[1]) - 1;
855
856 add_config(conf, param, value[0], 0, 0, value[1]);
857 add_setting(settings, param, value[0] >> shift);
858}
859
860
861static void pcs_add_conf4(struct pcs_device *pcs, struct device_node *np,
862 const char *name, enum pin_config_param param,
863 struct pcs_conf_vals **conf, unsigned long **settings)
864{
865 unsigned value[4];
866 int ret;
867
868
869 ret = of_property_read_u32_array(np, name, value, 4);
870 if (ret)
871 return;
872 if (!value[3]) {
873 dev_err(pcs->dev, "mask field of the property can't be 0\n");
874 return;
875 }
876 value[0] &= value[3];
877 value[1] &= value[3];
878 value[2] &= value[3];
879 ret = pcs_config_match(value[0], value[1], value[2]);
880 if (ret < 0)
881 dev_dbg(pcs->dev, "failed to match enable or disable bits\n");
882 add_config(conf, param, value[0], value[1], value[2], value[3]);
883 add_setting(settings, param, ret);
884}
885
886static int pcs_parse_pinconf(struct pcs_device *pcs, struct device_node *np,
887 struct pcs_function *func,
888 struct pinctrl_map **map)
889
890{
891 struct pinctrl_map *m = *map;
892 int i = 0, nconfs = 0;
893 unsigned long *settings = NULL, *s = NULL;
894 struct pcs_conf_vals *conf = NULL;
895 static const struct pcs_conf_type prop2[] = {
896 { "pinctrl-single,drive-strength", PIN_CONFIG_DRIVE_STRENGTH, },
897 { "pinctrl-single,slew-rate", PIN_CONFIG_SLEW_RATE, },
898 { "pinctrl-single,input-schmitt", PIN_CONFIG_INPUT_SCHMITT, },
899 { "pinctrl-single,low-power-mode", PIN_CONFIG_LOW_POWER_MODE, },
900 };
901 static const struct pcs_conf_type prop4[] = {
902 { "pinctrl-single,bias-pullup", PIN_CONFIG_BIAS_PULL_UP, },
903 { "pinctrl-single,bias-pulldown", PIN_CONFIG_BIAS_PULL_DOWN, },
904 { "pinctrl-single,input-schmitt-enable",
905 PIN_CONFIG_INPUT_SCHMITT_ENABLE, },
906 };
907
908
909 if (!PCS_HAS_PINCONF)
910 return 0;
911
912
913 for (i = 0; i < ARRAY_SIZE(prop2); i++) {
914 if (of_find_property(np, prop2[i].name, NULL))
915 nconfs++;
916 }
917 for (i = 0; i < ARRAY_SIZE(prop4); i++) {
918 if (of_find_property(np, prop4[i].name, NULL))
919 nconfs++;
920 }
921 if (!nconfs)
922 return 0;
923
924 func->conf = devm_kzalloc(pcs->dev,
925 sizeof(struct pcs_conf_vals) * nconfs,
926 GFP_KERNEL);
927 if (!func->conf)
928 return -ENOMEM;
929 func->nconfs = nconfs;
930 conf = &(func->conf[0]);
931 m++;
932 settings = devm_kzalloc(pcs->dev, sizeof(unsigned long) * nconfs,
933 GFP_KERNEL);
934 if (!settings)
935 return -ENOMEM;
936 s = &settings[0];
937
938 for (i = 0; i < ARRAY_SIZE(prop2); i++)
939 pcs_add_conf2(pcs, np, prop2[i].name, prop2[i].param,
940 &conf, &s);
941 for (i = 0; i < ARRAY_SIZE(prop4); i++)
942 pcs_add_conf4(pcs, np, prop4[i].name, prop4[i].param,
943 &conf, &s);
944 m->type = PIN_MAP_TYPE_CONFIGS_GROUP;
945 m->data.configs.group_or_pin = np->name;
946 m->data.configs.configs = settings;
947 m->data.configs.num_configs = nconfs;
948 return 0;
949}
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971static int pcs_parse_one_pinctrl_entry(struct pcs_device *pcs,
972 struct device_node *np,
973 struct pinctrl_map **map,
974 unsigned *num_maps,
975 const char **pgnames)
976{
977 const char *name = "pinctrl-single,pins";
978 struct pcs_func_vals *vals;
979 int rows, *pins, found = 0, res = -ENOMEM, i;
980 struct pcs_function *function;
981
982 rows = pinctrl_count_index_with_args(np, name);
983 if (rows <= 0) {
984 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
985 return -EINVAL;
986 }
987
988 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows, GFP_KERNEL);
989 if (!vals)
990 return -ENOMEM;
991
992 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows, GFP_KERNEL);
993 if (!pins)
994 goto free_vals;
995
996 for (i = 0; i < rows; i++) {
997 struct of_phandle_args pinctrl_spec;
998 unsigned int offset;
999 int pin;
1000
1001 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1002 if (res)
1003 return res;
1004
1005 if (pinctrl_spec.args_count < 2) {
1006 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1007 pinctrl_spec.args_count);
1008 break;
1009 }
1010
1011
1012 offset = pinctrl_spec.args[0];
1013 vals[found].reg = pcs->base + offset;
1014 vals[found].val = pinctrl_spec.args[1];
1015
1016 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x\n",
1017 pinctrl_spec.np->name, offset, pinctrl_spec.args[1]);
1018
1019 pin = pcs_get_pin_by_offset(pcs, offset);
1020 if (pin < 0) {
1021 dev_err(pcs->dev,
1022 "could not add functions for %s %ux\n",
1023 np->name, offset);
1024 break;
1025 }
1026 pins[found++] = pin;
1027 }
1028
1029 pgnames[0] = np->name;
1030 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1031 if (!function) {
1032 res = -ENOMEM;
1033 goto free_pins;
1034 }
1035
1036 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1037 if (res < 0)
1038 goto free_function;
1039
1040 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1041 (*map)->data.mux.group = np->name;
1042 (*map)->data.mux.function = np->name;
1043
1044 if (PCS_HAS_PINCONF) {
1045 res = pcs_parse_pinconf(pcs, np, function, map);
1046 if (res)
1047 goto free_pingroups;
1048 *num_maps = 2;
1049 } else {
1050 *num_maps = 1;
1051 }
1052 return 0;
1053
1054free_pingroups:
1055 pinctrl_generic_remove_last_group(pcs->pctl);
1056 *num_maps = 1;
1057free_function:
1058 pinmux_generic_remove_last_function(pcs->pctl);
1059
1060free_pins:
1061 devm_kfree(pcs->dev, pins);
1062
1063free_vals:
1064 devm_kfree(pcs->dev, vals);
1065
1066 return res;
1067}
1068
1069static int pcs_parse_bits_in_pinctrl_entry(struct pcs_device *pcs,
1070 struct device_node *np,
1071 struct pinctrl_map **map,
1072 unsigned *num_maps,
1073 const char **pgnames)
1074{
1075 const char *name = "pinctrl-single,bits";
1076 struct pcs_func_vals *vals;
1077 int rows, *pins, found = 0, res = -ENOMEM, i;
1078 int npins_in_row;
1079 struct pcs_function *function;
1080
1081 rows = pinctrl_count_index_with_args(np, name);
1082 if (rows <= 0) {
1083 dev_err(pcs->dev, "Invalid number of rows: %d\n", rows);
1084 return -EINVAL;
1085 }
1086
1087 npins_in_row = pcs->width / pcs->bits_per_pin;
1088
1089 vals = devm_kzalloc(pcs->dev, sizeof(*vals) * rows * npins_in_row,
1090 GFP_KERNEL);
1091 if (!vals)
1092 return -ENOMEM;
1093
1094 pins = devm_kzalloc(pcs->dev, sizeof(*pins) * rows * npins_in_row,
1095 GFP_KERNEL);
1096 if (!pins)
1097 goto free_vals;
1098
1099 for (i = 0; i < rows; i++) {
1100 struct of_phandle_args pinctrl_spec;
1101 unsigned offset, val;
1102 unsigned mask, bit_pos, val_pos, mask_pos, submask;
1103 unsigned pin_num_from_lsb;
1104 int pin;
1105
1106 res = pinctrl_parse_index_with_args(np, name, i, &pinctrl_spec);
1107 if (res)
1108 return res;
1109
1110 if (pinctrl_spec.args_count < 3) {
1111 dev_err(pcs->dev, "invalid args_count for spec: %i\n",
1112 pinctrl_spec.args_count);
1113 break;
1114 }
1115
1116
1117 offset = pinctrl_spec.args[0];
1118 val = pinctrl_spec.args[1];
1119 mask = pinctrl_spec.args[2];
1120
1121 dev_dbg(pcs->dev, "%s index: 0x%x value: 0x%x mask: 0x%x\n",
1122 pinctrl_spec.np->name, offset, val, mask);
1123
1124
1125 while (mask) {
1126 bit_pos = __ffs(mask);
1127 pin_num_from_lsb = bit_pos / pcs->bits_per_pin;
1128 mask_pos = ((pcs->fmask) << bit_pos);
1129 val_pos = val & mask_pos;
1130 submask = mask & mask_pos;
1131
1132 if ((mask & mask_pos) == 0) {
1133 dev_err(pcs->dev,
1134 "Invalid mask for %s at 0x%x\n",
1135 np->name, offset);
1136 break;
1137 }
1138
1139 mask &= ~mask_pos;
1140
1141 if (submask != mask_pos) {
1142 dev_warn(pcs->dev,
1143 "Invalid submask 0x%x for %s at 0x%x\n",
1144 submask, np->name, offset);
1145 continue;
1146 }
1147
1148 vals[found].mask = submask;
1149 vals[found].reg = pcs->base + offset;
1150 vals[found].val = val_pos;
1151
1152 pin = pcs_get_pin_by_offset(pcs, offset);
1153 if (pin < 0) {
1154 dev_err(pcs->dev,
1155 "could not add functions for %s %ux\n",
1156 np->name, offset);
1157 break;
1158 }
1159 pins[found++] = pin + pin_num_from_lsb;
1160 }
1161 }
1162
1163 pgnames[0] = np->name;
1164 function = pcs_add_function(pcs, np, np->name, vals, found, pgnames, 1);
1165 if (!function) {
1166 res = -ENOMEM;
1167 goto free_pins;
1168 }
1169
1170 res = pinctrl_generic_add_group(pcs->pctl, np->name, pins, found, pcs);
1171 if (res < 0)
1172 goto free_function;
1173
1174 (*map)->type = PIN_MAP_TYPE_MUX_GROUP;
1175 (*map)->data.mux.group = np->name;
1176 (*map)->data.mux.function = np->name;
1177
1178 if (PCS_HAS_PINCONF) {
1179 dev_err(pcs->dev, "pinconf not supported\n");
1180 goto free_pingroups;
1181 }
1182
1183 *num_maps = 1;
1184 return 0;
1185
1186free_pingroups:
1187 pinctrl_generic_remove_last_group(pcs->pctl);
1188 *num_maps = 1;
1189free_function:
1190 pinmux_generic_remove_last_function(pcs->pctl);
1191free_pins:
1192 devm_kfree(pcs->dev, pins);
1193
1194free_vals:
1195 devm_kfree(pcs->dev, vals);
1196
1197 return res;
1198}
1199
1200
1201
1202
1203
1204
1205
1206static int pcs_dt_node_to_map(struct pinctrl_dev *pctldev,
1207 struct device_node *np_config,
1208 struct pinctrl_map **map, unsigned *num_maps)
1209{
1210 struct pcs_device *pcs;
1211 const char **pgnames;
1212 int ret;
1213
1214 pcs = pinctrl_dev_get_drvdata(pctldev);
1215
1216
1217 *map = devm_kzalloc(pcs->dev, sizeof(**map) * 2, GFP_KERNEL);
1218 if (!*map)
1219 return -ENOMEM;
1220
1221 *num_maps = 0;
1222
1223 pgnames = devm_kzalloc(pcs->dev, sizeof(*pgnames), GFP_KERNEL);
1224 if (!pgnames) {
1225 ret = -ENOMEM;
1226 goto free_map;
1227 }
1228
1229 if (pcs->bits_per_mux) {
1230 ret = pcs_parse_bits_in_pinctrl_entry(pcs, np_config, map,
1231 num_maps, pgnames);
1232 if (ret < 0) {
1233 dev_err(pcs->dev, "no pins entries for %s\n",
1234 np_config->name);
1235 goto free_pgnames;
1236 }
1237 } else {
1238 ret = pcs_parse_one_pinctrl_entry(pcs, np_config, map,
1239 num_maps, pgnames);
1240 if (ret < 0) {
1241 dev_err(pcs->dev, "no pins entries for %s\n",
1242 np_config->name);
1243 goto free_pgnames;
1244 }
1245 }
1246
1247 return 0;
1248
1249free_pgnames:
1250 devm_kfree(pcs->dev, pgnames);
1251free_map:
1252 devm_kfree(pcs->dev, *map);
1253
1254 return ret;
1255}
1256
1257
1258
1259
1260
1261static void pcs_irq_free(struct pcs_device *pcs)
1262{
1263 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1264
1265 if (pcs_soc->irq < 0)
1266 return;
1267
1268 if (pcs->domain)
1269 irq_domain_remove(pcs->domain);
1270
1271 if (PCS_QUIRK_HAS_SHARED_IRQ)
1272 free_irq(pcs_soc->irq, pcs_soc);
1273 else
1274 irq_set_chained_handler(pcs_soc->irq, NULL);
1275}
1276
1277
1278
1279
1280
1281static void pcs_free_resources(struct pcs_device *pcs)
1282{
1283 pcs_irq_free(pcs);
1284 pinctrl_unregister(pcs->pctl);
1285
1286#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1287 if (pcs->missing_nr_pinctrl_cells)
1288 of_remove_property(pcs->np, pcs->missing_nr_pinctrl_cells);
1289#endif
1290}
1291
1292static int pcs_add_gpio_func(struct device_node *node, struct pcs_device *pcs)
1293{
1294 const char *propname = "pinctrl-single,gpio-range";
1295 const char *cellname = "#pinctrl-single,gpio-range-cells";
1296 struct of_phandle_args gpiospec;
1297 struct pcs_gpiofunc_range *range;
1298 int ret, i;
1299
1300 for (i = 0; ; i++) {
1301 ret = of_parse_phandle_with_args(node, propname, cellname,
1302 i, &gpiospec);
1303
1304 if (ret) {
1305 ret = 0;
1306 break;
1307 }
1308 range = devm_kzalloc(pcs->dev, sizeof(*range), GFP_KERNEL);
1309 if (!range) {
1310 ret = -ENOMEM;
1311 break;
1312 }
1313 range->offset = gpiospec.args[0];
1314 range->npins = gpiospec.args[1];
1315 range->gpiofunc = gpiospec.args[2];
1316 mutex_lock(&pcs->mutex);
1317 list_add_tail(&range->node, &pcs->gpiofuncs);
1318 mutex_unlock(&pcs->mutex);
1319 }
1320 return ret;
1321}
1322
1323
1324
1325
1326
1327
1328struct pcs_interrupt {
1329 void __iomem *reg;
1330 irq_hw_number_t hwirq;
1331 unsigned int irq;
1332 struct list_head node;
1333};
1334
1335
1336
1337
1338
1339
1340
1341static inline void pcs_irq_set(struct pcs_soc_data *pcs_soc,
1342 int irq, const bool enable)
1343{
1344 struct pcs_device *pcs;
1345 struct list_head *pos;
1346 unsigned mask;
1347
1348 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1349 list_for_each(pos, &pcs->irqs) {
1350 struct pcs_interrupt *pcswi;
1351 unsigned soc_mask;
1352
1353 pcswi = list_entry(pos, struct pcs_interrupt, node);
1354 if (irq != pcswi->irq)
1355 continue;
1356
1357 soc_mask = pcs_soc->irq_enable_mask;
1358 raw_spin_lock(&pcs->lock);
1359 mask = pcs->read(pcswi->reg);
1360 if (enable)
1361 mask |= soc_mask;
1362 else
1363 mask &= ~soc_mask;
1364 pcs->write(mask, pcswi->reg);
1365
1366
1367 mask = pcs->read(pcswi->reg);
1368 raw_spin_unlock(&pcs->lock);
1369 }
1370
1371 if (pcs_soc->rearm)
1372 pcs_soc->rearm();
1373}
1374
1375
1376
1377
1378
1379static void pcs_irq_mask(struct irq_data *d)
1380{
1381 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1382
1383 pcs_irq_set(pcs_soc, d->irq, false);
1384}
1385
1386
1387
1388
1389
1390static void pcs_irq_unmask(struct irq_data *d)
1391{
1392 struct pcs_soc_data *pcs_soc = irq_data_get_irq_chip_data(d);
1393
1394 pcs_irq_set(pcs_soc, d->irq, true);
1395}
1396
1397
1398
1399
1400
1401
1402
1403
1404
1405static int pcs_irq_set_wake(struct irq_data *d, unsigned int state)
1406{
1407 if (state)
1408 pcs_irq_unmask(d);
1409 else
1410 pcs_irq_mask(d);
1411
1412 return 0;
1413}
1414
1415
1416
1417
1418
1419
1420
1421
1422
1423static int pcs_irq_handle(struct pcs_soc_data *pcs_soc)
1424{
1425 struct pcs_device *pcs;
1426 struct list_head *pos;
1427 int count = 0;
1428
1429 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1430 list_for_each(pos, &pcs->irqs) {
1431 struct pcs_interrupt *pcswi;
1432 unsigned mask;
1433
1434 pcswi = list_entry(pos, struct pcs_interrupt, node);
1435 raw_spin_lock(&pcs->lock);
1436 mask = pcs->read(pcswi->reg);
1437 raw_spin_unlock(&pcs->lock);
1438 if (mask & pcs_soc->irq_status_mask) {
1439 generic_handle_irq(irq_find_mapping(pcs->domain,
1440 pcswi->hwirq));
1441 count++;
1442 }
1443 }
1444
1445 return count;
1446}
1447
1448
1449
1450
1451
1452
1453
1454
1455
1456static irqreturn_t pcs_irq_handler(int irq, void *d)
1457{
1458 struct pcs_soc_data *pcs_soc = d;
1459
1460 return pcs_irq_handle(pcs_soc) ? IRQ_HANDLED : IRQ_NONE;
1461}
1462
1463
1464
1465
1466
1467
1468
1469
1470
1471static void pcs_irq_chain_handler(struct irq_desc *desc)
1472{
1473 struct pcs_soc_data *pcs_soc = irq_desc_get_handler_data(desc);
1474 struct irq_chip *chip;
1475
1476 chip = irq_desc_get_chip(desc);
1477 chained_irq_enter(chip, desc);
1478 pcs_irq_handle(pcs_soc);
1479
1480 chained_irq_exit(chip, desc);
1481}
1482
1483static int pcs_irqdomain_map(struct irq_domain *d, unsigned int irq,
1484 irq_hw_number_t hwirq)
1485{
1486 struct pcs_soc_data *pcs_soc = d->host_data;
1487 struct pcs_device *pcs;
1488 struct pcs_interrupt *pcswi;
1489
1490 pcs = container_of(pcs_soc, struct pcs_device, socdata);
1491 pcswi = devm_kzalloc(pcs->dev, sizeof(*pcswi), GFP_KERNEL);
1492 if (!pcswi)
1493 return -ENOMEM;
1494
1495 pcswi->reg = pcs->base + hwirq;
1496 pcswi->hwirq = hwirq;
1497 pcswi->irq = irq;
1498
1499 mutex_lock(&pcs->mutex);
1500 list_add_tail(&pcswi->node, &pcs->irqs);
1501 mutex_unlock(&pcs->mutex);
1502
1503 irq_set_chip_data(irq, pcs_soc);
1504 irq_set_chip_and_handler(irq, &pcs->chip,
1505 handle_level_irq);
1506 irq_set_lockdep_class(irq, &pcs_lock_class, &pcs_request_class);
1507 irq_set_noprobe(irq);
1508
1509 return 0;
1510}
1511
1512static const struct irq_domain_ops pcs_irqdomain_ops = {
1513 .map = pcs_irqdomain_map,
1514 .xlate = irq_domain_xlate_onecell,
1515};
1516
1517
1518
1519
1520
1521
1522static int pcs_irq_init_chained_handler(struct pcs_device *pcs,
1523 struct device_node *np)
1524{
1525 struct pcs_soc_data *pcs_soc = &pcs->socdata;
1526 const char *name = "pinctrl";
1527 int num_irqs;
1528
1529 if (!pcs_soc->irq_enable_mask ||
1530 !pcs_soc->irq_status_mask) {
1531 pcs_soc->irq = -1;
1532 return -EINVAL;
1533 }
1534
1535 INIT_LIST_HEAD(&pcs->irqs);
1536 pcs->chip.name = name;
1537 pcs->chip.irq_ack = pcs_irq_mask;
1538 pcs->chip.irq_mask = pcs_irq_mask;
1539 pcs->chip.irq_unmask = pcs_irq_unmask;
1540 pcs->chip.irq_set_wake = pcs_irq_set_wake;
1541
1542 if (PCS_QUIRK_HAS_SHARED_IRQ) {
1543 int res;
1544
1545 res = request_irq(pcs_soc->irq, pcs_irq_handler,
1546 IRQF_SHARED | IRQF_NO_SUSPEND |
1547 IRQF_NO_THREAD,
1548 name, pcs_soc);
1549 if (res) {
1550 pcs_soc->irq = -1;
1551 return res;
1552 }
1553 } else {
1554 irq_set_chained_handler_and_data(pcs_soc->irq,
1555 pcs_irq_chain_handler,
1556 pcs_soc);
1557 }
1558
1559
1560
1561
1562
1563
1564
1565 num_irqs = pcs->size;
1566
1567 pcs->domain = irq_domain_add_simple(np, num_irqs, 0,
1568 &pcs_irqdomain_ops,
1569 pcs_soc);
1570 if (!pcs->domain) {
1571 irq_set_chained_handler(pcs_soc->irq, NULL);
1572 return -EINVAL;
1573 }
1574
1575 return 0;
1576}
1577
1578#ifdef CONFIG_PM
1579static int pinctrl_single_suspend(struct platform_device *pdev,
1580 pm_message_t state)
1581{
1582 struct pcs_device *pcs;
1583
1584 pcs = platform_get_drvdata(pdev);
1585 if (!pcs)
1586 return -EINVAL;
1587
1588 return pinctrl_force_sleep(pcs->pctl);
1589}
1590
1591static int pinctrl_single_resume(struct platform_device *pdev)
1592{
1593 struct pcs_device *pcs;
1594
1595 pcs = platform_get_drvdata(pdev);
1596 if (!pcs)
1597 return -EINVAL;
1598
1599 return pinctrl_force_default(pcs->pctl);
1600}
1601#endif
1602
1603
1604
1605
1606
1607
1608
1609
1610
1611
1612
1613static int pcs_quirk_missing_pinctrl_cells(struct pcs_device *pcs,
1614 struct device_node *np,
1615 int cells)
1616{
1617 struct property *p;
1618 const char *name = "#pinctrl-cells";
1619 int error;
1620 u32 val;
1621
1622 error = of_property_read_u32(np, name, &val);
1623 if (!error)
1624 return 0;
1625
1626 dev_warn(pcs->dev, "please update dts to use %s = <%i>\n",
1627 name, cells);
1628
1629 p = devm_kzalloc(pcs->dev, sizeof(*p), GFP_KERNEL);
1630 if (!p)
1631 return -ENOMEM;
1632
1633 p->length = sizeof(__be32);
1634 p->value = devm_kzalloc(pcs->dev, sizeof(__be32), GFP_KERNEL);
1635 if (!p->value)
1636 return -ENOMEM;
1637 *(__be32 *)p->value = cpu_to_be32(cells);
1638
1639 p->name = devm_kstrdup(pcs->dev, name, GFP_KERNEL);
1640 if (!p->name)
1641 return -ENOMEM;
1642
1643 pcs->missing_nr_pinctrl_cells = p;
1644
1645#if IS_BUILTIN(CONFIG_PINCTRL_SINGLE)
1646 error = of_add_property(np, pcs->missing_nr_pinctrl_cells);
1647#endif
1648
1649 return error;
1650}
1651
1652static int pcs_probe(struct platform_device *pdev)
1653{
1654 struct device_node *np = pdev->dev.of_node;
1655 struct pcs_pdata *pdata;
1656 struct resource *res;
1657 struct pcs_device *pcs;
1658 const struct pcs_soc_data *soc;
1659 int ret;
1660
1661 soc = of_device_get_match_data(&pdev->dev);
1662 if (WARN_ON(!soc))
1663 return -EINVAL;
1664
1665 pcs = devm_kzalloc(&pdev->dev, sizeof(*pcs), GFP_KERNEL);
1666 if (!pcs)
1667 return -ENOMEM;
1668
1669 pcs->dev = &pdev->dev;
1670 pcs->np = np;
1671 raw_spin_lock_init(&pcs->lock);
1672 mutex_init(&pcs->mutex);
1673 INIT_LIST_HEAD(&pcs->gpiofuncs);
1674 pcs->flags = soc->flags;
1675 memcpy(&pcs->socdata, soc, sizeof(*soc));
1676
1677 ret = of_property_read_u32(np, "pinctrl-single,register-width",
1678 &pcs->width);
1679 if (ret) {
1680 dev_err(pcs->dev, "register width not specified\n");
1681
1682 return ret;
1683 }
1684
1685 ret = of_property_read_u32(np, "pinctrl-single,function-mask",
1686 &pcs->fmask);
1687 if (!ret) {
1688 pcs->fshift = __ffs(pcs->fmask);
1689 pcs->fmax = pcs->fmask >> pcs->fshift;
1690 } else {
1691
1692 pcs->fmask = 0;
1693 pcs->fshift = 0;
1694 pcs->fmax = 0;
1695 }
1696
1697 ret = of_property_read_u32(np, "pinctrl-single,function-off",
1698 &pcs->foff);
1699 if (ret)
1700 pcs->foff = PCS_OFF_DISABLED;
1701
1702 pcs->bits_per_mux = of_property_read_bool(np,
1703 "pinctrl-single,bit-per-mux");
1704 ret = pcs_quirk_missing_pinctrl_cells(pcs, np,
1705 pcs->bits_per_mux ? 2 : 1);
1706 if (ret) {
1707 dev_err(&pdev->dev, "unable to patch #pinctrl-cells\n");
1708
1709 return ret;
1710 }
1711
1712 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1713 if (!res) {
1714 dev_err(pcs->dev, "could not get resource\n");
1715 return -ENODEV;
1716 }
1717
1718 pcs->res = devm_request_mem_region(pcs->dev, res->start,
1719 resource_size(res), DRIVER_NAME);
1720 if (!pcs->res) {
1721 dev_err(pcs->dev, "could not get mem_region\n");
1722 return -EBUSY;
1723 }
1724
1725 pcs->size = resource_size(pcs->res);
1726 pcs->base = devm_ioremap(pcs->dev, pcs->res->start, pcs->size);
1727 if (!pcs->base) {
1728 dev_err(pcs->dev, "could not ioremap\n");
1729 return -ENODEV;
1730 }
1731
1732 platform_set_drvdata(pdev, pcs);
1733
1734 switch (pcs->width) {
1735 case 8:
1736 pcs->read = pcs_readb;
1737 pcs->write = pcs_writeb;
1738 break;
1739 case 16:
1740 pcs->read = pcs_readw;
1741 pcs->write = pcs_writew;
1742 break;
1743 case 32:
1744 pcs->read = pcs_readl;
1745 pcs->write = pcs_writel;
1746 break;
1747 default:
1748 break;
1749 }
1750
1751 pcs->desc.name = DRIVER_NAME;
1752 pcs->desc.pctlops = &pcs_pinctrl_ops;
1753 pcs->desc.pmxops = &pcs_pinmux_ops;
1754 if (PCS_HAS_PINCONF)
1755 pcs->desc.confops = &pcs_pinconf_ops;
1756 pcs->desc.owner = THIS_MODULE;
1757
1758 ret = pcs_allocate_pin_table(pcs);
1759 if (ret < 0)
1760 goto free;
1761
1762 ret = pinctrl_register_and_init(&pcs->desc, pcs->dev, pcs, &pcs->pctl);
1763 if (ret) {
1764 dev_err(pcs->dev, "could not register single pinctrl driver\n");
1765 goto free;
1766 }
1767
1768 ret = pcs_add_gpio_func(np, pcs);
1769 if (ret < 0)
1770 goto free;
1771
1772 pcs->socdata.irq = irq_of_parse_and_map(np, 0);
1773 if (pcs->socdata.irq)
1774 pcs->flags |= PCS_FEAT_IRQ;
1775
1776
1777 pdata = dev_get_platdata(&pdev->dev);
1778 if (pdata) {
1779 if (pdata->rearm)
1780 pcs->socdata.rearm = pdata->rearm;
1781 if (pdata->irq) {
1782 pcs->socdata.irq = pdata->irq;
1783 pcs->flags |= PCS_FEAT_IRQ;
1784 }
1785 }
1786
1787 if (PCS_HAS_IRQ) {
1788 ret = pcs_irq_init_chained_handler(pcs, np);
1789 if (ret < 0)
1790 dev_warn(pcs->dev, "initialized with no interrupts\n");
1791 }
1792
1793 dev_info(pcs->dev, "%i pins, size %u\n", pcs->desc.npins, pcs->size);
1794
1795 return pinctrl_enable(pcs->pctl);
1796
1797free:
1798 pcs_free_resources(pcs);
1799
1800 return ret;
1801}
1802
1803static int pcs_remove(struct platform_device *pdev)
1804{
1805 struct pcs_device *pcs = platform_get_drvdata(pdev);
1806
1807 if (!pcs)
1808 return 0;
1809
1810 pcs_free_resources(pcs);
1811
1812 return 0;
1813}
1814
1815static const struct pcs_soc_data pinctrl_single_omap_wkup = {
1816 .flags = PCS_QUIRK_SHARED_IRQ,
1817 .irq_enable_mask = (1 << 14),
1818 .irq_status_mask = (1 << 15),
1819};
1820
1821static const struct pcs_soc_data pinctrl_single_dra7 = {
1822 .irq_enable_mask = (1 << 24),
1823 .irq_status_mask = (1 << 25),
1824};
1825
1826static const struct pcs_soc_data pinctrl_single_am437x = {
1827 .flags = PCS_QUIRK_SHARED_IRQ,
1828 .irq_enable_mask = (1 << 29),
1829 .irq_status_mask = (1 << 30),
1830};
1831
1832static const struct pcs_soc_data pinctrl_single = {
1833};
1834
1835static const struct pcs_soc_data pinconf_single = {
1836 .flags = PCS_FEAT_PINCONF,
1837};
1838
1839static const struct of_device_id pcs_of_match[] = {
1840 { .compatible = "ti,omap3-padconf", .data = &pinctrl_single_omap_wkup },
1841 { .compatible = "ti,omap4-padconf", .data = &pinctrl_single_omap_wkup },
1842 { .compatible = "ti,omap5-padconf", .data = &pinctrl_single_omap_wkup },
1843 { .compatible = "ti,dra7-padconf", .data = &pinctrl_single_dra7 },
1844 { .compatible = "ti,am437-padconf", .data = &pinctrl_single_am437x },
1845 { .compatible = "pinctrl-single", .data = &pinctrl_single },
1846 { .compatible = "pinconf-single", .data = &pinconf_single },
1847 { },
1848};
1849MODULE_DEVICE_TABLE(of, pcs_of_match);
1850
1851static struct platform_driver pcs_driver = {
1852 .probe = pcs_probe,
1853 .remove = pcs_remove,
1854 .driver = {
1855 .name = DRIVER_NAME,
1856 .of_match_table = pcs_of_match,
1857 },
1858#ifdef CONFIG_PM
1859 .suspend = pinctrl_single_suspend,
1860 .resume = pinctrl_single_resume,
1861#endif
1862};
1863
1864module_platform_driver(pcs_driver);
1865
1866MODULE_AUTHOR("Tony Lindgren <tony@atomide.com>");
1867MODULE_DESCRIPTION("One-register-per-pin type device tree based pinctrl driver");
1868MODULE_LICENSE("GPL v2");
1869