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16#include <linux/device.h>
17#include <linux/of_address.h>
18#include <linux/slab.h>
19#include <linux/err.h>
20#include <linux/soc/samsung/exynos-regs-pmu.h>
21
22#include "pinctrl-samsung.h"
23#include "pinctrl-exynos.h"
24
25static const struct samsung_pin_bank_type bank_type_off = {
26 .fld_width = { 4, 1, 2, 2, 2, 2, },
27 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, 0x10, 0x14, },
28};
29
30static const struct samsung_pin_bank_type bank_type_alive = {
31 .fld_width = { 4, 1, 2, 2, },
32 .reg_offset = { 0x00, 0x04, 0x08, 0x0c, },
33};
34
35
36#define S5P_OTHERS 0xE000
37
38#define S5P_OTHERS_RET_IO (1 << 31)
39#define S5P_OTHERS_RET_CF (1 << 30)
40#define S5P_OTHERS_RET_MMC (1 << 29)
41#define S5P_OTHERS_RET_UART (1 << 28)
42
43static void s5pv210_retention_disable(struct samsung_pinctrl_drv_data *drvdata)
44{
45 void __iomem *clk_base = (void __iomem *)drvdata->retention_ctrl->priv;
46 u32 tmp;
47
48 tmp = __raw_readl(clk_base + S5P_OTHERS);
49 tmp |= (S5P_OTHERS_RET_IO | S5P_OTHERS_RET_CF | S5P_OTHERS_RET_MMC |
50 S5P_OTHERS_RET_UART);
51 __raw_writel(tmp, clk_base + S5P_OTHERS);
52}
53
54static struct samsung_retention_ctrl *
55s5pv210_retention_init(struct samsung_pinctrl_drv_data *drvdata,
56 const struct samsung_retention_data *data)
57{
58 struct samsung_retention_ctrl *ctrl;
59 struct device_node *np;
60 void __iomem *clk_base;
61
62 ctrl = devm_kzalloc(drvdata->dev, sizeof(*ctrl), GFP_KERNEL);
63 if (!ctrl)
64 return ERR_PTR(-ENOMEM);
65
66 np = of_find_compatible_node(NULL, NULL, "samsung,s5pv210-clock");
67 if (!np) {
68 pr_err("%s: failed to find clock controller DT node\n",
69 __func__);
70 return ERR_PTR(-ENODEV);
71 }
72
73 clk_base = of_iomap(np, 0);
74 if (!clk_base) {
75 pr_err("%s: failed to map clock registers\n", __func__);
76 return ERR_PTR(-EINVAL);
77 }
78
79 ctrl->priv = (void __force *)clk_base;
80 ctrl->disable = s5pv210_retention_disable;
81
82 return ctrl;
83}
84
85static const struct samsung_retention_data s5pv210_retention_data __initconst = {
86 .init = s5pv210_retention_init,
87};
88
89
90static const struct samsung_pin_bank_data s5pv210_pin_bank[] __initconst = {
91 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
92 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpa1", 0x04),
93 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
94 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
95 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
96 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
97 EXYNOS_PIN_BANK_EINTG(6, 0x0c0, "gpd1", 0x18),
98 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpe0", 0x1c),
99 EXYNOS_PIN_BANK_EINTG(5, 0x100, "gpe1", 0x20),
100 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpf0", 0x24),
101 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpf1", 0x28),
102 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpf2", 0x2c),
103 EXYNOS_PIN_BANK_EINTG(6, 0x180, "gpf3", 0x30),
104 EXYNOS_PIN_BANK_EINTG(7, 0x1a0, "gpg0", 0x34),
105 EXYNOS_PIN_BANK_EINTG(7, 0x1c0, "gpg1", 0x38),
106 EXYNOS_PIN_BANK_EINTG(7, 0x1e0, "gpg2", 0x3c),
107 EXYNOS_PIN_BANK_EINTG(7, 0x200, "gpg3", 0x40),
108 EXYNOS_PIN_BANK_EINTN(7, 0x220, "gpi"),
109 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x44),
110 EXYNOS_PIN_BANK_EINTG(6, 0x260, "gpj1", 0x48),
111 EXYNOS_PIN_BANK_EINTG(8, 0x280, "gpj2", 0x4c),
112 EXYNOS_PIN_BANK_EINTG(8, 0x2a0, "gpj3", 0x50),
113 EXYNOS_PIN_BANK_EINTG(5, 0x2c0, "gpj4", 0x54),
114 EXYNOS_PIN_BANK_EINTN(8, 0x2e0, "mp01"),
115 EXYNOS_PIN_BANK_EINTN(4, 0x300, "mp02"),
116 EXYNOS_PIN_BANK_EINTN(8, 0x320, "mp03"),
117 EXYNOS_PIN_BANK_EINTN(8, 0x340, "mp04"),
118 EXYNOS_PIN_BANK_EINTN(8, 0x360, "mp05"),
119 EXYNOS_PIN_BANK_EINTN(8, 0x380, "mp06"),
120 EXYNOS_PIN_BANK_EINTN(8, 0x3a0, "mp07"),
121 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gph0", 0x00),
122 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gph1", 0x04),
123 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gph2", 0x08),
124 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gph3", 0x0c),
125};
126
127static const struct samsung_pin_ctrl s5pv210_pin_ctrl[] __initconst = {
128 {
129
130 .pin_banks = s5pv210_pin_bank,
131 .nr_banks = ARRAY_SIZE(s5pv210_pin_bank),
132 .eint_gpio_init = exynos_eint_gpio_init,
133 .eint_wkup_init = exynos_eint_wkup_init,
134 .suspend = exynos_pinctrl_suspend,
135 .resume = exynos_pinctrl_resume,
136 .retention_data = &s5pv210_retention_data,
137 },
138};
139
140const struct samsung_pinctrl_of_match_data s5pv210_of_data __initconst = {
141 .ctrl = s5pv210_pin_ctrl,
142 .num_ctrl = ARRAY_SIZE(s5pv210_pin_ctrl),
143};
144
145
146static atomic_t exynos_shared_retention_refcnt;
147
148
149static const struct samsung_pin_bank_data exynos3250_pin_banks0[] __initconst = {
150 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
151 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
152 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
153 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
154 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
155 EXYNOS_PIN_BANK_EINTG(4, 0x0a0, "gpd0", 0x14),
156 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpd1", 0x18),
157};
158
159
160static const struct samsung_pin_bank_data exynos3250_pin_banks1[] __initconst = {
161 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpe0"),
162 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpe1"),
163 EXYNOS_PIN_BANK_EINTN(3, 0x180, "gpe2"),
164 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpk0", 0x08),
165 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
166 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
167 EXYNOS_PIN_BANK_EINTG(4, 0x0c0, "gpl0", 0x18),
168 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
169 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
170 EXYNOS_PIN_BANK_EINTG(5, 0x2a0, "gpm2", 0x2c),
171 EXYNOS_PIN_BANK_EINTG(8, 0x2c0, "gpm3", 0x30),
172 EXYNOS_PIN_BANK_EINTG(8, 0x2e0, "gpm4", 0x34),
173 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
174 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
175 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
176 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
177};
178
179
180
181
182
183static const u32 exynos3250_retention_regs[] = {
184 S5P_PAD_RET_MAUDIO_OPTION,
185 S5P_PAD_RET_GPIO_OPTION,
186 S5P_PAD_RET_UART_OPTION,
187 S5P_PAD_RET_MMCA_OPTION,
188 S5P_PAD_RET_MMCB_OPTION,
189 S5P_PAD_RET_EBIA_OPTION,
190 S5P_PAD_RET_EBIB_OPTION,
191 S5P_PAD_RET_MMC2_OPTION,
192 S5P_PAD_RET_SPI_OPTION,
193};
194
195static const struct samsung_retention_data exynos3250_retention_data __initconst = {
196 .regs = exynos3250_retention_regs,
197 .nr_regs = ARRAY_SIZE(exynos3250_retention_regs),
198 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
199 .refcnt = &exynos_shared_retention_refcnt,
200 .init = exynos_retention_init,
201};
202
203
204
205
206
207static const struct samsung_pin_ctrl exynos3250_pin_ctrl[] __initconst = {
208 {
209
210 .pin_banks = exynos3250_pin_banks0,
211 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks0),
212 .eint_gpio_init = exynos_eint_gpio_init,
213 .suspend = exynos_pinctrl_suspend,
214 .resume = exynos_pinctrl_resume,
215 .retention_data = &exynos3250_retention_data,
216 }, {
217
218 .pin_banks = exynos3250_pin_banks1,
219 .nr_banks = ARRAY_SIZE(exynos3250_pin_banks1),
220 .eint_gpio_init = exynos_eint_gpio_init,
221 .eint_wkup_init = exynos_eint_wkup_init,
222 .suspend = exynos_pinctrl_suspend,
223 .resume = exynos_pinctrl_resume,
224 .retention_data = &exynos3250_retention_data,
225 },
226};
227
228const struct samsung_pinctrl_of_match_data exynos3250_of_data __initconst = {
229 .ctrl = exynos3250_pin_ctrl,
230 .num_ctrl = ARRAY_SIZE(exynos3250_pin_ctrl),
231};
232
233
234static const struct samsung_pin_bank_data exynos4210_pin_banks0[] __initconst = {
235 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
236 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
237 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
238 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
239 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
240 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
241 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
242 EXYNOS_PIN_BANK_EINTG(5, 0x0E0, "gpe0", 0x1c),
243 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpe1", 0x20),
244 EXYNOS_PIN_BANK_EINTG(6, 0x120, "gpe2", 0x24),
245 EXYNOS_PIN_BANK_EINTG(8, 0x140, "gpe3", 0x28),
246 EXYNOS_PIN_BANK_EINTG(8, 0x160, "gpe4", 0x2c),
247 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
248 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
249 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
250 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
251};
252
253
254static const struct samsung_pin_bank_data exynos4210_pin_banks1[] __initconst = {
255 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpj0", 0x00),
256 EXYNOS_PIN_BANK_EINTG(5, 0x020, "gpj1", 0x04),
257 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
258 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
259 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
260 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
261 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpl0", 0x18),
262 EXYNOS_PIN_BANK_EINTG(3, 0x0E0, "gpl1", 0x1c),
263 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
264 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
265 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
266 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
267 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
268 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
269 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
270 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
271 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
272 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
273 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
274 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
275};
276
277
278static const struct samsung_pin_bank_data exynos4210_pin_banks2[] __initconst = {
279 EXYNOS_PIN_BANK_EINTN(7, 0x000, "gpz"),
280};
281
282
283static const u32 exynos4_retention_regs[] = {
284 S5P_PAD_RET_GPIO_OPTION,
285 S5P_PAD_RET_UART_OPTION,
286 S5P_PAD_RET_MMCA_OPTION,
287 S5P_PAD_RET_MMCB_OPTION,
288 S5P_PAD_RET_EBIA_OPTION,
289 S5P_PAD_RET_EBIB_OPTION,
290};
291
292static const struct samsung_retention_data exynos4_retention_data __initconst = {
293 .regs = exynos4_retention_regs,
294 .nr_regs = ARRAY_SIZE(exynos4_retention_regs),
295 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
296 .refcnt = &exynos_shared_retention_refcnt,
297 .init = exynos_retention_init,
298};
299
300
301static const u32 exynos4_audio_retention_regs[] = {
302 S5P_PAD_RET_MAUDIO_OPTION,
303};
304
305static const struct samsung_retention_data exynos4_audio_retention_data __initconst = {
306 .regs = exynos4_audio_retention_regs,
307 .nr_regs = ARRAY_SIZE(exynos4_audio_retention_regs),
308 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
309 .init = exynos_retention_init,
310};
311
312
313
314
315
316static const struct samsung_pin_ctrl exynos4210_pin_ctrl[] __initconst = {
317 {
318
319 .pin_banks = exynos4210_pin_banks0,
320 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks0),
321 .eint_gpio_init = exynos_eint_gpio_init,
322 .suspend = exynos_pinctrl_suspend,
323 .resume = exynos_pinctrl_resume,
324 .retention_data = &exynos4_retention_data,
325 }, {
326
327 .pin_banks = exynos4210_pin_banks1,
328 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks1),
329 .eint_gpio_init = exynos_eint_gpio_init,
330 .eint_wkup_init = exynos_eint_wkup_init,
331 .suspend = exynos_pinctrl_suspend,
332 .resume = exynos_pinctrl_resume,
333 .retention_data = &exynos4_retention_data,
334 }, {
335
336 .pin_banks = exynos4210_pin_banks2,
337 .nr_banks = ARRAY_SIZE(exynos4210_pin_banks2),
338 .retention_data = &exynos4_audio_retention_data,
339 },
340};
341
342const struct samsung_pinctrl_of_match_data exynos4210_of_data __initconst = {
343 .ctrl = exynos4210_pin_ctrl,
344 .num_ctrl = ARRAY_SIZE(exynos4210_pin_ctrl),
345};
346
347
348static const struct samsung_pin_bank_data exynos4x12_pin_banks0[] __initconst = {
349 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
350 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
351 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpb", 0x08),
352 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpc0", 0x0c),
353 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpc1", 0x10),
354 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpd0", 0x14),
355 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpd1", 0x18),
356 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpf0", 0x30),
357 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpf1", 0x34),
358 EXYNOS_PIN_BANK_EINTG(8, 0x1C0, "gpf2", 0x38),
359 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf3", 0x3c),
360 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpj0", 0x40),
361 EXYNOS_PIN_BANK_EINTG(5, 0x260, "gpj1", 0x44),
362};
363
364
365static const struct samsung_pin_bank_data exynos4x12_pin_banks1[] __initconst = {
366 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpk0", 0x08),
367 EXYNOS_PIN_BANK_EINTG(7, 0x060, "gpk1", 0x0c),
368 EXYNOS_PIN_BANK_EINTG(7, 0x080, "gpk2", 0x10),
369 EXYNOS_PIN_BANK_EINTG(7, 0x0A0, "gpk3", 0x14),
370 EXYNOS_PIN_BANK_EINTG(7, 0x0C0, "gpl0", 0x18),
371 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpl1", 0x1c),
372 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpl2", 0x20),
373 EXYNOS_PIN_BANK_EINTG(8, 0x260, "gpm0", 0x24),
374 EXYNOS_PIN_BANK_EINTG(7, 0x280, "gpm1", 0x28),
375 EXYNOS_PIN_BANK_EINTG(5, 0x2A0, "gpm2", 0x2c),
376 EXYNOS_PIN_BANK_EINTG(8, 0x2C0, "gpm3", 0x30),
377 EXYNOS_PIN_BANK_EINTG(8, 0x2E0, "gpm4", 0x34),
378 EXYNOS_PIN_BANK_EINTN(6, 0x120, "gpy0"),
379 EXYNOS_PIN_BANK_EINTN(4, 0x140, "gpy1"),
380 EXYNOS_PIN_BANK_EINTN(6, 0x160, "gpy2"),
381 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy3"),
382 EXYNOS_PIN_BANK_EINTN(8, 0x1A0, "gpy4"),
383 EXYNOS_PIN_BANK_EINTN(8, 0x1C0, "gpy5"),
384 EXYNOS_PIN_BANK_EINTN(8, 0x1E0, "gpy6"),
385 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
386 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
387 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
388 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
389};
390
391
392static const struct samsung_pin_bank_data exynos4x12_pin_banks2[] __initconst = {
393 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
394};
395
396
397static const struct samsung_pin_bank_data exynos4x12_pin_banks3[] __initconst = {
398 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
399 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
400 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpv2", 0x08),
401 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv3", 0x0c),
402 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpv4", 0x10),
403};
404
405
406
407
408
409static const struct samsung_pin_ctrl exynos4x12_pin_ctrl[] __initconst = {
410 {
411
412 .pin_banks = exynos4x12_pin_banks0,
413 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks0),
414 .eint_gpio_init = exynos_eint_gpio_init,
415 .suspend = exynos_pinctrl_suspend,
416 .resume = exynos_pinctrl_resume,
417 .retention_data = &exynos4_retention_data,
418 }, {
419
420 .pin_banks = exynos4x12_pin_banks1,
421 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks1),
422 .eint_gpio_init = exynos_eint_gpio_init,
423 .eint_wkup_init = exynos_eint_wkup_init,
424 .suspend = exynos_pinctrl_suspend,
425 .resume = exynos_pinctrl_resume,
426 .retention_data = &exynos4_retention_data,
427 }, {
428
429 .pin_banks = exynos4x12_pin_banks2,
430 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks2),
431 .eint_gpio_init = exynos_eint_gpio_init,
432 .suspend = exynos_pinctrl_suspend,
433 .resume = exynos_pinctrl_resume,
434 .retention_data = &exynos4_audio_retention_data,
435 }, {
436
437 .pin_banks = exynos4x12_pin_banks3,
438 .nr_banks = ARRAY_SIZE(exynos4x12_pin_banks3),
439 .eint_gpio_init = exynos_eint_gpio_init,
440 .suspend = exynos_pinctrl_suspend,
441 .resume = exynos_pinctrl_resume,
442 },
443};
444
445const struct samsung_pinctrl_of_match_data exynos4x12_of_data __initconst = {
446 .ctrl = exynos4x12_pin_ctrl,
447 .num_ctrl = ARRAY_SIZE(exynos4x12_pin_ctrl),
448};
449
450
451static const struct samsung_pin_bank_data exynos5250_pin_banks0[] __initconst = {
452 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
453 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
454 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
455 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
456 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
457 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
458 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
459 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
460 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc1", 0x20),
461 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc2", 0x24),
462 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc3", 0x28),
463 EXYNOS_PIN_BANK_EINTG(4, 0x160, "gpd0", 0x2c),
464 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x30),
465 EXYNOS_PIN_BANK_EINTG(7, 0x2E0, "gpc4", 0x34),
466 EXYNOS_PIN_BANK_EINTN(6, 0x1A0, "gpy0"),
467 EXYNOS_PIN_BANK_EINTN(4, 0x1C0, "gpy1"),
468 EXYNOS_PIN_BANK_EINTN(6, 0x1E0, "gpy2"),
469 EXYNOS_PIN_BANK_EINTN(8, 0x200, "gpy3"),
470 EXYNOS_PIN_BANK_EINTN(8, 0x220, "gpy4"),
471 EXYNOS_PIN_BANK_EINTN(8, 0x240, "gpy5"),
472 EXYNOS_PIN_BANK_EINTN(8, 0x260, "gpy6"),
473 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
474 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
475 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
476 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
477};
478
479
480static const struct samsung_pin_bank_data exynos5250_pin_banks1[] __initconst = {
481 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
482 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
483 EXYNOS_PIN_BANK_EINTG(4, 0x040, "gpf0", 0x08),
484 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpf1", 0x0c),
485 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
486 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
487 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
488 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gph0", 0x1c),
489 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph1", 0x20),
490};
491
492
493static const struct samsung_pin_bank_data exynos5250_pin_banks2[] __initconst = {
494 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
495 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
496 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
497 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
498 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
499};
500
501
502static const struct samsung_pin_bank_data exynos5250_pin_banks3[] __initconst = {
503 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
504};
505
506
507
508
509
510static const struct samsung_pin_ctrl exynos5250_pin_ctrl[] __initconst = {
511 {
512
513 .pin_banks = exynos5250_pin_banks0,
514 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks0),
515 .eint_gpio_init = exynos_eint_gpio_init,
516 .eint_wkup_init = exynos_eint_wkup_init,
517 .suspend = exynos_pinctrl_suspend,
518 .resume = exynos_pinctrl_resume,
519 .retention_data = &exynos4_retention_data,
520 }, {
521
522 .pin_banks = exynos5250_pin_banks1,
523 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks1),
524 .eint_gpio_init = exynos_eint_gpio_init,
525 .suspend = exynos_pinctrl_suspend,
526 .resume = exynos_pinctrl_resume,
527 .retention_data = &exynos4_retention_data,
528 }, {
529
530 .pin_banks = exynos5250_pin_banks2,
531 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks2),
532 .eint_gpio_init = exynos_eint_gpio_init,
533 .suspend = exynos_pinctrl_suspend,
534 .resume = exynos_pinctrl_resume,
535 }, {
536
537 .pin_banks = exynos5250_pin_banks3,
538 .nr_banks = ARRAY_SIZE(exynos5250_pin_banks3),
539 .eint_gpio_init = exynos_eint_gpio_init,
540 .suspend = exynos_pinctrl_suspend,
541 .resume = exynos_pinctrl_resume,
542 .retention_data = &exynos4_audio_retention_data,
543 },
544};
545
546const struct samsung_pinctrl_of_match_data exynos5250_of_data __initconst = {
547 .ctrl = exynos5250_pin_ctrl,
548 .num_ctrl = ARRAY_SIZE(exynos5250_pin_ctrl),
549};
550
551
552static const struct samsung_pin_bank_data exynos5260_pin_banks0[] __initconst = {
553 EXYNOS_PIN_BANK_EINTG(4, 0x000, "gpa0", 0x00),
554 EXYNOS_PIN_BANK_EINTG(7, 0x020, "gpa1", 0x04),
555 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
556 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
557 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpb1", 0x10),
558 EXYNOS_PIN_BANK_EINTG(5, 0x0a0, "gpb2", 0x14),
559 EXYNOS_PIN_BANK_EINTG(8, 0x0c0, "gpb3", 0x18),
560 EXYNOS_PIN_BANK_EINTG(8, 0x0e0, "gpb4", 0x1c),
561 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gpb5", 0x20),
562 EXYNOS_PIN_BANK_EINTG(8, 0x120, "gpd0", 0x24),
563 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpd1", 0x28),
564 EXYNOS_PIN_BANK_EINTG(5, 0x160, "gpd2", 0x2c),
565 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpe0", 0x30),
566 EXYNOS_PIN_BANK_EINTG(5, 0x1a0, "gpe1", 0x34),
567 EXYNOS_PIN_BANK_EINTG(4, 0x1c0, "gpf0", 0x38),
568 EXYNOS_PIN_BANK_EINTG(8, 0x1e0, "gpf1", 0x3c),
569 EXYNOS_PIN_BANK_EINTG(2, 0x200, "gpk0", 0x40),
570 EXYNOS_PIN_BANK_EINTW(8, 0xc00, "gpx0", 0x00),
571 EXYNOS_PIN_BANK_EINTW(8, 0xc20, "gpx1", 0x04),
572 EXYNOS_PIN_BANK_EINTW(8, 0xc40, "gpx2", 0x08),
573 EXYNOS_PIN_BANK_EINTW(8, 0xc60, "gpx3", 0x0c),
574};
575
576
577static const struct samsung_pin_bank_data exynos5260_pin_banks1[] __initconst = {
578 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpc0", 0x00),
579 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpc1", 0x04),
580 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
581 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
582 EXYNOS_PIN_BANK_EINTG(4, 0x080, "gpc4", 0x10),
583};
584
585
586static const struct samsung_pin_bank_data exynos5260_pin_banks2[] __initconst = {
587 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz0", 0x00),
588 EXYNOS_PIN_BANK_EINTG(4, 0x020, "gpz1", 0x04),
589};
590
591
592
593
594
595static const struct samsung_pin_ctrl exynos5260_pin_ctrl[] __initconst = {
596 {
597
598 .pin_banks = exynos5260_pin_banks0,
599 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks0),
600 .eint_gpio_init = exynos_eint_gpio_init,
601 .eint_wkup_init = exynos_eint_wkup_init,
602 }, {
603
604 .pin_banks = exynos5260_pin_banks1,
605 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks1),
606 .eint_gpio_init = exynos_eint_gpio_init,
607 }, {
608
609 .pin_banks = exynos5260_pin_banks2,
610 .nr_banks = ARRAY_SIZE(exynos5260_pin_banks2),
611 .eint_gpio_init = exynos_eint_gpio_init,
612 },
613};
614
615const struct samsung_pinctrl_of_match_data exynos5260_of_data __initconst = {
616 .ctrl = exynos5260_pin_ctrl,
617 .num_ctrl = ARRAY_SIZE(exynos5260_pin_ctrl),
618};
619
620
621static const struct samsung_pin_bank_data exynos5410_pin_banks0[] __initconst = {
622 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
623 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
624 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
625 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
626 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
627 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
628 EXYNOS_PIN_BANK_EINTG(4, 0x0C0, "gpb3", 0x18),
629 EXYNOS_PIN_BANK_EINTG(7, 0x0E0, "gpc0", 0x1c),
630 EXYNOS_PIN_BANK_EINTG(4, 0x100, "gpc3", 0x20),
631 EXYNOS_PIN_BANK_EINTG(7, 0x120, "gpc1", 0x24),
632 EXYNOS_PIN_BANK_EINTG(7, 0x140, "gpc2", 0x28),
633 EXYNOS_PIN_BANK_EINTN(2, 0x160, "gpm5"),
634 EXYNOS_PIN_BANK_EINTG(8, 0x180, "gpd1", 0x2c),
635 EXYNOS_PIN_BANK_EINTG(8, 0x1A0, "gpe0", 0x30),
636 EXYNOS_PIN_BANK_EINTG(2, 0x1C0, "gpe1", 0x34),
637 EXYNOS_PIN_BANK_EINTG(6, 0x1E0, "gpf0", 0x38),
638 EXYNOS_PIN_BANK_EINTG(8, 0x200, "gpf1", 0x3c),
639 EXYNOS_PIN_BANK_EINTG(8, 0x220, "gpg0", 0x40),
640 EXYNOS_PIN_BANK_EINTG(8, 0x240, "gpg1", 0x44),
641 EXYNOS_PIN_BANK_EINTG(2, 0x260, "gpg2", 0x48),
642 EXYNOS_PIN_BANK_EINTG(4, 0x280, "gph0", 0x4c),
643 EXYNOS_PIN_BANK_EINTG(8, 0x2A0, "gph1", 0x50),
644 EXYNOS_PIN_BANK_EINTN(8, 0x2C0, "gpm7"),
645 EXYNOS_PIN_BANK_EINTN(6, 0x2E0, "gpy0"),
646 EXYNOS_PIN_BANK_EINTN(4, 0x300, "gpy1"),
647 EXYNOS_PIN_BANK_EINTN(6, 0x320, "gpy2"),
648 EXYNOS_PIN_BANK_EINTN(8, 0x340, "gpy3"),
649 EXYNOS_PIN_BANK_EINTN(8, 0x360, "gpy4"),
650 EXYNOS_PIN_BANK_EINTN(8, 0x380, "gpy5"),
651 EXYNOS_PIN_BANK_EINTN(8, 0x3A0, "gpy6"),
652 EXYNOS_PIN_BANK_EINTN(8, 0x3C0, "gpy7"),
653 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
654 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
655 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
656 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
657};
658
659
660static const struct samsung_pin_bank_data exynos5410_pin_banks1[] __initconst = {
661 EXYNOS_PIN_BANK_EINTG(5, 0x000, "gpj0", 0x00),
662 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpj1", 0x04),
663 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpj2", 0x08),
664 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpj3", 0x0c),
665 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpj4", 0x10),
666 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpk0", 0x14),
667 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpk1", 0x18),
668 EXYNOS_PIN_BANK_EINTG(8, 0x0E0, "gpk2", 0x1c),
669 EXYNOS_PIN_BANK_EINTG(7, 0x100, "gpk3", 0x20),
670};
671
672
673static const struct samsung_pin_bank_data exynos5410_pin_banks2[] __initconst = {
674 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpv0", 0x00),
675 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpv1", 0x04),
676 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpv2", 0x08),
677 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpv3", 0x0c),
678 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpv4", 0x10),
679};
680
681
682static const struct samsung_pin_bank_data exynos5410_pin_banks3[] __initconst = {
683 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
684};
685
686
687
688
689
690static const struct samsung_pin_ctrl exynos5410_pin_ctrl[] __initconst = {
691 {
692
693 .pin_banks = exynos5410_pin_banks0,
694 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks0),
695 .eint_gpio_init = exynos_eint_gpio_init,
696 .eint_wkup_init = exynos_eint_wkup_init,
697 .suspend = exynos_pinctrl_suspend,
698 .resume = exynos_pinctrl_resume,
699 }, {
700
701 .pin_banks = exynos5410_pin_banks1,
702 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks1),
703 .eint_gpio_init = exynos_eint_gpio_init,
704 .suspend = exynos_pinctrl_suspend,
705 .resume = exynos_pinctrl_resume,
706 }, {
707
708 .pin_banks = exynos5410_pin_banks2,
709 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks2),
710 .eint_gpio_init = exynos_eint_gpio_init,
711 .suspend = exynos_pinctrl_suspend,
712 .resume = exynos_pinctrl_resume,
713 }, {
714
715 .pin_banks = exynos5410_pin_banks3,
716 .nr_banks = ARRAY_SIZE(exynos5410_pin_banks3),
717 .eint_gpio_init = exynos_eint_gpio_init,
718 .suspend = exynos_pinctrl_suspend,
719 .resume = exynos_pinctrl_resume,
720 },
721};
722
723const struct samsung_pinctrl_of_match_data exynos5410_of_data __initconst = {
724 .ctrl = exynos5410_pin_ctrl,
725 .num_ctrl = ARRAY_SIZE(exynos5410_pin_ctrl),
726};
727
728
729static const struct samsung_pin_bank_data exynos5420_pin_banks0[] __initconst = {
730 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpy7", 0x00),
731 EXYNOS_PIN_BANK_EINTW(8, 0xC00, "gpx0", 0x00),
732 EXYNOS_PIN_BANK_EINTW(8, 0xC20, "gpx1", 0x04),
733 EXYNOS_PIN_BANK_EINTW(8, 0xC40, "gpx2", 0x08),
734 EXYNOS_PIN_BANK_EINTW(8, 0xC60, "gpx3", 0x0c),
735};
736
737
738static const struct samsung_pin_bank_data exynos5420_pin_banks1[] __initconst = {
739 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpc0", 0x00),
740 EXYNOS_PIN_BANK_EINTG(8, 0x020, "gpc1", 0x04),
741 EXYNOS_PIN_BANK_EINTG(7, 0x040, "gpc2", 0x08),
742 EXYNOS_PIN_BANK_EINTG(4, 0x060, "gpc3", 0x0c),
743 EXYNOS_PIN_BANK_EINTG(2, 0x080, "gpc4", 0x10),
744 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpd1", 0x14),
745 EXYNOS_PIN_BANK_EINTN(6, 0x0C0, "gpy0"),
746 EXYNOS_PIN_BANK_EINTN(4, 0x0E0, "gpy1"),
747 EXYNOS_PIN_BANK_EINTN(6, 0x100, "gpy2"),
748 EXYNOS_PIN_BANK_EINTN(8, 0x120, "gpy3"),
749 EXYNOS_PIN_BANK_EINTN(8, 0x140, "gpy4"),
750 EXYNOS_PIN_BANK_EINTN(8, 0x160, "gpy5"),
751 EXYNOS_PIN_BANK_EINTN(8, 0x180, "gpy6"),
752};
753
754
755static const struct samsung_pin_bank_data exynos5420_pin_banks2[] __initconst = {
756 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpe0", 0x00),
757 EXYNOS_PIN_BANK_EINTG(2, 0x020, "gpe1", 0x04),
758 EXYNOS_PIN_BANK_EINTG(6, 0x040, "gpf0", 0x08),
759 EXYNOS_PIN_BANK_EINTG(8, 0x060, "gpf1", 0x0c),
760 EXYNOS_PIN_BANK_EINTG(8, 0x080, "gpg0", 0x10),
761 EXYNOS_PIN_BANK_EINTG(8, 0x0A0, "gpg1", 0x14),
762 EXYNOS_PIN_BANK_EINTG(2, 0x0C0, "gpg2", 0x18),
763 EXYNOS_PIN_BANK_EINTG(4, 0x0E0, "gpj4", 0x1c),
764};
765
766
767static const struct samsung_pin_bank_data exynos5420_pin_banks3[] __initconst = {
768 EXYNOS_PIN_BANK_EINTG(8, 0x000, "gpa0", 0x00),
769 EXYNOS_PIN_BANK_EINTG(6, 0x020, "gpa1", 0x04),
770 EXYNOS_PIN_BANK_EINTG(8, 0x040, "gpa2", 0x08),
771 EXYNOS_PIN_BANK_EINTG(5, 0x060, "gpb0", 0x0c),
772 EXYNOS_PIN_BANK_EINTG(5, 0x080, "gpb1", 0x10),
773 EXYNOS_PIN_BANK_EINTG(4, 0x0A0, "gpb2", 0x14),
774 EXYNOS_PIN_BANK_EINTG(8, 0x0C0, "gpb3", 0x18),
775 EXYNOS_PIN_BANK_EINTG(2, 0x0E0, "gpb4", 0x1c),
776 EXYNOS_PIN_BANK_EINTG(8, 0x100, "gph0", 0x20),
777};
778
779
780static const struct samsung_pin_bank_data exynos5420_pin_banks4[] __initconst = {
781 EXYNOS_PIN_BANK_EINTG(7, 0x000, "gpz", 0x00),
782};
783
784
785static const u32 exynos5420_retention_regs[] = {
786 EXYNOS_PAD_RET_DRAM_OPTION,
787 EXYNOS_PAD_RET_JTAG_OPTION,
788 EXYNOS5420_PAD_RET_GPIO_OPTION,
789 EXYNOS5420_PAD_RET_UART_OPTION,
790 EXYNOS5420_PAD_RET_MMCA_OPTION,
791 EXYNOS5420_PAD_RET_MMCB_OPTION,
792 EXYNOS5420_PAD_RET_MMCC_OPTION,
793 EXYNOS5420_PAD_RET_HSI_OPTION,
794 EXYNOS_PAD_RET_EBIA_OPTION,
795 EXYNOS_PAD_RET_EBIB_OPTION,
796 EXYNOS5420_PAD_RET_SPI_OPTION,
797 EXYNOS5420_PAD_RET_DRAM_COREBLK_OPTION,
798};
799
800static const struct samsung_retention_data exynos5420_retention_data __initconst = {
801 .regs = exynos5420_retention_regs,
802 .nr_regs = ARRAY_SIZE(exynos5420_retention_regs),
803 .value = EXYNOS_WAKEUP_FROM_LOWPWR,
804 .refcnt = &exynos_shared_retention_refcnt,
805 .init = exynos_retention_init,
806};
807
808
809
810
811
812static const struct samsung_pin_ctrl exynos5420_pin_ctrl[] __initconst = {
813 {
814
815 .pin_banks = exynos5420_pin_banks0,
816 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks0),
817 .eint_gpio_init = exynos_eint_gpio_init,
818 .eint_wkup_init = exynos_eint_wkup_init,
819 .retention_data = &exynos5420_retention_data,
820 }, {
821
822 .pin_banks = exynos5420_pin_banks1,
823 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks1),
824 .eint_gpio_init = exynos_eint_gpio_init,
825 .retention_data = &exynos5420_retention_data,
826 }, {
827
828 .pin_banks = exynos5420_pin_banks2,
829 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks2),
830 .eint_gpio_init = exynos_eint_gpio_init,
831 .retention_data = &exynos5420_retention_data,
832 }, {
833
834 .pin_banks = exynos5420_pin_banks3,
835 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks3),
836 .eint_gpio_init = exynos_eint_gpio_init,
837 .retention_data = &exynos5420_retention_data,
838 }, {
839
840 .pin_banks = exynos5420_pin_banks4,
841 .nr_banks = ARRAY_SIZE(exynos5420_pin_banks4),
842 .eint_gpio_init = exynos_eint_gpio_init,
843 .retention_data = &exynos4_audio_retention_data,
844 },
845};
846
847const struct samsung_pinctrl_of_match_data exynos5420_of_data __initconst = {
848 .ctrl = exynos5420_pin_ctrl,
849 .num_ctrl = ARRAY_SIZE(exynos5420_pin_ctrl),
850};
851
