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21#include <linux/err.h>
22#include <linux/init.h>
23#include <linux/io.h>
24#include <linux/of.h>
25#include <linux/platform_device.h>
26#include <linux/pinctrl/machine.h>
27#include <linux/pinctrl/pinctrl.h>
28#include <linux/pinctrl/pinmux.h>
29#include <linux/pinctrl/pinconf.h>
30#include <linux/slab.h>
31
32#include "../core.h"
33#include "../pinctrl-utils.h"
34#include "pinctrl-tegra.h"
35
36struct tegra_pmx {
37 struct device *dev;
38 struct pinctrl_dev *pctl;
39
40 const struct tegra_pinctrl_soc_data *soc;
41 const char **group_pins;
42
43 int nbanks;
44 void __iomem **regs;
45};
46
47static inline u32 pmx_readl(struct tegra_pmx *pmx, u32 bank, u32 reg)
48{
49 return readl(pmx->regs[bank] + reg);
50}
51
52static inline void pmx_writel(struct tegra_pmx *pmx, u32 val, u32 bank, u32 reg)
53{
54 writel(val, pmx->regs[bank] + reg);
55}
56
57static int tegra_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
58{
59 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
60
61 return pmx->soc->ngroups;
62}
63
64static const char *tegra_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
65 unsigned group)
66{
67 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
68
69 return pmx->soc->groups[group].name;
70}
71
72static int tegra_pinctrl_get_group_pins(struct pinctrl_dev *pctldev,
73 unsigned group,
74 const unsigned **pins,
75 unsigned *num_pins)
76{
77 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
78
79 *pins = pmx->soc->groups[group].pins;
80 *num_pins = pmx->soc->groups[group].npins;
81
82 return 0;
83}
84
85#ifdef CONFIG_DEBUG_FS
86static void tegra_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
87 struct seq_file *s,
88 unsigned offset)
89{
90 seq_printf(s, " %s", dev_name(pctldev->dev));
91}
92#endif
93
94static const struct cfg_param {
95 const char *property;
96 enum tegra_pinconf_param param;
97} cfg_params[] = {
98 {"nvidia,pull", TEGRA_PINCONF_PARAM_PULL},
99 {"nvidia,tristate", TEGRA_PINCONF_PARAM_TRISTATE},
100 {"nvidia,enable-input", TEGRA_PINCONF_PARAM_ENABLE_INPUT},
101 {"nvidia,open-drain", TEGRA_PINCONF_PARAM_OPEN_DRAIN},
102 {"nvidia,lock", TEGRA_PINCONF_PARAM_LOCK},
103 {"nvidia,io-reset", TEGRA_PINCONF_PARAM_IORESET},
104 {"nvidia,rcv-sel", TEGRA_PINCONF_PARAM_RCV_SEL},
105 {"nvidia,io-hv", TEGRA_PINCONF_PARAM_RCV_SEL},
106 {"nvidia,high-speed-mode", TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE},
107 {"nvidia,schmitt", TEGRA_PINCONF_PARAM_SCHMITT},
108 {"nvidia,low-power-mode", TEGRA_PINCONF_PARAM_LOW_POWER_MODE},
109 {"nvidia,pull-down-strength", TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH},
110 {"nvidia,pull-up-strength", TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH},
111 {"nvidia,slew-rate-falling", TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING},
112 {"nvidia,slew-rate-rising", TEGRA_PINCONF_PARAM_SLEW_RATE_RISING},
113 {"nvidia,drive-type", TEGRA_PINCONF_PARAM_DRIVE_TYPE},
114};
115
116static int tegra_pinctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
117 struct device_node *np,
118 struct pinctrl_map **map,
119 unsigned *reserved_maps,
120 unsigned *num_maps)
121{
122 struct device *dev = pctldev->dev;
123 int ret, i;
124 const char *function;
125 u32 val;
126 unsigned long config;
127 unsigned long *configs = NULL;
128 unsigned num_configs = 0;
129 unsigned reserve;
130 struct property *prop;
131 const char *group;
132
133 ret = of_property_read_string(np, "nvidia,function", &function);
134 if (ret < 0) {
135
136 if (ret != -EINVAL)
137 dev_err(dev,
138 "could not parse property nvidia,function\n");
139 function = NULL;
140 }
141
142 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
143 ret = of_property_read_u32(np, cfg_params[i].property, &val);
144 if (!ret) {
145 config = TEGRA_PINCONF_PACK(cfg_params[i].param, val);
146 ret = pinctrl_utils_add_config(pctldev, &configs,
147 &num_configs, config);
148 if (ret < 0)
149 goto exit;
150
151 } else if (ret != -EINVAL) {
152 dev_err(dev, "could not parse property %s\n",
153 cfg_params[i].property);
154 }
155 }
156
157 reserve = 0;
158 if (function != NULL)
159 reserve++;
160 if (num_configs)
161 reserve++;
162 ret = of_property_count_strings(np, "nvidia,pins");
163 if (ret < 0) {
164 dev_err(dev, "could not parse property nvidia,pins\n");
165 goto exit;
166 }
167 reserve *= ret;
168
169 ret = pinctrl_utils_reserve_map(pctldev, map, reserved_maps,
170 num_maps, reserve);
171 if (ret < 0)
172 goto exit;
173
174 of_property_for_each_string(np, "nvidia,pins", prop, group) {
175 if (function) {
176 ret = pinctrl_utils_add_map_mux(pctldev, map,
177 reserved_maps, num_maps, group,
178 function);
179 if (ret < 0)
180 goto exit;
181 }
182
183 if (num_configs) {
184 ret = pinctrl_utils_add_map_configs(pctldev, map,
185 reserved_maps, num_maps, group,
186 configs, num_configs,
187 PIN_MAP_TYPE_CONFIGS_GROUP);
188 if (ret < 0)
189 goto exit;
190 }
191 }
192
193 ret = 0;
194
195exit:
196 kfree(configs);
197 return ret;
198}
199
200static int tegra_pinctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
201 struct device_node *np_config,
202 struct pinctrl_map **map,
203 unsigned *num_maps)
204{
205 unsigned reserved_maps;
206 struct device_node *np;
207 int ret;
208
209 reserved_maps = 0;
210 *map = NULL;
211 *num_maps = 0;
212
213 for_each_child_of_node(np_config, np) {
214 ret = tegra_pinctrl_dt_subnode_to_map(pctldev, np, map,
215 &reserved_maps, num_maps);
216 if (ret < 0) {
217 pinctrl_utils_free_map(pctldev, *map,
218 *num_maps);
219 of_node_put(np);
220 return ret;
221 }
222 }
223
224 return 0;
225}
226
227static const struct pinctrl_ops tegra_pinctrl_ops = {
228 .get_groups_count = tegra_pinctrl_get_groups_count,
229 .get_group_name = tegra_pinctrl_get_group_name,
230 .get_group_pins = tegra_pinctrl_get_group_pins,
231#ifdef CONFIG_DEBUG_FS
232 .pin_dbg_show = tegra_pinctrl_pin_dbg_show,
233#endif
234 .dt_node_to_map = tegra_pinctrl_dt_node_to_map,
235 .dt_free_map = pinctrl_utils_free_map,
236};
237
238static int tegra_pinctrl_get_funcs_count(struct pinctrl_dev *pctldev)
239{
240 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
241
242 return pmx->soc->nfunctions;
243}
244
245static const char *tegra_pinctrl_get_func_name(struct pinctrl_dev *pctldev,
246 unsigned function)
247{
248 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
249
250 return pmx->soc->functions[function].name;
251}
252
253static int tegra_pinctrl_get_func_groups(struct pinctrl_dev *pctldev,
254 unsigned function,
255 const char * const **groups,
256 unsigned * const num_groups)
257{
258 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
259
260 *groups = pmx->soc->functions[function].groups;
261 *num_groups = pmx->soc->functions[function].ngroups;
262
263 return 0;
264}
265
266static int tegra_pinctrl_set_mux(struct pinctrl_dev *pctldev,
267 unsigned function,
268 unsigned group)
269{
270 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
271 const struct tegra_pingroup *g;
272 int i;
273 u32 val;
274
275 g = &pmx->soc->groups[group];
276
277 if (WARN_ON(g->mux_reg < 0))
278 return -EINVAL;
279
280 for (i = 0; i < ARRAY_SIZE(g->funcs); i++) {
281 if (g->funcs[i] == function)
282 break;
283 }
284 if (WARN_ON(i == ARRAY_SIZE(g->funcs)))
285 return -EINVAL;
286
287 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
288 val &= ~(0x3 << g->mux_bit);
289 val |= i << g->mux_bit;
290 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
291
292 return 0;
293}
294
295static const struct pinmux_ops tegra_pinmux_ops = {
296 .get_functions_count = tegra_pinctrl_get_funcs_count,
297 .get_function_name = tegra_pinctrl_get_func_name,
298 .get_function_groups = tegra_pinctrl_get_func_groups,
299 .set_mux = tegra_pinctrl_set_mux,
300};
301
302static int tegra_pinconf_reg(struct tegra_pmx *pmx,
303 const struct tegra_pingroup *g,
304 enum tegra_pinconf_param param,
305 bool report_err,
306 s8 *bank, s16 *reg, s8 *bit, s8 *width)
307{
308 switch (param) {
309 case TEGRA_PINCONF_PARAM_PULL:
310 *bank = g->pupd_bank;
311 *reg = g->pupd_reg;
312 *bit = g->pupd_bit;
313 *width = 2;
314 break;
315 case TEGRA_PINCONF_PARAM_TRISTATE:
316 *bank = g->tri_bank;
317 *reg = g->tri_reg;
318 *bit = g->tri_bit;
319 *width = 1;
320 break;
321 case TEGRA_PINCONF_PARAM_ENABLE_INPUT:
322 *bank = g->mux_bank;
323 *reg = g->mux_reg;
324 *bit = g->einput_bit;
325 *width = 1;
326 break;
327 case TEGRA_PINCONF_PARAM_OPEN_DRAIN:
328 *bank = g->mux_bank;
329 *reg = g->mux_reg;
330 *bit = g->odrain_bit;
331 *width = 1;
332 break;
333 case TEGRA_PINCONF_PARAM_LOCK:
334 *bank = g->mux_bank;
335 *reg = g->mux_reg;
336 *bit = g->lock_bit;
337 *width = 1;
338 break;
339 case TEGRA_PINCONF_PARAM_IORESET:
340 *bank = g->mux_bank;
341 *reg = g->mux_reg;
342 *bit = g->ioreset_bit;
343 *width = 1;
344 break;
345 case TEGRA_PINCONF_PARAM_RCV_SEL:
346 *bank = g->mux_bank;
347 *reg = g->mux_reg;
348 *bit = g->rcv_sel_bit;
349 *width = 1;
350 break;
351 case TEGRA_PINCONF_PARAM_HIGH_SPEED_MODE:
352 if (pmx->soc->hsm_in_mux) {
353 *bank = g->mux_bank;
354 *reg = g->mux_reg;
355 } else {
356 *bank = g->drv_bank;
357 *reg = g->drv_reg;
358 }
359 *bit = g->hsm_bit;
360 *width = 1;
361 break;
362 case TEGRA_PINCONF_PARAM_SCHMITT:
363 if (pmx->soc->schmitt_in_mux) {
364 *bank = g->mux_bank;
365 *reg = g->mux_reg;
366 } else {
367 *bank = g->drv_bank;
368 *reg = g->drv_reg;
369 }
370 *bit = g->schmitt_bit;
371 *width = 1;
372 break;
373 case TEGRA_PINCONF_PARAM_LOW_POWER_MODE:
374 *bank = g->drv_bank;
375 *reg = g->drv_reg;
376 *bit = g->lpmd_bit;
377 *width = 2;
378 break;
379 case TEGRA_PINCONF_PARAM_DRIVE_DOWN_STRENGTH:
380 *bank = g->drv_bank;
381 *reg = g->drv_reg;
382 *bit = g->drvdn_bit;
383 *width = g->drvdn_width;
384 break;
385 case TEGRA_PINCONF_PARAM_DRIVE_UP_STRENGTH:
386 *bank = g->drv_bank;
387 *reg = g->drv_reg;
388 *bit = g->drvup_bit;
389 *width = g->drvup_width;
390 break;
391 case TEGRA_PINCONF_PARAM_SLEW_RATE_FALLING:
392 *bank = g->drv_bank;
393 *reg = g->drv_reg;
394 *bit = g->slwf_bit;
395 *width = g->slwf_width;
396 break;
397 case TEGRA_PINCONF_PARAM_SLEW_RATE_RISING:
398 *bank = g->drv_bank;
399 *reg = g->drv_reg;
400 *bit = g->slwr_bit;
401 *width = g->slwr_width;
402 break;
403 case TEGRA_PINCONF_PARAM_DRIVE_TYPE:
404 if (pmx->soc->drvtype_in_mux) {
405 *bank = g->mux_bank;
406 *reg = g->mux_reg;
407 } else {
408 *bank = g->drv_bank;
409 *reg = g->drv_reg;
410 }
411 *bit = g->drvtype_bit;
412 *width = 2;
413 break;
414 default:
415 dev_err(pmx->dev, "Invalid config param %04x\n", param);
416 return -ENOTSUPP;
417 }
418
419 if (*reg < 0 || *bit < 0) {
420 if (report_err) {
421 const char *prop = "unknown";
422 int i;
423
424 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
425 if (cfg_params[i].param == param) {
426 prop = cfg_params[i].property;
427 break;
428 }
429 }
430
431 dev_err(pmx->dev,
432 "Config param %04x (%s) not supported on group %s\n",
433 param, prop, g->name);
434 }
435 return -ENOTSUPP;
436 }
437
438 return 0;
439}
440
441static int tegra_pinconf_get(struct pinctrl_dev *pctldev,
442 unsigned pin, unsigned long *config)
443{
444 dev_err(pctldev->dev, "pin_config_get op not supported\n");
445 return -ENOTSUPP;
446}
447
448static int tegra_pinconf_set(struct pinctrl_dev *pctldev,
449 unsigned pin, unsigned long *configs,
450 unsigned num_configs)
451{
452 dev_err(pctldev->dev, "pin_config_set op not supported\n");
453 return -ENOTSUPP;
454}
455
456static int tegra_pinconf_group_get(struct pinctrl_dev *pctldev,
457 unsigned group, unsigned long *config)
458{
459 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
460 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(*config);
461 u16 arg;
462 const struct tegra_pingroup *g;
463 int ret;
464 s8 bank, bit, width;
465 s16 reg;
466 u32 val, mask;
467
468 g = &pmx->soc->groups[group];
469
470 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
471 &width);
472 if (ret < 0)
473 return ret;
474
475 val = pmx_readl(pmx, bank, reg);
476 mask = (1 << width) - 1;
477 arg = (val >> bit) & mask;
478
479 *config = TEGRA_PINCONF_PACK(param, arg);
480
481 return 0;
482}
483
484static int tegra_pinconf_group_set(struct pinctrl_dev *pctldev,
485 unsigned group, unsigned long *configs,
486 unsigned num_configs)
487{
488 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
489 enum tegra_pinconf_param param;
490 u16 arg;
491 const struct tegra_pingroup *g;
492 int ret, i;
493 s8 bank, bit, width;
494 s16 reg;
495 u32 val, mask;
496
497 g = &pmx->soc->groups[group];
498
499 for (i = 0; i < num_configs; i++) {
500 param = TEGRA_PINCONF_UNPACK_PARAM(configs[i]);
501 arg = TEGRA_PINCONF_UNPACK_ARG(configs[i]);
502
503 ret = tegra_pinconf_reg(pmx, g, param, true, &bank, ®, &bit,
504 &width);
505 if (ret < 0)
506 return ret;
507
508 val = pmx_readl(pmx, bank, reg);
509
510
511 if (param == TEGRA_PINCONF_PARAM_LOCK) {
512 if ((val & BIT(bit)) && !arg) {
513 dev_err(pctldev->dev, "LOCK bit cannot be cleared\n");
514 return -EINVAL;
515 }
516 }
517
518
519 if (width == 1)
520 arg = !!arg;
521
522
523 mask = (1 << width) - 1;
524 if (arg & ~mask) {
525 dev_err(pctldev->dev,
526 "config %lx: %x too big for %d bit register\n",
527 configs[i], arg, width);
528 return -EINVAL;
529 }
530
531
532 val &= ~(mask << bit);
533 val |= arg << bit;
534 pmx_writel(pmx, val, bank, reg);
535 }
536
537 return 0;
538}
539
540#ifdef CONFIG_DEBUG_FS
541static void tegra_pinconf_dbg_show(struct pinctrl_dev *pctldev,
542 struct seq_file *s, unsigned offset)
543{
544}
545
546static const char *strip_prefix(const char *s)
547{
548 const char *comma = strchr(s, ',');
549 if (!comma)
550 return s;
551
552 return comma + 1;
553}
554
555static void tegra_pinconf_group_dbg_show(struct pinctrl_dev *pctldev,
556 struct seq_file *s, unsigned group)
557{
558 struct tegra_pmx *pmx = pinctrl_dev_get_drvdata(pctldev);
559 const struct tegra_pingroup *g;
560 int i, ret;
561 s8 bank, bit, width;
562 s16 reg;
563 u32 val;
564
565 g = &pmx->soc->groups[group];
566
567 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
568 ret = tegra_pinconf_reg(pmx, g, cfg_params[i].param, false,
569 &bank, ®, &bit, &width);
570 if (ret < 0)
571 continue;
572
573 val = pmx_readl(pmx, bank, reg);
574 val >>= bit;
575 val &= (1 << width) - 1;
576
577 seq_printf(s, "\n\t%s=%u",
578 strip_prefix(cfg_params[i].property), val);
579 }
580}
581
582static void tegra_pinconf_config_dbg_show(struct pinctrl_dev *pctldev,
583 struct seq_file *s,
584 unsigned long config)
585{
586 enum tegra_pinconf_param param = TEGRA_PINCONF_UNPACK_PARAM(config);
587 u16 arg = TEGRA_PINCONF_UNPACK_ARG(config);
588 const char *pname = "unknown";
589 int i;
590
591 for (i = 0; i < ARRAY_SIZE(cfg_params); i++) {
592 if (cfg_params[i].param == param) {
593 pname = cfg_params[i].property;
594 break;
595 }
596 }
597
598 seq_printf(s, "%s=%d", strip_prefix(pname), arg);
599}
600#endif
601
602static const struct pinconf_ops tegra_pinconf_ops = {
603 .pin_config_get = tegra_pinconf_get,
604 .pin_config_set = tegra_pinconf_set,
605 .pin_config_group_get = tegra_pinconf_group_get,
606 .pin_config_group_set = tegra_pinconf_group_set,
607#ifdef CONFIG_DEBUG_FS
608 .pin_config_dbg_show = tegra_pinconf_dbg_show,
609 .pin_config_group_dbg_show = tegra_pinconf_group_dbg_show,
610 .pin_config_config_dbg_show = tegra_pinconf_config_dbg_show,
611#endif
612};
613
614static struct pinctrl_gpio_range tegra_pinctrl_gpio_range = {
615 .name = "Tegra GPIOs",
616 .id = 0,
617 .base = 0,
618};
619
620static struct pinctrl_desc tegra_pinctrl_desc = {
621 .pctlops = &tegra_pinctrl_ops,
622 .pmxops = &tegra_pinmux_ops,
623 .confops = &tegra_pinconf_ops,
624 .owner = THIS_MODULE,
625};
626
627static void tegra_pinctrl_clear_parked_bits(struct tegra_pmx *pmx)
628{
629 int i = 0;
630 const struct tegra_pingroup *g;
631 u32 val;
632
633 for (i = 0; i < pmx->soc->ngroups; ++i) {
634 g = &pmx->soc->groups[i];
635 if (g->parked_bit >= 0) {
636 val = pmx_readl(pmx, g->mux_bank, g->mux_reg);
637 val &= ~(1 << g->parked_bit);
638 pmx_writel(pmx, val, g->mux_bank, g->mux_reg);
639 }
640 }
641}
642
643static bool gpio_node_has_range(void)
644{
645 struct device_node *np;
646 bool has_prop = false;
647
648 np = of_find_compatible_node(NULL, NULL, "nvidia,tegra30-gpio");
649 if (!np)
650 return has_prop;
651
652 has_prop = of_find_property(np, "gpio-ranges", NULL);
653
654 of_node_put(np);
655
656 return has_prop;
657}
658
659int tegra_pinctrl_probe(struct platform_device *pdev,
660 const struct tegra_pinctrl_soc_data *soc_data)
661{
662 struct tegra_pmx *pmx;
663 struct resource *res;
664 int i;
665 const char **group_pins;
666 int fn, gn, gfn;
667
668 pmx = devm_kzalloc(&pdev->dev, sizeof(*pmx), GFP_KERNEL);
669 if (!pmx)
670 return -ENOMEM;
671
672 pmx->dev = &pdev->dev;
673 pmx->soc = soc_data;
674
675
676
677
678
679 pmx->group_pins = devm_kzalloc(&pdev->dev,
680 soc_data->ngroups * 4 * sizeof(*pmx->group_pins),
681 GFP_KERNEL);
682 if (!pmx->group_pins)
683 return -ENOMEM;
684
685 group_pins = pmx->group_pins;
686 for (fn = 0; fn < soc_data->nfunctions; fn++) {
687 struct tegra_function *func = &soc_data->functions[fn];
688
689 func->groups = group_pins;
690
691 for (gn = 0; gn < soc_data->ngroups; gn++) {
692 const struct tegra_pingroup *g = &soc_data->groups[gn];
693
694 if (g->mux_reg == -1)
695 continue;
696
697 for (gfn = 0; gfn < 4; gfn++)
698 if (g->funcs[gfn] == fn)
699 break;
700 if (gfn == 4)
701 continue;
702
703 BUG_ON(group_pins - pmx->group_pins >=
704 soc_data->ngroups * 4);
705 *group_pins++ = g->name;
706 func->ngroups++;
707 }
708 }
709
710 tegra_pinctrl_gpio_range.npins = pmx->soc->ngpios;
711 tegra_pinctrl_desc.name = dev_name(&pdev->dev);
712 tegra_pinctrl_desc.pins = pmx->soc->pins;
713 tegra_pinctrl_desc.npins = pmx->soc->npins;
714
715 for (i = 0; ; i++) {
716 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
717 if (!res)
718 break;
719 }
720 pmx->nbanks = i;
721
722 pmx->regs = devm_kzalloc(&pdev->dev, pmx->nbanks * sizeof(*pmx->regs),
723 GFP_KERNEL);
724 if (!pmx->regs)
725 return -ENOMEM;
726
727 for (i = 0; i < pmx->nbanks; i++) {
728 res = platform_get_resource(pdev, IORESOURCE_MEM, i);
729 pmx->regs[i] = devm_ioremap_resource(&pdev->dev, res);
730 if (IS_ERR(pmx->regs[i]))
731 return PTR_ERR(pmx->regs[i]);
732 }
733
734 pmx->pctl = devm_pinctrl_register(&pdev->dev, &tegra_pinctrl_desc, pmx);
735 if (IS_ERR(pmx->pctl)) {
736 dev_err(&pdev->dev, "Couldn't register pinctrl driver\n");
737 return PTR_ERR(pmx->pctl);
738 }
739
740 tegra_pinctrl_clear_parked_bits(pmx);
741
742 if (!gpio_node_has_range())
743 pinctrl_add_gpio_range(pmx->pctl, &tegra_pinctrl_gpio_range);
744
745 platform_set_drvdata(pdev, pmx);
746
747 dev_dbg(&pdev->dev, "Probed Tegra pinctrl driver\n");
748
749 return 0;
750}
751EXPORT_SYMBOL_GPL(tegra_pinctrl_probe);
752
